2 * ngene.h: nGene PCIe bridge driver
4 * Copyright (C) 2005-2007 Micronas
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * To obtain the license, point your browser to
17 * http://www.gnu.org/copyleft/gpl.html
23 #include <linux/types.h>
24 #include <linux/sched.h>
25 #include <linux/interrupt.h>
26 #include <linux/i2c.h>
28 #include <linux/scatterlist.h>
30 #include <linux/dvb/frontend.h>
32 #include <media/dmxdev.h>
33 #include <media/dvbdev.h>
34 #include <media/dvb_demux.h>
35 #include <media/dvb_ca_en50221.h>
36 #include <media/dvb_frontend.h>
37 #include <media/dvb_ringbuffer.h>
38 #include <media/dvb_net.h>
41 #define DEVICE_NAME "ngene"
43 #define NGENE_VID 0x18c3
44 #define NGENE_PID 0x0720
47 #define VIDEO_CAP_AVC 128
48 #define VIDEO_CAP_H264 128
49 #define VIDEO_CAP_VC1 256
50 #define VIDEO_CAP_WMV9 256
51 #define VIDEO_CAP_MPEG4 512
54 #define DEMOD_TYPE_STV090X 0
55 #define DEMOD_TYPE_DRXK 1
56 #define DEMOD_TYPE_STV0367 2
58 #define DEMOD_TYPE_XO2 32
59 #define DEMOD_TYPE_STV0910 (DEMOD_TYPE_XO2 + 0)
60 #define DEMOD_TYPE_SONY_CT2 (DEMOD_TYPE_XO2 + 1)
61 #define DEMOD_TYPE_SONY_ISDBT (DEMOD_TYPE_XO2 + 2)
62 #define DEMOD_TYPE_SONY_C2T2 (DEMOD_TYPE_XO2 + 3)
63 #define DEMOD_TYPE_ST_ATSC (DEMOD_TYPE_XO2 + 4)
64 #define DEMOD_TYPE_SONY_C2T2I (DEMOD_TYPE_XO2 + 5)
66 #define NGENE_XO2_TYPE_NONE 0
67 #define NGENE_XO2_TYPE_DUOFLEX 1
68 #define NGENE_XO2_TYPE_CI 2
71 STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */
73 STREAM_AUDIOIN1, /* I2S or SPI Input */
80 SMODE_AUDIO_SPDIF = 0x20,
82 SMODE_TRANSPORT_STREAM = 0x08,
83 SMODE_AUDIO_CAPTURE = 0x04,
84 SMODE_VBI_CAPTURE = 0x02,
85 SMODE_VIDEO_CAPTURE = 0x01
88 enum STREAM_FLAG_BITS {
89 SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */
90 SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */
91 SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */
92 SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */
93 SFLAG_COLORBAR = 0x04, /* Select colorbar */
96 #define PROGRAM_ROM 0x0000
97 #define PROGRAM_SRAM 0x1000
98 #define PERIPHERALS0 0x8000
99 #define PERIPHERALS1 0x9000
100 #define SHARED_BUFFER 0xC000
102 #define HOST_TO_NGENE (SHARED_BUFFER+0x0000)
103 #define NGENE_TO_HOST (SHARED_BUFFER+0x0100)
104 #define NGENE_COMMAND (SHARED_BUFFER+0x0200)
105 #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
106 #define NGENE_STATUS (SHARED_BUFFER+0x0208)
107 #define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)
108 #define NGENE_EVENT (SHARED_BUFFER+0x0210)
109 #define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)
110 #define VARIABLES (SHARED_BUFFER+0x0210)
112 #define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)
113 #define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)
114 #define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)
116 #define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)
117 #define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)
118 #define EEPROM_AREA (SHARED_BUFFER+0x0A00)
120 #define SG_V_IN_1 (SHARED_BUFFER+0x0A80)
121 #define SG_VBI_1 (SHARED_BUFFER+0x0B00)
122 #define SG_A_IN_1 (SHARED_BUFFER+0x0B80)
123 #define SG_V_IN_2 (SHARED_BUFFER+0x0C00)
124 #define SG_VBI_2 (SHARED_BUFFER+0x0C80)
125 #define SG_A_IN_2 (SHARED_BUFFER+0x0D00)
126 #define SG_V_OUT (SHARED_BUFFER+0x0D80)
127 #define SG_A_OUT2 (SHARED_BUFFER+0x0E00)
129 #define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)
130 #define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)
131 #define DATA_A_OUT (SHARED_BUFFER+0x0F80)
132 #define DATA_V_IN_1 (SHARED_BUFFER+0x1000)
133 #define DATA_V_IN_2 (SHARED_BUFFER+0x2000)
134 #define DATA_V_OUT (SHARED_BUFFER+0x3000)
136 #define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)
138 #define TIMESTAMPS 0xA000
139 #define SCRATCHPAD 0xA080
140 #define FORCE_INT 0xA088
141 #define FORCE_NMI 0xA090
142 #define INT_STATUS 0xA0A0
144 #define DEV_VER 0x9004
146 #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
154 } __attribute__ ((__packed__));
156 struct SHARED_MEMORY {
169 u8 pad1[0xc260 - 0xc218];
176 u8 pad2[0xd000 - 0xc268];
178 } __attribute__ ((__packed__));
180 struct BUFFER_STREAM_RESULTS {
181 u32 Clock; /* Stream time in 100ns units */
182 u16 RemainingLines; /* Remaining lines in this field.
183 0 for complete field */
184 u8 FieldCount; /* Video field number */
185 u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
187 u16 BlockCount; /* Audio block count (unused) */
190 } __attribute__ ((__packed__));
192 struct HW_SCATTER_GATHER_ELEMENT {
196 } __attribute__ ((__packed__));
198 struct BUFFER_HEADER {
200 struct BUFFER_STREAM_RESULTS SR;
202 u32 Number_of_entries_1;
204 u64 Address_of_first_entry_1;
206 u32 Number_of_entries_2;
208 u64 Address_of_first_entry_2;
209 } __attribute__ ((__packed__));
211 struct EVENT_BUFFER {
218 } __attribute__ ((__packed__));
220 /* Firmware commands. */
224 CMD_FWLOAD_PREPARE = 0x01,
225 CMD_FWLOAD_FINISH = 0x02,
227 CMD_I2C_WRITE = 0x04,
229 CMD_I2C_WRITE_NOSTOP = 0x05,
230 CMD_I2C_CONTINUE_WRITE = 0x06,
231 CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,
233 CMD_DEBUG_OUTPUT = 0x09,
236 CMD_CONFIGURE_BUFFER = 0x11,
237 CMD_CONFIGURE_FREE_BUFFER = 0x12,
240 CMD_SPI_WRITE = 0x14,
243 CMD_MEM_WRITE = 0x21,
245 CMD_SFR_WRITE = 0x23,
246 CMD_IRAM_READ = 0x24,
247 CMD_IRAM_WRITE = 0x25,
248 CMD_SET_GPIO_PIN = 0x26,
249 CMD_SET_GPIO_INT = 0x27,
250 CMD_CONFIGURE_UART = 0x28,
251 CMD_WRITE_UART = 0x29,
263 } __attribute__ ((__packed__));
265 struct FW_I2C_WRITE {
266 struct FW_HEADER hdr;
269 } __attribute__ ((__packed__));
271 struct FW_I2C_CONTINUE_WRITE {
272 struct FW_HEADER hdr;
274 } __attribute__ ((__packed__));
277 struct FW_HEADER hdr;
279 u8 Data[252]; /* followed by two bytes of read data count */
280 } __attribute__ ((__packed__));
282 struct FW_SPI_WRITE {
283 struct FW_HEADER hdr;
286 } __attribute__ ((__packed__));
289 struct FW_HEADER hdr;
291 u8 Data[252]; /* followed by two bytes of read data count */
292 } __attribute__ ((__packed__));
294 struct FW_FWLOAD_PREPARE {
295 struct FW_HEADER hdr;
296 } __attribute__ ((__packed__));
298 struct FW_FWLOAD_FINISH {
299 struct FW_HEADER hdr;
300 u16 Address; /* address of final block */
302 } __attribute__ ((__packed__));
305 * Meaning of FW_STREAM_CONTROL::Mode bits:
306 * Bit 7: Loopback PEXin to PEXout using TVOut channel
308 * Bit 5: Audio select; 0=I2S, 1=SPDIF
310 * Bit 3: Enable transport stream
311 * Bit 2: Enable audio capture
312 * Bit 1: Enable ITU-Video VBI capture
313 * Bit 0: Enable ITU-Video capture
315 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
316 * Bit 7: continuous capture
317 * Bit 6: capture one field
318 * Bit 5: capture one frame
320 * Bit 3: starting field; 0=odd, 1=even
321 * Bit 2: sample size; 0=8-bit, 1=10-bit
322 * Bit 1: data format; 0=UYVY, 1=YUY2
323 * Bit 0: resets buffer pointers
327 SMODE_LOOPBACK = 0x80,
329 _SMODE_AUDIO_SPDIF = 0x20,
330 _SMODE_AVSYNC = 0x10,
331 _SMODE_TRANSPORT_STREAM = 0x08,
332 _SMODE_AUDIO_CAPTURE = 0x04,
333 _SMODE_VBI_CAPTURE = 0x02,
334 _SMODE_VIDEO_CAPTURE = 0x01
338 /* Meaning of FW_STREAM_CONTROL::Stream bits:
339 * Bit 3: Audio sample count: 0 = relative, 1 = absolute
340 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
341 * Bits 1-0: stream select, UVI1, UVI2, TVOUT
344 struct FW_STREAM_CONTROL {
345 struct FW_HEADER hdr;
346 u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */
347 u8 Control; /* Value written to UVI1_CTL */
348 u8 Mode; /* Controls clock source */
349 u8 SetupDataLen; /* Length of setup data, MSB=1 write
351 u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer
353 u64 Buffer_Address; /* Address of first buffer header */
354 u16 BytesPerVideoLine;
355 u16 MaxLinesPerField;
356 u16 MinLinesPerField;
359 u16 MaxVBILinesPerField;
360 u16 MinVBILinesPerField;
361 u16 SetupDataAddr; /* ngene relative address of setup data */
362 u8 SetupData[32]; /* setup data */
363 } __attribute__((__packed__));
365 #define AUDIO_BLOCK_SIZE 256
366 #define TS_BLOCK_SIZE 256
369 struct FW_HEADER hdr;
371 } __attribute__ ((__packed__));
373 struct FW_MEM_WRITE {
374 struct FW_HEADER hdr;
377 } __attribute__ ((__packed__));
379 struct FW_SFR_IRAM_READ {
380 struct FW_HEADER hdr;
382 } __attribute__ ((__packed__));
384 struct FW_SFR_IRAM_WRITE {
385 struct FW_HEADER hdr;
388 } __attribute__ ((__packed__));
390 struct FW_SET_GPIO_PIN {
391 struct FW_HEADER hdr;
393 } __attribute__ ((__packed__));
395 struct FW_SET_GPIO_INT {
396 struct FW_HEADER hdr;
398 } __attribute__ ((__packed__));
400 struct FW_SET_DEBUGMODE {
401 struct FW_HEADER hdr;
403 } __attribute__ ((__packed__));
405 struct FW_CONFIGURE_BUFFERS {
406 struct FW_HEADER hdr;
408 } __attribute__ ((__packed__));
410 enum _BUFFER_CONFIGS {
411 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */
412 BUFFER_CONFIG_4422 = 0,
413 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */
414 BUFFER_CONFIG_3333 = 1,
415 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */
416 BUFFER_CONFIG_8022 = 2,
417 BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */
420 struct FW_CONFIGURE_FREE_BUFFERS {
421 struct FW_HEADER hdr;
423 u8 UVI1_BufferLength;
424 u8 UVI2_BufferLength;
426 u8 AUD1_BufferLength;
427 u8 AUD2_BufferLength;
430 } __attribute__ ((__packed__));
432 struct FW_CONFIGURE_UART {
433 struct FW_HEADER hdr;
435 } __attribute__ ((__packed__));
438 _UART_BAUDRATE_19200 = 0,
439 _UART_BAUDRATE_9600 = 1,
440 _UART_BAUDRATE_4800 = 2,
441 _UART_BAUDRATE_2400 = 3,
442 _UART_RX_ENABLE = 0x40,
443 _UART_TX_ENABLE = 0x80,
446 struct FW_WRITE_UART {
447 struct FW_HEADER hdr;
449 } __attribute__ ((__packed__));
452 struct ngene_command {
458 struct FW_HEADER hdr;
459 struct FW_I2C_WRITE I2CWrite;
460 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite;
461 struct FW_I2C_READ I2CRead;
462 struct FW_STREAM_CONTROL StreamControl;
463 struct FW_FWLOAD_PREPARE FWLoadPrepare;
464 struct FW_FWLOAD_FINISH FWLoadFinish;
465 struct FW_MEM_READ MemoryRead;
466 struct FW_MEM_WRITE MemoryWrite;
467 struct FW_SFR_IRAM_READ SfrIramRead;
468 struct FW_SFR_IRAM_WRITE SfrIramWrite;
469 struct FW_SPI_WRITE SPIWrite;
470 struct FW_SPI_READ SPIRead;
471 struct FW_SET_GPIO_PIN SetGpioPin;
472 struct FW_SET_GPIO_INT SetGpioInt;
473 struct FW_SET_DEBUGMODE SetDebugMode;
474 struct FW_CONFIGURE_BUFFERS ConfigureBuffers;
475 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;
476 struct FW_CONFIGURE_UART ConfigureUart;
477 struct FW_WRITE_UART WriteUart;
479 } __attribute__ ((__packed__));
481 #define NGENE_INTERFACE_VERSION 0x103
482 #define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */
483 #define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */
484 #define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */
485 #define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */
486 #define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page
487 Max: (1920x1080i60) */
489 #define OVERFLOW_BUFFER_SIZE (8192)
491 #define RING_SIZE_VIDEO 4
492 #define RING_SIZE_AUDIO 8
493 #define RING_SIZE_TS 8
495 #define NUM_SCATTER_GATHER_ENTRIES 8
497 #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
498 RING_SIZE_VIDEO * 2) + \
499 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
500 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
501 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
502 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
503 (RING_SIZE_TS * PAGE_SIZE * 4) + \
504 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
506 #define EVENT_QUEUE_SIZE 16
508 /* Gathers the current state of a single channel. */
510 struct SBufferHeader {
511 struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */
512 struct SBufferHeader *Next;
514 struct HW_SCATTER_GATHER_ELEMENT *scList1;
516 struct HW_SCATTER_GATHER_ELEMENT *scList2;
519 /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
520 #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
536 struct SRingBufferDescriptor {
537 struct SBufferHeader *Head; /* Points to first buffer in ring buffer
539 u64 PAHead; /* Physical address of first buffer */
540 u32 MemSize; /* Memory size of allocated ring buffers
541 (needed for freeing) */
542 u32 NumBuffers; /* Number of buffers in the ring */
543 u32 Buffer1Length; /* Allocated length of Buffer 1 */
544 u32 Buffer2Length; /* Allocated length of Buffer 2 */
545 void *SCListMem; /* Memory to hold scatter gather lists for this
547 u64 PASCListMem; /* Physical address .. */
548 u32 SCListMemSize; /* Size of this memory */
551 enum STREAMMODEFLAGS {
552 StreamMode_NONE = 0, /* Stream not used */
553 StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
554 StreamMode_TSIN = 2, /* Transport stream input (all) */
555 StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
557 StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */
561 enum BufferExchangeFlags {
562 BEF_EVEN_FIELD = 0x00000001,
563 BEF_CONTINUATION = 0x00000002,
564 BEF_MORE_DATA = 0x00000004,
565 BEF_OVERFLOW = 0x00000008,
566 DF_SWAP32 = 0x00010000,
569 typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);
571 struct MICI_STREAMINFO {
572 IBufferExchange *pExchange;
573 IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */
579 u16 nBytesPerLineVideo;
581 u16 nBytesPerLineVBI;
582 u32 CaptureLength; /* Used for audio and transport stream */
585 /****************************************************************************/
586 /* STRUCTS ******************************************************************/
587 /****************************************************************************/
589 /* sound hardware definition */
590 #define MIXER_ADDR_TVTUNER 0
591 #define MIXER_ADDR_LAST 0
593 struct ngene_channel;
595 /*struct sound chip*/
598 struct ngene_channel *chan;
599 struct snd_card *card;
601 struct snd_pcm_substream *substream;
605 spinlock_t mixer_lock;
607 int mixer_volume[MIXER_ADDR_LAST + 1][2];
608 int capture_source[MIXER_ADDR_LAST + 1][2];
612 struct ngene_overlay {
615 enum v4l2_field field;
616 struct v4l2_clip *clips;
621 struct ngene_tvnorm {
624 u16 swidth, sheight; /* scaled standard width, height */
630 struct ngene_channel *ch;
631 enum v4l2_priority prio;
635 struct videobuf_queue vbuf_q;
636 struct videobuf_queue vbi;
640 enum v4l2_buf_type type;
641 const struct ngene_format *fmt;
643 const struct ngene_format *ovfmt;
644 struct ngene_overlay ov;
648 struct ngene_channel {
649 struct device device;
650 struct i2c_adapter i2c_adapter;
651 struct i2c_client *i2c_client[1];
661 int (*gate_ctrl)(struct dvb_frontend *, int);
663 struct dvb_frontend *fe;
664 struct dvb_frontend *fe2;
665 struct dmxdev dmxdev;
666 struct dvb_demux demux;
667 struct dvb_net dvbnet;
668 struct dmx_frontend hw_frontend;
669 struct dmx_frontend mem_frontend;
671 struct video_device *v4l_dev;
672 struct dvb_device *ci_dev;
673 struct tasklet_struct demux_tasklet;
675 struct SBufferHeader *nextBuffer;
677 enum HWSTATE HWState;
681 IBufferExchange *pBufferExchange;
682 IBufferExchange *pBufferExchange2;
684 spinlock_t state_lock;
688 u16 nBytesPerVBILine;
692 struct SRingBufferDescriptor RingBuffer;
693 struct SRingBufferDescriptor TSRingBuffer;
694 struct SRingBufferDescriptor TSIdleBuffer;
701 int (*set_tone)(struct dvb_frontend *, enum fe_sec_tone_mode);
704 /* stuff from analog driver */
707 struct mychip *mychip;
708 struct snd_card *soundcard;
713 int soundbuffisallocated;
720 struct ngene_tvnorm *tvnorms;
726 struct v4l2_prio_state prio;
727 struct ngene_vopen init;
729 struct v4l2_framebuffer fbuf;
730 struct ngene_buffer *screen; /* overlay */
731 struct list_head capture; /* video capture queue */
733 struct semaphore reslock;
744 struct device device;
745 struct i2c_adapter i2c_adapter;
748 struct dvb_ca_en50221 *en;
753 typedef void (rx_cb_t)(struct ngene *, u32, u8);
754 typedef void (tx_cb_t)(struct ngene *, u32);
758 struct pci_dev *pci_dev;
759 unsigned char __iomem *iomem;
761 /*struct i2c_adapter i2c_adapter;*/
764 u32 fw_interface_version;
767 bool cmd_timeout_workaround;
771 void *OverflowBuffer;
772 dma_addr_t PAOverflowBuffer;
773 void *FWInterfaceBuffer;
774 dma_addr_t PAFWInterfaceBuffer;
778 struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE];
779 int EventQueueOverflowCount;
780 int EventQueueOverflowFlag;
781 struct tasklet_struct event_tasklet;
782 struct EVENT_BUFFER *EventBuffer;
783 int EventQueueWriteIndex;
784 int EventQueueReadIndex;
786 wait_queue_head_t cmd_wq;
788 struct mutex cmd_mutex;
789 struct mutex stream_mutex;
790 struct semaphore pll_mutex;
791 struct mutex i2c_switch_mutex;
792 int i2c_current_channel;
796 struct dvb_adapter adapter[MAX_STREAM];
797 struct dvb_adapter *first_adapter; /* "one_adapter" modprobe opt */
798 struct ngene_channel channel[MAX_STREAM];
800 struct ngene_info *card_info;
802 tx_cb_t *TxEventNotify;
803 rx_cb_t *RxEventNotify;
805 wait_queue_head_t tx_wq;
806 wait_queue_head_t rx_wq;
807 #define UART_RBUF_LEN 4096
808 u8 uart_rbuf[UART_RBUF_LEN];
809 int uart_rp, uart_wp;
811 #define TS_FILLER 0x6f
814 #define TSOUT_BUF_SIZE (512*188*8)
815 struct dvb_ringbuffer tsout_rbuf;
818 #define TSIN_BUF_SIZE (512*188*8)
819 struct dvb_ringbuffer tsin_rbuf;
822 #define AIN_BUF_SIZE (128*1024)
823 struct dvb_ringbuffer ain_rbuf;
827 #define VIN_BUF_SIZE (4*1920*1080)
828 struct dvb_ringbuffer vin_rbuf;
830 unsigned long exp_val;
839 #define NGENE_TERRATEC 1
840 #define NGENE_SIDEWINDER 2
841 #define NGENE_RACER 3
842 #define NGENE_VIPER 4
843 #define NGENE_PYTHON 5
844 #define NGENE_VBOX_V1 6
845 #define NGENE_VBOX_V2 7
851 int io_type[MAX_STREAM];
852 #define NGENE_IO_NONE 0
853 #define NGENE_IO_TV 1
854 #define NGENE_IO_HDTV 2
855 #define NGENE_IO_TSIN 4
856 #define NGENE_IO_TSOUT 8
857 #define NGENE_IO_AIN 16
860 void *tuner_config[4];
862 int (*demod_attach[4])(struct ngene_channel *);
863 int (*tuner_attach[4])(struct ngene_channel *);
874 int (*gate_ctrl)(struct dvb_frontend *, int);
875 int (*switch_ctrl)(struct ngene_channel *, int, int);
879 struct ngene_format {
881 int fourcc; /* video4linux 2 */
882 int btformat; /* BT848_COLOR_FMT_* */
884 int btswap; /* BT848_COLOR_CTL_* */
885 int depth; /* bit/pixel */
887 int hshift, vshift; /* for planar modes */
891 #define RESOURCE_OVERLAY 1
892 #define RESOURCE_VIDEO 2
893 #define RESOURCE_VBI 4
895 struct ngene_buffer {
896 /* common v4l buffer stuff -- must be first */
897 struct videobuf_buffer vb;
900 const struct ngene_format *fmt;
908 /* Provided by ngene-core.c */
909 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id);
910 void ngene_remove(struct pci_dev *pdev);
911 void ngene_shutdown(struct pci_dev *pdev);
912 int ngene_command(struct ngene *dev, struct ngene_command *com);
913 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level);
914 void set_transfer(struct ngene_channel *chan, int state);
915 void FillTSBuffer(void *Buffer, int Length, u32 Flags);
917 /* Provided by ngene-cards.c */
918 int ngene_port_has_cxd2099(struct i2c_adapter *i2c, u8 *type);
920 /* Provided by ngene-i2c.c */
921 int ngene_i2c_init(struct ngene *dev, int dev_nr);
923 /* Provided by ngene-dvb.c */
924 extern struct dvb_device ngene_dvbdev_ci;
925 void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
926 void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
927 int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed);
928 int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed);
929 int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
930 int (*start_feed)(struct dvb_demux_feed *),
931 int (*stop_feed)(struct dvb_demux_feed *),
933 int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
934 struct dvb_demux *dvbdemux,
935 struct dmx_frontend *hw_frontend,
936 struct dmx_frontend *mem_frontend,
937 struct dvb_adapter *dvb_adapter);