drivers/media/platform/exynos4-is/fimc-is.c

   1 /*
   2  * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *
   6  * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
   7  *          Younghwan Joo <yhwan.joo@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  14
  15 #include <linux/device.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/dma-contiguous.h>
  19 #include <linux/errno.h>
  20 #include <linux/firmware.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_graph.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/slab.h>
  32 #include <linux/types.h>
  33 #include <linux/videodev2.h>
  34 #include <media/videobuf2-dma-contig.h>
  35
  36 #include "media-dev.h"
  37 #include "fimc-is.h"
  38 #include "fimc-is-command.h"
  39 #include "fimc-is-errno.h"
  40 #include "fimc-is-i2c.h"
  41 #include "fimc-is-param.h"
  42 #include "fimc-is-regs.h"
  43
  44
  45 static char *fimc_is_clocks[ISS_CLKS_MAX] = {
  46         [ISS_CLK_PPMUISPX]              = "ppmuispx",
  47         [ISS_CLK_PPMUISPMX]             = "ppmuispmx",
  48         [ISS_CLK_LITE0]                 = "lite0",
  49         [ISS_CLK_LITE1]                 = "lite1",
  50         [ISS_CLK_MPLL]                  = "mpll",
  51         [ISS_CLK_ISP]                   = "isp",
  52         [ISS_CLK_DRC]                   = "drc",
  53         [ISS_CLK_FD]                    = "fd",
  54         [ISS_CLK_MCUISP]                = "mcuisp",
  55         [ISS_CLK_GICISP]                = "gicisp",
  56         [ISS_CLK_PWM_ISP]               = "pwm_isp",
  57         [ISS_CLK_MCUCTL_ISP]            = "mcuctl_isp",
  58         [ISS_CLK_UART]                  = "uart",
  59         [ISS_CLK_ISP_DIV0]              = "ispdiv0",
  60         [ISS_CLK_ISP_DIV1]              = "ispdiv1",
  61         [ISS_CLK_MCUISP_DIV0]           = "mcuispdiv0",
  62         [ISS_CLK_MCUISP_DIV1]           = "mcuispdiv1",
  63         [ISS_CLK_ACLK200]               = "aclk200",
  64         [ISS_CLK_ACLK200_DIV]           = "div_aclk200",
  65         [ISS_CLK_ACLK400MCUISP]         = "aclk400mcuisp",
  66         [ISS_CLK_ACLK400MCUISP_DIV]     = "div_aclk400mcuisp",
  67 };
  68
  69 static void fimc_is_put_clocks(struct fimc_is *is)
  70 {
  71         int i;
  72
  73         for (i = 0; i < ISS_CLKS_MAX; i++) {
  74                 if (IS_ERR(is->clocks[i]))
  75                         continue;
  76                 clk_put(is->clocks[i]);
  77                 is->clocks[i] = ERR_PTR(-EINVAL);
  78         }
  79 }
  80
  81 static int fimc_is_get_clocks(struct fimc_is *is)
  82 {
  83         int i, ret;
  84
  85         for (i = 0; i < ISS_CLKS_MAX; i++)
  86                 is->clocks[i] = ERR_PTR(-EINVAL);
  87
  88         for (i = 0; i < ISS_CLKS_MAX; i++) {
  89                 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
  90                 if (IS_ERR(is->clocks[i])) {
  91                         ret = PTR_ERR(is->clocks[i]);
  92                         goto err;
  93                 }
  94         }
  95
  96         return 0;
  97 err:
  98         fimc_is_put_clocks(is);
  99         dev_err(&is->pdev->dev, "failed to get clock: %s\n",
 100                 fimc_is_clocks[i]);
 101         return ret;
 102 }
 103
 104 static int fimc_is_setup_clocks(struct fimc_is *is)
 105 {
 106         int ret;
 107
 108         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
 109                                         is->clocks[ISS_CLK_ACLK200_DIV]);
 110         if (ret < 0)
 111                 return ret;
 112
 113         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
 114                                         is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
 115         if (ret < 0)
 116                 return ret;
 117
 118         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
 119         if (ret < 0)
 120                 return ret;
 121
 122         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
 123         if (ret < 0)
 124                 return ret;
 125
 126         ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
 127                                         ATCLK_MCUISP_FREQUENCY);
 128         if (ret < 0)
 129                 return ret;
 130
 131         return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
 132                                         ATCLK_MCUISP_FREQUENCY);
 133 }
 134
 135 static int fimc_is_enable_clocks(struct fimc_is *is)
 136 {
 137         int i, ret;
 138
 139         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
 140                 if (IS_ERR(is->clocks[i]))
 141                         continue;
 142                 ret = clk_prepare_enable(is->clocks[i]);
 143                 if (ret < 0) {
 144                         dev_err(&is->pdev->dev, "clock %s enable failed\n",
 145                                 fimc_is_clocks[i]);
 146                         for (--i; i >= 0; i--)
 147                                 clk_disable(is->clocks[i]);
 148                         return ret;
 149                 }
 150                 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
 151         }
 152         return 0;
 153 }
 154
 155 static void fimc_is_disable_clocks(struct fimc_is *is)
 156 {
 157         int i;
 158
 159         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
 160                 if (!IS_ERR(is->clocks[i])) {
 161                         clk_disable_unprepare(is->clocks[i]);
 162                         pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
 163                 }
 164         }
 165 }
 166
 167 static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
 168                                                 struct device_node *node)
 169 {
 170         struct fimc_is_sensor *sensor = &is->sensor[index];
 171         struct device_node *ep, *port;
 172         u32 tmp = 0;
 173         int ret;
 174
 175         sensor->drvdata = fimc_is_sensor_get_drvdata(node);
 176         if (!sensor->drvdata) {
 177                 dev_err(&is->pdev->dev, "no driver data found for: %s\n",
 178                                                          node->full_name);
 179                 return -EINVAL;
 180         }
 181
 182         ep = of_graph_get_next_endpoint(node, NULL);
 183         if (!ep)
 184                 return -ENXIO;
 185
 186         port = of_graph_get_remote_port(ep);
 187         of_node_put(ep);
 188         if (!port)
 189                 return -ENXIO;
 190
 191         /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
 192         ret = of_property_read_u32(port, "reg", &tmp);
 193         if (ret < 0) {
 194                 dev_err(&is->pdev->dev, "reg property not found at: %s\n",
 195                                                          port->full_name);
 196                 of_node_put(port);
 197                 return ret;
 198         }
 199
 200         of_node_put(port);
 201         sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
 202         return 0;
 203 }
 204
 205 static int fimc_is_register_subdevs(struct fimc_is *is)
 206 {
 207         struct device_node *i2c_bus, *child;
 208         int ret, index = 0;
 209
 210         ret = fimc_isp_subdev_create(&is->isp);
 211         if (ret < 0)
 212                 return ret;
 213
 214         for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) {
 215                 for_each_available_child_of_node(i2c_bus, child) {
 216                         ret = fimc_is_parse_sensor_config(is, index, child);
 217
 218                         if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) {
 219                                 of_node_put(child);
 220                                 return ret;
 221                         }
 222                         index++;
 223                 }
 224         }
 225         return 0;
 226 }
 227
 228 static int fimc_is_unregister_subdevs(struct fimc_is *is)
 229 {
 230         fimc_isp_subdev_destroy(&is->isp);
 231         return 0;
 232 }
 233
 234 static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
 235 {
 236         const struct firmware *fw;
 237         void *buf;
 238         int ret;
 239
 240         ret = reject_firmware(&fw, file_name, &is->pdev->dev);
 241         if (ret < 0) {
 242                 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
 243                 return ret;
 244         }
 245         buf = is->memory.vaddr + is->setfile.base;
 246         memcpy(buf, fw->data, fw->size);
 247         fimc_is_mem_barrier();
 248         is->setfile.size = fw->size;
 249
 250         pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
 251
 252         memcpy(is->fw.setfile_info,
 253                 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
 254                 FIMC_IS_SETFILE_INFO_LEN - 1);
 255
 256         is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
 257         is->setfile.state = 1;
 258
 259         pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
 260                  is->setfile.base, fw->size);
 261
 262         release_firmware(fw);
 263         return ret;
 264 }
 265
 266 int fimc_is_cpu_set_power(struct fimc_is *is, int on)
 267 {
 268         unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
 269
 270         if (on) {
 271                 /* Disable watchdog */
 272                 mcuctl_write(0, is, REG_WDT_ISP);
 273
 274                 /* Cortex-A5 start address setting */
 275                 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
 276
 277                 /* Enable and start Cortex-A5 */
 278                 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
 279                 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
 280         } else {
 281                 /* A5 power off */
 282                 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
 283                 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
 284
 285                 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
 286                         if (timeout == 0)
 287                                 return -ETIME;
 288                         timeout--;
 289                         udelay(1);
 290                 }
 291         }
 292
 293         return 0;
 294 }
 295
 296 /* Wait until @bit of @is->state is set to @state in the interrupt handler. */
 297 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
 298                        unsigned int state, unsigned int timeout)
 299 {
 300
 301         int ret = wait_event_timeout(is->irq_queue,
 302                                      !state ^ test_bit(bit, &is->state),
 303                                      timeout);
 304         if (ret == 0) {
 305                 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
 306                 return -ETIME;
 307         }
 308         return 0;
 309 }
 310
 311 int fimc_is_start_firmware(struct fimc_is *is)
 312 {
 313         struct device *dev = &is->pdev->dev;
 314         int ret;
 315
 316         if (is->fw.f_w == NULL) {
 317                 dev_err(dev, "firmware is not loaded\n");
 318                 return -EINVAL;
 319         }
 320
 321         memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
 322         wmb();
 323
 324         ret = fimc_is_cpu_set_power(is, 1);
 325         if (ret < 0)
 326                 return ret;
 327
 328         ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
 329                                  msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
 330         if (ret < 0)
 331                 dev_err(dev, "FIMC-IS CPU power on failed\n");
 332
 333         return ret;
 334 }
 335
 336 /* Allocate working memory for the FIMC-IS CPU. */
 337 static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
 338 {
 339         struct device *dev = &is->pdev->dev;
 340
 341         is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
 342                                               &is->memory.paddr, GFP_KERNEL);
 343         if (is->memory.vaddr == NULL)
 344                 return -ENOMEM;
 345
 346         is->memory.size = FIMC_IS_CPU_MEM_SIZE;
 347         memset(is->memory.vaddr, 0, is->memory.size);
 348
 349         dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
 350
 351         if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
 352                 dev_err(dev, "invalid firmware memory alignment: %#x\n",
 353                         (u32)is->memory.paddr);
 354                 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
 355                                   is->memory.paddr);
 356                 return -EIO;
 357         }
 358
 359         is->is_p_region = (struct is_region *)(is->memory.vaddr +
 360                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
 361
 362         is->is_dma_p_region = is->memory.paddr +
 363                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
 364
 365         is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
 366                                 FIMC_IS_SHARED_REGION_OFFSET);
 367         return 0;
 368 }
 369
 370 static void fimc_is_free_cpu_memory(struct fimc_is *is)
 371 {
 372         struct device *dev = &is->pdev->dev;
 373
 374         if (is->memory.vaddr == NULL)
 375                 return;
 376
 377         dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
 378                           is->memory.paddr);
 379 }
 380
 381 static void fimc_is_load_firmware(const struct firmware *fw, void *context)
 382 {
 383         struct fimc_is *is = context;
 384         struct device *dev = &is->pdev->dev;
 385         void *buf;
 386         int ret;
 387
 388         if (fw == NULL) {
 389                 dev_err(dev, "firmware request failed\n");
 390                 return;
 391         }
 392         mutex_lock(&is->lock);
 393
 394         if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
 395                 dev_err(dev, "wrong firmware size: %zu\n", fw->size);
 396                 goto done;
 397         }
 398
 399         is->fw.size = fw->size;
 400
 401         ret = fimc_is_alloc_cpu_memory(is);
 402         if (ret < 0) {
 403                 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
 404                 goto done;
 405         }
 406
 407         memcpy(is->memory.vaddr, fw->data, fw->size);
 408         wmb();
 409
 410         /* Read firmware description. */
 411         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
 412         memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
 413         is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
 414
 415         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
 416         memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
 417         is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
 418
 419         is->fw.state = 1;
 420
 421         dev_info(dev, "loaded firmware: %s, rev. %s\n",
 422                  is->fw.info, is->fw.version);
 423         dev_dbg(dev, "FW size: %zu, paddr: %pad\n", fw->size, &is->memory.paddr);
 424
 425         is->is_shared_region->chip_id = 0xe4412;
 426         is->is_shared_region->chip_rev_no = 1;
 427
 428         fimc_is_mem_barrier();
 429
 430         /*
 431          * FIXME: The firmware is not being released for now, as it is
 432          * needed around for copying to the IS working memory every
 433          * time before the Cortex-A5 is restarted.
 434          */
 435         release_firmware(is->fw.f_w);
 436         is->fw.f_w = fw;
 437 done:
 438         mutex_unlock(&is->lock);
 439 }
 440
 441 static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
 442 {
 443         return reject_firmware_nowait(THIS_MODULE,
 444                                 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev,
 445                                 GFP_KERNEL, is, fimc_is_load_firmware);
 446 }
 447
 448 /* General IS interrupt handler */
 449 static void fimc_is_general_irq_handler(struct fimc_is *is)
 450 {
 451         is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
 452
 453         switch (is->i2h_cmd.cmd) {
 454         case IHC_GET_SENSOR_NUM:
 455                 fimc_is_hw_get_params(is, 1);
 456                 fimc_is_hw_wait_intmsr0_intmsd0(is);
 457                 fimc_is_hw_set_sensor_num(is);
 458                 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
 459                 break;
 460         case IHC_SET_FACE_MARK:
 461         case IHC_FRAME_DONE:
 462                 fimc_is_hw_get_params(is, 2);
 463                 break;
 464         case IHC_SET_SHOT_MARK:
 465         case IHC_AA_DONE:
 466         case IH_REPLY_DONE:
 467                 fimc_is_hw_get_params(is, 3);
 468                 break;
 469         case IH_REPLY_NOT_DONE:
 470                 fimc_is_hw_get_params(is, 4);
 471                 break;
 472         case IHC_NOT_READY:
 473                 break;
 474         default:
 475                 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
 476         }
 477
 478         fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
 479
 480         switch (is->i2h_cmd.cmd) {
 481         case IHC_GET_SENSOR_NUM:
 482                 fimc_is_hw_set_intgr0_gd0(is);
 483                 set_bit(IS_ST_A5_PWR_ON, &is->state);
 484                 break;
 485
 486         case IHC_SET_SHOT_MARK:
 487                 break;
 488
 489         case IHC_SET_FACE_MARK:
 490                 is->fd_header.count = is->i2h_cmd.args[0];
 491                 is->fd_header.index = is->i2h_cmd.args[1];
 492                 is->fd_header.offset = 0;
 493                 break;
 494
 495         case IHC_FRAME_DONE:
 496                 break;
 497
 498         case IHC_AA_DONE:
 499                 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
 500                          is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
 501                 break;
 502
 503         case IH_REPLY_DONE:
 504                 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
 505
 506                 switch (is->i2h_cmd.args[0]) {
 507                 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
 508                         /* Get CAC margin */
 509                         set_bit(IS_ST_CHANGE_MODE, &is->state);
 510                         is->isp.cac_margin_x = is->i2h_cmd.args[1];
 511                         is->isp.cac_margin_y = is->i2h_cmd.args[2];
 512                         pr_debug("CAC margin (x,y): (%d,%d)\n",
 513                                  is->isp.cac_margin_x, is->isp.cac_margin_y);
 514                         break;
 515
 516                 case HIC_STREAM_ON:
 517                         clear_bit(IS_ST_STREAM_OFF, &is->state);
 518                         set_bit(IS_ST_STREAM_ON, &is->state);
 519                         break;
 520
 521                 case HIC_STREAM_OFF:
 522                         clear_bit(IS_ST_STREAM_ON, &is->state);
 523                         set_bit(IS_ST_STREAM_OFF, &is->state);
 524                         break;
 525
 526                 case HIC_SET_PARAMETER:
 527                         is->config[is->config_index].p_region_index[0] = 0;
 528                         is->config[is->config_index].p_region_index[1] = 0;
 529                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
 530                         pr_debug("HIC_SET_PARAMETER\n");
 531                         break;
 532
 533                 case HIC_GET_PARAMETER:
 534                         break;
 535
 536                 case HIC_SET_TUNE:
 537                         break;
 538
 539                 case HIC_GET_STATUS:
 540                         break;
 541
 542                 case HIC_OPEN_SENSOR:
 543                         set_bit(IS_ST_OPEN_SENSOR, &is->state);
 544                         pr_debug("data lanes: %d, settle line: %d\n",
 545                                  is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
 546                         break;
 547
 548                 case HIC_CLOSE_SENSOR:
 549                         clear_bit(IS_ST_OPEN_SENSOR, &is->state);
 550                         is->sensor_index = 0;
 551                         break;
 552
 553                 case HIC_MSG_TEST:
 554                         pr_debug("config MSG level completed\n");
 555                         break;
 556
 557                 case HIC_POWER_DOWN:
 558                         clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
 559                         break;
 560
 561                 case HIC_GET_SET_FILE_ADDR:
 562                         is->setfile.base = is->i2h_cmd.args[1];
 563                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
 564                         break;
 565
 566                 case HIC_LOAD_SET_FILE:
 567                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
 568                         break;
 569                 }
 570                 break;
 571
 572         case IH_REPLY_NOT_DONE:
 573                 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
 574                        is->i2h_cmd.args[1],
 575                        fimc_is_strerr(is->i2h_cmd.args[1]));
 576
 577                 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
 578                         pr_err("IS_ERROR_TIME_OUT\n");
 579
 580                 switch (is->i2h_cmd.args[1]) {
 581                 case IS_ERROR_SET_PARAMETER:
 582                         fimc_is_mem_barrier();
 583                 }
 584
 585                 switch (is->i2h_cmd.args[0]) {
 586                 case HIC_SET_PARAMETER:
 587                         is->config[is->config_index].p_region_index[0] = 0;
 588                         is->config[is->config_index].p_region_index[1] = 0;
 589                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
 590                         break;
 591                 }
 592                 break;
 593
 594         case IHC_NOT_READY:
 595                 pr_err("IS control sequence error: Not Ready\n");
 596                 break;
 597         }
 598
 599         wake_up(&is->irq_queue);
 600 }
 601
 602 static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
 603 {
 604         struct fimc_is *is = priv;
 605         unsigned long flags;
 606         u32 status;
 607
 608         spin_lock_irqsave(&is->slock, flags);
 609         status = mcuctl_read(is, MCUCTL_REG_INTSR1);
 610
 611         if (status & (1UL << FIMC_IS_INT_GENERAL))
 612                 fimc_is_general_irq_handler(is);
 613
 614         if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
 615                 fimc_isp_irq_handler(is);
 616
 617         spin_unlock_irqrestore(&is->slock, flags);
 618         return IRQ_HANDLED;
 619 }
 620
 621 static int fimc_is_hw_open_sensor(struct fimc_is *is,
 622                                   struct fimc_is_sensor *sensor)
 623 {
 624         struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
 625
 626         fimc_is_hw_wait_intmsr0_intmsd0(is);
 627
 628         soe->self_calibration_mode = 1;
 629         soe->actuator_type = 0;
 630         soe->mipi_lane_num = 0;
 631         soe->mclk = 0;
 632         soe->mipi_speed = 0;
 633         soe->fast_open_sensor = 0;
 634         soe->i2c_sclk = 88000000;
 635
 636         fimc_is_mem_barrier();
 637
 638         /*
 639          * Some user space use cases hang up here without this
 640          * empirically chosen delay.
 641          */
 642         udelay(100);
 643
 644         mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
 645         mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
 646         mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
 647         mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
 648         mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
 649
 650         fimc_is_hw_set_intgr0_gd0(is);
 651
 652         return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
 653                                   sensor->drvdata->open_timeout);
 654 }
 655
 656
 657 int fimc_is_hw_initialize(struct fimc_is *is)
 658 {
 659         const int config_ids[] = {
 660                 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
 661                 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
 662         };
 663         struct device *dev = &is->pdev->dev;
 664         u32 prev_id;
 665         int i, ret;
 666
 667         /* Sensor initialization. Only one sensor is currently supported. */
 668         ret = fimc_is_hw_open_sensor(is, &is->sensor[0]);
 669         if (ret < 0)
 670                 return ret;
 671
 672         /* Get the setfile address. */
 673         fimc_is_hw_get_setfile_addr(is);
 674
 675         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
 676                                  FIMC_IS_CONFIG_TIMEOUT);
 677         if (ret < 0) {
 678                 dev_err(dev, "get setfile address timed out\n");
 679                 return ret;
 680         }
 681         pr_debug("setfile.base: %#x\n", is->setfile.base);
 682
 683         /* Load the setfile. */
 684         fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
 685         clear_bit(IS_ST_SETFILE_LOADED, &is->state);
 686         fimc_is_hw_load_setfile(is);
 687         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
 688                                  FIMC_IS_CONFIG_TIMEOUT);
 689         if (ret < 0) {
 690                 dev_err(dev, "loading setfile timed out\n");
 691                 return ret;
 692         }
 693
 694         pr_debug("setfile: base: %#x, size: %d\n",
 695                  is->setfile.base, is->setfile.size);
 696         pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
 697
 698         /* Check magic number. */
 699         if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
 700             FIMC_IS_MAGIC_NUMBER) {
 701                 dev_err(dev, "magic number error!\n");
 702                 return -EIO;
 703         }
 704
 705         pr_debug("shared region: %pad, parameter region: %pad\n",
 706                  &is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
 707                  &is->is_dma_p_region);
 708
 709         is->setfile.sub_index = 0;
 710
 711         /* Stream off. */
 712         fimc_is_hw_stream_off(is);
 713         ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
 714                                  FIMC_IS_CONFIG_TIMEOUT);
 715         if (ret < 0) {
 716                 dev_err(dev, "stream off timeout\n");
 717                 return ret;
 718         }
 719
 720         /* Preserve previous mode. */
 721         prev_id = is->config_index;
 722
 723         /* Set initial parameter values. */
 724         for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
 725                 is->config_index = config_ids[i];
 726                 fimc_is_set_initial_params(is);
 727                 ret = fimc_is_itf_s_param(is, true);
 728                 if (ret < 0) {
 729                         is->config_index = prev_id;
 730                         return ret;
 731                 }
 732         }
 733         is->config_index = prev_id;
 734
 735         set_bit(IS_ST_INIT_DONE, &is->state);
 736         dev_info(dev, "initialization sequence completed (%d)\n",
 737                                                 is->config_index);
 738         return 0;
 739 }
 740
 741 static int fimc_is_log_show(struct seq_file *s, void *data)
 742 {
 743         struct fimc_is *is = s->private;
 744         const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
 745
 746         if (is->memory.vaddr == NULL) {
 747                 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
 748                 return -EIO;
 749         }
 750
 751         seq_printf(s, "%s\n", buf);
 752         return 0;
 753 }
 754
 755 static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
 756 {
 757         return single_open(file, fimc_is_log_show, inode->i_private);
 758 }
 759
 760 static const struct file_operations fimc_is_debugfs_fops = {
 761         .open           = fimc_is_debugfs_open,
 762         .read           = seq_read,
 763         .llseek         = seq_lseek,
 764         .release        = single_release,
 765 };
 766
 767 static void fimc_is_debugfs_remove(struct fimc_is *is)
 768 {
 769         debugfs_remove_recursive(is->debugfs_entry);
 770         is->debugfs_entry = NULL;
 771 }
 772
 773 static int fimc_is_debugfs_create(struct fimc_is *is)
 774 {
 775         struct dentry *dentry;
 776
 777         is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
 778
 779         dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
 780                                      is, &fimc_is_debugfs_fops);
 781         if (!dentry)
 782                 fimc_is_debugfs_remove(is);
 783
 784         return is->debugfs_entry == NULL ? -EIO : 0;
 785 }
 786
 787 static int fimc_is_runtime_resume(struct device *dev);
 788 static int fimc_is_runtime_suspend(struct device *dev);
 789
 790 static int fimc_is_probe(struct platform_device *pdev)
 791 {
 792         struct device *dev = &pdev->dev;
 793         struct fimc_is *is;
 794         struct resource res;
 795         struct device_node *node;
 796         int ret;
 797
 798         is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
 799         if (!is)
 800                 return -ENOMEM;
 801
 802         is->pdev = pdev;
 803         is->isp.pdev = pdev;
 804
 805         init_waitqueue_head(&is->irq_queue);
 806         spin_lock_init(&is->slock);
 807         mutex_init(&is->lock);
 808
 809         ret = of_address_to_resource(dev->of_node, 0, &res);
 810         if (ret < 0)
 811                 return ret;
 812
 813         is->regs = devm_ioremap_resource(dev, &res);
 814         if (IS_ERR(is->regs))
 815                 return PTR_ERR(is->regs);
 816
 817         node = of_get_child_by_name(dev->of_node, "pmu");
 818         if (!node)
 819                 return -ENODEV;
 820
 821         is->pmu_regs = of_iomap(node, 0);
 822         if (!is->pmu_regs)
 823                 return -ENOMEM;
 824
 825         is->irq = irq_of_parse_and_map(dev->of_node, 0);
 826         if (!is->irq) {
 827                 dev_err(dev, "no irq found\n");
 828                 return -EINVAL;
 829         }
 830
 831         ret = fimc_is_get_clocks(is);
 832         if (ret < 0)
 833                 return ret;
 834
 835         platform_set_drvdata(pdev, is);
 836
 837         ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
 838         if (ret < 0) {
 839                 dev_err(dev, "irq request failed\n");
 840                 goto err_clk;
 841         }
 842         pm_runtime_enable(dev);
 843
 844         if (!pm_runtime_enabled(dev)) {
 845                 ret = fimc_is_runtime_resume(dev);
 846                 if (ret < 0)
 847                         goto err_irq;
 848         }
 849
 850         ret = pm_runtime_get_sync(dev);
 851         if (ret < 0)
 852                 goto err_pm;
 853
 854         vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
 855
 856         ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
 857         if (ret < 0)
 858                 goto err_pm;
 859
 860         /*
 861          * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
 862          * will be created within the subdev's registered() callback.
 863          */
 864         ret = fimc_is_register_subdevs(is);
 865         if (ret < 0)
 866                 goto err_of_dep;
 867
 868         ret = fimc_is_debugfs_create(is);
 869         if (ret < 0)
 870                 goto err_sd;
 871
 872         ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
 873         if (ret < 0)
 874                 goto err_dfs;
 875
 876         pm_runtime_put_sync(dev);
 877
 878         dev_dbg(dev, "FIMC-IS registered successfully\n");
 879         return 0;
 880
 881 err_dfs:
 882         fimc_is_debugfs_remove(is);
 883 err_sd:
 884         fimc_is_unregister_subdevs(is);
 885 err_of_dep:
 886         of_platform_depopulate(dev);
 887 err_pm:
 888         if (!pm_runtime_enabled(dev))
 889                 fimc_is_runtime_suspend(dev);
 890 err_irq:
 891         free_irq(is->irq, is);
 892 err_clk:
 893         fimc_is_put_clocks(is);
 894         return ret;
 895 }
 896
 897 static int fimc_is_runtime_resume(struct device *dev)
 898 {
 899         struct fimc_is *is = dev_get_drvdata(dev);
 900         int ret;
 901
 902         ret = fimc_is_setup_clocks(is);
 903         if (ret)
 904                 return ret;
 905
 906         return fimc_is_enable_clocks(is);
 907 }
 908
 909 static int fimc_is_runtime_suspend(struct device *dev)
 910 {
 911         struct fimc_is *is = dev_get_drvdata(dev);
 912
 913         fimc_is_disable_clocks(is);
 914         return 0;
 915 }
 916
 917 #ifdef CONFIG_PM_SLEEP
 918 static int fimc_is_resume(struct device *dev)
 919 {
 920         /* TODO: */
 921         return 0;
 922 }
 923
 924 static int fimc_is_suspend(struct device *dev)
 925 {
 926         struct fimc_is *is = dev_get_drvdata(dev);
 927
 928         /* TODO: */
 929         if (test_bit(IS_ST_A5_PWR_ON, &is->state))
 930                 return -EBUSY;
 931
 932         return 0;
 933 }
 934 #endif /* CONFIG_PM_SLEEP */
 935
 936 static int fimc_is_remove(struct platform_device *pdev)
 937 {
 938         struct device *dev = &pdev->dev;
 939         struct fimc_is *is = dev_get_drvdata(dev);
 940
 941         pm_runtime_disable(dev);
 942         pm_runtime_set_suspended(dev);
 943         if (!pm_runtime_status_suspended(dev))
 944                 fimc_is_runtime_suspend(dev);
 945         free_irq(is->irq, is);
 946         of_platform_depopulate(dev);
 947         fimc_is_unregister_subdevs(is);
 948         vb2_dma_contig_clear_max_seg_size(dev);
 949         fimc_is_put_clocks(is);
 950         fimc_is_debugfs_remove(is);
 951         release_firmware(is->fw.f_w);
 952         fimc_is_free_cpu_memory(is);
 953
 954         return 0;
 955 }
 956
 957 static const struct of_device_id fimc_is_of_match[] = {
 958         { .compatible = "samsung,exynos4212-fimc-is" },
 959         { /* sentinel */ },
 960 };
 961 MODULE_DEVICE_TABLE(of, fimc_is_of_match);
 962
 963 static const struct dev_pm_ops fimc_is_pm_ops = {
 964         SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
 965         SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
 966                            NULL)
 967 };
 968
 969 static struct platform_driver fimc_is_driver = {
 970         .probe          = fimc_is_probe,
 971         .remove         = fimc_is_remove,
 972         .driver = {
 973                 .of_match_table = fimc_is_of_match,
 974                 .name           = FIMC_IS_DRV_NAME,
 975                 .pm             = &fimc_is_pm_ops,
 976         }
 977 };
 978
 979 static int fimc_is_module_init(void)
 980 {
 981         int ret;
 982
 983         ret = fimc_is_register_i2c_driver();
 984         if (ret < 0)
 985                 return ret;
 986
 987         ret = platform_driver_register(&fimc_is_driver);
 988
 989         if (ret < 0)
 990                 fimc_is_unregister_i2c_driver();
 991
 992         return ret;
 993 }
 994
 995 static void fimc_is_module_exit(void)
 996 {
 997         fimc_is_unregister_i2c_driver();
 998         platform_driver_unregister(&fimc_is_driver);
 999 }
1000
1001 module_init(fimc_is_module_init);
1002 module_exit(fimc_is_module_exit);
1003
1004 MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
1005 MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
1006 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1007 MODULE_LICENSE("GPL v2");