2 * Copyright (c) 2016 MediaTek Inc.
3 * Author: Tiffany Lin <tiffany.lin@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/pm_runtime.h>
19 #include <soc/mediatek/smi.h>
21 #include "mtk_vcodec_dec_pm.h"
22 #include "mtk_vcodec_util.h"
25 int mtk_vcodec_init_dec_pm(struct mtk_vcodec_dev *mtkdev)
27 struct device_node *node;
28 struct platform_device *pdev;
29 struct mtk_vcodec_pm *pm;
32 pdev = mtkdev->plat_dev;
35 node = of_parse_phandle(pdev->dev.of_node, "mediatek,larb", 0);
37 mtk_v4l2_err("of_parse_phandle mediatek,larb fail!");
41 pdev = of_find_device_by_node(node);
46 pm->larbvdec = &pdev->dev;
47 pdev = mtkdev->plat_dev;
50 pm->vcodecpll = devm_clk_get(&pdev->dev, "vcodecpll");
51 if (IS_ERR(pm->vcodecpll)) {
52 mtk_v4l2_err("devm_clk_get vcodecpll fail");
53 ret = PTR_ERR(pm->vcodecpll);
56 pm->univpll_d2 = devm_clk_get(&pdev->dev, "univpll_d2");
57 if (IS_ERR(pm->univpll_d2)) {
58 mtk_v4l2_err("devm_clk_get univpll_d2 fail");
59 ret = PTR_ERR(pm->univpll_d2);
62 pm->clk_cci400_sel = devm_clk_get(&pdev->dev, "clk_cci400_sel");
63 if (IS_ERR(pm->clk_cci400_sel)) {
64 mtk_v4l2_err("devm_clk_get clk_cci400_sel fail");
65 ret = PTR_ERR(pm->clk_cci400_sel);
68 pm->vdec_sel = devm_clk_get(&pdev->dev, "vdec_sel");
69 if (IS_ERR(pm->vdec_sel)) {
70 mtk_v4l2_err("devm_clk_get vdec_sel fail");
71 ret = PTR_ERR(pm->vdec_sel);
74 pm->vdecpll = devm_clk_get(&pdev->dev, "vdecpll");
75 if (IS_ERR(pm->vdecpll)) {
76 mtk_v4l2_err("devm_clk_get vdecpll fail");
77 ret = PTR_ERR(pm->vdecpll);
80 pm->vencpll = devm_clk_get(&pdev->dev, "vencpll");
81 if (IS_ERR(pm->vencpll)) {
82 mtk_v4l2_err("devm_clk_get vencpll fail");
83 ret = PTR_ERR(pm->vencpll);
86 pm->venc_lt_sel = devm_clk_get(&pdev->dev, "venc_lt_sel");
87 if (IS_ERR(pm->venc_lt_sel)) {
88 mtk_v4l2_err("devm_clk_get venc_lt_sel fail");
89 ret = PTR_ERR(pm->venc_lt_sel);
92 pm->vdec_bus_clk_src = devm_clk_get(&pdev->dev, "vdec_bus_clk_src");
93 if (IS_ERR(pm->vdec_bus_clk_src)) {
94 mtk_v4l2_err("devm_clk_get vdec_bus_clk_src");
95 ret = PTR_ERR(pm->vdec_bus_clk_src);
98 pm_runtime_enable(&pdev->dev);
103 void mtk_vcodec_release_dec_pm(struct mtk_vcodec_dev *dev)
105 pm_runtime_disable(dev->pm.dev);
106 put_device(dev->pm.larbvdec);
109 void mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm)
113 ret = pm_runtime_get_sync(pm->dev);
115 mtk_v4l2_err("pm_runtime_get_sync fail %d", ret);
118 void mtk_vcodec_dec_pw_off(struct mtk_vcodec_pm *pm)
122 ret = pm_runtime_put_sync(pm->dev);
124 mtk_v4l2_err("pm_runtime_put_sync fail %d", ret);
127 void mtk_vcodec_dec_clock_on(struct mtk_vcodec_pm *pm)
131 ret = clk_set_rate(pm->vcodecpll, 1482 * 1000000);
133 mtk_v4l2_err("clk_set_rate vcodecpll fail %d", ret);
135 ret = clk_set_rate(pm->vencpll, 800 * 1000000);
137 mtk_v4l2_err("clk_set_rate vencpll fail %d", ret);
139 ret = clk_prepare_enable(pm->vcodecpll);
141 mtk_v4l2_err("clk_prepare_enable vcodecpll fail %d", ret);
143 ret = clk_prepare_enable(pm->vencpll);
145 mtk_v4l2_err("clk_prepare_enable vencpll fail %d", ret);
147 ret = clk_prepare_enable(pm->vdec_bus_clk_src);
149 mtk_v4l2_err("clk_prepare_enable vdec_bus_clk_src fail %d",
152 ret = clk_prepare_enable(pm->venc_lt_sel);
154 mtk_v4l2_err("clk_prepare_enable venc_lt_sel fail %d", ret);
156 ret = clk_set_parent(pm->venc_lt_sel, pm->vdec_bus_clk_src);
158 mtk_v4l2_err("clk_set_parent venc_lt_sel vdec_bus_clk_src fail %d",
161 ret = clk_prepare_enable(pm->univpll_d2);
163 mtk_v4l2_err("clk_prepare_enable univpll_d2 fail %d", ret);
165 ret = clk_prepare_enable(pm->clk_cci400_sel);
167 mtk_v4l2_err("clk_prepare_enable clk_cci400_sel fail %d", ret);
169 ret = clk_set_parent(pm->clk_cci400_sel, pm->univpll_d2);
171 mtk_v4l2_err("clk_set_parent clk_cci400_sel univpll_d2 fail %d",
174 ret = clk_prepare_enable(pm->vdecpll);
176 mtk_v4l2_err("clk_prepare_enable vdecpll fail %d", ret);
178 ret = clk_prepare_enable(pm->vdec_sel);
180 mtk_v4l2_err("clk_prepare_enable vdec_sel fail %d", ret);
182 ret = clk_set_parent(pm->vdec_sel, pm->vdecpll);
184 mtk_v4l2_err("clk_set_parent vdec_sel vdecpll fail %d", ret);
186 ret = mtk_smi_larb_get(pm->larbvdec);
188 mtk_v4l2_err("mtk_smi_larb_get larbvdec fail %d", ret);
192 void mtk_vcodec_dec_clock_off(struct mtk_vcodec_pm *pm)
194 mtk_smi_larb_put(pm->larbvdec);
195 clk_disable_unprepare(pm->vdec_sel);
196 clk_disable_unprepare(pm->vdecpll);
197 clk_disable_unprepare(pm->univpll_d2);
198 clk_disable_unprepare(pm->clk_cci400_sel);
199 clk_disable_unprepare(pm->venc_lt_sel);
200 clk_disable_unprepare(pm->vdec_bus_clk_src);
201 clk_disable_unprepare(pm->vencpll);
202 clk_disable_unprepare(pm->vcodecpll);