2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author: Jacob Chen <jacob-chen@iotwrt.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/pm_runtime.h>
20 enum e_rga_start_pos {
27 struct rga_addr_offset {
33 struct rga_corners_addr_offset {
34 struct rga_addr_offset left_top;
35 struct rga_addr_offset right_top;
36 struct rga_addr_offset left_bottom;
37 struct rga_addr_offset right_bottom;
40 static unsigned int rga_get_scaling(unsigned int src, unsigned int dst)
43 * The rga hw scaling factor is a normalized inverse of the
45 * For example: When source width is 100 and destination width is 200
46 * (scaling of 2x), then the hw factor is NC * 100 / 200.
47 * The normalization factor (NC) is 2^16 = 0x10000.
50 return (src > dst) ? ((dst << 16) / src) : ((src << 16) / dst);
53 static struct rga_corners_addr_offset
54 rga_get_addr_offset(struct rga_frame *frm, unsigned int x, unsigned int y,
55 unsigned int w, unsigned int h)
57 struct rga_corners_addr_offset offsets;
58 struct rga_addr_offset *lt, *lb, *rt, *rb;
59 unsigned int x_div = 0,
60 y_div = 0, uv_stride = 0, pixel_width = 0, uv_factor = 0;
62 lt = &offsets.left_top;
63 lb = &offsets.left_bottom;
64 rt = &offsets.right_top;
65 rb = &offsets.right_bottom;
67 x_div = frm->fmt->x_div;
68 y_div = frm->fmt->y_div;
69 uv_factor = frm->fmt->uv_factor;
70 uv_stride = frm->stride / x_div;
71 pixel_width = frm->stride / frm->width;
73 lt->y_off = y * frm->stride + x * pixel_width;
75 frm->width * frm->height + (y / y_div) * uv_stride + x / x_div;
76 lt->v_off = lt->u_off + frm->width * frm->height / uv_factor;
78 lb->y_off = lt->y_off + (h - 1) * frm->stride;
79 lb->u_off = lt->u_off + (h / y_div - 1) * uv_stride;
80 lb->v_off = lt->v_off + (h / y_div - 1) * uv_stride;
82 rt->y_off = lt->y_off + (w - 1) * pixel_width;
83 rt->u_off = lt->u_off + w / x_div - 1;
84 rt->v_off = lt->v_off + w / x_div - 1;
86 rb->y_off = lb->y_off + (w - 1) * pixel_width;
87 rb->u_off = lb->u_off + w / x_div - 1;
88 rb->v_off = lb->v_off + w / x_div - 1;
93 static struct rga_addr_offset *rga_lookup_draw_pos(struct
94 rga_corners_addr_offset
95 * offsets, u32 rotate_mode,
98 static enum e_rga_start_pos rot_mir_point_matrix[4][4] = {
116 switch (rot_mir_point_matrix[rotate_mode][mirr_mode]) {
118 return &offsets->left_top;
120 return &offsets->left_bottom;
122 return &offsets->right_top;
124 return &offsets->right_bottom;
130 static void rga_cmd_set_src_addr(struct rga_ctx *ctx, void *mmu_pages)
132 struct rockchip_rga *rga = ctx->rga;
133 u32 *dest = rga->cmdbuf_virt;
136 reg = RGA_MMU_SRC_BASE - RGA_MODE_BASE_REG;
137 dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
139 reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
140 dest[reg >> 2] |= 0x7;
143 static void rga_cmd_set_src1_addr(struct rga_ctx *ctx, void *mmu_pages)
145 struct rockchip_rga *rga = ctx->rga;
146 u32 *dest = rga->cmdbuf_virt;
149 reg = RGA_MMU_SRC1_BASE - RGA_MODE_BASE_REG;
150 dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
152 reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
153 dest[reg >> 2] |= 0x7 << 4;
156 static void rga_cmd_set_dst_addr(struct rga_ctx *ctx, void *mmu_pages)
158 struct rockchip_rga *rga = ctx->rga;
159 u32 *dest = rga->cmdbuf_virt;
162 reg = RGA_MMU_DST_BASE - RGA_MODE_BASE_REG;
163 dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
165 reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
166 dest[reg >> 2] |= 0x7 << 8;
169 static void rga_cmd_set_trans_info(struct rga_ctx *ctx)
171 struct rockchip_rga *rga = ctx->rga;
172 u32 *dest = rga->cmdbuf_virt;
173 unsigned int scale_dst_w, scale_dst_h;
174 unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y;
175 union rga_src_info src_info;
176 union rga_dst_info dst_info;
177 union rga_src_x_factor x_factor;
178 union rga_src_y_factor y_factor;
179 union rga_src_vir_info src_vir_info;
180 union rga_src_act_info src_act_info;
181 union rga_dst_vir_info dst_vir_info;
182 union rga_dst_act_info dst_act_info;
184 struct rga_addr_offset *dst_offset;
185 struct rga_corners_addr_offset offsets;
186 struct rga_corners_addr_offset src_offsets;
188 src_h = ctx->in.crop.height;
189 src_w = ctx->in.crop.width;
190 src_x = ctx->in.crop.left;
191 src_y = ctx->in.crop.top;
192 dst_h = ctx->out.crop.height;
193 dst_w = ctx->out.crop.width;
194 dst_x = ctx->out.crop.left;
195 dst_y = ctx->out.crop.top;
197 src_info.val = dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2];
198 dst_info.val = dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2];
199 x_factor.val = dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2];
200 y_factor.val = dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2];
201 src_vir_info.val = dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
202 src_act_info.val = dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
203 dst_vir_info.val = dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
204 dst_act_info.val = dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
206 src_info.data.format = ctx->in.fmt->hw_format;
207 src_info.data.swap = ctx->in.fmt->color_swap;
208 dst_info.data.format = ctx->out.fmt->hw_format;
209 dst_info.data.swap = ctx->out.fmt->color_swap;
212 * CSC mode must only be set when the colorspace families differ between
213 * input and output. It must remain unset (zeroed) if both are the same.
216 if (RGA_COLOR_FMT_IS_YUV(ctx->in.fmt->hw_format) &&
217 RGA_COLOR_FMT_IS_RGB(ctx->out.fmt->hw_format)) {
218 switch (ctx->in.colorspace) {
219 case V4L2_COLORSPACE_REC709:
220 src_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
223 src_info.data.csc_mode = RGA_SRC_CSC_MODE_BT601_R0;
228 if (RGA_COLOR_FMT_IS_RGB(ctx->in.fmt->hw_format) &&
229 RGA_COLOR_FMT_IS_YUV(ctx->out.fmt->hw_format)) {
230 switch (ctx->out.colorspace) {
231 case V4L2_COLORSPACE_REC709:
232 dst_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
235 dst_info.data.csc_mode = RGA_DST_CSC_MODE_BT601_R0;
241 src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_X;
244 src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_Y;
246 switch (ctx->rotate) {
248 src_info.data.rot_mode = RGA_SRC_ROT_MODE_90_DEGREE;
251 src_info.data.rot_mode = RGA_SRC_ROT_MODE_180_DEGREE;
254 src_info.data.rot_mode = RGA_SRC_ROT_MODE_270_DEGREE;
257 src_info.data.rot_mode = RGA_SRC_ROT_MODE_0_DEGREE;
262 * Cacluate the up/down scaling mode/factor.
264 * RGA used to scale the picture first, and then rotate second,
265 * so we need to swap the w/h when rotate degree is 90/270.
267 if (src_info.data.rot_mode == RGA_SRC_ROT_MODE_90_DEGREE ||
268 src_info.data.rot_mode == RGA_SRC_ROT_MODE_270_DEGREE) {
269 if (rga->version.major == 0 || rga->version.minor == 0) {
272 if (abs(src_w - dst_h) < 16)
283 if (src_w == scale_dst_w) {
284 src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_NO;
286 } else if (src_w > scale_dst_w) {
287 src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_DOWN;
288 x_factor.data.down_scale_factor =
289 rga_get_scaling(src_w, scale_dst_w) + 1;
291 src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_UP;
292 x_factor.data.up_scale_factor =
293 rga_get_scaling(src_w - 1, scale_dst_w - 1);
296 if (src_h == scale_dst_h) {
297 src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_NO;
299 } else if (src_h > scale_dst_h) {
300 src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_DOWN;
301 y_factor.data.down_scale_factor =
302 rga_get_scaling(src_h, scale_dst_h) + 1;
304 src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_UP;
305 y_factor.data.up_scale_factor =
306 rga_get_scaling(src_h - 1, scale_dst_h - 1);
310 * Cacluate the framebuffer virtual strides and active size,
311 * note that the step of vir_stride / vir_width is 4 byte words
313 src_vir_info.data.vir_stride = ctx->in.stride >> 2;
314 src_vir_info.data.vir_width = ctx->in.stride >> 2;
316 src_act_info.data.act_height = src_h - 1;
317 src_act_info.data.act_width = src_w - 1;
319 dst_vir_info.data.vir_stride = ctx->out.stride >> 2;
320 dst_act_info.data.act_height = dst_h - 1;
321 dst_act_info.data.act_width = dst_w - 1;
324 * Cacluate the source framebuffer base address with offset pixel.
326 src_offsets = rga_get_addr_offset(&ctx->in, src_x, src_y,
330 * Configure the dest framebuffer base address with pixel offset.
332 offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y, dst_w, dst_h);
333 dst_offset = rga_lookup_draw_pos(&offsets, src_info.data.rot_mode,
334 src_info.data.mir_mode);
336 dest[(RGA_SRC_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
337 src_offsets.left_top.y_off;
338 dest[(RGA_SRC_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
339 src_offsets.left_top.u_off;
340 dest[(RGA_SRC_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
341 src_offsets.left_top.v_off;
343 dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2] = x_factor.val;
344 dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2] = y_factor.val;
345 dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = src_vir_info.val;
346 dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = src_act_info.val;
348 dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2] = src_info.val;
350 dest[(RGA_DST_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
352 dest[(RGA_DST_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
354 dest[(RGA_DST_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
357 dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = dst_vir_info.val;
358 dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = dst_act_info.val;
360 dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2] = dst_info.val;
363 static void rga_cmd_set_mode(struct rga_ctx *ctx)
365 struct rockchip_rga *rga = ctx->rga;
366 u32 *dest = rga->cmdbuf_virt;
367 union rga_mode_ctrl mode;
368 union rga_alpha_ctrl0 alpha_ctrl0;
369 union rga_alpha_ctrl1 alpha_ctrl1;
375 mode.data.gradient_sat = 1;
376 mode.data.render = RGA_MODE_RENDER_BITBLT;
377 mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
379 /* disable alpha blending */
380 dest[(RGA_ALPHA_CTRL0 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl0.val;
381 dest[(RGA_ALPHA_CTRL1 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl1.val;
383 dest[(RGA_MODE_CTRL - RGA_MODE_BASE_REG) >> 2] = mode.val;
386 static void rga_cmd_set(struct rga_ctx *ctx)
388 struct rockchip_rga *rga = ctx->rga;
390 memset(rga->cmdbuf_virt, 0, RGA_CMDBUF_SIZE * 4);
392 rga_cmd_set_src_addr(ctx, rga->src_mmu_pages);
394 * Due to hardware bug,
395 * src1 mmu also should be configured when using alpha blending.
397 rga_cmd_set_src1_addr(ctx, rga->dst_mmu_pages);
399 rga_cmd_set_dst_addr(ctx, rga->dst_mmu_pages);
400 rga_cmd_set_mode(ctx);
402 rga_cmd_set_trans_info(ctx);
404 rga_write(rga, RGA_CMD_BASE, rga->cmdbuf_phy);
406 /* sync CMD buf for RGA */
407 dma_sync_single_for_device(rga->dev, rga->cmdbuf_phy,
408 PAGE_SIZE, DMA_BIDIRECTIONAL);
411 void rga_hw_start(struct rockchip_rga *rga)
413 struct rga_ctx *ctx = rga->curr;
417 rga_write(rga, RGA_SYS_CTRL, 0x00);
419 rga_write(rga, RGA_SYS_CTRL, 0x22);
421 rga_write(rga, RGA_INT, 0x600);
423 rga_write(rga, RGA_CMD_CTRL, 0x1);