2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author: Jacob Chen <jacob-chen@iotwrt.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #define RGA_CMDBUF_SIZE 0x20
20 #define MAX_WIDTH 8192
21 #define MAX_HEIGHT 8192
26 #define DEFAULT_WIDTH 100
27 #define DEFAULT_HEIGHT 100
29 #define RGA_TIMEOUT 500
31 /* Registers address */
32 #define RGA_SYS_CTRL 0x0000
33 #define RGA_CMD_CTRL 0x0004
34 #define RGA_CMD_BASE 0x0008
35 #define RGA_INT 0x0010
36 #define RGA_MMU_CTRL0 0x0014
37 #define RGA_VERSION_INFO 0x0028
39 #define RGA_MODE_BASE_REG 0x0100
40 #define RGA_MODE_MAX_REG 0x017C
42 #define RGA_MODE_CTRL 0x0100
43 #define RGA_SRC_INFO 0x0104
44 #define RGA_SRC_Y_RGB_BASE_ADDR 0x0108
45 #define RGA_SRC_CB_BASE_ADDR 0x010c
46 #define RGA_SRC_CR_BASE_ADDR 0x0110
47 #define RGA_SRC1_RGB_BASE_ADDR 0x0114
48 #define RGA_SRC_VIR_INFO 0x0118
49 #define RGA_SRC_ACT_INFO 0x011c
50 #define RGA_SRC_X_FACTOR 0x0120
51 #define RGA_SRC_Y_FACTOR 0x0124
52 #define RGA_SRC_BG_COLOR 0x0128
53 #define RGA_SRC_FG_COLOR 0x012c
54 #define RGA_SRC_TR_COLOR0 0x0130
55 #define RGA_SRC_TR_COLOR1 0x0134
57 #define RGA_DST_INFO 0x0138
58 #define RGA_DST_Y_RGB_BASE_ADDR 0x013c
59 #define RGA_DST_CB_BASE_ADDR 0x0140
60 #define RGA_DST_CR_BASE_ADDR 0x0144
61 #define RGA_DST_VIR_INFO 0x0148
62 #define RGA_DST_ACT_INFO 0x014c
64 #define RGA_ALPHA_CTRL0 0x0150
65 #define RGA_ALPHA_CTRL1 0x0154
66 #define RGA_FADING_CTRL 0x0158
67 #define RGA_PAT_CON 0x015c
68 #define RGA_ROP_CON0 0x0160
69 #define RGA_ROP_CON1 0x0164
70 #define RGA_MASK_BASE 0x0168
72 #define RGA_MMU_CTRL1 0x016C
73 #define RGA_MMU_SRC_BASE 0x0170
74 #define RGA_MMU_SRC1_BASE 0x0174
75 #define RGA_MMU_DST_BASE 0x0178
78 #define RGA_MODE_RENDER_BITBLT 0
79 #define RGA_MODE_RENDER_COLOR_PALETTE 1
80 #define RGA_MODE_RENDER_RECTANGLE_FILL 2
81 #define RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM 3
83 #define RGA_MODE_BITBLT_MODE_SRC_TO_DST 0
84 #define RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST 1
86 #define RGA_MODE_CF_ROP4_SOLID 0
87 #define RGA_MODE_CF_ROP4_PATTERN 1
89 #define RGA_COLOR_FMT_ABGR8888 0
90 #define RGA_COLOR_FMT_XBGR8888 1
91 #define RGA_COLOR_FMT_RGB888 2
92 #define RGA_COLOR_FMT_BGR565 4
93 #define RGA_COLOR_FMT_ABGR1555 5
94 #define RGA_COLOR_FMT_ABGR4444 6
95 #define RGA_COLOR_FMT_YUV422SP 8
96 #define RGA_COLOR_FMT_YUV422P 9
97 #define RGA_COLOR_FMT_YUV420SP 10
98 #define RGA_COLOR_FMT_YUV420P 11
99 /* SRC_COLOR Palette */
100 #define RGA_COLOR_FMT_CP_1BPP 12
101 #define RGA_COLOR_FMT_CP_2BPP 13
102 #define RGA_COLOR_FMT_CP_4BPP 14
103 #define RGA_COLOR_FMT_CP_8BPP 15
104 #define RGA_COLOR_FMT_MASK 15
106 #define RGA_COLOR_FMT_IS_YUV(fmt) \
107 (((fmt) >= RGA_COLOR_FMT_YUV422SP) && ((fmt) < RGA_COLOR_FMT_CP_1BPP))
108 #define RGA_COLOR_FMT_IS_RGB(fmt) \
109 ((fmt) < RGA_COLOR_FMT_YUV422SP)
111 #define RGA_COLOR_NONE_SWAP 0
112 #define RGA_COLOR_RB_SWAP 1
113 #define RGA_COLOR_ALPHA_SWAP 2
114 #define RGA_COLOR_UV_SWAP 4
116 #define RGA_SRC_CSC_MODE_BYPASS 0
117 #define RGA_SRC_CSC_MODE_BT601_R0 1
118 #define RGA_SRC_CSC_MODE_BT601_R1 2
119 #define RGA_SRC_CSC_MODE_BT709_R0 3
120 #define RGA_SRC_CSC_MODE_BT709_R1 4
122 #define RGA_SRC_ROT_MODE_0_DEGREE 0
123 #define RGA_SRC_ROT_MODE_90_DEGREE 1
124 #define RGA_SRC_ROT_MODE_180_DEGREE 2
125 #define RGA_SRC_ROT_MODE_270_DEGREE 3
127 #define RGA_SRC_MIRR_MODE_NO 0
128 #define RGA_SRC_MIRR_MODE_X 1
129 #define RGA_SRC_MIRR_MODE_Y 2
130 #define RGA_SRC_MIRR_MODE_X_Y 3
132 #define RGA_SRC_HSCL_MODE_NO 0
133 #define RGA_SRC_HSCL_MODE_DOWN 1
134 #define RGA_SRC_HSCL_MODE_UP 2
136 #define RGA_SRC_VSCL_MODE_NO 0
137 #define RGA_SRC_VSCL_MODE_DOWN 1
138 #define RGA_SRC_VSCL_MODE_UP 2
140 #define RGA_SRC_TRANS_ENABLE_R 1
141 #define RGA_SRC_TRANS_ENABLE_G 2
142 #define RGA_SRC_TRANS_ENABLE_B 4
143 #define RGA_SRC_TRANS_ENABLE_A 8
145 #define RGA_SRC_BIC_COE_SELEC_CATROM 0
146 #define RGA_SRC_BIC_COE_SELEC_MITCHELL 1
147 #define RGA_SRC_BIC_COE_SELEC_HERMITE 2
148 #define RGA_SRC_BIC_COE_SELEC_BSPLINE 3
150 #define RGA_DST_DITHER_MODE_888_TO_666 0
151 #define RGA_DST_DITHER_MODE_888_TO_565 1
152 #define RGA_DST_DITHER_MODE_888_TO_555 2
153 #define RGA_DST_DITHER_MODE_888_TO_444 3
155 #define RGA_DST_CSC_MODE_BYPASS 0
156 #define RGA_DST_CSC_MODE_BT601_R0 1
157 #define RGA_DST_CSC_MODE_BT601_R1 2
158 #define RGA_DST_CSC_MODE_BT709_R0 3
160 #define RGA_ALPHA_ROP_MODE_2 0
161 #define RGA_ALPHA_ROP_MODE_3 1
162 #define RGA_ALPHA_ROP_MODE_4 2
164 #define RGA_ALPHA_SELECT_ALPHA 0
165 #define RGA_ALPHA_SELECT_ROP 1
167 #define RGA_ALPHA_MASK_BIG_ENDIAN 0
168 #define RGA_ALPHA_MASK_LITTLE_ENDIAN 1
170 #define RGA_ALPHA_NORMAL 0
171 #define RGA_ALPHA_REVERSE 1
173 #define RGA_ALPHA_BLEND_GLOBAL 0
174 #define RGA_ALPHA_BLEND_NORMAL 1
175 #define RGA_ALPHA_BLEND_MULTIPLY 2
177 #define RGA_ALPHA_CAL_CUT 0
178 #define RGA_ALPHA_CAL_NORMAL 1
180 #define RGA_ALPHA_FACTOR_ZERO 0
181 #define RGA_ALPHA_FACTOR_ONE 1
182 #define RGA_ALPHA_FACTOR_OTHER 2
183 #define RGA_ALPHA_FACTOR_OTHER_REVERSE 3
184 #define RGA_ALPHA_FACTOR_SELF 4
186 #define RGA_ALPHA_COLOR_NORMAL 0
187 #define RGA_ALPHA_COLOR_MULTIPLY_CAL 1
189 /* Registers union */
190 union rga_mode_ctrl {
194 unsigned int render:3;
196 unsigned int bitblt:1;
197 unsigned int cf_rop4_pat:1;
198 unsigned int alpha_zero_key:1;
199 unsigned int gradient_sat:1;
201 unsigned int reserved:25;
209 unsigned int format:4;
212 unsigned int cp_endian:1;
214 unsigned int csc_mode:2;
215 unsigned int rot_mode:2;
216 unsigned int mir_mode:2;
217 unsigned int hscl_mode:2;
218 unsigned int vscl_mode:2;
220 unsigned int trans_mode:1;
221 unsigned int trans_enable:4;
223 unsigned int dither_up_en:1;
224 unsigned int bic_coe_sel:2;
226 unsigned int reserved:6;
230 union rga_src_vir_info {
234 unsigned int vir_width:15;
235 unsigned int reserved:1;
237 unsigned int vir_stride:10;
239 unsigned int reserved1:6;
243 union rga_src_act_info {
247 unsigned int act_width:13;
248 unsigned int reserved:3;
250 unsigned int act_height:13;
251 unsigned int reserved1:3;
255 union rga_src_x_factor {
259 unsigned int down_scale_factor:16;
261 unsigned int up_scale_factor:16;
265 union rga_src_y_factor {
269 unsigned int down_scale_factor:16;
271 unsigned int up_scale_factor:16;
275 /* Alpha / Red / Green / Blue */
276 union rga_src_cp_gr_color {
280 unsigned int gradient_x:16;
282 unsigned int gradient_y:16;
286 union rga_src_transparency_color0 {
290 unsigned int trans_rmin:8;
292 unsigned int trans_gmin:8;
294 unsigned int trans_bmin:8;
296 unsigned int trans_amin:8;
300 union rga_src_transparency_color1 {
304 unsigned int trans_rmax:8;
306 unsigned int trans_gmax:8;
308 unsigned int trans_bmax:8;
310 unsigned int trans_amax:8;
318 unsigned int format:4;
322 unsigned int src1_format:3;
324 unsigned int src1_swap:2;
326 unsigned int dither_up_en:1;
327 unsigned int dither_down_en:1;
328 unsigned int dither_down_mode:2;
330 unsigned int csc_mode:2;
331 unsigned int csc_clip:1;
333 unsigned int reserved:13;
337 union rga_dst_vir_info {
341 unsigned int vir_stride:15;
342 unsigned int reserved:1;
344 unsigned int src1_vir_stride:15;
345 unsigned int reserved1:1;
349 union rga_dst_act_info {
353 unsigned int act_width:12;
354 unsigned int reserved:4;
356 unsigned int act_height:12;
357 unsigned int reserved1:4;
361 union rga_alpha_ctrl0 {
365 unsigned int rop_en:1;
366 unsigned int rop_select:1;
367 unsigned int rop_mode:2;
369 unsigned int src_fading_val:8;
371 unsigned int dst_fading_val:8;
372 unsigned int mask_endian:1;
374 unsigned int reserved:11;
378 union rga_alpha_ctrl1 {
382 unsigned int dst_color_m0:1;
383 unsigned int src_color_m0:1;
385 unsigned int dst_factor_m0:3;
386 unsigned int src_factor_m0:3;
388 unsigned int dst_alpha_cal_m0:1;
389 unsigned int src_alpha_cal_m0:1;
391 unsigned int dst_blend_m0:2;
392 unsigned int src_blend_m0:2;
394 unsigned int dst_alpha_m0:1;
395 unsigned int src_alpha_m0:1;
397 unsigned int dst_factor_m1:3;
398 unsigned int src_factor_m1:3;
400 unsigned int dst_alpha_cal_m1:1;
401 unsigned int src_alpha_cal_m1:1;
403 unsigned int dst_blend_m1:2;
404 unsigned int src_blend_m1:2;
406 unsigned int dst_alpha_m1:1;
407 unsigned int src_alpha_m1:1;
409 unsigned int reserved:2;
413 union rga_fading_ctrl {
417 unsigned int fading_offset_r:8;
419 unsigned int fading_offset_g:8;
421 unsigned int fading_offset_b:8;
423 unsigned int fading_en:1;
424 unsigned int reserved:7;
432 unsigned int width:8;
434 unsigned int height:8;
436 unsigned int offset_x:8;
438 unsigned int offset_y:8;