2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author: Jacob Chen <jacob-chen@iotwrt.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/reset.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 #include <linux/timer.h>
28 #include <linux/platform_device.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-event.h>
31 #include <media/v4l2-ioctl.h>
32 #include <media/v4l2-mem2mem.h>
33 #include <media/videobuf2-dma-sg.h>
34 #include <media/videobuf2-v4l2.h>
40 module_param(debug, int, 0644);
42 static void device_run(void *prv)
44 struct rga_ctx *ctx = prv;
45 struct rockchip_rga *rga = ctx->rga;
46 struct vb2_v4l2_buffer *src, *dst;
49 spin_lock_irqsave(&rga->ctrl_lock, flags);
53 src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
54 dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
56 rga_buf_map(&src->vb2_buf);
57 rga_buf_map(&dst->vb2_buf);
61 spin_unlock_irqrestore(&rga->ctrl_lock, flags);
64 static irqreturn_t rga_isr(int irq, void *prv)
66 struct rockchip_rga *rga = prv;
69 intr = rga_read(rga, RGA_INT) & 0xf;
71 rga_mod(rga, RGA_INT, intr << 4, 0xf << 4);
74 struct vb2_v4l2_buffer *src, *dst;
75 struct rga_ctx *ctx = rga->curr;
81 src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
82 dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
87 dst->timecode = src->timecode;
88 dst->vb2_buf.timestamp = src->vb2_buf.timestamp;
89 dst->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
90 dst->flags |= src->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
92 v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
93 v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
94 v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx);
100 static struct v4l2_m2m_ops rga_m2m_ops = {
101 .device_run = device_run,
105 queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
107 struct rga_ctx *ctx = priv;
110 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
111 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
112 src_vq->drv_priv = ctx;
113 src_vq->ops = &rga_qops;
114 src_vq->mem_ops = &vb2_dma_sg_memops;
115 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
116 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
117 src_vq->lock = &ctx->rga->mutex;
118 src_vq->dev = ctx->rga->v4l2_dev.dev;
120 ret = vb2_queue_init(src_vq);
124 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
125 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
126 dst_vq->drv_priv = ctx;
127 dst_vq->ops = &rga_qops;
128 dst_vq->mem_ops = &vb2_dma_sg_memops;
129 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
130 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
131 dst_vq->lock = &ctx->rga->mutex;
132 dst_vq->dev = ctx->rga->v4l2_dev.dev;
134 return vb2_queue_init(dst_vq);
137 static int rga_s_ctrl(struct v4l2_ctrl *ctrl)
139 struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx,
143 spin_lock_irqsave(&ctx->rga->ctrl_lock, flags);
146 ctx->hflip = ctrl->val;
149 ctx->vflip = ctrl->val;
151 case V4L2_CID_ROTATE:
152 ctx->rotate = ctrl->val;
154 case V4L2_CID_BG_COLOR:
155 ctx->fill_color = ctrl->val;
158 spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags);
162 static const struct v4l2_ctrl_ops rga_ctrl_ops = {
163 .s_ctrl = rga_s_ctrl,
166 static int rga_setup_ctrls(struct rga_ctx *ctx)
168 struct rockchip_rga *rga = ctx->rga;
170 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
172 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
173 V4L2_CID_HFLIP, 0, 1, 1, 0);
175 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
176 V4L2_CID_VFLIP, 0, 1, 1, 0);
178 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
179 V4L2_CID_ROTATE, 0, 270, 90, 0);
181 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
182 V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0);
184 if (ctx->ctrl_handler.error) {
185 int err = ctx->ctrl_handler.error;
187 v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__);
188 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
195 static struct rga_fmt formats[] = {
197 .fourcc = V4L2_PIX_FMT_ARGB32,
198 .color_swap = RGA_COLOR_RB_SWAP,
199 .hw_format = RGA_COLOR_FMT_ABGR8888,
206 .fourcc = V4L2_PIX_FMT_XRGB32,
207 .color_swap = RGA_COLOR_RB_SWAP,
208 .hw_format = RGA_COLOR_FMT_XBGR8888,
215 .fourcc = V4L2_PIX_FMT_ABGR32,
216 .color_swap = RGA_COLOR_ALPHA_SWAP,
217 .hw_format = RGA_COLOR_FMT_ABGR8888,
224 .fourcc = V4L2_PIX_FMT_XBGR32,
225 .color_swap = RGA_COLOR_ALPHA_SWAP,
226 .hw_format = RGA_COLOR_FMT_XBGR8888,
233 .fourcc = V4L2_PIX_FMT_RGB24,
234 .color_swap = RGA_COLOR_NONE_SWAP,
235 .hw_format = RGA_COLOR_FMT_RGB888,
242 .fourcc = V4L2_PIX_FMT_BGR24,
243 .color_swap = RGA_COLOR_RB_SWAP,
244 .hw_format = RGA_COLOR_FMT_RGB888,
251 .fourcc = V4L2_PIX_FMT_ARGB444,
252 .color_swap = RGA_COLOR_RB_SWAP,
253 .hw_format = RGA_COLOR_FMT_ABGR4444,
260 .fourcc = V4L2_PIX_FMT_ARGB555,
261 .color_swap = RGA_COLOR_RB_SWAP,
262 .hw_format = RGA_COLOR_FMT_ABGR1555,
269 .fourcc = V4L2_PIX_FMT_RGB565,
270 .color_swap = RGA_COLOR_RB_SWAP,
271 .hw_format = RGA_COLOR_FMT_BGR565,
278 .fourcc = V4L2_PIX_FMT_NV21,
279 .color_swap = RGA_COLOR_UV_SWAP,
280 .hw_format = RGA_COLOR_FMT_YUV420SP,
287 .fourcc = V4L2_PIX_FMT_NV61,
288 .color_swap = RGA_COLOR_UV_SWAP,
289 .hw_format = RGA_COLOR_FMT_YUV422SP,
296 .fourcc = V4L2_PIX_FMT_NV12,
297 .color_swap = RGA_COLOR_NONE_SWAP,
298 .hw_format = RGA_COLOR_FMT_YUV420SP,
305 .fourcc = V4L2_PIX_FMT_NV16,
306 .color_swap = RGA_COLOR_NONE_SWAP,
307 .hw_format = RGA_COLOR_FMT_YUV422SP,
314 .fourcc = V4L2_PIX_FMT_YUV420,
315 .color_swap = RGA_COLOR_NONE_SWAP,
316 .hw_format = RGA_COLOR_FMT_YUV420P,
323 .fourcc = V4L2_PIX_FMT_YUV422P,
324 .color_swap = RGA_COLOR_NONE_SWAP,
325 .hw_format = RGA_COLOR_FMT_YUV422P,
332 .fourcc = V4L2_PIX_FMT_YVU420,
333 .color_swap = RGA_COLOR_UV_SWAP,
334 .hw_format = RGA_COLOR_FMT_YUV420P,
342 #define NUM_FORMATS ARRAY_SIZE(formats)
344 static struct rga_fmt *rga_fmt_find(struct v4l2_format *f)
348 for (i = 0; i < NUM_FORMATS; i++) {
349 if (formats[i].fourcc == f->fmt.pix.pixelformat)
355 static struct rga_frame def_frame = {
356 .width = DEFAULT_WIDTH,
357 .height = DEFAULT_HEIGHT,
358 .colorspace = V4L2_COLORSPACE_DEFAULT,
361 .crop.width = DEFAULT_WIDTH,
362 .crop.height = DEFAULT_HEIGHT,
366 struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type)
369 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
371 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
374 return ERR_PTR(-EINVAL);
378 static int rga_open(struct file *file)
380 struct rockchip_rga *rga = video_drvdata(file);
381 struct rga_ctx *ctx = NULL;
384 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
388 /* Set default formats */
390 ctx->out = def_frame;
392 if (mutex_lock_interruptible(&rga->mutex)) {
396 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init);
397 if (IS_ERR(ctx->fh.m2m_ctx)) {
398 ret = PTR_ERR(ctx->fh.m2m_ctx);
399 mutex_unlock(&rga->mutex);
403 v4l2_fh_init(&ctx->fh, video_devdata(file));
404 file->private_data = &ctx->fh;
405 v4l2_fh_add(&ctx->fh);
407 rga_setup_ctrls(ctx);
409 /* Write the default values to the ctx struct */
410 v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
412 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
413 mutex_unlock(&rga->mutex);
418 static int rga_release(struct file *file)
420 struct rga_ctx *ctx =
421 container_of(file->private_data, struct rga_ctx, fh);
422 struct rockchip_rga *rga = ctx->rga;
424 mutex_lock(&rga->mutex);
426 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
428 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
429 v4l2_fh_del(&ctx->fh);
430 v4l2_fh_exit(&ctx->fh);
433 mutex_unlock(&rga->mutex);
438 static const struct v4l2_file_operations rga_fops = {
439 .owner = THIS_MODULE,
441 .release = rga_release,
442 .poll = v4l2_m2m_fop_poll,
443 .unlocked_ioctl = video_ioctl2,
444 .mmap = v4l2_m2m_fop_mmap,
448 vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
450 strlcpy(cap->driver, RGA_NAME, sizeof(cap->driver));
451 strlcpy(cap->card, "rockchip-rga", sizeof(cap->card));
452 strlcpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info));
457 static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)
461 if (f->index >= NUM_FORMATS)
464 fmt = &formats[f->index];
465 f->pixelformat = fmt->fourcc;
470 static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
472 struct rga_ctx *ctx = prv;
473 struct vb2_queue *vq;
474 struct rga_frame *frm;
476 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
479 frm = rga_get_frame(ctx, f->type);
483 f->fmt.pix.width = frm->width;
484 f->fmt.pix.height = frm->height;
485 f->fmt.pix.field = V4L2_FIELD_NONE;
486 f->fmt.pix.pixelformat = frm->fmt->fourcc;
487 f->fmt.pix.bytesperline = frm->stride;
488 f->fmt.pix.sizeimage = frm->size;
489 f->fmt.pix.colorspace = frm->colorspace;
494 static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
498 fmt = rga_fmt_find(f);
501 f->fmt.pix.pixelformat = fmt->fourcc;
504 f->fmt.pix.field = V4L2_FIELD_NONE;
506 if (f->fmt.pix.width > MAX_WIDTH)
507 f->fmt.pix.width = MAX_WIDTH;
508 if (f->fmt.pix.height > MAX_HEIGHT)
509 f->fmt.pix.height = MAX_HEIGHT;
511 if (f->fmt.pix.width < MIN_WIDTH)
512 f->fmt.pix.width = MIN_WIDTH;
513 if (f->fmt.pix.height < MIN_HEIGHT)
514 f->fmt.pix.height = MIN_HEIGHT;
516 if (fmt->hw_format >= RGA_COLOR_FMT_YUV422SP)
517 f->fmt.pix.bytesperline = f->fmt.pix.width;
519 f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
521 f->fmt.pix.sizeimage =
522 f->fmt.pix.height * (f->fmt.pix.width * fmt->depth) >> 3;
527 static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
529 struct rga_ctx *ctx = prv;
530 struct rockchip_rga *rga = ctx->rga;
531 struct vb2_queue *vq;
532 struct rga_frame *frm;
536 /* Adjust all values accordingly to the hardware capabilities
539 ret = vidioc_try_fmt(file, prv, f);
542 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
543 if (vb2_is_busy(vq)) {
544 v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type);
547 frm = rga_get_frame(ctx, f->type);
550 fmt = rga_fmt_find(f);
553 frm->width = f->fmt.pix.width;
554 frm->height = f->fmt.pix.height;
555 frm->size = f->fmt.pix.sizeimage;
557 frm->stride = f->fmt.pix.bytesperline;
558 frm->colorspace = f->fmt.pix.colorspace;
560 /* Reset crop settings */
563 frm->crop.width = frm->width;
564 frm->crop.height = frm->height;
569 static int vidioc_g_selection(struct file *file, void *prv,
570 struct v4l2_selection *s)
572 struct rga_ctx *ctx = prv;
574 bool use_frame = false;
576 f = rga_get_frame(ctx, s->type);
581 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
582 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
583 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
586 case V4L2_SEL_TGT_CROP_DEFAULT:
587 case V4L2_SEL_TGT_CROP_BOUNDS:
588 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
591 case V4L2_SEL_TGT_COMPOSE:
592 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
596 case V4L2_SEL_TGT_CROP:
597 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
610 s->r.width = f->width;
611 s->r.height = f->height;
617 static int vidioc_s_selection(struct file *file, void *prv,
618 struct v4l2_selection *s)
620 struct rga_ctx *ctx = prv;
621 struct rockchip_rga *rga = ctx->rga;
625 f = rga_get_frame(ctx, s->type);
630 case V4L2_SEL_TGT_COMPOSE:
632 * COMPOSE target is only valid for capture buffer type, return
633 * error for output buffer type
635 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
638 case V4L2_SEL_TGT_CROP:
640 * CROP target is only valid for output buffer type, return
641 * error for capture buffer type
643 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
647 * bound and default crop/compose targets are invalid targets to
654 if (s->r.top < 0 || s->r.left < 0) {
655 v4l2_dbg(debug, 1, &rga->v4l2_dev,
656 "doesn't support negative values for top & left.\n");
660 if (s->r.left + s->r.width > f->width ||
661 s->r.top + s->r.height > f->height ||
662 s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
663 v4l2_dbg(debug, 1, &rga->v4l2_dev, "unsupported crop value.\n");
672 static const struct v4l2_ioctl_ops rga_ioctl_ops = {
673 .vidioc_querycap = vidioc_querycap,
675 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
676 .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
677 .vidioc_try_fmt_vid_cap = vidioc_try_fmt,
678 .vidioc_s_fmt_vid_cap = vidioc_s_fmt,
680 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
681 .vidioc_g_fmt_vid_out = vidioc_g_fmt,
682 .vidioc_try_fmt_vid_out = vidioc_try_fmt,
683 .vidioc_s_fmt_vid_out = vidioc_s_fmt,
685 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
686 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
687 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
688 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
689 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
690 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
691 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
693 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
694 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
696 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
697 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
699 .vidioc_g_selection = vidioc_g_selection,
700 .vidioc_s_selection = vidioc_s_selection,
703 static struct video_device rga_videodev = {
704 .name = "rockchip-rga",
706 .ioctl_ops = &rga_ioctl_ops,
708 .release = video_device_release,
709 .vfl_dir = VFL_DIR_M2M,
710 .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
713 static int rga_enable_clocks(struct rockchip_rga *rga)
717 ret = clk_prepare_enable(rga->sclk);
719 dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
723 ret = clk_prepare_enable(rga->aclk);
725 dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret);
726 goto err_disable_sclk;
729 ret = clk_prepare_enable(rga->hclk);
731 dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret);
732 goto err_disable_aclk;
738 clk_disable_unprepare(rga->sclk);
740 clk_disable_unprepare(rga->aclk);
745 static void rga_disable_clocks(struct rockchip_rga *rga)
747 clk_disable_unprepare(rga->sclk);
748 clk_disable_unprepare(rga->hclk);
749 clk_disable_unprepare(rga->aclk);
752 static int rga_parse_dt(struct rockchip_rga *rga)
754 struct reset_control *core_rst, *axi_rst, *ahb_rst;
756 core_rst = devm_reset_control_get(rga->dev, "core");
757 if (IS_ERR(core_rst)) {
758 dev_err(rga->dev, "failed to get core reset controller\n");
759 return PTR_ERR(core_rst);
762 axi_rst = devm_reset_control_get(rga->dev, "axi");
763 if (IS_ERR(axi_rst)) {
764 dev_err(rga->dev, "failed to get axi reset controller\n");
765 return PTR_ERR(axi_rst);
768 ahb_rst = devm_reset_control_get(rga->dev, "ahb");
769 if (IS_ERR(ahb_rst)) {
770 dev_err(rga->dev, "failed to get ahb reset controller\n");
771 return PTR_ERR(ahb_rst);
774 reset_control_assert(core_rst);
776 reset_control_deassert(core_rst);
778 reset_control_assert(axi_rst);
780 reset_control_deassert(axi_rst);
782 reset_control_assert(ahb_rst);
784 reset_control_deassert(ahb_rst);
786 rga->sclk = devm_clk_get(rga->dev, "sclk");
787 if (IS_ERR(rga->sclk)) {
788 dev_err(rga->dev, "failed to get sclk clock\n");
789 return PTR_ERR(rga->sclk);
792 rga->aclk = devm_clk_get(rga->dev, "aclk");
793 if (IS_ERR(rga->aclk)) {
794 dev_err(rga->dev, "failed to get aclk clock\n");
795 return PTR_ERR(rga->aclk);
798 rga->hclk = devm_clk_get(rga->dev, "hclk");
799 if (IS_ERR(rga->hclk)) {
800 dev_err(rga->dev, "failed to get hclk clock\n");
801 return PTR_ERR(rga->hclk);
807 static int rga_probe(struct platform_device *pdev)
809 struct rockchip_rga *rga;
810 struct video_device *vfd;
811 struct resource *res;
815 if (!pdev->dev.of_node)
818 rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL);
822 rga->dev = &pdev->dev;
823 spin_lock_init(&rga->ctrl_lock);
824 mutex_init(&rga->mutex);
826 ret = rga_parse_dt(rga);
828 dev_err(&pdev->dev, "Unable to parse OF data\n");
830 pm_runtime_enable(rga->dev);
832 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
834 rga->regs = devm_ioremap_resource(rga->dev, res);
835 if (IS_ERR(rga->regs)) {
836 ret = PTR_ERR(rga->regs);
840 irq = platform_get_irq(pdev, 0);
842 dev_err(rga->dev, "failed to get irq\n");
847 ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
848 dev_name(rga->dev), rga);
850 dev_err(rga->dev, "failed to request irq\n");
854 ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev);
857 vfd = video_device_alloc();
859 v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n");
864 vfd->lock = &rga->mutex;
865 vfd->v4l2_dev = &rga->v4l2_dev;
867 video_set_drvdata(vfd, rga);
870 platform_set_drvdata(pdev, rga);
871 rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops);
872 if (IS_ERR(rga->m2m_dev)) {
873 v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n");
874 ret = PTR_ERR(rga->m2m_dev);
875 goto unreg_video_dev;
878 pm_runtime_get_sync(rga->dev);
880 rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF;
881 rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F;
883 v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n",
884 rga->version.major, rga->version.minor);
886 pm_runtime_put(rga->dev);
888 /* Create CMD buffer */
889 rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE,
890 &rga->cmdbuf_phy, GFP_KERNEL,
891 DMA_ATTR_WRITE_COMBINE);
894 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
896 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
898 def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
899 def_frame.size = def_frame.stride * def_frame.height;
901 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
903 v4l2_err(&rga->v4l2_dev, "Failed to register video device\n");
907 v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n",
908 vfd->name, video_device_node_name(vfd));
913 video_device_release(vfd);
915 video_unregister_device(rga->vfd);
917 v4l2_device_unregister(&rga->v4l2_dev);
919 pm_runtime_disable(rga->dev);
924 static int rga_remove(struct platform_device *pdev)
926 struct rockchip_rga *rga = platform_get_drvdata(pdev);
928 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt,
929 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
931 free_pages((unsigned long)rga->src_mmu_pages, 3);
932 free_pages((unsigned long)rga->dst_mmu_pages, 3);
934 v4l2_info(&rga->v4l2_dev, "Removing\n");
936 v4l2_m2m_release(rga->m2m_dev);
937 video_unregister_device(rga->vfd);
938 v4l2_device_unregister(&rga->v4l2_dev);
940 pm_runtime_disable(rga->dev);
945 static int __maybe_unused rga_runtime_suspend(struct device *dev)
947 struct rockchip_rga *rga = dev_get_drvdata(dev);
949 rga_disable_clocks(rga);
954 static int __maybe_unused rga_runtime_resume(struct device *dev)
956 struct rockchip_rga *rga = dev_get_drvdata(dev);
958 return rga_enable_clocks(rga);
961 static const struct dev_pm_ops rga_pm = {
962 SET_RUNTIME_PM_OPS(rga_runtime_suspend,
963 rga_runtime_resume, NULL)
966 static const struct of_device_id rockchip_rga_match[] = {
968 .compatible = "rockchip,rk3288-rga",
971 .compatible = "rockchip,rk3399-rga",
976 MODULE_DEVICE_TABLE(of, rockchip_rga_match);
978 static struct platform_driver rga_pdrv = {
980 .remove = rga_remove,
984 .of_match_table = rockchip_rga_match,
988 module_platform_driver(rga_pdrv);
990 MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>");
991 MODULE_DESCRIPTION("Rockchip Raster 2d Graphic Acceleration Unit");
992 MODULE_LICENSE("GPL");