drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c

   1 /*
   2  * c8sectpfe-core.c - C8SECTPFE STi DVB driver
   3  *
   4  * Copyright (c) STMicroelectronics 2015
   5  *
   6  *   Author:Peter Bennett <peter.bennett@st.com>
   7  *          Peter Griffin <peter.griffin@linaro.org>
   8  *
   9  *      This program is free software; you can redistribute it and/or
  10  *      modify it under the terms of the GNU General Public License as
  11  *      published by the Free Software Foundation; either version 2 of
  12  *      the License, or (at your option) any later version.
  13  */
  14 #include <linux/atomic.h>
  15 #include <linux/clk.h>
  16 #include <linux/completion.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/dvb/dmx.h>
  21 #include <linux/dvb/frontend.h>
  22 #include <linux/errno.h>
  23 #include <linux/firmware.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/of_gpio.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/usb.h>
  32 #include <linux/slab.h>
  33 #include <linux/time.h>
  34 #include <linux/version.h>
  35 #include <linux/wait.h>
  36 #include <linux/pinctrl/pinctrl.h>
  37
  38 #include "c8sectpfe-core.h"
  39 #include "c8sectpfe-common.h"
  40 #include "c8sectpfe-debugfs.h"
  41 #include "dmxdev.h"
  42 #include "dvb_demux.h"
  43 #include "dvb_frontend.h"
  44 #include "dvb_net.h"
  45
  46 #define FIRMWARE_MEMDMA "/*(DEBLOBBED)*/"
  47 /*(DEBLOBBED)*/
  48
  49 #define PID_TABLE_SIZE 1024
  50 #define POLL_MSECS 50
  51
  52 static int load_c8sectpfe_fw(struct c8sectpfei *fei);
  53
  54 #define TS_PKT_SIZE 188
  55 #define HEADER_SIZE (4)
  56 #define PACKET_SIZE (TS_PKT_SIZE+HEADER_SIZE)
  57
  58 #define FEI_ALIGNMENT (32)
  59 /* hw requires minimum of 8*PACKET_SIZE and padded to 8byte boundary */
  60 #define FEI_BUFFER_SIZE (8*PACKET_SIZE*340)
  61
  62 #define FIFO_LEN 1024
  63
  64 static void c8sectpfe_timer_interrupt(unsigned long ac8sectpfei)
  65 {
  66         struct c8sectpfei *fei = (struct c8sectpfei *)ac8sectpfei;
  67         struct channel_info *channel;
  68         int chan_num;
  69
  70         /* iterate through input block channels */
  71         for (chan_num = 0; chan_num < fei->tsin_count; chan_num++) {
  72                 channel = fei->channel_data[chan_num];
  73
  74                 /* is this descriptor initialised and TP enabled */
  75                 if (channel->irec && readl(channel->irec + DMA_PRDS_TPENABLE))
  76                         tasklet_schedule(&channel->tsklet);
  77         }
  78
  79         fei->timer.expires = jiffies +  msecs_to_jiffies(POLL_MSECS);
  80         add_timer(&fei->timer);
  81 }
  82
  83 static void channel_swdemux_tsklet(unsigned long data)
  84 {
  85         struct channel_info *channel = (struct channel_info *)data;
  86         struct c8sectpfei *fei;
  87         unsigned long wp, rp;
  88         int pos, num_packets, n, size;
  89         u8 *buf;
  90
  91         if (unlikely(!channel || !channel->irec))
  92                 return;
  93
  94         fei = channel->fei;
  95
  96         wp = readl(channel->irec + DMA_PRDS_BUSWP_TP(0));
  97         rp = readl(channel->irec + DMA_PRDS_BUSRP_TP(0));
  98
  99         pos = rp - channel->back_buffer_busaddr;
 100
 101         /* has it wrapped */
 102         if (wp < rp)
 103                 wp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE;
 104
 105         size = wp - rp;
 106         num_packets = size / PACKET_SIZE;
 107
 108         /* manage cache so data is visible to CPU */
 109         dma_sync_single_for_cpu(fei->dev,
 110                                 rp,
 111                                 size,
 112                                 DMA_FROM_DEVICE);
 113
 114         buf = (u8 *) channel->back_buffer_aligned;
 115
 116         dev_dbg(fei->dev,
 117                 "chan=%d channel=%p num_packets = %d, buf = %p, pos = 0x%x\n\trp=0x%lx, wp=0x%lx\n",
 118                 channel->tsin_id, channel, num_packets, buf, pos, rp, wp);
 119
 120         for (n = 0; n < num_packets; n++) {
 121                 dvb_dmx_swfilter_packets(
 122                         &fei->c8sectpfe[0]->
 123                                 demux[channel->demux_mapping].dvb_demux,
 124                         &buf[pos], 1);
 125
 126                 pos += PACKET_SIZE;
 127         }
 128
 129         /* advance the read pointer */
 130         if (wp == (channel->back_buffer_busaddr + FEI_BUFFER_SIZE))
 131                 writel(channel->back_buffer_busaddr, channel->irec +
 132                         DMA_PRDS_BUSRP_TP(0));
 133         else
 134                 writel(wp, channel->irec + DMA_PRDS_BUSRP_TP(0));
 135 }
 136
 137 static int c8sectpfe_start_feed(struct dvb_demux_feed *dvbdmxfeed)
 138 {
 139         struct dvb_demux *demux = dvbdmxfeed->demux;
 140         struct stdemux *stdemux = (struct stdemux *)demux->priv;
 141         struct c8sectpfei *fei = stdemux->c8sectpfei;
 142         struct channel_info *channel;
 143         u32 tmp;
 144         unsigned long *bitmap;
 145         int ret;
 146
 147         switch (dvbdmxfeed->type) {
 148         case DMX_TYPE_TS:
 149                 break;
 150         case DMX_TYPE_SEC:
 151                 break;
 152         default:
 153                 dev_err(fei->dev, "%s:%d Error bailing\n"
 154                         , __func__, __LINE__);
 155                 return -EINVAL;
 156         }
 157
 158         if (dvbdmxfeed->type == DMX_TYPE_TS) {
 159                 switch (dvbdmxfeed->pes_type) {
 160                 case DMX_PES_VIDEO:
 161                 case DMX_PES_AUDIO:
 162                 case DMX_PES_TELETEXT:
 163                 case DMX_PES_PCR:
 164                 case DMX_PES_OTHER:
 165                         break;
 166                 default:
 167                         dev_err(fei->dev, "%s:%d Error bailing\n"
 168                                 , __func__, __LINE__);
 169                         return -EINVAL;
 170                 }
 171         }
 172
 173         if (!atomic_read(&fei->fw_loaded)) {
 174                 ret = load_c8sectpfe_fw(fei);
 175                 if (ret)
 176                         return ret;
 177         }
 178
 179         mutex_lock(&fei->lock);
 180
 181         channel = fei->channel_data[stdemux->tsin_index];
 182
 183         bitmap = (unsigned long *) channel->pid_buffer_aligned;
 184
 185         /* 8192 is a special PID */
 186         if (dvbdmxfeed->pid == 8192) {
 187                 tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 188                 tmp &= ~C8SECTPFE_PID_ENABLE;
 189                 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 190
 191         } else {
 192                 bitmap_set(bitmap, dvbdmxfeed->pid, 1);
 193         }
 194
 195         /* manage cache so PID bitmap is visible to HW */
 196         dma_sync_single_for_device(fei->dev,
 197                                         channel->pid_buffer_busaddr,
 198                                         PID_TABLE_SIZE,
 199                                         DMA_TO_DEVICE);
 200
 201         channel->active = 1;
 202
 203         if (fei->global_feed_count == 0) {
 204                 fei->timer.expires = jiffies +
 205                         msecs_to_jiffies(msecs_to_jiffies(POLL_MSECS));
 206
 207                 add_timer(&fei->timer);
 208         }
 209
 210         if (stdemux->running_feed_count == 0) {
 211
 212                 dev_dbg(fei->dev, "Starting channel=%p\n", channel);
 213
 214                 tasklet_init(&channel->tsklet, channel_swdemux_tsklet,
 215                              (unsigned long) channel);
 216
 217                 /* Reset the internal inputblock sram pointers */
 218                 writel(channel->fifo,
 219                         fei->io + C8SECTPFE_IB_BUFF_STRT(channel->tsin_id));
 220                 writel(channel->fifo + FIFO_LEN - 1,
 221                         fei->io + C8SECTPFE_IB_BUFF_END(channel->tsin_id));
 222
 223                 writel(channel->fifo,
 224                         fei->io + C8SECTPFE_IB_READ_PNT(channel->tsin_id));
 225                 writel(channel->fifo,
 226                         fei->io + C8SECTPFE_IB_WRT_PNT(channel->tsin_id));
 227
 228
 229                 /* reset read / write memdma ptrs for this channel */
 230                 writel(channel->back_buffer_busaddr, channel->irec +
 231                         DMA_PRDS_BUSBASE_TP(0));
 232
 233                 tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 234                 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
 235
 236                 writel(channel->back_buffer_busaddr, channel->irec +
 237                         DMA_PRDS_BUSWP_TP(0));
 238
 239                 /* Issue a reset and enable InputBlock */
 240                 writel(C8SECTPFE_SYS_ENABLE | C8SECTPFE_SYS_RESET
 241                         , fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
 242
 243                 /* and enable the tp */
 244                 writel(0x1, channel->irec + DMA_PRDS_TPENABLE);
 245
 246                 dev_dbg(fei->dev, "%s:%d Starting DMA feed on stdemux=%p\n"
 247                         , __func__, __LINE__, stdemux);
 248         }
 249
 250         stdemux->running_feed_count++;
 251         fei->global_feed_count++;
 252
 253         mutex_unlock(&fei->lock);
 254
 255         return 0;
 256 }
 257
 258 static int c8sectpfe_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
 259 {
 260
 261         struct dvb_demux *demux = dvbdmxfeed->demux;
 262         struct stdemux *stdemux = (struct stdemux *)demux->priv;
 263         struct c8sectpfei *fei = stdemux->c8sectpfei;
 264         struct channel_info *channel;
 265         int idlereq;
 266         u32 tmp;
 267         int ret;
 268         unsigned long *bitmap;
 269
 270         if (!atomic_read(&fei->fw_loaded)) {
 271                 ret = load_c8sectpfe_fw(fei);
 272                 if (ret)
 273                         return ret;
 274         }
 275
 276         mutex_lock(&fei->lock);
 277
 278         channel = fei->channel_data[stdemux->tsin_index];
 279
 280         bitmap = (unsigned long *) channel->pid_buffer_aligned;
 281
 282         if (dvbdmxfeed->pid == 8192) {
 283                 tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 284                 tmp |= C8SECTPFE_PID_ENABLE;
 285                 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 286         } else {
 287                 bitmap_clear(bitmap, dvbdmxfeed->pid, 1);
 288         }
 289
 290         /* manage cache so data is visible to HW */
 291         dma_sync_single_for_device(fei->dev,
 292                                         channel->pid_buffer_busaddr,
 293                                         PID_TABLE_SIZE,
 294                                         DMA_TO_DEVICE);
 295
 296         if (--stdemux->running_feed_count == 0) {
 297
 298                 channel = fei->channel_data[stdemux->tsin_index];
 299
 300                 /* TP re-configuration on page 168 of functional spec */
 301
 302                 /* disable IB (prevents more TS data going to memdma) */
 303                 writel(0, fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
 304
 305                 /* disable this channels descriptor */
 306                 writel(0,  channel->irec + DMA_PRDS_TPENABLE);
 307
 308                 tasklet_disable(&channel->tsklet);
 309
 310                 /* now request memdma channel goes idle */
 311                 idlereq = (1 << channel->tsin_id) | IDLEREQ;
 312                 writel(idlereq, fei->io + DMA_IDLE_REQ);
 313
 314                 /* wait for idle irq handler to signal completion */
 315                 ret = wait_for_completion_timeout(&channel->idle_completion,
 316                                                 msecs_to_jiffies(100));
 317
 318                 if (ret == 0)
 319                         dev_warn(fei->dev,
 320                                 "Timeout waiting for idle irq on tsin%d\n",
 321                                 channel->tsin_id);
 322
 323                 reinit_completion(&channel->idle_completion);
 324
 325                 /* reset read / write ptrs for this channel */
 326
 327                 writel(channel->back_buffer_busaddr,
 328                         channel->irec + DMA_PRDS_BUSBASE_TP(0));
 329
 330                 tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 331                 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
 332
 333                 writel(channel->back_buffer_busaddr,
 334                         channel->irec + DMA_PRDS_BUSWP_TP(0));
 335
 336                 dev_dbg(fei->dev,
 337                         "%s:%d stopping DMA feed on stdemux=%p channel=%d\n",
 338                         __func__, __LINE__, stdemux, channel->tsin_id);
 339
 340                 /* turn off all PIDS in the bitmap */
 341                 memset((void *)channel->pid_buffer_aligned
 342                         , 0x00, PID_TABLE_SIZE);
 343
 344                 /* manage cache so data is visible to HW */
 345                 dma_sync_single_for_device(fei->dev,
 346                                         channel->pid_buffer_busaddr,
 347                                         PID_TABLE_SIZE,
 348                                         DMA_TO_DEVICE);
 349
 350                 channel->active = 0;
 351         }
 352
 353         if (--fei->global_feed_count == 0) {
 354                 dev_dbg(fei->dev, "%s:%d global_feed_count=%d\n"
 355                         , __func__, __LINE__, fei->global_feed_count);
 356
 357                 del_timer(&fei->timer);
 358         }
 359
 360         mutex_unlock(&fei->lock);
 361
 362         return 0;
 363 }
 364
 365 static struct channel_info *find_channel(struct c8sectpfei *fei, int tsin_num)
 366 {
 367         int i;
 368
 369         for (i = 0; i < C8SECTPFE_MAX_TSIN_CHAN; i++) {
 370                 if (!fei->channel_data[i])
 371                         continue;
 372
 373                 if (fei->channel_data[i]->tsin_id == tsin_num)
 374                         return fei->channel_data[i];
 375         }
 376
 377         return NULL;
 378 }
 379
 380 static void c8sectpfe_getconfig(struct c8sectpfei *fei)
 381 {
 382         struct c8sectpfe_hw *hw = &fei->hw_stats;
 383
 384         hw->num_ib = readl(fei->io + SYS_CFG_NUM_IB);
 385         hw->num_mib = readl(fei->io + SYS_CFG_NUM_MIB);
 386         hw->num_swts = readl(fei->io + SYS_CFG_NUM_SWTS);
 387         hw->num_tsout = readl(fei->io + SYS_CFG_NUM_TSOUT);
 388         hw->num_ccsc = readl(fei->io + SYS_CFG_NUM_CCSC);
 389         hw->num_ram = readl(fei->io + SYS_CFG_NUM_RAM);
 390         hw->num_tp = readl(fei->io + SYS_CFG_NUM_TP);
 391
 392         dev_info(fei->dev, "C8SECTPFE hw supports the following:\n");
 393         dev_info(fei->dev, "Input Blocks: %d\n", hw->num_ib);
 394         dev_info(fei->dev, "Merged Input Blocks: %d\n", hw->num_mib);
 395         dev_info(fei->dev, "Software Transport Stream Inputs: %d\n"
 396                                 , hw->num_swts);
 397         dev_info(fei->dev, "Transport Stream Output: %d\n", hw->num_tsout);
 398         dev_info(fei->dev, "Cable Card Converter: %d\n", hw->num_ccsc);
 399         dev_info(fei->dev, "RAMs supported by C8SECTPFE: %d\n", hw->num_ram);
 400         dev_info(fei->dev, "Tango TPs supported by C8SECTPFE: %d\n"
 401                         , hw->num_tp);
 402 }
 403
 404 static irqreturn_t c8sectpfe_idle_irq_handler(int irq, void *priv)
 405 {
 406         struct c8sectpfei *fei = priv;
 407         struct channel_info *chan;
 408         int bit;
 409         unsigned long tmp = readl(fei->io + DMA_IDLE_REQ);
 410
 411         /* page 168 of functional spec: Clear the idle request
 412            by writing 0 to the C8SECTPFE_DMA_IDLE_REQ register. */
 413
 414         /* signal idle completion */
 415         for_each_set_bit(bit, &tmp, fei->hw_stats.num_ib) {
 416
 417                 chan = find_channel(fei, bit);
 418
 419                 if (chan)
 420                         complete(&chan->idle_completion);
 421         }
 422
 423         writel(0, fei->io + DMA_IDLE_REQ);
 424
 425         return IRQ_HANDLED;
 426 }
 427
 428
 429 static void free_input_block(struct c8sectpfei *fei, struct channel_info *tsin)
 430 {
 431         if (!fei || !tsin)
 432                 return;
 433
 434         if (tsin->back_buffer_busaddr)
 435                 if (!dma_mapping_error(fei->dev, tsin->back_buffer_busaddr))
 436                         dma_unmap_single(fei->dev, tsin->back_buffer_busaddr,
 437                                 FEI_BUFFER_SIZE, DMA_BIDIRECTIONAL);
 438
 439         kfree(tsin->back_buffer_start);
 440
 441         if (tsin->pid_buffer_busaddr)
 442                 if (!dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr))
 443                         dma_unmap_single(fei->dev, tsin->pid_buffer_busaddr,
 444                                 PID_TABLE_SIZE, DMA_BIDIRECTIONAL);
 445
 446         kfree(tsin->pid_buffer_start);
 447 }
 448
 449 #define MAX_NAME 20
 450
 451 static int configure_memdma_and_inputblock(struct c8sectpfei *fei,
 452                                 struct channel_info *tsin)
 453 {
 454         int ret;
 455         u32 tmp;
 456         char tsin_pin_name[MAX_NAME];
 457
 458         if (!fei || !tsin)
 459                 return -EINVAL;
 460
 461         dev_dbg(fei->dev, "%s:%d Configuring channel=%p tsin=%d\n"
 462                 , __func__, __LINE__, tsin, tsin->tsin_id);
 463
 464         init_completion(&tsin->idle_completion);
 465
 466         tsin->back_buffer_start = kzalloc(FEI_BUFFER_SIZE +
 467                                         FEI_ALIGNMENT, GFP_KERNEL);
 468
 469         if (!tsin->back_buffer_start) {
 470                 ret = -ENOMEM;
 471                 goto err_unmap;
 472         }
 473
 474         /* Ensure backbuffer is 32byte aligned */
 475         tsin->back_buffer_aligned = tsin->back_buffer_start
 476                 + FEI_ALIGNMENT;
 477
 478         tsin->back_buffer_aligned = (void *)
 479                 (((uintptr_t) tsin->back_buffer_aligned) & ~0x1F);
 480
 481         tsin->back_buffer_busaddr = dma_map_single(fei->dev,
 482                                         (void *)tsin->back_buffer_aligned,
 483                                         FEI_BUFFER_SIZE,
 484                                         DMA_BIDIRECTIONAL);
 485
 486         if (dma_mapping_error(fei->dev, tsin->back_buffer_busaddr)) {
 487                 dev_err(fei->dev, "failed to map back_buffer\n");
 488                 ret = -EFAULT;
 489                 goto err_unmap;
 490         }
 491
 492         /*
 493          * The pid buffer can be configured (in hw) for byte or bit
 494          * per pid. By powers of deduction we conclude stih407 family
 495          * is configured (at SoC design stage) for bit per pid.
 496          */
 497         tsin->pid_buffer_start = kzalloc(2048, GFP_KERNEL);
 498
 499         if (!tsin->pid_buffer_start) {
 500                 ret = -ENOMEM;
 501                 goto err_unmap;
 502         }
 503
 504         /*
 505          * PID buffer needs to be aligned to size of the pid table
 506          * which at bit per pid is 1024 bytes (8192 pids / 8).
 507          * PIDF_BASE register enforces this alignment when writing
 508          * the register.
 509          */
 510
 511         tsin->pid_buffer_aligned = tsin->pid_buffer_start +
 512                 PID_TABLE_SIZE;
 513
 514         tsin->pid_buffer_aligned = (void *)
 515                 (((uintptr_t) tsin->pid_buffer_aligned) & ~0x3ff);
 516
 517         tsin->pid_buffer_busaddr = dma_map_single(fei->dev,
 518                                                 tsin->pid_buffer_aligned,
 519                                                 PID_TABLE_SIZE,
 520                                                 DMA_BIDIRECTIONAL);
 521
 522         if (dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr)) {
 523                 dev_err(fei->dev, "failed to map pid_bitmap\n");
 524                 ret = -EFAULT;
 525                 goto err_unmap;
 526         }
 527
 528         /* manage cache so pid bitmap is visible to HW */
 529         dma_sync_single_for_device(fei->dev,
 530                                 tsin->pid_buffer_busaddr,
 531                                 PID_TABLE_SIZE,
 532                                 DMA_TO_DEVICE);
 533
 534         snprintf(tsin_pin_name, MAX_NAME, "tsin%d-%s", tsin->tsin_id,
 535                 (tsin->serial_not_parallel ? "serial" : "parallel"));
 536
 537         tsin->pstate = pinctrl_lookup_state(fei->pinctrl, tsin_pin_name);
 538         if (IS_ERR(tsin->pstate)) {
 539                 dev_err(fei->dev, "%s: pinctrl_lookup_state couldn't find %s state\n"
 540                         , __func__, tsin_pin_name);
 541                 ret = PTR_ERR(tsin->pstate);
 542                 goto err_unmap;
 543         }
 544
 545         ret = pinctrl_select_state(fei->pinctrl, tsin->pstate);
 546
 547         if (ret) {
 548                 dev_err(fei->dev, "%s: pinctrl_select_state failed\n"
 549                         , __func__);
 550                 goto err_unmap;
 551         }
 552
 553         /* Enable this input block */
 554         tmp = readl(fei->io + SYS_INPUT_CLKEN);
 555         tmp |= BIT(tsin->tsin_id);
 556         writel(tmp, fei->io + SYS_INPUT_CLKEN);
 557
 558         if (tsin->serial_not_parallel)
 559                 tmp |= C8SECTPFE_SERIAL_NOT_PARALLEL;
 560
 561         if (tsin->invert_ts_clk)
 562                 tmp |= C8SECTPFE_INVERT_TSCLK;
 563
 564         if (tsin->async_not_sync)
 565                 tmp |= C8SECTPFE_ASYNC_NOT_SYNC;
 566
 567         tmp |= C8SECTPFE_ALIGN_BYTE_SOP | C8SECTPFE_BYTE_ENDIANNESS_MSB;
 568
 569         writel(tmp, fei->io + C8SECTPFE_IB_IP_FMT_CFG(tsin->tsin_id));
 570
 571         writel(C8SECTPFE_SYNC(0x9) |
 572                 C8SECTPFE_DROP(0x9) |
 573                 C8SECTPFE_TOKEN(0x47),
 574                 fei->io + C8SECTPFE_IB_SYNCLCKDRP_CFG(tsin->tsin_id));
 575
 576         writel(TS_PKT_SIZE, fei->io + C8SECTPFE_IB_PKT_LEN(tsin->tsin_id));
 577
 578         /* Place the FIFO's at the end of the irec descriptors */
 579
 580         tsin->fifo = (tsin->tsin_id * FIFO_LEN);
 581
 582         writel(tsin->fifo, fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id));
 583         writel(tsin->fifo + FIFO_LEN - 1,
 584                 fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id));
 585
 586         writel(tsin->fifo, fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id));
 587         writel(tsin->fifo, fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id));
 588
 589         writel(tsin->pid_buffer_busaddr,
 590                 fei->io + PIDF_BASE(tsin->tsin_id));
 591
 592         dev_dbg(fei->dev, "chan=%d PIDF_BASE=0x%x pid_bus_addr=%pad\n",
 593                 tsin->tsin_id, readl(fei->io + PIDF_BASE(tsin->tsin_id)),
 594                 &tsin->pid_buffer_busaddr);
 595
 596         /* Configure and enable HW PID filtering */
 597
 598         /*
 599          * The PID value is created by assembling the first 8 bytes of
 600          * the TS packet into a 64-bit word in big-endian format. A
 601          * slice of that 64-bit word is taken from
 602          * (PID_OFFSET+PID_NUM_BITS-1) to PID_OFFSET.
 603          */
 604         tmp = (C8SECTPFE_PID_ENABLE | C8SECTPFE_PID_NUMBITS(13)
 605                 | C8SECTPFE_PID_OFFSET(40));
 606
 607         writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(tsin->tsin_id));
 608
 609         dev_dbg(fei->dev, "chan=%d setting wp: %d, rp: %d, buf: %d-%d\n",
 610                 tsin->tsin_id,
 611                 readl(fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id)),
 612                 readl(fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id)),
 613                 readl(fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id)),
 614                 readl(fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id)));
 615
 616         /* Get base addpress of pointer record block from DMEM */
 617         tsin->irec = fei->io + DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET +
 618                         readl(fei->io + DMA_PTRREC_BASE);
 619
 620         /* fill out pointer record data structure */
 621
 622         /* advance pointer record block to our channel */
 623         tsin->irec += (tsin->tsin_id * DMA_PRDS_SIZE);
 624
 625         writel(tsin->fifo, tsin->irec + DMA_PRDS_MEMBASE);
 626
 627         writel(tsin->fifo + FIFO_LEN - 1, tsin->irec + DMA_PRDS_MEMTOP);
 628
 629         writel((188 + 7)&~7, tsin->irec + DMA_PRDS_PKTSIZE);
 630
 631         writel(0x1, tsin->irec + DMA_PRDS_TPENABLE);
 632
 633         /* read/write pointers with physical bus address */
 634
 635         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSBASE_TP(0));
 636
 637         tmp = tsin->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 638         writel(tmp, tsin->irec + DMA_PRDS_BUSTOP_TP(0));
 639
 640         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSWP_TP(0));
 641         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSRP_TP(0));
 642
 643         /* initialize tasklet */
 644         tasklet_init(&tsin->tsklet, channel_swdemux_tsklet,
 645                 (unsigned long) tsin);
 646
 647         return 0;
 648
 649 err_unmap:
 650         free_input_block(fei, tsin);
 651         return ret;
 652 }
 653
 654 static irqreturn_t c8sectpfe_error_irq_handler(int irq, void *priv)
 655 {
 656         struct c8sectpfei *fei = priv;
 657
 658         dev_err(fei->dev, "%s: error handling not yet implemented\n"
 659                 , __func__);
 660
 661         /*
 662          * TODO FIXME we should detect some error conditions here
 663          * and ideally so something about them!
 664          */
 665
 666         return IRQ_HANDLED;
 667 }
 668
 669 static int c8sectpfe_probe(struct platform_device *pdev)
 670 {
 671         struct device *dev = &pdev->dev;
 672         struct device_node *child, *np = dev->of_node;
 673         struct c8sectpfei *fei;
 674         struct resource *res;
 675         int ret, index = 0;
 676         struct channel_info *tsin;
 677
 678         /* Allocate the c8sectpfei structure */
 679         fei = devm_kzalloc(dev, sizeof(struct c8sectpfei), GFP_KERNEL);
 680         if (!fei)
 681                 return -ENOMEM;
 682
 683         fei->dev = dev;
 684
 685         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "c8sectpfe");
 686         fei->io = devm_ioremap_resource(dev, res);
 687         if (IS_ERR(fei->io))
 688                 return PTR_ERR(fei->io);
 689
 690         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 691                                         "c8sectpfe-ram");
 692         fei->sram = devm_ioremap_resource(dev, res);
 693         if (IS_ERR(fei->sram))
 694                 return PTR_ERR(fei->sram);
 695
 696         fei->sram_size = res->end - res->start;
 697
 698         fei->idle_irq = platform_get_irq_byname(pdev, "c8sectpfe-idle-irq");
 699         if (fei->idle_irq < 0) {
 700                 dev_err(dev, "Can't get c8sectpfe-idle-irq\n");
 701                 return fei->idle_irq;
 702         }
 703
 704         fei->error_irq = platform_get_irq_byname(pdev, "c8sectpfe-error-irq");
 705         if (fei->error_irq < 0) {
 706                 dev_err(dev, "Can't get c8sectpfe-error-irq\n");
 707                 return fei->error_irq;
 708         }
 709
 710         platform_set_drvdata(pdev, fei);
 711
 712         fei->c8sectpfeclk = devm_clk_get(dev, "c8sectpfe");
 713         if (IS_ERR(fei->c8sectpfeclk)) {
 714                 dev_err(dev, "c8sectpfe clk not found\n");
 715                 return PTR_ERR(fei->c8sectpfeclk);
 716         }
 717
 718         ret = clk_prepare_enable(fei->c8sectpfeclk);
 719         if (ret) {
 720                 dev_err(dev, "Failed to enable c8sectpfe clock\n");
 721                 return ret;
 722         }
 723
 724         /* to save power disable all IP's (on by default) */
 725         writel(0, fei->io + SYS_INPUT_CLKEN);
 726
 727         /* Enable memdma clock */
 728         writel(MEMDMAENABLE, fei->io + SYS_OTHER_CLKEN);
 729
 730         /* clear internal sram */
 731         memset_io(fei->sram, 0x0, fei->sram_size);
 732
 733         c8sectpfe_getconfig(fei);
 734
 735         ret = devm_request_irq(dev, fei->idle_irq, c8sectpfe_idle_irq_handler,
 736                         0, "c8sectpfe-idle-irq", fei);
 737         if (ret) {
 738                 dev_err(dev, "Can't register c8sectpfe-idle-irq IRQ.\n");
 739                 goto err_clk_disable;
 740         }
 741
 742         ret = devm_request_irq(dev, fei->error_irq,
 743                                 c8sectpfe_error_irq_handler, 0,
 744                                 "c8sectpfe-error-irq", fei);
 745         if (ret) {
 746                 dev_err(dev, "Can't register c8sectpfe-error-irq IRQ.\n");
 747                 goto err_clk_disable;
 748         }
 749
 750         fei->tsin_count = of_get_child_count(np);
 751
 752         if (fei->tsin_count > C8SECTPFE_MAX_TSIN_CHAN ||
 753                 fei->tsin_count > fei->hw_stats.num_ib) {
 754
 755                 dev_err(dev, "More tsin declared than exist on SoC!\n");
 756                 ret = -EINVAL;
 757                 goto err_clk_disable;
 758         }
 759
 760         fei->pinctrl = devm_pinctrl_get(dev);
 761
 762         if (IS_ERR(fei->pinctrl)) {
 763                 dev_err(dev, "Error getting tsin pins\n");
 764                 ret = PTR_ERR(fei->pinctrl);
 765                 goto err_clk_disable;
 766         }
 767
 768         for_each_child_of_node(np, child) {
 769                 struct device_node *i2c_bus;
 770
 771                 fei->channel_data[index] = devm_kzalloc(dev,
 772                                                 sizeof(struct channel_info),
 773                                                 GFP_KERNEL);
 774
 775                 if (!fei->channel_data[index]) {
 776                         ret = -ENOMEM;
 777                         goto err_clk_disable;
 778                 }
 779
 780                 tsin = fei->channel_data[index];
 781
 782                 tsin->fei = fei;
 783
 784                 ret = of_property_read_u32(child, "tsin-num", &tsin->tsin_id);
 785                 if (ret) {
 786                         dev_err(&pdev->dev, "No tsin_num found\n");
 787                         goto err_clk_disable;
 788                 }
 789
 790                 /* sanity check value */
 791                 if (tsin->tsin_id > fei->hw_stats.num_ib) {
 792                         dev_err(&pdev->dev,
 793                                 "tsin-num %d specified greater than number\n\tof input block hw in SoC! (%d)",
 794                                 tsin->tsin_id, fei->hw_stats.num_ib);
 795                         ret = -EINVAL;
 796                         goto err_clk_disable;
 797                 }
 798
 799                 tsin->invert_ts_clk = of_property_read_bool(child,
 800                                                         "invert-ts-clk");
 801
 802                 tsin->serial_not_parallel = of_property_read_bool(child,
 803                                                         "serial-not-parallel");
 804
 805                 tsin->async_not_sync = of_property_read_bool(child,
 806                                                         "async-not-sync");
 807
 808                 ret = of_property_read_u32(child, "dvb-card",
 809                                         &tsin->dvb_card);
 810                 if (ret) {
 811                         dev_err(&pdev->dev, "No dvb-card found\n");
 812                         goto err_clk_disable;
 813                 }
 814
 815                 i2c_bus = of_parse_phandle(child, "i2c-bus", 0);
 816                 if (!i2c_bus) {
 817                         dev_err(&pdev->dev, "No i2c-bus found\n");
 818                         ret = -ENODEV;
 819                         goto err_clk_disable;
 820                 }
 821                 tsin->i2c_adapter =
 822                         of_find_i2c_adapter_by_node(i2c_bus);
 823                 if (!tsin->i2c_adapter) {
 824                         dev_err(&pdev->dev, "No i2c adapter found\n");
 825                         of_node_put(i2c_bus);
 826                         ret = -ENODEV;
 827                         goto err_clk_disable;
 828                 }
 829                 of_node_put(i2c_bus);
 830
 831                 tsin->rst_gpio = of_get_named_gpio(child, "reset-gpios", 0);
 832
 833                 ret = gpio_is_valid(tsin->rst_gpio);
 834                 if (!ret) {
 835                         dev_err(dev,
 836                                 "reset gpio for tsin%d not valid (gpio=%d)\n",
 837                                 tsin->tsin_id, tsin->rst_gpio);
 838                         goto err_clk_disable;
 839                 }
 840
 841                 ret = devm_gpio_request_one(dev, tsin->rst_gpio,
 842                                         GPIOF_OUT_INIT_LOW, "NIM reset");
 843                 if (ret && ret != -EBUSY) {
 844                         dev_err(dev, "Can't request tsin%d reset gpio\n"
 845                                 , fei->channel_data[index]->tsin_id);
 846                         goto err_clk_disable;
 847                 }
 848
 849                 if (!ret) {
 850                         /* toggle reset lines */
 851                         gpio_direction_output(tsin->rst_gpio, 0);
 852                         usleep_range(3500, 5000);
 853                         gpio_direction_output(tsin->rst_gpio, 1);
 854                         usleep_range(3000, 5000);
 855                 }
 856
 857                 tsin->demux_mapping = index;
 858
 859                 dev_dbg(fei->dev,
 860                         "channel=%p n=%d tsin_num=%d, invert-ts-clk=%d\n\tserial-not-parallel=%d pkt-clk-valid=%d dvb-card=%d\n",
 861                         fei->channel_data[index], index,
 862                         tsin->tsin_id, tsin->invert_ts_clk,
 863                         tsin->serial_not_parallel, tsin->async_not_sync,
 864                         tsin->dvb_card);
 865
 866                 index++;
 867         }
 868
 869         /* Setup timer interrupt */
 870         setup_timer(&fei->timer, c8sectpfe_timer_interrupt,
 871                     (unsigned long)fei);
 872
 873         mutex_init(&fei->lock);
 874
 875         /* Get the configuration information about the tuners */
 876         ret = c8sectpfe_tuner_register_frontend(&fei->c8sectpfe[0],
 877                                         (void *)fei,
 878                                         c8sectpfe_start_feed,
 879                                         c8sectpfe_stop_feed);
 880         if (ret) {
 881                 dev_err(dev, "c8sectpfe_tuner_register_frontend failed (%d)\n",
 882                         ret);
 883                 goto err_clk_disable;
 884         }
 885
 886         c8sectpfe_debugfs_init(fei);
 887
 888         return 0;
 889
 890 err_clk_disable:
 891         clk_disable_unprepare(fei->c8sectpfeclk);
 892         return ret;
 893 }
 894
 895 static int c8sectpfe_remove(struct platform_device *pdev)
 896 {
 897         struct c8sectpfei *fei = platform_get_drvdata(pdev);
 898         struct channel_info *channel;
 899         int i;
 900
 901         wait_for_completion(&fei->fw_ack);
 902
 903         c8sectpfe_tuner_unregister_frontend(fei->c8sectpfe[0], fei);
 904
 905         /*
 906          * Now loop through and un-configure each of the InputBlock resources
 907          */
 908         for (i = 0; i < fei->tsin_count; i++) {
 909                 channel = fei->channel_data[i];
 910                 free_input_block(fei, channel);
 911         }
 912
 913         c8sectpfe_debugfs_exit(fei);
 914
 915         dev_info(fei->dev, "Stopping memdma SLIM core\n");
 916         if (readl(fei->io + DMA_CPU_RUN))
 917                 writel(0x0,  fei->io + DMA_CPU_RUN);
 918
 919         /* unclock all internal IP's */
 920         if (readl(fei->io + SYS_INPUT_CLKEN))
 921                 writel(0, fei->io + SYS_INPUT_CLKEN);
 922
 923         if (readl(fei->io + SYS_OTHER_CLKEN))
 924                 writel(0, fei->io + SYS_OTHER_CLKEN);
 925
 926         if (fei->c8sectpfeclk)
 927                 clk_disable_unprepare(fei->c8sectpfeclk);
 928
 929         return 0;
 930 }
 931
 932
 933 static int configure_channels(struct c8sectpfei *fei)
 934 {
 935         int index = 0, ret;
 936         struct channel_info *tsin;
 937         struct device_node *child, *np = fei->dev->of_node;
 938
 939         /* iterate round each tsin and configure memdma descriptor and IB hw */
 940         for_each_child_of_node(np, child) {
 941
 942                 tsin = fei->channel_data[index];
 943
 944                 ret = configure_memdma_and_inputblock(fei,
 945                                                 fei->channel_data[index]);
 946
 947                 if (ret) {
 948                         dev_err(fei->dev,
 949                                 "configure_memdma_and_inputblock failed\n");
 950                         goto err_unmap;
 951                 }
 952                 index++;
 953         }
 954
 955         return 0;
 956
 957 err_unmap:
 958         for (index = 0; index < fei->tsin_count; index++) {
 959                 tsin = fei->channel_data[index];
 960                 free_input_block(fei, tsin);
 961         }
 962         return ret;
 963 }
 964
 965 static int
 966 c8sectpfe_elf_sanity_check(struct c8sectpfei *fei, const struct firmware *fw)
 967 {
 968         struct elf32_hdr *ehdr;
 969         char class;
 970
 971         if (!fw) {
 972                 dev_err(fei->dev, "failed to load %s\n", FIRMWARE_MEMDMA);
 973                 return -EINVAL;
 974         }
 975
 976         if (fw->size < sizeof(struct elf32_hdr)) {
 977                 dev_err(fei->dev, "Image is too small\n");
 978                 return -EINVAL;
 979         }
 980
 981         ehdr = (struct elf32_hdr *)fw->data;
 982
 983         /* We only support ELF32 at this point */
 984         class = ehdr->e_ident[EI_CLASS];
 985         if (class != ELFCLASS32) {
 986                 dev_err(fei->dev, "Unsupported class: %d\n", class);
 987                 return -EINVAL;
 988         }
 989
 990         if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) {
 991                 dev_err(fei->dev, "Unsupported firmware endianness\n");
 992                 return -EINVAL;
 993         }
 994
 995         if (fw->size < ehdr->e_shoff + sizeof(struct elf32_shdr)) {
 996                 dev_err(fei->dev, "Image is too small\n");
 997                 return -EINVAL;
 998         }
 999
1000         if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) {
1001                 dev_err(fei->dev, "Image is corrupted (bad magic)\n");
1002                 return -EINVAL;
1003         }
1004
1005         /* Check ELF magic */
1006         ehdr = (Elf32_Ehdr *)fw->data;
1007         if (ehdr->e_ident[EI_MAG0] != ELFMAG0 ||
1008             ehdr->e_ident[EI_MAG1] != ELFMAG1 ||
1009             ehdr->e_ident[EI_MAG2] != ELFMAG2 ||
1010             ehdr->e_ident[EI_MAG3] != ELFMAG3) {
1011                 dev_err(fei->dev, "Invalid ELF magic\n");
1012                 return -EINVAL;
1013         }
1014
1015         if (ehdr->e_type != ET_EXEC) {
1016                 dev_err(fei->dev, "Unsupported ELF header type\n");
1017                 return -EINVAL;
1018         }
1019
1020         if (ehdr->e_phoff > fw->size) {
1021                 dev_err(fei->dev, "Firmware size is too small\n");
1022                 return -EINVAL;
1023         }
1024
1025         return 0;
1026 }
1027
1028
1029 static void load_imem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr,
1030                         const struct firmware *fw, u8 __iomem *dest,
1031                         int seg_num)
1032 {
1033         const u8 *imem_src = fw->data + phdr->p_offset;
1034         int i;
1035
1036         /*
1037          * For IMEM segments, the segment contains 24-bit
1038          * instructions which must be padded to 32-bit
1039          * instructions before being written. The written
1040          * segment is padded with NOP instructions.
1041          */
1042
1043         dev_dbg(fei->dev,
1044                 "Loading IMEM segment %d 0x%08x\n\t (0x%x bytes) -> 0x%p (0x%x bytes)\n",
1045 seg_num,
1046                 phdr->p_paddr, phdr->p_filesz,
1047                 dest, phdr->p_memsz + phdr->p_memsz / 3);
1048
1049         for (i = 0; i < phdr->p_filesz; i++) {
1050
1051                 writeb(readb((void __iomem *)imem_src), (void __iomem *)dest);
1052
1053                 /* Every 3 bytes, add an additional
1054                  * padding zero in destination */
1055                 if (i % 3 == 2) {
1056                         dest++;
1057                         writeb(0x00, (void __iomem *)dest);
1058                 }
1059
1060                 dest++;
1061                 imem_src++;
1062         }
1063 }
1064
1065 static void load_dmem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr,
1066                         const struct firmware *fw, u8 __iomem *dst, int seg_num)
1067 {
1068         /*
1069          * For DMEM segments copy the segment data from the ELF
1070          * file and pad segment with zeroes
1071          */
1072
1073         dev_dbg(fei->dev,
1074                 "Loading DMEM segment %d 0x%08x\n\t(0x%x bytes) -> 0x%p (0x%x bytes)\n",
1075                 seg_num, phdr->p_paddr, phdr->p_filesz,
1076                 dst, phdr->p_memsz);
1077
1078         memcpy((void __force *)dst, (void *)fw->data + phdr->p_offset,
1079                 phdr->p_filesz);
1080
1081         memset((void __force *)dst + phdr->p_filesz, 0,
1082                 phdr->p_memsz - phdr->p_filesz);
1083 }
1084
1085 static int load_slim_core_fw(const struct firmware *fw, struct c8sectpfei *fei)
1086 {
1087         Elf32_Ehdr *ehdr;
1088         Elf32_Phdr *phdr;
1089         u8 __iomem *dst;
1090         int err = 0, i;
1091
1092         if (!fw || !fei)
1093                 return -EINVAL;
1094
1095         ehdr = (Elf32_Ehdr *)fw->data;
1096         phdr = (Elf32_Phdr *)(fw->data + ehdr->e_phoff);
1097
1098         /* go through the available ELF segments */
1099         for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
1100
1101                 /* Only consider LOAD segments */
1102                 if (phdr->p_type != PT_LOAD)
1103                         continue;
1104
1105                 /*
1106                  * Check segment is contained within the fw->data buffer
1107                  */
1108                 if (phdr->p_offset + phdr->p_filesz > fw->size) {
1109                         dev_err(fei->dev,
1110                                 "Segment %d is outside of firmware file\n", i);
1111                         err = -EINVAL;
1112                         break;
1113                 }
1114
1115                 /*
1116                  * MEMDMA IMEM has executable flag set, otherwise load
1117                  * this segment into DMEM.
1118                  *
1119                  */
1120
1121                 if (phdr->p_flags & PF_X) {
1122                         dst = (u8 __iomem *) fei->io + DMA_MEMDMA_IMEM;
1123                         /*
1124                          * The Slim ELF file uses 32-bit word addressing for
1125                          * load offsets.
1126                          */
1127                         dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int);
1128                         load_imem_segment(fei, phdr, fw, dst, i);
1129                 } else {
1130                         dst = (u8 __iomem *) fei->io + DMA_MEMDMA_DMEM;
1131                         /*
1132                          * The Slim ELF file uses 32-bit word addressing for
1133                          * load offsets.
1134                          */
1135                         dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int);
1136                         load_dmem_segment(fei, phdr, fw, dst, i);
1137                 }
1138         }
1139
1140         release_firmware(fw);
1141         return err;
1142 }
1143
1144 static int load_c8sectpfe_fw(struct c8sectpfei *fei)
1145 {
1146         const struct firmware *fw;
1147         int err;
1148
1149         dev_info(fei->dev, "Loading firmware: %s\n", FIRMWARE_MEMDMA);
1150
1151         err = reject_firmware(&fw, FIRMWARE_MEMDMA, fei->dev);
1152         if (err)
1153                 return err;
1154
1155         err = c8sectpfe_elf_sanity_check(fei, fw);
1156         if (err) {
1157                 dev_err(fei->dev, "c8sectpfe_elf_sanity_check failed err=(%d)\n"
1158                         , err);
1159                 release_firmware(fw);
1160                 return err;
1161         }
1162
1163         err = load_slim_core_fw(fw, fei);
1164         if (err) {
1165                 dev_err(fei->dev, "load_slim_core_fw failed err=(%d)\n", err);
1166                 return err;
1167         }
1168
1169         /* now the firmware is loaded configure the input blocks */
1170         err = configure_channels(fei);
1171         if (err) {
1172                 dev_err(fei->dev, "configure_channels failed err=(%d)\n", err);
1173                 return err;
1174         }
1175
1176         /*
1177          * STBus target port can access IMEM and DMEM ports
1178          * without waiting for CPU
1179          */
1180         writel(0x1, fei->io + DMA_PER_STBUS_SYNC);
1181
1182         dev_info(fei->dev, "Boot the memdma SLIM core\n");
1183         writel(0x1,  fei->io + DMA_CPU_RUN);
1184
1185         atomic_set(&fei->fw_loaded, 1);
1186
1187         return 0;
1188 }
1189
1190 static const struct of_device_id c8sectpfe_match[] = {
1191         { .compatible = "st,stih407-c8sectpfe" },
1192         { /* sentinel */ },
1193 };
1194 MODULE_DEVICE_TABLE(of, c8sectpfe_match);
1195
1196 static struct platform_driver c8sectpfe_driver = {
1197         .driver = {
1198                 .name = "c8sectpfe",
1199                 .of_match_table = of_match_ptr(c8sectpfe_match),
1200         },
1201         .probe  = c8sectpfe_probe,
1202         .remove = c8sectpfe_remove,
1203 };
1204
1205 module_platform_driver(c8sectpfe_driver);
1206
1207 MODULE_AUTHOR("Peter Bennett <peter.bennett@st.com>");
1208 MODULE_AUTHOR("Peter Griffin <peter.griffin@linaro.org>");
1209 MODULE_DESCRIPTION("C8SECTPFE STi DVB Driver");
1210 MODULE_LICENSE("GPL");