drivers/mfd/intel_soc_pmic_bxtwc.c

   1 /*
   2  * MFD core driver for Intel Broxton Whiskey Cove PMIC
   3  *
   4  * Copyright (C) 2015 Intel Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/acpi.h>
  18 #include <linux/err.h>
  19 #include <linux/delay.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/kernel.h>
  22 #include <linux/mfd/core.h>
  23 #include <linux/mfd/intel_soc_pmic.h>
  24 #include <linux/mfd/intel_soc_pmic_bxtwc.h>
  25 #include <asm/intel_pmc_ipc.h>
  26
  27 /* PMIC device registers */
  28 #define REG_ADDR_MASK           0xFF00
  29 #define REG_ADDR_SHIFT          8
  30 #define REG_OFFSET_MASK         0xFF
  31
  32 /* Interrupt Status Registers */
  33 #define BXTWC_IRQLVL1           0x4E02
  34
  35 #define BXTWC_PWRBTNIRQ         0x4E03
  36 #define BXTWC_THRM0IRQ          0x4E04
  37 #define BXTWC_THRM1IRQ          0x4E05
  38 #define BXTWC_THRM2IRQ          0x4E06
  39 #define BXTWC_BCUIRQ            0x4E07
  40 #define BXTWC_ADCIRQ            0x4E08
  41 #define BXTWC_CHGR0IRQ          0x4E09
  42 #define BXTWC_CHGR1IRQ          0x4E0A
  43 #define BXTWC_GPIOIRQ0          0x4E0B
  44 #define BXTWC_GPIOIRQ1          0x4E0C
  45 #define BXTWC_CRITIRQ           0x4E0D
  46 #define BXTWC_TMUIRQ            0x4FB6
  47
  48 /* Interrupt MASK Registers */
  49 #define BXTWC_MIRQLVL1          0x4E0E
  50 #define BXTWC_MIRQLVL1_MCHGR    BIT(5)
  51
  52 #define BXTWC_MPWRBTNIRQ        0x4E0F
  53 #define BXTWC_MTHRM0IRQ         0x4E12
  54 #define BXTWC_MTHRM1IRQ         0x4E13
  55 #define BXTWC_MTHRM2IRQ         0x4E14
  56 #define BXTWC_MBCUIRQ           0x4E15
  57 #define BXTWC_MADCIRQ           0x4E16
  58 #define BXTWC_MCHGR0IRQ         0x4E17
  59 #define BXTWC_MCHGR1IRQ         0x4E18
  60 #define BXTWC_MGPIO0IRQ         0x4E19
  61 #define BXTWC_MGPIO1IRQ         0x4E1A
  62 #define BXTWC_MCRITIRQ          0x4E1B
  63 #define BXTWC_MTMUIRQ           0x4FB7
  64
  65 /* Whiskey Cove PMIC share same ACPI ID between different platforms */
  66 #define BROXTON_PMIC_WC_HRV     4
  67
  68 enum bxtwc_irqs {
  69         BXTWC_PWRBTN_LVL1_IRQ = 0,
  70         BXTWC_TMU_LVL1_IRQ,
  71         BXTWC_THRM_LVL1_IRQ,
  72         BXTWC_BCU_LVL1_IRQ,
  73         BXTWC_ADC_LVL1_IRQ,
  74         BXTWC_CHGR_LVL1_IRQ,
  75         BXTWC_GPIO_LVL1_IRQ,
  76         BXTWC_CRIT_LVL1_IRQ,
  77 };
  78
  79 enum bxtwc_irqs_pwrbtn {
  80         BXTWC_PWRBTN_IRQ = 0,
  81         BXTWC_UIBTN_IRQ,
  82 };
  83
  84 enum bxtwc_irqs_bcu {
  85         BXTWC_BCU_IRQ = 0,
  86 };
  87
  88 enum bxtwc_irqs_adc {
  89         BXTWC_ADC_IRQ = 0,
  90 };
  91
  92 enum bxtwc_irqs_chgr {
  93         BXTWC_USBC_IRQ = 0,
  94         BXTWC_CHGR0_IRQ,
  95         BXTWC_CHGR1_IRQ,
  96 };
  97
  98 enum bxtwc_irqs_tmu {
  99         BXTWC_TMU_IRQ = 0,
 100 };
 101
 102 enum bxtwc_irqs_crit {
 103         BXTWC_CRIT_IRQ = 0,
 104 };
 105
 106 static const struct regmap_irq bxtwc_regmap_irqs[] = {
 107         REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
 108         REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
 109         REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
 110         REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
 111         REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
 112         REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
 113         REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
 114         REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
 115 };
 116
 117 static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = {
 118         REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, 0x01),
 119 };
 120
 121 static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
 122         REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
 123 };
 124
 125 static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
 126         REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff),
 127 };
 128
 129 static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
 130         REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, 0x20),
 131         REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f),
 132         REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f),
 133 };
 134
 135 static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
 136         REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
 137 };
 138
 139 static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
 140         REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03),
 141 };
 142
 143 static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
 144         .name = "bxtwc_irq_chip",
 145         .status_base = BXTWC_IRQLVL1,
 146         .mask_base = BXTWC_MIRQLVL1,
 147         .irqs = bxtwc_regmap_irqs,
 148         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
 149         .num_regs = 1,
 150 };
 151
 152 static struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {
 153         .name = "bxtwc_irq_chip_pwrbtn",
 154         .status_base = BXTWC_PWRBTNIRQ,
 155         .mask_base = BXTWC_MPWRBTNIRQ,
 156         .irqs = bxtwc_regmap_irqs_pwrbtn,
 157         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_pwrbtn),
 158         .num_regs = 1,
 159 };
 160
 161 static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
 162         .name = "bxtwc_irq_chip_tmu",
 163         .status_base = BXTWC_TMUIRQ,
 164         .mask_base = BXTWC_MTMUIRQ,
 165         .irqs = bxtwc_regmap_irqs_tmu,
 166         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
 167         .num_regs = 1,
 168 };
 169
 170 static struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
 171         .name = "bxtwc_irq_chip_bcu",
 172         .status_base = BXTWC_BCUIRQ,
 173         .mask_base = BXTWC_MBCUIRQ,
 174         .irqs = bxtwc_regmap_irqs_bcu,
 175         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),
 176         .num_regs = 1,
 177 };
 178
 179 static struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
 180         .name = "bxtwc_irq_chip_adc",
 181         .status_base = BXTWC_ADCIRQ,
 182         .mask_base = BXTWC_MADCIRQ,
 183         .irqs = bxtwc_regmap_irqs_adc,
 184         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),
 185         .num_regs = 1,
 186 };
 187
 188 static struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
 189         .name = "bxtwc_irq_chip_chgr",
 190         .status_base = BXTWC_CHGR0IRQ,
 191         .mask_base = BXTWC_MCHGR0IRQ,
 192         .irqs = bxtwc_regmap_irqs_chgr,
 193         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),
 194         .num_regs = 2,
 195 };
 196
 197 static struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
 198         .name = "bxtwc_irq_chip_crit",
 199         .status_base = BXTWC_CRITIRQ,
 200         .mask_base = BXTWC_MCRITIRQ,
 201         .irqs = bxtwc_regmap_irqs_crit,
 202         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),
 203         .num_regs = 1,
 204 };
 205
 206 static struct resource gpio_resources[] = {
 207         DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
 208 };
 209
 210 static struct resource adc_resources[] = {
 211         DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
 212 };
 213
 214 static struct resource usbc_resources[] = {
 215         DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
 216 };
 217
 218 static struct resource charger_resources[] = {
 219         DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
 220         DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
 221 };
 222
 223 static struct resource thermal_resources[] = {
 224         DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
 225 };
 226
 227 static struct resource bcu_resources[] = {
 228         DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
 229 };
 230
 231 static struct resource tmu_resources[] = {
 232         DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
 233 };
 234
 235 static struct mfd_cell bxt_wc_dev[] = {
 236         {
 237                 .name = "bxt_wcove_gpadc",
 238                 .num_resources = ARRAY_SIZE(adc_resources),
 239                 .resources = adc_resources,
 240         },
 241         {
 242                 .name = "bxt_wcove_thermal",
 243                 .num_resources = ARRAY_SIZE(thermal_resources),
 244                 .resources = thermal_resources,
 245         },
 246         {
 247                 .name = "bxt_wcove_usbc",
 248                 .num_resources = ARRAY_SIZE(usbc_resources),
 249                 .resources = usbc_resources,
 250         },
 251         {
 252                 .name = "bxt_wcove_ext_charger",
 253                 .num_resources = ARRAY_SIZE(charger_resources),
 254                 .resources = charger_resources,
 255         },
 256         {
 257                 .name = "bxt_wcove_bcu",
 258                 .num_resources = ARRAY_SIZE(bcu_resources),
 259                 .resources = bcu_resources,
 260         },
 261         {
 262                 .name = "bxt_wcove_tmu",
 263                 .num_resources = ARRAY_SIZE(tmu_resources),
 264                 .resources = tmu_resources,
 265         },
 266
 267         {
 268                 .name = "bxt_wcove_gpio",
 269                 .num_resources = ARRAY_SIZE(gpio_resources),
 270                 .resources = gpio_resources,
 271         },
 272         {
 273                 .name = "bxt_wcove_region",
 274         },
 275 };
 276
 277 static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
 278                                     unsigned int *val)
 279 {
 280         int ret;
 281         int i2c_addr;
 282         u8 ipc_in[2];
 283         u8 ipc_out[4];
 284         struct intel_soc_pmic *pmic = context;
 285
 286         if (!pmic)
 287                 return -EINVAL;
 288
 289         if (reg & REG_ADDR_MASK)
 290                 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
 291         else
 292                 i2c_addr = BXTWC_DEVICE1_ADDR;
 293
 294         reg &= REG_OFFSET_MASK;
 295
 296         ipc_in[0] = reg;
 297         ipc_in[1] = i2c_addr;
 298         ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
 299                         PMC_IPC_PMIC_ACCESS_READ,
 300                         ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1);
 301         if (ret) {
 302                 dev_err(pmic->dev, "Failed to read from PMIC\n");
 303                 return ret;
 304         }
 305         *val = ipc_out[0];
 306
 307         return 0;
 308 }
 309
 310 static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
 311                                        unsigned int val)
 312 {
 313         int ret;
 314         int i2c_addr;
 315         u8 ipc_in[3];
 316         struct intel_soc_pmic *pmic = context;
 317
 318         if (!pmic)
 319                 return -EINVAL;
 320
 321         if (reg & REG_ADDR_MASK)
 322                 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
 323         else
 324                 i2c_addr = BXTWC_DEVICE1_ADDR;
 325
 326         reg &= REG_OFFSET_MASK;
 327
 328         ipc_in[0] = reg;
 329         ipc_in[1] = i2c_addr;
 330         ipc_in[2] = val;
 331         ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
 332                         PMC_IPC_PMIC_ACCESS_WRITE,
 333                         ipc_in, sizeof(ipc_in), NULL, 0);
 334         if (ret) {
 335                 dev_err(pmic->dev, "Failed to write to PMIC\n");
 336                 return ret;
 337         }
 338
 339         return 0;
 340 }
 341
 342 /* sysfs interfaces to r/w PMIC registers, required by initial script */
 343 static unsigned long bxtwc_reg_addr;
 344 static ssize_t bxtwc_reg_show(struct device *dev,
 345                 struct device_attribute *attr, char *buf)
 346 {
 347         return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
 348 }
 349
 350 static ssize_t bxtwc_reg_store(struct device *dev,
 351         struct device_attribute *attr, const char *buf, size_t count)
 352 {
 353         if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
 354                 dev_err(dev, "Invalid register address\n");
 355                 return -EINVAL;
 356         }
 357         return (ssize_t)count;
 358 }
 359
 360 static ssize_t bxtwc_val_show(struct device *dev,
 361                 struct device_attribute *attr, char *buf)
 362 {
 363         int ret;
 364         unsigned int val;
 365         struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
 366
 367         ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
 368         if (ret < 0) {
 369                 dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
 370                 return -EIO;
 371         }
 372
 373         return sprintf(buf, "0x%02x\n", val);
 374 }
 375
 376 static ssize_t bxtwc_val_store(struct device *dev,
 377         struct device_attribute *attr, const char *buf, size_t count)
 378 {
 379         int ret;
 380         unsigned int val;
 381         struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
 382
 383         ret = kstrtouint(buf, 0, &val);
 384         if (ret)
 385                 return ret;
 386
 387         ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
 388         if (ret) {
 389                 dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
 390                         val, bxtwc_reg_addr);
 391                 return -EIO;
 392         }
 393         return count;
 394 }
 395
 396 static DEVICE_ATTR(addr, S_IWUSR | S_IRUSR, bxtwc_reg_show, bxtwc_reg_store);
 397 static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store);
 398 static struct attribute *bxtwc_attrs[] = {
 399         &dev_attr_addr.attr,
 400         &dev_attr_val.attr,
 401         NULL
 402 };
 403
 404 static const struct attribute_group bxtwc_group = {
 405         .attrs = bxtwc_attrs,
 406 };
 407
 408 static const struct regmap_config bxtwc_regmap_config = {
 409         .reg_bits = 16,
 410         .val_bits = 8,
 411         .reg_write = regmap_ipc_byte_reg_write,
 412         .reg_read = regmap_ipc_byte_reg_read,
 413 };
 414
 415 static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
 416                                 struct regmap_irq_chip_data *pdata,
 417                                 int pirq, int irq_flags,
 418                                 const struct regmap_irq_chip *chip,
 419                                 struct regmap_irq_chip_data **data)
 420 {
 421         int irq;
 422
 423         irq = regmap_irq_get_virq(pdata, pirq);
 424         if (irq < 0) {
 425                 dev_err(pmic->dev,
 426                         "Failed to get parent vIRQ(%d) for chip %s, ret:%d\n",
 427                         pirq, chip->name, irq);
 428                 return irq;
 429         }
 430
 431         return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
 432                                         0, chip, data);
 433 }
 434
 435 static int bxtwc_probe(struct platform_device *pdev)
 436 {
 437         int ret;
 438         acpi_handle handle;
 439         acpi_status status;
 440         unsigned long long hrv;
 441         struct intel_soc_pmic *pmic;
 442
 443         handle = ACPI_HANDLE(&pdev->dev);
 444         status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
 445         if (ACPI_FAILURE(status)) {
 446                 dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
 447                 return -ENODEV;
 448         }
 449         if (hrv != BROXTON_PMIC_WC_HRV) {
 450                 dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
 451                         hrv);
 452                 return -ENODEV;
 453         }
 454
 455         pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
 456         if (!pmic)
 457                 return -ENOMEM;
 458
 459         ret = platform_get_irq(pdev, 0);
 460         if (ret < 0) {
 461                 dev_err(&pdev->dev, "Invalid IRQ\n");
 462                 return ret;
 463         }
 464         pmic->irq = ret;
 465
 466         dev_set_drvdata(&pdev->dev, pmic);
 467         pmic->dev = &pdev->dev;
 468
 469         pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
 470                                         &bxtwc_regmap_config);
 471         if (IS_ERR(pmic->regmap)) {
 472                 ret = PTR_ERR(pmic->regmap);
 473                 dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
 474                 return ret;
 475         }
 476
 477         ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
 478                                        IRQF_ONESHOT | IRQF_SHARED,
 479                                        0, &bxtwc_regmap_irq_chip,
 480                                        &pmic->irq_chip_data);
 481         if (ret) {
 482                 dev_err(&pdev->dev, "Failed to add IRQ chip\n");
 483                 return ret;
 484         }
 485
 486         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 487                                          BXTWC_PWRBTN_LVL1_IRQ,
 488                                          IRQF_ONESHOT,
 489                                          &bxtwc_regmap_irq_chip_pwrbtn,
 490                                          &pmic->irq_chip_data_pwrbtn);
 491         if (ret) {
 492                 dev_err(&pdev->dev, "Failed to add PWRBTN IRQ chip\n");
 493                 return ret;
 494         }
 495
 496         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 497                                          BXTWC_TMU_LVL1_IRQ,
 498                                          IRQF_ONESHOT,
 499                                          &bxtwc_regmap_irq_chip_tmu,
 500                                          &pmic->irq_chip_data_tmu);
 501         if (ret) {
 502                 dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
 503                 return ret;
 504         }
 505
 506         /* Add chained IRQ handler for BCU IRQs */
 507         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 508                                          BXTWC_BCU_LVL1_IRQ,
 509                                          IRQF_ONESHOT,
 510                                          &bxtwc_regmap_irq_chip_bcu,
 511                                          &pmic->irq_chip_data_bcu);
 512
 513
 514         if (ret) {
 515                 dev_err(&pdev->dev, "Failed to add BUC IRQ chip\n");
 516                 return ret;
 517         }
 518
 519         /* Add chained IRQ handler for ADC IRQs */
 520         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 521                                          BXTWC_ADC_LVL1_IRQ,
 522                                          IRQF_ONESHOT,
 523                                          &bxtwc_regmap_irq_chip_adc,
 524                                          &pmic->irq_chip_data_adc);
 525
 526
 527         if (ret) {
 528                 dev_err(&pdev->dev, "Failed to add ADC IRQ chip\n");
 529                 return ret;
 530         }
 531
 532         /* Add chained IRQ handler for CHGR IRQs */
 533         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 534                                          BXTWC_CHGR_LVL1_IRQ,
 535                                          IRQF_ONESHOT,
 536                                          &bxtwc_regmap_irq_chip_chgr,
 537                                          &pmic->irq_chip_data_chgr);
 538
 539
 540         if (ret) {
 541                 dev_err(&pdev->dev, "Failed to add CHGR IRQ chip\n");
 542                 return ret;
 543         }
 544
 545         /* Add chained IRQ handler for CRIT IRQs */
 546         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 547                                          BXTWC_CRIT_LVL1_IRQ,
 548                                          IRQF_ONESHOT,
 549                                          &bxtwc_regmap_irq_chip_crit,
 550                                          &pmic->irq_chip_data_crit);
 551
 552
 553         if (ret) {
 554                 dev_err(&pdev->dev, "Failed to add CRIT IRQ chip\n");
 555                 return ret;
 556         }
 557
 558         ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
 559                                    ARRAY_SIZE(bxt_wc_dev), NULL, 0, NULL);
 560         if (ret) {
 561                 dev_err(&pdev->dev, "Failed to add devices\n");
 562                 return ret;
 563         }
 564
 565         ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
 566         if (ret) {
 567                 dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
 568                 return ret;
 569         }
 570
 571         /*
 572          * There is known hw bug. Upon reset BIT 5 of register
 573          * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
 574          * later it's set to 1(masked) automatically by hardware. So we
 575          * have the software workaround here to unmaksed it in order to let
 576          * charger interrutp work.
 577          */
 578         regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1,
 579                                 BXTWC_MIRQLVL1_MCHGR, 0);
 580
 581         return 0;
 582 }
 583
 584 static int bxtwc_remove(struct platform_device *pdev)
 585 {
 586         sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
 587
 588         return 0;
 589 }
 590
 591 static void bxtwc_shutdown(struct platform_device *pdev)
 592 {
 593         struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
 594
 595         disable_irq(pmic->irq);
 596 }
 597
 598 #ifdef CONFIG_PM_SLEEP
 599 static int bxtwc_suspend(struct device *dev)
 600 {
 601         struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
 602
 603         disable_irq(pmic->irq);
 604
 605         return 0;
 606 }
 607
 608 static int bxtwc_resume(struct device *dev)
 609 {
 610         struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
 611
 612         enable_irq(pmic->irq);
 613         return 0;
 614 }
 615 #endif
 616 static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
 617
 618 static const struct acpi_device_id bxtwc_acpi_ids[] = {
 619         { "INT34D3", },
 620         { }
 621 };
 622 MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);
 623
 624 static struct platform_driver bxtwc_driver = {
 625         .probe = bxtwc_probe,
 626         .remove = bxtwc_remove,
 627         .shutdown = bxtwc_shutdown,
 628         .driver = {
 629                 .name   = "BXTWC PMIC",
 630                 .pm     = &bxtwc_pm_ops,
 631                 .acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
 632         },
 633 };
 634
 635 module_platform_driver(bxtwc_driver);
 636
 637 MODULE_LICENSE("GPL v2");
 638 MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");