GNU Linux-libre 4.9.309-gnu1
[releases.git] / drivers / mfd / rts5227.c
1 /* Driver for Realtek PCI-Express card reader
2  *
3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation; either version 2, or (at your option) any
8  * later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, see <http://www.gnu.org/licenses/>.
17  *
18  * Author:
19  *   Wei WANG <wei_wang@realsil.com.cn>
20  *   Roger Tseng <rogerable@realtek.com>
21  */
22
23 #include <linux/module.h>
24 #include <linux/delay.h>
25 #include <linux/mfd/rtsx_pci.h>
26
27 #include "rtsx_pcr.h"
28
29 static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
30 {
31         u8 val;
32
33         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
34         return val & 0x0F;
35 }
36
37 static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
38 {
39         u8 driving_3v3[4][3] = {
40                 {0x13, 0x13, 0x13},
41                 {0x96, 0x96, 0x96},
42                 {0x7F, 0x7F, 0x7F},
43                 {0x96, 0x96, 0x96},
44         };
45         u8 driving_1v8[4][3] = {
46                 {0x99, 0x99, 0x99},
47                 {0xAA, 0xAA, 0xAA},
48                 {0xFE, 0xFE, 0xFE},
49                 {0xB3, 0xB3, 0xB3},
50         };
51         u8 (*driving)[3], drive_sel;
52
53         if (voltage == OUTPUT_3V3) {
54                 driving = driving_3v3;
55                 drive_sel = pcr->sd30_drive_sel_3v3;
56         } else {
57                 driving = driving_1v8;
58                 drive_sel = pcr->sd30_drive_sel_1v8;
59         }
60
61         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
62                         0xFF, driving[drive_sel][0]);
63         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
64                         0xFF, driving[drive_sel][1]);
65         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
66                         0xFF, driving[drive_sel][2]);
67 }
68
69 static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
70 {
71         u32 reg;
72
73         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
74         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
75
76         if (!rtsx_vendor_setting_valid(reg))
77                 return;
78
79         pcr->aspm_en = rtsx_reg_to_aspm(reg);
80         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
81         pcr->card_drive_sel &= 0x3F;
82         pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
83
84         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
85         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
86         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
87         if (rtsx_reg_check_reverse_socket(reg))
88                 pcr->flags |= PCR_REVERSE_SOCKET;
89 }
90
91 static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
92 {
93         /* Set relink_time to 0 */
94         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
95         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
96         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
97
98         if (pm_state == HOST_ENTER_S3)
99                 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x10);
100
101         rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
102 }
103
104 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
105 {
106         u16 cap;
107
108         rtsx_pci_init_cmd(pcr);
109
110         /* Configure GPIO as output */
111         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
112         /* Reset ASPM state to default value */
113         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
114         /* Switch LDO3318 source from DV33 to card_3v3 */
115         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
116         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
117         /* LED shine disabled, set initial shine cycle period */
118         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
119         /* Configure LTR */
120         pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
121         if (cap & PCI_EXP_DEVCTL2_LTR_EN)
122                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
123         /* Configure OBFF */
124         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
125         /* Configure driving */
126         rts5227_fill_driving(pcr, OUTPUT_3V3);
127         /* Configure force_clock_req */
128         if (pcr->flags & PCR_REVERSE_SOCKET)
129                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8);
130         else
131                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88);
132         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
133
134         return rtsx_pci_send_cmd(pcr, 100);
135 }
136
137 static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
138 {
139         int err;
140
141         err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
142         if (err < 0)
143                 return err;
144
145         /* Optimize RX sensitivity */
146         return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
147 }
148
149 static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
150 {
151         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
152 }
153
154 static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
155 {
156         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
157 }
158
159 static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
160 {
161         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
162 }
163
164 static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
165 {
166         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
167 }
168
169 static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
170 {
171         int err;
172
173         rtsx_pci_init_cmd(pcr);
174         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
175                         SD_POWER_MASK, SD_PARTIAL_POWER_ON);
176         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
177                         LDO3318_PWR_MASK, 0x02);
178         err = rtsx_pci_send_cmd(pcr, 100);
179         if (err < 0)
180                 return err;
181
182         /* To avoid too large in-rush current */
183         udelay(150);
184
185         rtsx_pci_init_cmd(pcr);
186         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
187                         SD_POWER_MASK, SD_POWER_ON);
188         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
189                         LDO3318_PWR_MASK, 0x06);
190         return rtsx_pci_send_cmd(pcr, 100);
191 }
192
193 static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
194 {
195         rtsx_pci_init_cmd(pcr);
196         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
197                         SD_POWER_MASK | PMOS_STRG_MASK,
198                         SD_POWER_OFF | PMOS_STRG_400mA);
199         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
200                         LDO3318_PWR_MASK, 0X00);
201         return rtsx_pci_send_cmd(pcr, 100);
202 }
203
204 static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
205 {
206         int err;
207
208         if (voltage == OUTPUT_3V3) {
209                 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
210                 if (err < 0)
211                         return err;
212         } else if (voltage == OUTPUT_1V8) {
213                 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
214                 if (err < 0)
215                         return err;
216                 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
217                 if (err < 0)
218                         return err;
219         } else {
220                 return -EINVAL;
221         }
222
223         /* set pad drive */
224         rtsx_pci_init_cmd(pcr);
225         rts5227_fill_driving(pcr, voltage);
226         return rtsx_pci_send_cmd(pcr, 100);
227 }
228
229 static const struct pcr_ops rts5227_pcr_ops = {
230         .fetch_vendor_settings = rts5227_fetch_vendor_settings,
231         .extra_init_hw = rts5227_extra_init_hw,
232         .optimize_phy = rts5227_optimize_phy,
233         .turn_on_led = rts5227_turn_on_led,
234         .turn_off_led = rts5227_turn_off_led,
235         .enable_auto_blink = rts5227_enable_auto_blink,
236         .disable_auto_blink = rts5227_disable_auto_blink,
237         .card_power_on = rts5227_card_power_on,
238         .card_power_off = rts5227_card_power_off,
239         .switch_output_voltage = rts5227_switch_output_voltage,
240         .cd_deglitch = NULL,
241         .conv_clk_and_div_n = NULL,
242         .force_power_down = rts5227_force_power_down,
243 };
244
245 /* SD Pull Control Enable:
246  *     SD_DAT[3:0] ==> pull up
247  *     SD_CD       ==> pull up
248  *     SD_WP       ==> pull up
249  *     SD_CMD      ==> pull up
250  *     SD_CLK      ==> pull down
251  */
252 static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
253         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
254         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
255         0,
256 };
257
258 /* SD Pull Control Disable:
259  *     SD_DAT[3:0] ==> pull down
260  *     SD_CD       ==> pull up
261  *     SD_WP       ==> pull down
262  *     SD_CMD      ==> pull down
263  *     SD_CLK      ==> pull down
264  */
265 static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
266         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
267         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
268         0,
269 };
270
271 /* MS Pull Control Enable:
272  *     MS CD       ==> pull up
273  *     others      ==> pull down
274  */
275 static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
276         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
277         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
278         0,
279 };
280
281 /* MS Pull Control Disable:
282  *     MS CD       ==> pull up
283  *     others      ==> pull down
284  */
285 static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
286         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
287         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
288         0,
289 };
290
291 void rts5227_init_params(struct rtsx_pcr *pcr)
292 {
293         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
294         pcr->num_slots = 2;
295         pcr->ops = &rts5227_pcr_ops;
296
297         pcr->flags = 0;
298         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
299         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
300         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
301         pcr->aspm_en = ASPM_L1_EN;
302         pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
303         pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
304
305         pcr->ic_version = rts5227_get_ic_version(pcr);
306         pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
307         pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
308         pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
309         pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
310
311         pcr->reg_pm_ctrl3 = PM_CTRL3;
312 }
313
314 static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
315 {
316         int err;
317
318         err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
319                 0x00);
320         if (err < 0)
321                 return err;
322
323         if (is_version(pcr, 0x522A, IC_VER_A)) {
324                 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
325                         PHY_RCR2_INIT_27S);
326                 if (err)
327                         return err;
328
329                 rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
330                 rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
331                 rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
332                 rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
333         }
334
335         return 0;
336 }
337
338 static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
339 {
340         rts5227_extra_init_hw(pcr);
341
342         rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
343                 FUNC_FORCE_UPME_XMT_DBG);
344         rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
345         rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
346         rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
347
348         return 0;
349 }
350
351 /* rts522a operations mainly derived from rts5227, except phy/hw init setting.
352  */
353 static const struct pcr_ops rts522a_pcr_ops = {
354         .fetch_vendor_settings = rts5227_fetch_vendor_settings,
355         .extra_init_hw = rts522a_extra_init_hw,
356         .optimize_phy = rts522a_optimize_phy,
357         .turn_on_led = rts5227_turn_on_led,
358         .turn_off_led = rts5227_turn_off_led,
359         .enable_auto_blink = rts5227_enable_auto_blink,
360         .disable_auto_blink = rts5227_disable_auto_blink,
361         .card_power_on = rts5227_card_power_on,
362         .card_power_off = rts5227_card_power_off,
363         .switch_output_voltage = rts5227_switch_output_voltage,
364         .cd_deglitch = NULL,
365         .conv_clk_and_div_n = NULL,
366         .force_power_down = rts5227_force_power_down,
367 };
368
369 void rts522a_init_params(struct rtsx_pcr *pcr)
370 {
371         rts5227_init_params(pcr);
372         pcr->ops = &rts522a_pcr_ops;
373
374         pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
375 }