2 * Copyright 2015 IBM Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/spinlock.h>
11 #include <linux/uaccess.h>
12 #include <linux/delay.h>
18 #define CXL_ERROR_DETECTED_EVENT 1
19 #define CXL_SLOT_RESET_EVENT 2
20 #define CXL_RESUME_EVENT 3
22 static void pci_error_handlers(struct cxl_afu *afu,
24 pci_channel_state_t state)
26 struct pci_dev *afu_dev;
31 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
35 switch (bus_error_event) {
36 case CXL_ERROR_DETECTED_EVENT:
37 afu_dev->error_state = state;
39 if (afu_dev->driver->err_handler &&
40 afu_dev->driver->err_handler->error_detected)
41 afu_dev->driver->err_handler->error_detected(afu_dev, state);
43 case CXL_SLOT_RESET_EVENT:
44 afu_dev->error_state = state;
46 if (afu_dev->driver->err_handler &&
47 afu_dev->driver->err_handler->slot_reset)
48 afu_dev->driver->err_handler->slot_reset(afu_dev);
50 case CXL_RESUME_EVENT:
51 if (afu_dev->driver->err_handler &&
52 afu_dev->driver->err_handler->resume)
53 afu_dev->driver->err_handler->resume(afu_dev);
59 static irqreturn_t guest_handle_psl_slice_error(struct cxl_context *ctx, u64 dsisr,
62 pr_devel("in %s\n", __func__);
63 dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%.16llx\n", errstat);
65 return cxl_ops->ack_irq(ctx, 0, errstat);
68 static ssize_t guest_collect_vpd(struct cxl *adapter, struct cxl_afu *afu,
69 void *buf, size_t len)
71 unsigned int entries, mod;
72 unsigned long **vpd_buf = NULL;
74 int rc = 0, i, tocopy;
80 /* number of entries in the list */
81 entries = len / SG_BUFFER_SIZE;
82 mod = len % SG_BUFFER_SIZE;
86 if (entries > SG_MAX_ENTRIES) {
87 entries = SG_MAX_ENTRIES;
88 len = SG_MAX_ENTRIES * SG_BUFFER_SIZE;
92 vpd_buf = kzalloc(entries * sizeof(unsigned long *), GFP_KERNEL);
96 le = (struct sg_list *)get_zeroed_page(GFP_KERNEL);
102 for (i = 0; i < entries; i++) {
103 vpd_buf[i] = (unsigned long *)get_zeroed_page(GFP_KERNEL);
108 le[i].phys_addr = cpu_to_be64(virt_to_phys(vpd_buf[i]));
109 le[i].len = cpu_to_be64(SG_BUFFER_SIZE);
110 if ((i == (entries - 1)) && mod)
111 le[i].len = cpu_to_be64(mod);
115 rc = cxl_h_collect_vpd_adapter(adapter->guest->handle,
116 virt_to_phys(le), entries, &out);
118 rc = cxl_h_collect_vpd(afu->guest->handle, 0,
119 virt_to_phys(le), entries, &out);
120 pr_devel("length of available (entries: %i), vpd: %#llx\n",
125 * hcall returns in 'out' the size of available VPDs.
126 * It fills the buffer with as much data as possible.
132 for (i = 0; i < entries; i++) {
133 if (len < SG_BUFFER_SIZE)
136 tocopy = SG_BUFFER_SIZE;
137 memcpy(buf, vpd_buf[i], tocopy);
144 for (i = 0; i < entries; i++) {
146 free_page((unsigned long) vpd_buf[i]);
148 free_page((unsigned long) le);
154 static int guest_get_irq_info(struct cxl_context *ctx, struct cxl_irq_info *info)
156 return cxl_h_collect_int_info(ctx->afu->guest->handle, ctx->process_token, info);
159 static irqreturn_t guest_psl_irq(int irq, void *data)
161 struct cxl_context *ctx = data;
162 struct cxl_irq_info irq_info;
165 pr_devel("%d: received PSL interrupt %i\n", ctx->pe, irq);
166 rc = guest_get_irq_info(ctx, &irq_info);
168 WARN(1, "Unable to get IRQ info: %i\n", rc);
172 rc = cxl_irq_psl8(irq, ctx, &irq_info);
176 static int afu_read_error_state(struct cxl_afu *afu, int *state_out)
184 rc = cxl_h_read_error_state(afu->guest->handle, &state);
186 WARN_ON(state != H_STATE_NORMAL &&
187 state != H_STATE_DISABLE &&
188 state != H_STATE_TEMP_UNAVAILABLE &&
189 state != H_STATE_PERM_UNAVAILABLE);
190 *state_out = state & 0xffffffff;
195 static irqreturn_t guest_slice_irq_err(int irq, void *data)
197 struct cxl_afu *afu = data;
199 u64 serr, afu_error, dsisr;
201 rc = cxl_h_get_fn_error_interrupt(afu->guest->handle, &serr);
203 dev_crit(&afu->dev, "Couldn't read PSL_SERR_An: %d\n", rc);
206 afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An);
207 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
208 cxl_afu_decode_psl_serr(afu, serr);
209 dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error);
210 dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr);
212 rc = cxl_h_ack_fn_error_interrupt(afu->guest->handle, serr);
214 dev_crit(&afu->dev, "Couldn't ack slice error interrupt: %d\n",
221 static int irq_alloc_range(struct cxl *adapter, int len, int *irq)
224 struct irq_avail *cur;
226 for (i = 0; i < adapter->guest->irq_nranges; i++) {
227 cur = &adapter->guest->irq_avail[i];
228 n = bitmap_find_next_zero_area(cur->bitmap, cur->range,
230 if (n < cur->range) {
231 bitmap_set(cur->bitmap, n, len);
232 *irq = cur->offset + n;
233 pr_devel("guest: allocate IRQs %#x->%#x\n",
234 *irq, *irq + len - 1);
242 static int irq_free_range(struct cxl *adapter, int irq, int len)
245 struct irq_avail *cur;
250 for (i = 0; i < adapter->guest->irq_nranges; i++) {
251 cur = &adapter->guest->irq_avail[i];
252 if (irq >= cur->offset &&
253 (irq + len) <= (cur->offset + cur->range)) {
254 n = irq - cur->offset;
255 bitmap_clear(cur->bitmap, n, len);
256 pr_devel("guest: release IRQs %#x->%#x\n",
264 static int guest_reset(struct cxl *adapter)
266 struct cxl_afu *afu = NULL;
269 pr_devel("Adapter reset request\n");
270 spin_lock(&adapter->afu_list_lock);
271 for (i = 0; i < adapter->slices; i++) {
272 if ((afu = adapter->afu[i])) {
273 pci_error_handlers(afu, CXL_ERROR_DETECTED_EVENT,
274 pci_channel_io_frozen);
275 cxl_context_detach_all(afu);
279 rc = cxl_h_reset_adapter(adapter->guest->handle);
280 for (i = 0; i < adapter->slices; i++) {
281 if (!rc && (afu = adapter->afu[i])) {
282 pci_error_handlers(afu, CXL_SLOT_RESET_EVENT,
283 pci_channel_io_normal);
284 pci_error_handlers(afu, CXL_RESUME_EVENT, 0);
287 spin_unlock(&adapter->afu_list_lock);
291 static int guest_alloc_one_irq(struct cxl *adapter)
295 spin_lock(&adapter->guest->irq_alloc_lock);
296 if (irq_alloc_range(adapter, 1, &irq))
298 spin_unlock(&adapter->guest->irq_alloc_lock);
302 static void guest_release_one_irq(struct cxl *adapter, int irq)
304 spin_lock(&adapter->guest->irq_alloc_lock);
305 irq_free_range(adapter, irq, 1);
306 spin_unlock(&adapter->guest->irq_alloc_lock);
309 static int guest_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
310 struct cxl *adapter, unsigned int num)
314 memset(irqs, 0, sizeof(struct cxl_irq_ranges));
316 spin_lock(&adapter->guest->irq_alloc_lock);
317 for (i = 0; i < CXL_IRQ_RANGES && num; i++) {
320 if (irq_alloc_range(adapter, try, &irq) == 0)
326 irqs->offset[i] = irq;
327 irqs->range[i] = try;
332 spin_unlock(&adapter->guest->irq_alloc_lock);
336 for (i = 0; i < CXL_IRQ_RANGES; i++)
337 irq_free_range(adapter, irqs->offset[i], irqs->range[i]);
338 spin_unlock(&adapter->guest->irq_alloc_lock);
342 static void guest_release_irq_ranges(struct cxl_irq_ranges *irqs,
347 spin_lock(&adapter->guest->irq_alloc_lock);
348 for (i = 0; i < CXL_IRQ_RANGES; i++)
349 irq_free_range(adapter, irqs->offset[i], irqs->range[i]);
350 spin_unlock(&adapter->guest->irq_alloc_lock);
353 static int guest_register_serr_irq(struct cxl_afu *afu)
355 afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
356 dev_name(&afu->dev));
357 if (!afu->err_irq_name)
360 if (!(afu->serr_virq = cxl_map_irq(afu->adapter, afu->serr_hwirq,
361 guest_slice_irq_err, afu, afu->err_irq_name))) {
362 kfree(afu->err_irq_name);
363 afu->err_irq_name = NULL;
370 static void guest_release_serr_irq(struct cxl_afu *afu)
372 cxl_unmap_irq(afu->serr_virq, afu);
373 cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq);
374 kfree(afu->err_irq_name);
377 static int guest_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
379 return cxl_h_control_faults(ctx->afu->guest->handle, ctx->process_token,
380 tfc >> 32, (psl_reset_mask != 0));
383 static void disable_afu_irqs(struct cxl_context *ctx)
385 irq_hw_number_t hwirq;
389 pr_devel("Disabling AFU(%d) interrupts\n", ctx->afu->slice);
390 for (r = 0; r < CXL_IRQ_RANGES; r++) {
391 hwirq = ctx->irqs.offset[r];
392 for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
393 virq = irq_find_mapping(NULL, hwirq);
399 static void enable_afu_irqs(struct cxl_context *ctx)
401 irq_hw_number_t hwirq;
405 pr_devel("Enabling AFU(%d) interrupts\n", ctx->afu->slice);
406 for (r = 0; r < CXL_IRQ_RANGES; r++) {
407 hwirq = ctx->irqs.offset[r];
408 for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
409 virq = irq_find_mapping(NULL, hwirq);
415 static int _guest_afu_cr_readXX(int sz, struct cxl_afu *afu, int cr_idx,
416 u64 offset, u64 *val)
422 if (afu->crs_len < sz)
425 if (unlikely(offset >= afu->crs_len))
428 cr = get_zeroed_page(GFP_KERNEL);
432 rc = cxl_h_get_config(afu->guest->handle, cr_idx, offset,
433 virt_to_phys((void *)cr), sz);
443 *val = in_le16((u16 *)cr);
446 *val = in_le32((unsigned *)cr);
449 *val = in_le64((u64 *)cr);
459 static int guest_afu_cr_read32(struct cxl_afu *afu, int cr_idx, u64 offset,
465 rc = _guest_afu_cr_readXX(4, afu, cr_idx, offset, &val);
471 static int guest_afu_cr_read16(struct cxl_afu *afu, int cr_idx, u64 offset,
477 rc = _guest_afu_cr_readXX(2, afu, cr_idx, offset, &val);
483 static int guest_afu_cr_read8(struct cxl_afu *afu, int cr_idx, u64 offset,
489 rc = _guest_afu_cr_readXX(1, afu, cr_idx, offset, &val);
495 static int guest_afu_cr_read64(struct cxl_afu *afu, int cr_idx, u64 offset,
498 return _guest_afu_cr_readXX(8, afu, cr_idx, offset, out);
501 static int guest_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in)
503 /* config record is not writable from guest */
507 static int guest_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in)
509 /* config record is not writable from guest */
513 static int guest_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in)
515 /* config record is not writable from guest */
519 static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
521 struct cxl_process_element_hcall *elem;
522 struct cxl *adapter = ctx->afu->adapter;
523 const struct cred *cred;
526 u64 mmio_addr, mmio_size;
529 /* Must be 8 byte aligned and cannot cross a 4096 byte boundary */
530 if (!(elem = (struct cxl_process_element_hcall *)
531 get_zeroed_page(GFP_KERNEL)))
534 elem->version = cpu_to_be64(CXL_PROCESS_ELEMENT_VERSION);
537 flags |= CXL_PE_TRANSLATION_ENABLED;
538 flags |= CXL_PE_PRIVILEGED_PROCESS;
539 if (mfmsr() & MSR_SF)
540 flags |= CXL_PE_64_BIT;
543 flags |= CXL_PE_PROBLEM_STATE;
544 flags |= CXL_PE_TRANSLATION_ENABLED;
545 if (!test_tsk_thread_flag(current, TIF_32BIT))
546 flags |= CXL_PE_64_BIT;
547 cred = get_current_cred();
548 if (uid_eq(cred->euid, GLOBAL_ROOT_UID))
549 flags |= CXL_PE_PRIVILEGED_PROCESS;
552 elem->flags = cpu_to_be64(flags);
553 elem->common.tid = cpu_to_be32(0); /* Unused */
554 elem->common.pid = cpu_to_be32(pid);
555 elem->common.csrp = cpu_to_be64(0); /* disable */
556 elem->common.u.psl8.aurp0 = cpu_to_be64(0); /* disable */
557 elem->common.u.psl8.aurp1 = cpu_to_be64(0); /* disable */
559 cxl_prefault(ctx, wed);
561 elem->common.u.psl8.sstp0 = cpu_to_be64(ctx->sstp0);
562 elem->common.u.psl8.sstp1 = cpu_to_be64(ctx->sstp1);
565 * Ensure we have at least one interrupt allocated to take faults for
566 * kernel contexts that may not have allocated any AFU IRQs at all:
568 if (ctx->irqs.range[0] == 0) {
569 rc = afu_register_irqs(ctx, 0);
574 for (r = 0; r < CXL_IRQ_RANGES; r++) {
575 for (i = 0; i < ctx->irqs.range[r]; i++) {
576 if (r == 0 && i == 0) {
577 elem->pslVirtualIsn = cpu_to_be32(ctx->irqs.offset[0]);
579 idx = ctx->irqs.offset[r] + i - adapter->guest->irq_base_offset;
580 elem->applicationVirtualIsnBitmap[idx / 8] |= 0x80 >> (idx % 8);
584 elem->common.amr = cpu_to_be64(amr);
585 elem->common.wed = cpu_to_be64(wed);
587 disable_afu_irqs(ctx);
589 rc = cxl_h_attach_process(ctx->afu->guest->handle, elem,
590 &ctx->process_token, &mmio_addr, &mmio_size);
591 if (rc == H_SUCCESS) {
592 if (ctx->master || !ctx->afu->pp_psa) {
593 ctx->psn_phys = ctx->afu->psn_phys;
594 ctx->psn_size = ctx->afu->adapter->ps_size;
596 ctx->psn_phys = mmio_addr;
597 ctx->psn_size = mmio_size;
599 if (ctx->afu->pp_psa && mmio_size &&
600 ctx->afu->pp_size == 0) {
602 * There's no property in the device tree to read the
603 * pp_size. We only find out at the 1st attach.
604 * Compared to bare-metal, it is too late and we
605 * should really lock here. However, on powerVM,
606 * pp_size is really only used to display in /sys.
607 * Being discussed with pHyp for their next release.
609 ctx->afu->pp_size = mmio_size;
611 /* from PAPR: process element is bytes 4-7 of process token */
612 ctx->external_pe = ctx->process_token & 0xFFFFFFFF;
613 pr_devel("CXL pe=%i is known as %i for pHyp, mmio_size=%#llx",
614 ctx->pe, ctx->external_pe, ctx->psn_size);
615 ctx->pe_inserted = true;
616 enable_afu_irqs(ctx);
620 free_page((u64)elem);
624 static int guest_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, u64 amr)
626 pr_devel("in %s\n", __func__);
631 ctx->kernel = kernel;
632 if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
633 return attach_afu_directed(ctx, wed, amr);
635 /* dedicated mode not supported on FW840 */
640 static int detach_afu_directed(struct cxl_context *ctx)
642 if (!ctx->pe_inserted)
644 if (cxl_h_detach_process(ctx->afu->guest->handle, ctx->process_token))
649 static int guest_detach_process(struct cxl_context *ctx)
651 pr_devel("in %s\n", __func__);
652 trace_cxl_detach(ctx);
654 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
657 if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
658 return detach_afu_directed(ctx);
663 static void guest_release_afu(struct device *dev)
665 struct cxl_afu *afu = to_cxl_afu(dev);
667 pr_devel("%s\n", __func__);
669 idr_destroy(&afu->contexts_idr);
675 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len)
677 return guest_collect_vpd(NULL, afu, buf, len);
680 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
681 static ssize_t guest_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
682 loff_t off, size_t count)
687 tbuf = (void *) get_zeroed_page(GFP_KERNEL);
691 rc = cxl_h_get_afu_err(afu->guest->handle,
698 if (count > ERR_BUFF_MAX_COPY_SIZE)
699 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
700 memcpy(buf, tbuf, count);
702 free_page((u64)tbuf);
707 static int guest_afu_check_and_enable(struct cxl_afu *afu)
712 static bool guest_support_attributes(const char *attr_name,
716 case CXL_ADAPTER_ATTRS:
717 if ((strcmp(attr_name, "base_image") == 0) ||
718 (strcmp(attr_name, "load_image_on_perst") == 0) ||
719 (strcmp(attr_name, "perst_reloads_same_image") == 0) ||
720 (strcmp(attr_name, "image_loaded") == 0))
723 case CXL_AFU_MASTER_ATTRS:
724 if ((strcmp(attr_name, "pp_mmio_off") == 0))
736 static int activate_afu_directed(struct cxl_afu *afu)
740 dev_info(&afu->dev, "Activating AFU(%d) directed mode\n", afu->slice);
742 afu->current_mode = CXL_MODE_DIRECTED;
744 afu->num_procs = afu->max_procs_virtualised;
746 if ((rc = cxl_chardev_m_afu_add(afu)))
749 if ((rc = cxl_sysfs_afu_m_add(afu)))
752 if ((rc = cxl_chardev_s_afu_add(afu)))
757 cxl_sysfs_afu_m_remove(afu);
759 cxl_chardev_afu_remove(afu);
763 static int guest_afu_activate_mode(struct cxl_afu *afu, int mode)
767 if (!(mode & afu->modes_supported))
770 if (mode == CXL_MODE_DIRECTED)
771 return activate_afu_directed(afu);
773 if (mode == CXL_MODE_DEDICATED)
774 dev_err(&afu->dev, "Dedicated mode not supported\n");
779 static int deactivate_afu_directed(struct cxl_afu *afu)
781 dev_info(&afu->dev, "Deactivating AFU(%d) directed mode\n", afu->slice);
783 afu->current_mode = 0;
786 cxl_sysfs_afu_m_remove(afu);
787 cxl_chardev_afu_remove(afu);
789 cxl_ops->afu_reset(afu);
794 static int guest_afu_deactivate_mode(struct cxl_afu *afu, int mode)
798 if (!(mode & afu->modes_supported))
801 if (mode == CXL_MODE_DIRECTED)
802 return deactivate_afu_directed(afu);
806 static int guest_afu_reset(struct cxl_afu *afu)
808 pr_devel("AFU(%d) reset request\n", afu->slice);
809 return cxl_h_reset_afu(afu->guest->handle);
812 static int guest_map_slice_regs(struct cxl_afu *afu)
814 if (!(afu->p2n_mmio = ioremap(afu->guest->p2n_phys, afu->guest->p2n_size))) {
815 dev_err(&afu->dev, "Error mapping AFU(%d) MMIO regions\n",
822 static void guest_unmap_slice_regs(struct cxl_afu *afu)
825 iounmap(afu->p2n_mmio);
828 static int afu_update_state(struct cxl_afu *afu)
832 rc = afu_read_error_state(afu, &cur_state);
836 if (afu->guest->previous_state == cur_state)
839 pr_devel("AFU(%d) update state to %#x\n", afu->slice, cur_state);
843 afu->guest->previous_state = cur_state;
846 case H_STATE_DISABLE:
847 pci_error_handlers(afu, CXL_ERROR_DETECTED_EVENT,
848 pci_channel_io_frozen);
850 cxl_context_detach_all(afu);
851 if ((rc = cxl_ops->afu_reset(afu)))
852 pr_devel("reset hcall failed %d\n", rc);
854 rc = afu_read_error_state(afu, &cur_state);
855 if (!rc && cur_state == H_STATE_NORMAL) {
856 pci_error_handlers(afu, CXL_SLOT_RESET_EVENT,
857 pci_channel_io_normal);
858 pci_error_handlers(afu, CXL_RESUME_EVENT, 0);
860 afu->guest->previous_state = 0;
863 case H_STATE_TEMP_UNAVAILABLE:
864 afu->guest->previous_state = cur_state;
867 case H_STATE_PERM_UNAVAILABLE:
868 dev_err(&afu->dev, "AFU is in permanent error state\n");
869 pci_error_handlers(afu, CXL_ERROR_DETECTED_EVENT,
870 pci_channel_io_perm_failure);
871 afu->guest->previous_state = cur_state;
875 pr_err("Unexpected AFU(%d) error state: %#x\n",
876 afu->slice, cur_state);
883 static void afu_handle_errstate(struct work_struct *work)
885 struct cxl_afu_guest *afu_guest =
886 container_of(to_delayed_work(work), struct cxl_afu_guest, work_err);
888 if (!afu_update_state(afu_guest->parent) &&
889 afu_guest->previous_state == H_STATE_PERM_UNAVAILABLE)
892 if (afu_guest->handle_err)
893 schedule_delayed_work(&afu_guest->work_err,
894 msecs_to_jiffies(3000));
897 static bool guest_link_ok(struct cxl *cxl, struct cxl_afu *afu)
901 if (afu && (!afu_read_error_state(afu, &state))) {
902 if (state == H_STATE_NORMAL)
909 static int afu_properties_look_ok(struct cxl_afu *afu)
911 if (afu->pp_irqs < 0) {
912 dev_err(&afu->dev, "Unexpected per-process minimum interrupt value\n");
916 if (afu->max_procs_virtualised < 1) {
917 dev_err(&afu->dev, "Unexpected max number of processes virtualised value\n");
921 if (afu->crs_len < 0) {
922 dev_err(&afu->dev, "Unexpected configuration record size value\n");
929 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np)
935 pr_devel("in %s - AFU(%d)\n", __func__, slice);
936 if (!(afu = cxl_alloc_afu(adapter, slice)))
939 if (!(afu->guest = kzalloc(sizeof(struct cxl_afu_guest), GFP_KERNEL))) {
944 if ((rc = dev_set_name(&afu->dev, "afu%i.%i",
945 adapter->adapter_num,
951 if ((rc = cxl_of_read_afu_handle(afu, afu_np)))
954 if ((rc = cxl_ops->afu_reset(afu)))
957 if ((rc = cxl_of_read_afu_properties(afu, afu_np)))
960 if ((rc = afu_properties_look_ok(afu)))
963 if ((rc = guest_map_slice_regs(afu)))
966 if ((rc = guest_register_serr_irq(afu)))
970 * After we call this function we must not free the afu directly, even
971 * if it returns an error!
973 if ((rc = cxl_register_afu(afu)))
976 if ((rc = cxl_sysfs_afu_add(afu)))
980 * pHyp doesn't expose the programming models supported by the
981 * AFU. pHyp currently only supports directed mode. If it adds
982 * dedicated mode later, this version of cxl has no way to
983 * detect it. So we'll initialize the driver, but the first
985 * Being discussed with pHyp to do better (likely new property)
987 if (afu->max_procs_virtualised == 1)
988 afu->modes_supported = CXL_MODE_DEDICATED;
990 afu->modes_supported = CXL_MODE_DIRECTED;
992 if ((rc = cxl_afu_select_best_mode(afu)))
995 adapter->afu[afu->slice] = afu;
1000 * wake up the cpu periodically to check the state
1001 * of the AFU using "afu" stored in the guest structure.
1003 afu->guest->parent = afu;
1004 afu->guest->handle_err = true;
1005 INIT_DELAYED_WORK(&afu->guest->work_err, afu_handle_errstate);
1006 schedule_delayed_work(&afu->guest->work_err, msecs_to_jiffies(1000));
1008 if ((rc = cxl_pci_vphb_add(afu)))
1009 dev_info(&afu->dev, "Can't register vPHB\n");
1014 cxl_sysfs_afu_remove(afu);
1016 device_unregister(&afu->dev);
1018 guest_release_serr_irq(afu);
1020 guest_unmap_slice_regs(afu);
1029 void cxl_guest_remove_afu(struct cxl_afu *afu)
1034 /* flush and stop pending job */
1035 afu->guest->handle_err = false;
1036 flush_delayed_work(&afu->guest->work_err);
1038 cxl_pci_vphb_remove(afu);
1039 cxl_sysfs_afu_remove(afu);
1041 spin_lock(&afu->adapter->afu_list_lock);
1042 afu->adapter->afu[afu->slice] = NULL;
1043 spin_unlock(&afu->adapter->afu_list_lock);
1045 cxl_context_detach_all(afu);
1046 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1047 guest_release_serr_irq(afu);
1048 guest_unmap_slice_regs(afu);
1050 device_unregister(&afu->dev);
1053 static void free_adapter(struct cxl *adapter)
1055 struct irq_avail *cur;
1058 if (adapter->guest) {
1059 if (adapter->guest->irq_avail) {
1060 for (i = 0; i < adapter->guest->irq_nranges; i++) {
1061 cur = &adapter->guest->irq_avail[i];
1064 kfree(adapter->guest->irq_avail);
1066 kfree(adapter->guest->status);
1067 kfree(adapter->guest);
1069 cxl_remove_adapter_nr(adapter);
1073 static int properties_look_ok(struct cxl *adapter)
1075 /* The absence of this property means that the operational
1076 * status is unknown or okay
1078 if (strlen(adapter->guest->status) &&
1079 strcmp(adapter->guest->status, "okay")) {
1080 pr_err("ABORTING:Bad operational status of the device\n");
1087 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1089 return guest_collect_vpd(adapter, NULL, buf, len);
1092 void cxl_guest_remove_adapter(struct cxl *adapter)
1094 pr_devel("in %s\n", __func__);
1096 cxl_sysfs_adapter_remove(adapter);
1098 cxl_guest_remove_chardev(adapter);
1099 device_unregister(&adapter->dev);
1102 static void release_adapter(struct device *dev)
1104 free_adapter(to_cxl_adapter(dev));
1107 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *pdev)
1109 struct cxl *adapter;
1113 if (!(adapter = cxl_alloc_adapter()))
1114 return ERR_PTR(-ENOMEM);
1116 if (!(adapter->guest = kzalloc(sizeof(struct cxl_guest), GFP_KERNEL))) {
1117 free_adapter(adapter);
1118 return ERR_PTR(-ENOMEM);
1121 adapter->slices = 0;
1122 adapter->guest->pdev = pdev;
1123 adapter->dev.parent = &pdev->dev;
1124 adapter->dev.release = release_adapter;
1125 dev_set_drvdata(&pdev->dev, adapter);
1128 * Hypervisor controls PSL timebase initialization (p1 register).
1129 * On FW840, PSL is initialized.
1131 adapter->psl_timebase_synced = true;
1133 if ((rc = cxl_of_read_adapter_handle(adapter, np)))
1136 if ((rc = cxl_of_read_adapter_properties(adapter, np)))
1139 if ((rc = properties_look_ok(adapter)))
1142 if ((rc = cxl_guest_add_chardev(adapter)))
1146 * After we call this function we must not free the adapter directly,
1147 * even if it returns an error!
1149 if ((rc = cxl_register_adapter(adapter)))
1152 if ((rc = cxl_sysfs_adapter_add(adapter)))
1155 /* release the context lock as the adapter is configured */
1156 cxl_adapter_context_unlock(adapter);
1161 device_unregister(&adapter->dev);
1163 cxl_guest_remove_chardev(adapter);
1166 free_adapter(adapter);
1170 void cxl_guest_reload_module(struct cxl *adapter)
1172 struct platform_device *pdev;
1174 pdev = adapter->guest->pdev;
1175 cxl_guest_remove_adapter(adapter);
1180 const struct cxl_backend_ops cxl_guest_ops = {
1181 .module = THIS_MODULE,
1182 .adapter_reset = guest_reset,
1183 .alloc_one_irq = guest_alloc_one_irq,
1184 .release_one_irq = guest_release_one_irq,
1185 .alloc_irq_ranges = guest_alloc_irq_ranges,
1186 .release_irq_ranges = guest_release_irq_ranges,
1188 .handle_psl_slice_error = guest_handle_psl_slice_error,
1189 .psl_interrupt = guest_psl_irq,
1190 .ack_irq = guest_ack_irq,
1191 .attach_process = guest_attach_process,
1192 .detach_process = guest_detach_process,
1193 .update_ivtes = NULL,
1194 .support_attributes = guest_support_attributes,
1195 .link_ok = guest_link_ok,
1196 .release_afu = guest_release_afu,
1197 .afu_read_err_buffer = guest_afu_read_err_buffer,
1198 .afu_check_and_enable = guest_afu_check_and_enable,
1199 .afu_activate_mode = guest_afu_activate_mode,
1200 .afu_deactivate_mode = guest_afu_deactivate_mode,
1201 .afu_reset = guest_afu_reset,
1202 .afu_cr_read8 = guest_afu_cr_read8,
1203 .afu_cr_read16 = guest_afu_cr_read16,
1204 .afu_cr_read32 = guest_afu_cr_read32,
1205 .afu_cr_read64 = guest_afu_cr_read64,
1206 .afu_cr_write8 = guest_afu_cr_write8,
1207 .afu_cr_write16 = guest_afu_cr_write16,
1208 .afu_cr_write32 = guest_afu_cr_write32,
1209 .read_adapter_vpd = cxl_guest_read_adapter_vpd,