drivers/misc/cxl/native.c

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #include <linux/spinlock.h>
  11 #include <linux/sched.h>
  12 #include <linux/sched/clock.h>
  13 #include <linux/slab.h>
  14 #include <linux/mutex.h>
  15 #include <linux/mm.h>
  16 #include <linux/uaccess.h>
  17 #include <linux/delay.h>
  18 #include <asm/synch.h>
  19 #include <misc/cxl-base.h>
  20
  21 #include "cxl.h"
  22 #include "trace.h"
  23
  24 static int afu_control(struct cxl_afu *afu, u64 command, u64 clear,
  25                        u64 result, u64 mask, bool enabled)
  26 {
  27         u64 AFU_Cntl;
  28         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
  29         int rc = 0;
  30
  31         spin_lock(&afu->afu_cntl_lock);
  32         pr_devel("AFU command starting: %llx\n", command);
  33
  34         trace_cxl_afu_ctrl(afu, command);
  35
  36         AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
  37         cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command);
  38
  39         AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
  40         while ((AFU_Cntl & mask) != result) {
  41                 if (time_after_eq(jiffies, timeout)) {
  42                         dev_warn(&afu->dev, "WARNING: AFU control timed out!\n");
  43                         rc = -EBUSY;
  44                         goto out;
  45                 }
  46
  47                 if (!cxl_ops->link_ok(afu->adapter, afu)) {
  48                         afu->enabled = enabled;
  49                         rc = -EIO;
  50                         goto out;
  51                 }
  52
  53                 pr_devel_ratelimited("AFU control... (0x%016llx)\n",
  54                                      AFU_Cntl | command);
  55                 cpu_relax();
  56                 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
  57         }
  58
  59         if (AFU_Cntl & CXL_AFU_Cntl_An_RA) {
  60                 /*
  61                  * Workaround for a bug in the XSL used in the Mellanox CX4
  62                  * that fails to clear the RA bit after an AFU reset,
  63                  * preventing subsequent AFU resets from working.
  64                  */
  65                 cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA);
  66         }
  67
  68         pr_devel("AFU command complete: %llx\n", command);
  69         afu->enabled = enabled;
  70 out:
  71         trace_cxl_afu_ctrl_done(afu, command, rc);
  72         spin_unlock(&afu->afu_cntl_lock);
  73
  74         return rc;
  75 }
  76
  77 static int afu_enable(struct cxl_afu *afu)
  78 {
  79         pr_devel("AFU enable request\n");
  80
  81         return afu_control(afu, CXL_AFU_Cntl_An_E, 0,
  82                            CXL_AFU_Cntl_An_ES_Enabled,
  83                            CXL_AFU_Cntl_An_ES_MASK, true);
  84 }
  85
  86 int cxl_afu_disable(struct cxl_afu *afu)
  87 {
  88         pr_devel("AFU disable request\n");
  89
  90         return afu_control(afu, 0, CXL_AFU_Cntl_An_E,
  91                            CXL_AFU_Cntl_An_ES_Disabled,
  92                            CXL_AFU_Cntl_An_ES_MASK, false);
  93 }
  94
  95 /* This will disable as well as reset */
  96 static int native_afu_reset(struct cxl_afu *afu)
  97 {
  98         int rc;
  99         u64 serr;
 100
 101         pr_devel("AFU reset request\n");
 102
 103         rc = afu_control(afu, CXL_AFU_Cntl_An_RA, 0,
 104                            CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled,
 105                            CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK,
 106                            false);
 107
 108         /*
 109          * Re-enable any masked interrupts when the AFU is not
 110          * activated to avoid side effects after attaching a process
 111          * in dedicated mode.
 112          */
 113         if (afu->current_mode == 0) {
 114                 serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
 115                 serr &= ~CXL_PSL_SERR_An_IRQ_MASKS;
 116                 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
 117         }
 118
 119         return rc;
 120 }
 121
 122 static int native_afu_check_and_enable(struct cxl_afu *afu)
 123 {
 124         if (!cxl_ops->link_ok(afu->adapter, afu)) {
 125                 WARN(1, "Refusing to enable afu while link down!\n");
 126                 return -EIO;
 127         }
 128         if (afu->enabled)
 129                 return 0;
 130         return afu_enable(afu);
 131 }
 132
 133 int cxl_psl_purge(struct cxl_afu *afu)
 134 {
 135         u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
 136         u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
 137         u64 dsisr, dar;
 138         u64 start, end;
 139         u64 trans_fault = 0x0ULL;
 140         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 141         int rc = 0;
 142
 143         trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc);
 144
 145         pr_devel("PSL purge request\n");
 146
 147         if (cxl_is_power8())
 148                 trans_fault = CXL_PSL_DSISR_TRANS;
 149         if (cxl_is_power9())
 150                 trans_fault = CXL_PSL9_DSISR_An_TF;
 151
 152         if (!cxl_ops->link_ok(afu->adapter, afu)) {
 153                 dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n");
 154                 rc = -EIO;
 155                 goto out;
 156         }
 157
 158         if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
 159                 WARN(1, "psl_purge request while AFU not disabled!\n");
 160                 cxl_afu_disable(afu);
 161         }
 162
 163         cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
 164                        PSL_CNTL | CXL_PSL_SCNTL_An_Pc);
 165         start = local_clock();
 166         PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
 167         while ((PSL_CNTL &  CXL_PSL_SCNTL_An_Ps_MASK)
 168                         == CXL_PSL_SCNTL_An_Ps_Pending) {
 169                 if (time_after_eq(jiffies, timeout)) {
 170                         dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n");
 171                         rc = -EBUSY;
 172                         goto out;
 173                 }
 174                 if (!cxl_ops->link_ok(afu->adapter, afu)) {
 175                         rc = -EIO;
 176                         goto out;
 177                 }
 178
 179                 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
 180                 pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx  PSL_DSISR: 0x%016llx\n",
 181                                      PSL_CNTL, dsisr);
 182
 183                 if (dsisr & trans_fault) {
 184                         dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
 185                         dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n",
 186                                    dsisr, dar);
 187                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
 188                 } else if (dsisr) {
 189                         dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n",
 190                                    dsisr);
 191                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
 192                 } else {
 193                         cpu_relax();
 194                 }
 195                 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
 196         }
 197         end = local_clock();
 198         pr_devel("PSL purged in %lld ns\n", end - start);
 199
 200         cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
 201                        PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc);
 202 out:
 203         trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc);
 204         return rc;
 205 }
 206
 207 static int spa_max_procs(int spa_size)
 208 {
 209         /*
 210          * From the CAIA:
 211          *    end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255
 212          * Most of that junk is really just an overly-complicated way of saying
 213          * the last 256 bytes are __aligned(128), so it's really:
 214          *    end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255
 215          * and
 216          *    end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1
 217          * so
 218          *    sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256
 219          * Ignore the alignment (which is safe in this case as long as we are
 220          * careful with our rounding) and solve for n:
 221          */
 222         return ((spa_size / 8) - 96) / 17;
 223 }
 224
 225 static int cxl_alloc_spa(struct cxl_afu *afu, int mode)
 226 {
 227         unsigned spa_size;
 228
 229         /* Work out how many pages to allocate */
 230         afu->native->spa_order = -1;
 231         do {
 232                 afu->native->spa_order++;
 233                 spa_size = (1 << afu->native->spa_order) * PAGE_SIZE;
 234
 235                 if (spa_size > 0x100000) {
 236                         dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n",
 237                                         afu->native->spa_max_procs, afu->native->spa_size);
 238                         if (mode != CXL_MODE_DEDICATED)
 239                                 afu->num_procs = afu->native->spa_max_procs;
 240                         break;
 241                 }
 242
 243                 afu->native->spa_size = spa_size;
 244                 afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size);
 245         } while (afu->native->spa_max_procs < afu->num_procs);
 246
 247         if (!(afu->native->spa = (struct cxl_process_element *)
 248               __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) {
 249                 pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n");
 250                 return -ENOMEM;
 251         }
 252         pr_devel("spa pages: %i afu->spa_max_procs: %i   afu->num_procs: %i\n",
 253                  1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs);
 254
 255         return 0;
 256 }
 257
 258 static void attach_spa(struct cxl_afu *afu)
 259 {
 260         u64 spap;
 261
 262         afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa +
 263                                             ((afu->native->spa_max_procs + 3) * 128));
 264
 265         spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr;
 266         spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size;
 267         spap |= CXL_PSL_SPAP_V;
 268         pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n",
 269                 afu->native->spa, afu->native->spa_max_procs,
 270                 afu->native->sw_command_status, spap);
 271         cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);
 272 }
 273
 274 static inline void detach_spa(struct cxl_afu *afu)
 275 {
 276         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);
 277 }
 278
 279 void cxl_release_spa(struct cxl_afu *afu)
 280 {
 281         if (afu->native->spa) {
 282                 free_pages((unsigned long) afu->native->spa,
 283                         afu->native->spa_order);
 284                 afu->native->spa = NULL;
 285         }
 286 }
 287
 288 /*
 289  * Invalidation of all ERAT entries is no longer required by CAIA2. Use
 290  * only for debug.
 291  */
 292 int cxl_invalidate_all_psl9(struct cxl *adapter)
 293 {
 294         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 295         u64 ierat;
 296
 297         pr_devel("CXL adapter - invalidation of all ERAT entries\n");
 298
 299         /* Invalidates all ERAT entries for Radix or HPT */
 300         ierat = CXL_XSL9_IERAT_IALL;
 301         if (radix_enabled())
 302                 ierat |= CXL_XSL9_IERAT_INVR;
 303         cxl_p1_write(adapter, CXL_XSL9_IERAT, ierat);
 304
 305         while (cxl_p1_read(adapter, CXL_XSL9_IERAT) & CXL_XSL9_IERAT_IINPROG) {
 306                 if (time_after_eq(jiffies, timeout)) {
 307                         dev_warn(&adapter->dev,
 308                         "WARNING: CXL adapter invalidation of all ERAT entries timed out!\n");
 309                         return -EBUSY;
 310                 }
 311                 if (!cxl_ops->link_ok(adapter, NULL))
 312                         return -EIO;
 313                 cpu_relax();
 314         }
 315         return 0;
 316 }
 317
 318 int cxl_invalidate_all_psl8(struct cxl *adapter)
 319 {
 320         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 321
 322         pr_devel("CXL adapter wide TLBIA & SLBIA\n");
 323
 324         cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A);
 325
 326         cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL);
 327         while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) {
 328                 if (time_after_eq(jiffies, timeout)) {
 329                         dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n");
 330                         return -EBUSY;
 331                 }
 332                 if (!cxl_ops->link_ok(adapter, NULL))
 333                         return -EIO;
 334                 cpu_relax();
 335         }
 336
 337         cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL);
 338         while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) {
 339                 if (time_after_eq(jiffies, timeout)) {
 340                         dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n");
 341                         return -EBUSY;
 342                 }
 343                 if (!cxl_ops->link_ok(adapter, NULL))
 344                         return -EIO;
 345                 cpu_relax();
 346         }
 347         return 0;
 348 }
 349
 350 int cxl_data_cache_flush(struct cxl *adapter)
 351 {
 352         u64 reg;
 353         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 354
 355         /*
 356          * Do a datacache flush only if datacache is available.
 357          * In case of PSL9D datacache absent hence flush operation.
 358          * would timeout.
 359          */
 360         if (adapter->native->no_data_cache) {
 361                 pr_devel("No PSL data cache. Ignoring cache flush req.\n");
 362                 return 0;
 363         }
 364
 365         pr_devel("Flushing data cache\n");
 366         reg = cxl_p1_read(adapter, CXL_PSL_Control);
 367         reg |= CXL_PSL_Control_Fr;
 368         cxl_p1_write(adapter, CXL_PSL_Control, reg);
 369
 370         reg = cxl_p1_read(adapter, CXL_PSL_Control);
 371         while ((reg & CXL_PSL_Control_Fs_MASK) != CXL_PSL_Control_Fs_Complete) {
 372                 if (time_after_eq(jiffies, timeout)) {
 373                         dev_warn(&adapter->dev, "WARNING: cache flush timed out!\n");
 374                         return -EBUSY;
 375                 }
 376
 377                 if (!cxl_ops->link_ok(adapter, NULL)) {
 378                         dev_warn(&adapter->dev, "WARNING: link down when flushing cache\n");
 379                         return -EIO;
 380                 }
 381                 cpu_relax();
 382                 reg = cxl_p1_read(adapter, CXL_PSL_Control);
 383         }
 384
 385         reg &= ~CXL_PSL_Control_Fr;
 386         cxl_p1_write(adapter, CXL_PSL_Control, reg);
 387         return 0;
 388 }
 389
 390 static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1)
 391 {
 392         int rc;
 393
 394         /* 1. Disable SSTP by writing 0 to SSTP1[V] */
 395         cxl_p2n_write(afu, CXL_SSTP1_An, 0);
 396
 397         /* 2. Invalidate all SLB entries */
 398         if ((rc = cxl_afu_slbia(afu)))
 399                 return rc;
 400
 401         /* 3. Set SSTP0_An */
 402         cxl_p2n_write(afu, CXL_SSTP0_An, sstp0);
 403
 404         /* 4. Set SSTP1_An */
 405         cxl_p2n_write(afu, CXL_SSTP1_An, sstp1);
 406
 407         return 0;
 408 }
 409
 410 /* Using per slice version may improve performance here. (ie. SLBIA_An) */
 411 static void slb_invalid(struct cxl_context *ctx)
 412 {
 413         struct cxl *adapter = ctx->afu->adapter;
 414         u64 slbia;
 415
 416         WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex));
 417
 418         cxl_p1_write(adapter, CXL_PSL_LBISEL,
 419                         ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) |
 420                         be32_to_cpu(ctx->elem->lpid));
 421         cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID);
 422
 423         while (1) {
 424                 if (!cxl_ops->link_ok(adapter, NULL))
 425                         break;
 426                 slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA);
 427                 if (!(slbia & CXL_TLB_SLB_P))
 428                         break;
 429                 cpu_relax();
 430         }
 431 }
 432
 433 static int do_process_element_cmd(struct cxl_context *ctx,
 434                                   u64 cmd, u64 pe_state)
 435 {
 436         u64 state;
 437         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 438         int rc = 0;
 439
 440         trace_cxl_llcmd(ctx, cmd);
 441
 442         WARN_ON(!ctx->afu->enabled);
 443
 444         ctx->elem->software_state = cpu_to_be32(pe_state);
 445         smp_wmb();
 446         *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
 447         smp_mb();
 448         cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
 449         while (1) {
 450                 if (time_after_eq(jiffies, timeout)) {
 451                         dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
 452                         rc = -EBUSY;
 453                         goto out;
 454                 }
 455                 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
 456                         dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
 457                         rc = -EIO;
 458                         goto out;
 459                 }
 460                 state = be64_to_cpup(ctx->afu->native->sw_command_status);
 461                 if (state == ~0ULL) {
 462                         pr_err("cxl: Error adding process element to AFU\n");
 463                         rc = -1;
 464                         goto out;
 465                 }
 466                 if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK  | CXL_SPA_SW_LINK_MASK)) ==
 467                     (cmd | (cmd >> 16) | ctx->pe))
 468                         break;
 469                 /*
 470                  * The command won't finish in the PSL if there are
 471                  * outstanding DSIs.  Hence we need to yield here in
 472                  * case there are outstanding DSIs that we need to
 473                  * service.  Tuning possiblity: we could wait for a
 474                  * while before sched
 475                  */
 476                 schedule();
 477
 478         }
 479 out:
 480         trace_cxl_llcmd_done(ctx, cmd, rc);
 481         return rc;
 482 }
 483
 484 static int add_process_element(struct cxl_context *ctx)
 485 {
 486         int rc = 0;
 487
 488         mutex_lock(&ctx->afu->native->spa_mutex);
 489         pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
 490         if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V)))
 491                 ctx->pe_inserted = true;
 492         pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
 493         mutex_unlock(&ctx->afu->native->spa_mutex);
 494         return rc;
 495 }
 496
 497 static int terminate_process_element(struct cxl_context *ctx)
 498 {
 499         int rc = 0;
 500
 501         /* fast path terminate if it's already invalid */
 502         if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V)))
 503                 return rc;
 504
 505         mutex_lock(&ctx->afu->native->spa_mutex);
 506         pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
 507         /* We could be asked to terminate when the hw is down. That
 508          * should always succeed: it's not running if the hw has gone
 509          * away and is being reset.
 510          */
 511         if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
 512                 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
 513                                             CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T);
 514         ctx->elem->software_state = 0;  /* Remove Valid bit */
 515         pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
 516         mutex_unlock(&ctx->afu->native->spa_mutex);
 517         return rc;
 518 }
 519
 520 static int remove_process_element(struct cxl_context *ctx)
 521 {
 522         int rc = 0;
 523
 524         mutex_lock(&ctx->afu->native->spa_mutex);
 525         pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
 526
 527         /* We could be asked to remove when the hw is down. Again, if
 528          * the hw is down, the PE is gone, so we succeed.
 529          */
 530         if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
 531                 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0);
 532
 533         if (!rc)
 534                 ctx->pe_inserted = false;
 535         if (cxl_is_power8())
 536                 slb_invalid(ctx);
 537         pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
 538         mutex_unlock(&ctx->afu->native->spa_mutex);
 539
 540         return rc;
 541 }
 542
 543 void cxl_assign_psn_space(struct cxl_context *ctx)
 544 {
 545         if (!ctx->afu->pp_size || ctx->master) {
 546                 ctx->psn_phys = ctx->afu->psn_phys;
 547                 ctx->psn_size = ctx->afu->adapter->ps_size;
 548         } else {
 549                 ctx->psn_phys = ctx->afu->psn_phys +
 550                         (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe);
 551                 ctx->psn_size = ctx->afu->pp_size;
 552         }
 553 }
 554
 555 static int activate_afu_directed(struct cxl_afu *afu)
 556 {
 557         int rc;
 558
 559         dev_info(&afu->dev, "Activating AFU directed mode\n");
 560
 561         afu->num_procs = afu->max_procs_virtualised;
 562         if (afu->native->spa == NULL) {
 563                 if (cxl_alloc_spa(afu, CXL_MODE_DIRECTED))
 564                         return -ENOMEM;
 565         }
 566         attach_spa(afu);
 567
 568         cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);
 569         if (cxl_is_power8())
 570                 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
 571         cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
 572
 573         afu->current_mode = CXL_MODE_DIRECTED;
 574
 575         if ((rc = cxl_chardev_m_afu_add(afu)))
 576                 return rc;
 577
 578         if ((rc = cxl_sysfs_afu_m_add(afu)))
 579                 goto err;
 580
 581         if ((rc = cxl_chardev_s_afu_add(afu)))
 582                 goto err1;
 583
 584         return 0;
 585 err1:
 586         cxl_sysfs_afu_m_remove(afu);
 587 err:
 588         cxl_chardev_afu_remove(afu);
 589         return rc;
 590 }
 591
 592 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 593 #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
 594 #else
 595 #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
 596 #endif
 597
 598 u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9)
 599 {
 600         u64 sr = 0;
 601
 602         set_endian(sr);
 603         if (master)
 604                 sr |= CXL_PSL_SR_An_MP;
 605         if (mfspr(SPRN_LPCR) & LPCR_TC)
 606                 sr |= CXL_PSL_SR_An_TC;
 607         if (kernel) {
 608                 if (!real_mode)
 609                         sr |= CXL_PSL_SR_An_R;
 610                 sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV;
 611         } else {
 612                 sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
 613                 if (radix_enabled())
 614                         sr |= CXL_PSL_SR_An_HV;
 615                 else
 616                         sr &= ~(CXL_PSL_SR_An_HV);
 617                 if (!test_tsk_thread_flag(current, TIF_32BIT))
 618                         sr |= CXL_PSL_SR_An_SF;
 619         }
 620         if (p9) {
 621                 if (radix_enabled())
 622                         sr |= CXL_PSL_SR_An_XLAT_ror;
 623                 else
 624                         sr |= CXL_PSL_SR_An_XLAT_hpt;
 625         }
 626         return sr;
 627 }
 628
 629 static u64 calculate_sr(struct cxl_context *ctx)
 630 {
 631         return cxl_calculate_sr(ctx->master, ctx->kernel, ctx->real_mode,
 632                                 cxl_is_power9());
 633 }
 634
 635 static void update_ivtes_directed(struct cxl_context *ctx)
 636 {
 637         bool need_update = (ctx->status == STARTED);
 638         int r;
 639
 640         if (need_update) {
 641                 WARN_ON(terminate_process_element(ctx));
 642                 WARN_ON(remove_process_element(ctx));
 643         }
 644
 645         for (r = 0; r < CXL_IRQ_RANGES; r++) {
 646                 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
 647                 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
 648         }
 649
 650         /*
 651          * Theoretically we could use the update llcmd, instead of a
 652          * terminate/remove/add (or if an atomic update was required we could
 653          * do a suspend/update/resume), however it seems there might be issues
 654          * with the update llcmd on some cards (including those using an XSL on
 655          * an ASIC) so for now it's safest to go with the commands that are
 656          * known to work. In the future if we come across a situation where the
 657          * card may be performing transactions using the same PE while we are
 658          * doing this update we might need to revisit this.
 659          */
 660         if (need_update)
 661                 WARN_ON(add_process_element(ctx));
 662 }
 663
 664 static int process_element_entry_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
 665 {
 666         u32 pid;
 667
 668         cxl_assign_psn_space(ctx);
 669
 670         ctx->elem->ctxtime = 0; /* disable */
 671         ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
 672         ctx->elem->haurp = 0; /* disable */
 673
 674         if (ctx->kernel)
 675                 pid = 0;
 676         else {
 677                 if (ctx->mm == NULL) {
 678                         pr_devel("%s: unable to get mm for pe=%d pid=%i\n",
 679                                 __func__, ctx->pe, pid_nr(ctx->pid));
 680                         return -EINVAL;
 681                 }
 682                 pid = ctx->mm->context.id;
 683         }
 684
 685         ctx->elem->common.tid = 0;
 686         ctx->elem->common.pid = cpu_to_be32(pid);
 687
 688         ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
 689
 690         ctx->elem->common.csrp = 0; /* disable */
 691
 692         cxl_prefault(ctx, wed);
 693
 694         /*
 695          * Ensure we have the multiplexed PSL interrupt set up to take faults
 696          * for kernel contexts that may not have allocated any AFU IRQs at all:
 697          */
 698         if (ctx->irqs.range[0] == 0) {
 699                 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
 700                 ctx->irqs.range[0] = 1;
 701         }
 702
 703         ctx->elem->common.amr = cpu_to_be64(amr);
 704         ctx->elem->common.wed = cpu_to_be64(wed);
 705
 706         return 0;
 707 }
 708
 709 int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
 710 {
 711         int result;
 712
 713         /* fill the process element entry */
 714         result = process_element_entry_psl9(ctx, wed, amr);
 715         if (result)
 716                 return result;
 717
 718         update_ivtes_directed(ctx);
 719
 720         /* first guy needs to enable */
 721         result = cxl_ops->afu_check_and_enable(ctx->afu);
 722         if (result)
 723                 return result;
 724
 725         return add_process_element(ctx);
 726 }
 727
 728 int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
 729 {
 730         u32 pid;
 731         int result;
 732
 733         cxl_assign_psn_space(ctx);
 734
 735         ctx->elem->ctxtime = 0; /* disable */
 736         ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
 737         ctx->elem->haurp = 0; /* disable */
 738         ctx->elem->u.sdr = cpu_to_be64(mfspr(SPRN_SDR1));
 739
 740         pid = current->pid;
 741         if (ctx->kernel)
 742                 pid = 0;
 743         ctx->elem->common.tid = 0;
 744         ctx->elem->common.pid = cpu_to_be32(pid);
 745
 746         ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
 747
 748         ctx->elem->common.csrp = 0; /* disable */
 749         ctx->elem->common.u.psl8.aurp0 = 0; /* disable */
 750         ctx->elem->common.u.psl8.aurp1 = 0; /* disable */
 751
 752         cxl_prefault(ctx, wed);
 753
 754         ctx->elem->common.u.psl8.sstp0 = cpu_to_be64(ctx->sstp0);
 755         ctx->elem->common.u.psl8.sstp1 = cpu_to_be64(ctx->sstp1);
 756
 757         /*
 758          * Ensure we have the multiplexed PSL interrupt set up to take faults
 759          * for kernel contexts that may not have allocated any AFU IRQs at all:
 760          */
 761         if (ctx->irqs.range[0] == 0) {
 762                 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
 763                 ctx->irqs.range[0] = 1;
 764         }
 765
 766         update_ivtes_directed(ctx);
 767
 768         ctx->elem->common.amr = cpu_to_be64(amr);
 769         ctx->elem->common.wed = cpu_to_be64(wed);
 770
 771         /* first guy needs to enable */
 772         if ((result = cxl_ops->afu_check_and_enable(ctx->afu)))
 773                 return result;
 774
 775         return add_process_element(ctx);
 776 }
 777
 778 static int deactivate_afu_directed(struct cxl_afu *afu)
 779 {
 780         dev_info(&afu->dev, "Deactivating AFU directed mode\n");
 781
 782         afu->current_mode = 0;
 783         afu->num_procs = 0;
 784
 785         cxl_sysfs_afu_m_remove(afu);
 786         cxl_chardev_afu_remove(afu);
 787
 788         /*
 789          * The CAIA section 2.2.1 indicates that the procedure for starting and
 790          * stopping an AFU in AFU directed mode is AFU specific, which is not
 791          * ideal since this code is generic and with one exception has no
 792          * knowledge of the AFU. This is in contrast to the procedure for
 793          * disabling a dedicated process AFU, which is documented to just
 794          * require a reset. The architecture does indicate that both an AFU
 795          * reset and an AFU disable should result in the AFU being disabled and
 796          * we do both followed by a PSL purge for safety.
 797          *
 798          * Notably we used to have some issues with the disable sequence on PSL
 799          * cards, which is why we ended up using this heavy weight procedure in
 800          * the first place, however a bug was discovered that had rendered the
 801          * disable operation ineffective, so it is conceivable that was the
 802          * sole explanation for those difficulties. Careful regression testing
 803          * is recommended if anyone attempts to remove or reorder these
 804          * operations.
 805          *
 806          * The XSL on the Mellanox CX4 behaves a little differently from the
 807          * PSL based cards and will time out an AFU reset if the AFU is still
 808          * enabled. That card is special in that we do have a means to identify
 809          * it from this code, so in that case we skip the reset and just use a
 810          * disable/purge to avoid the timeout and corresponding noise in the
 811          * kernel log.
 812          */
 813         if (afu->adapter->native->sl_ops->needs_reset_before_disable)
 814                 cxl_ops->afu_reset(afu);
 815         cxl_afu_disable(afu);
 816         cxl_psl_purge(afu);
 817
 818         return 0;
 819 }
 820
 821 int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu)
 822 {
 823         dev_info(&afu->dev, "Activating dedicated process mode\n");
 824
 825         /*
 826          * If XSL is set to dedicated mode (Set in PSL_SCNTL reg), the
 827          * XSL and AFU are programmed to work with a single context.
 828          * The context information should be configured in the SPA area
 829          * index 0 (so PSL_SPAP must be configured before enabling the
 830          * AFU).
 831          */
 832         afu->num_procs = 1;
 833         if (afu->native->spa == NULL) {
 834                 if (cxl_alloc_spa(afu, CXL_MODE_DEDICATED))
 835                         return -ENOMEM;
 836         }
 837         attach_spa(afu);
 838
 839         cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
 840         cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
 841
 842         afu->current_mode = CXL_MODE_DEDICATED;
 843
 844         return cxl_chardev_d_afu_add(afu);
 845 }
 846
 847 int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu)
 848 {
 849         dev_info(&afu->dev, "Activating dedicated process mode\n");
 850
 851         cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
 852
 853         cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */
 854         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);    /* disable */
 855         cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
 856         cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID));
 857         cxl_p1n_write(afu, CXL_HAURP_An, 0);       /* disable */
 858         cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1));
 859
 860         cxl_p2n_write(afu, CXL_CSRP_An, 0);        /* disable */
 861         cxl_p2n_write(afu, CXL_AURP0_An, 0);       /* disable */
 862         cxl_p2n_write(afu, CXL_AURP1_An, 0);       /* disable */
 863
 864         afu->current_mode = CXL_MODE_DEDICATED;
 865         afu->num_procs = 1;
 866
 867         return cxl_chardev_d_afu_add(afu);
 868 }
 869
 870 void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx)
 871 {
 872         int r;
 873
 874         for (r = 0; r < CXL_IRQ_RANGES; r++) {
 875                 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
 876                 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
 877         }
 878 }
 879
 880 void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx)
 881 {
 882         struct cxl_afu *afu = ctx->afu;
 883
 884         cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An,
 885                        (((u64)ctx->irqs.offset[0] & 0xffff) << 48) |
 886                        (((u64)ctx->irqs.offset[1] & 0xffff) << 32) |
 887                        (((u64)ctx->irqs.offset[2] & 0xffff) << 16) |
 888                         ((u64)ctx->irqs.offset[3] & 0xffff));
 889         cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64)
 890                        (((u64)ctx->irqs.range[0] & 0xffff) << 48) |
 891                        (((u64)ctx->irqs.range[1] & 0xffff) << 32) |
 892                        (((u64)ctx->irqs.range[2] & 0xffff) << 16) |
 893                         ((u64)ctx->irqs.range[3] & 0xffff));
 894 }
 895
 896 int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
 897 {
 898         struct cxl_afu *afu = ctx->afu;
 899         int result;
 900
 901         /* fill the process element entry */
 902         result = process_element_entry_psl9(ctx, wed, amr);
 903         if (result)
 904                 return result;
 905
 906         if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
 907                 afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
 908
 909         result = cxl_ops->afu_reset(afu);
 910         if (result)
 911                 return result;
 912
 913         return afu_enable(afu);
 914 }
 915
 916 int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
 917 {
 918         struct cxl_afu *afu = ctx->afu;
 919         u64 pid;
 920         int rc;
 921
 922         pid = (u64)current->pid << 32;
 923         if (ctx->kernel)
 924                 pid = 0;
 925         cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid);
 926
 927         cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
 928
 929         if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
 930                 return rc;
 931
 932         cxl_prefault(ctx, wed);
 933
 934         if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
 935                 afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
 936
 937         cxl_p2n_write(afu, CXL_PSL_AMR_An, amr);
 938
 939         /* master only context for dedicated */
 940         cxl_assign_psn_space(ctx);
 941
 942         if ((rc = cxl_ops->afu_reset(afu)))
 943                 return rc;
 944
 945         cxl_p2n_write(afu, CXL_PSL_WED_An, wed);
 946
 947         return afu_enable(afu);
 948 }
 949
 950 static int deactivate_dedicated_process(struct cxl_afu *afu)
 951 {
 952         dev_info(&afu->dev, "Deactivating dedicated process mode\n");
 953
 954         afu->current_mode = 0;
 955         afu->num_procs = 0;
 956
 957         cxl_chardev_afu_remove(afu);
 958
 959         return 0;
 960 }
 961
 962 static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode)
 963 {
 964         if (mode == CXL_MODE_DIRECTED)
 965                 return deactivate_afu_directed(afu);
 966         if (mode == CXL_MODE_DEDICATED)
 967                 return deactivate_dedicated_process(afu);
 968         return 0;
 969 }
 970
 971 static int native_afu_activate_mode(struct cxl_afu *afu, int mode)
 972 {
 973         if (!mode)
 974                 return 0;
 975         if (!(mode & afu->modes_supported))
 976                 return -EINVAL;
 977
 978         if (!cxl_ops->link_ok(afu->adapter, afu)) {
 979                 WARN(1, "Device link is down, refusing to activate!\n");
 980                 return -EIO;
 981         }
 982
 983         if (mode == CXL_MODE_DIRECTED)
 984                 return activate_afu_directed(afu);
 985         if ((mode == CXL_MODE_DEDICATED) &&
 986             (afu->adapter->native->sl_ops->activate_dedicated_process))
 987                 return afu->adapter->native->sl_ops->activate_dedicated_process(afu);
 988
 989         return -EINVAL;
 990 }
 991
 992 static int native_attach_process(struct cxl_context *ctx, bool kernel,
 993                                 u64 wed, u64 amr)
 994 {
 995         if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
 996                 WARN(1, "Device link is down, refusing to attach process!\n");
 997                 return -EIO;
 998         }
 999
1000         ctx->kernel = kernel;
1001         if ((ctx->afu->current_mode == CXL_MODE_DIRECTED) &&
1002             (ctx->afu->adapter->native->sl_ops->attach_afu_directed))
1003                 return ctx->afu->adapter->native->sl_ops->attach_afu_directed(ctx, wed, amr);
1004
1005         if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
1006             (ctx->afu->adapter->native->sl_ops->attach_dedicated_process))
1007                 return ctx->afu->adapter->native->sl_ops->attach_dedicated_process(ctx, wed, amr);
1008
1009         return -EINVAL;
1010 }
1011
1012 static inline int detach_process_native_dedicated(struct cxl_context *ctx)
1013 {
1014         /*
1015          * The CAIA section 2.1.1 indicates that we need to do an AFU reset to
1016          * stop the AFU in dedicated mode (we therefore do not make that
1017          * optional like we do in the afu directed path). It does not indicate
1018          * that we need to do an explicit disable (which should occur
1019          * implicitly as part of the reset) or purge, but we do these as well
1020          * to be on the safe side.
1021          *
1022          * Notably we used to have some issues with the disable sequence
1023          * (before the sequence was spelled out in the architecture) which is
1024          * why we were so heavy weight in the first place, however a bug was
1025          * discovered that had rendered the disable operation ineffective, so
1026          * it is conceivable that was the sole explanation for those
1027          * difficulties. Point is, we should be careful and do some regression
1028          * testing if we ever attempt to remove any part of this procedure.
1029          */
1030         cxl_ops->afu_reset(ctx->afu);
1031         cxl_afu_disable(ctx->afu);
1032         cxl_psl_purge(ctx->afu);
1033         return 0;
1034 }
1035
1036 static void native_update_ivtes(struct cxl_context *ctx)
1037 {
1038         if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
1039                 return update_ivtes_directed(ctx);
1040         if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
1041             (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes))
1042                 return ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
1043         WARN(1, "native_update_ivtes: Bad mode\n");
1044 }
1045
1046 static inline int detach_process_native_afu_directed(struct cxl_context *ctx)
1047 {
1048         if (!ctx->pe_inserted)
1049                 return 0;
1050         if (terminate_process_element(ctx))
1051                 return -1;
1052         if (remove_process_element(ctx))
1053                 return -1;
1054
1055         return 0;
1056 }
1057
1058 static int native_detach_process(struct cxl_context *ctx)
1059 {
1060         trace_cxl_detach(ctx);
1061
1062         if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
1063                 return detach_process_native_dedicated(ctx);
1064
1065         return detach_process_native_afu_directed(ctx);
1066 }
1067
1068 static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)
1069 {
1070         /* If the adapter has gone away, we can't get any meaningful
1071          * information.
1072          */
1073         if (!cxl_ops->link_ok(afu->adapter, afu))
1074                 return -EIO;
1075
1076         info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1077         info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
1078         if (cxl_is_power8())
1079                 info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
1080         info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);
1081         info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1082         info->proc_handle = 0;
1083
1084         return 0;
1085 }
1086
1087 void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx)
1088 {
1089         u64 fir1, fir2, serr;
1090
1091         fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR1);
1092         fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR2);
1093
1094         dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
1095         dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
1096         if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
1097                 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
1098                 cxl_afu_decode_psl_serr(ctx->afu, serr);
1099         }
1100 }
1101
1102 void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx)
1103 {
1104         u64 fir1, fir2, fir_slice, serr, afu_debug;
1105
1106         fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1);
1107         fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2);
1108         fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An);
1109         afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
1110
1111         dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
1112         dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
1113         if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
1114                 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
1115                 cxl_afu_decode_psl_serr(ctx->afu, serr);
1116         }
1117         dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
1118         dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
1119 }
1120
1121 static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx,
1122                                                 u64 dsisr, u64 errstat)
1123 {
1124
1125         dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat);
1126
1127         if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers)
1128                 ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx);
1129
1130         if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) {
1131                 dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
1132                 ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter);
1133         }
1134
1135         return cxl_ops->ack_irq(ctx, 0, errstat);
1136 }
1137
1138 static bool cxl_is_translation_fault(struct cxl_afu *afu, u64 dsisr)
1139 {
1140         if ((cxl_is_power8()) && (dsisr & CXL_PSL_DSISR_TRANS))
1141                 return true;
1142
1143         if ((cxl_is_power9()) && (dsisr & CXL_PSL9_DSISR_An_TF))
1144                 return true;
1145
1146         return false;
1147 }
1148
1149 irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info)
1150 {
1151         if (cxl_is_translation_fault(afu, irq_info->dsisr))
1152                 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1153         else
1154                 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1155
1156         return IRQ_HANDLED;
1157 }
1158
1159 static irqreturn_t native_irq_multiplexed(int irq, void *data)
1160 {
1161         struct cxl_afu *afu = data;
1162         struct cxl_context *ctx;
1163         struct cxl_irq_info irq_info;
1164         u64 phreg = cxl_p2n_read(afu, CXL_PSL_PEHandle_An);
1165         int ph, ret = IRQ_HANDLED, res;
1166
1167         /* check if eeh kicked in while the interrupt was in flight */
1168         if (unlikely(phreg == ~0ULL)) {
1169                 dev_warn(&afu->dev,
1170                          "Ignoring slice interrupt(%d) due to fenced card",
1171                          irq);
1172                 return IRQ_HANDLED;
1173         }
1174         /* Mask the pe-handle from register value */
1175         ph = phreg & 0xffff;
1176         if ((res = native_get_irq_info(afu, &irq_info))) {
1177                 WARN(1, "Unable to get CXL IRQ Info: %i\n", res);
1178                 if (afu->adapter->native->sl_ops->fail_irq)
1179                         return afu->adapter->native->sl_ops->fail_irq(afu, &irq_info);
1180                 return ret;
1181         }
1182
1183         rcu_read_lock();
1184         ctx = idr_find(&afu->contexts_idr, ph);
1185         if (ctx) {
1186                 if (afu->adapter->native->sl_ops->handle_interrupt)
1187                         ret = afu->adapter->native->sl_ops->handle_interrupt(irq, ctx, &irq_info);
1188                 rcu_read_unlock();
1189                 return ret;
1190         }
1191         rcu_read_unlock();
1192
1193         WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR"
1194                 " %016llx\n(Possible AFU HW issue - was a term/remove acked"
1195                 " with outstanding transactions?)\n", ph, irq_info.dsisr,
1196                 irq_info.dar);
1197         if (afu->adapter->native->sl_ops->fail_irq)
1198                 ret = afu->adapter->native->sl_ops->fail_irq(afu, &irq_info);
1199         return ret;
1200 }
1201
1202 static void native_irq_wait(struct cxl_context *ctx)
1203 {
1204         u64 dsisr;
1205         int timeout = 1000;
1206         int ph;
1207
1208         /*
1209          * Wait until no further interrupts are presented by the PSL
1210          * for this context.
1211          */
1212         while (timeout--) {
1213                 ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff;
1214                 if (ph != ctx->pe)
1215                         return;
1216                 dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An);
1217                 if (cxl_is_power8() &&
1218                    ((dsisr & CXL_PSL_DSISR_PENDING) == 0))
1219                         return;
1220                 if (cxl_is_power9() &&
1221                    ((dsisr & CXL_PSL9_DSISR_PENDING) == 0))
1222                         return;
1223                 /*
1224                  * We are waiting for the workqueue to process our
1225                  * irq, so need to let that run here.
1226                  */
1227                 msleep(1);
1228         }
1229
1230         dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i"
1231                  " DSISR %016llx!\n", ph, dsisr);
1232         return;
1233 }
1234
1235 static irqreturn_t native_slice_irq_err(int irq, void *data)
1236 {
1237         struct cxl_afu *afu = data;
1238         u64 errstat, serr, afu_error, dsisr;
1239         u64 fir_slice, afu_debug, irq_mask;
1240
1241         /*
1242          * slice err interrupt is only used with full PSL (no XSL)
1243          */
1244         serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1245         errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1246         afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An);
1247         dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1248         cxl_afu_decode_psl_serr(afu, serr);
1249
1250         if (cxl_is_power8()) {
1251                 fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);
1252                 afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);
1253                 dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
1254                 dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
1255         }
1256         dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat);
1257         dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error);
1258         dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr);
1259
1260         /* mask off the IRQ so it won't retrigger until the AFU is reset */
1261         irq_mask = (serr & CXL_PSL_SERR_An_IRQS) >> 32;
1262         serr |= irq_mask;
1263         cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
1264         dev_info(&afu->dev, "Further such interrupts will be masked until the AFU is reset\n");
1265
1266         return IRQ_HANDLED;
1267 }
1268
1269 void cxl_native_err_irq_dump_regs(struct cxl *adapter)
1270 {
1271         u64 fir1, fir2;
1272
1273         fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
1274         fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
1275
1276         dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2);
1277 }
1278
1279 static irqreturn_t native_irq_err(int irq, void *data)
1280 {
1281         struct cxl *adapter = data;
1282         u64 err_ivte;
1283
1284         WARN(1, "CXL ERROR interrupt %i\n", irq);
1285
1286         err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE);
1287         dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte);
1288
1289         if (adapter->native->sl_ops->debugfs_stop_trace) {
1290                 dev_crit(&adapter->dev, "STOPPING CXL TRACE\n");
1291                 adapter->native->sl_ops->debugfs_stop_trace(adapter);
1292         }
1293
1294         if (adapter->native->sl_ops->err_irq_dump_registers)
1295                 adapter->native->sl_ops->err_irq_dump_registers(adapter);
1296
1297         return IRQ_HANDLED;
1298 }
1299
1300 int cxl_native_register_psl_err_irq(struct cxl *adapter)
1301 {
1302         int rc;
1303
1304         adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
1305                                       dev_name(&adapter->dev));
1306         if (!adapter->irq_name)
1307                 return -ENOMEM;
1308
1309         if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter,
1310                                        &adapter->native->err_hwirq,
1311                                        &adapter->native->err_virq,
1312                                        adapter->irq_name))) {
1313                 kfree(adapter->irq_name);
1314                 adapter->irq_name = NULL;
1315                 return rc;
1316         }
1317
1318         cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff);
1319
1320         return 0;
1321 }
1322
1323 void cxl_native_release_psl_err_irq(struct cxl *adapter)
1324 {
1325         if (adapter->native->err_virq == 0 ||
1326             adapter->native->err_virq !=
1327             irq_find_mapping(NULL, adapter->native->err_hwirq))
1328                 return;
1329
1330         cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
1331         cxl_unmap_irq(adapter->native->err_virq, adapter);
1332         cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq);
1333         kfree(adapter->irq_name);
1334         adapter->native->err_virq = 0;
1335 }
1336
1337 int cxl_native_register_serr_irq(struct cxl_afu *afu)
1338 {
1339         u64 serr;
1340         int rc;
1341
1342         afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
1343                                       dev_name(&afu->dev));
1344         if (!afu->err_irq_name)
1345                 return -ENOMEM;
1346
1347         if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu,
1348                                        &afu->serr_hwirq,
1349                                        &afu->serr_virq, afu->err_irq_name))) {
1350                 kfree(afu->err_irq_name);
1351                 afu->err_irq_name = NULL;
1352                 return rc;
1353         }
1354
1355         serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1356         if (cxl_is_power8())
1357                 serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);
1358         if (cxl_is_power9()) {
1359                 /*
1360                  * By default, all errors are masked. So don't set all masks.
1361                  * Slice errors will be transfered.
1362                  */
1363                 serr = (serr & ~0xff0000007fffffffULL) | (afu->serr_hwirq & 0xffff);
1364         }
1365         cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
1366
1367         return 0;
1368 }
1369
1370 void cxl_native_release_serr_irq(struct cxl_afu *afu)
1371 {
1372         if (afu->serr_virq == 0 ||
1373             afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq))
1374                 return;
1375
1376         cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000);
1377         cxl_unmap_irq(afu->serr_virq, afu);
1378         cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq);
1379         kfree(afu->err_irq_name);
1380         afu->serr_virq = 0;
1381 }
1382
1383 int cxl_native_register_psl_irq(struct cxl_afu *afu)
1384 {
1385         int rc;
1386
1387         afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s",
1388                                       dev_name(&afu->dev));
1389         if (!afu->psl_irq_name)
1390                 return -ENOMEM;
1391
1392         if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed,
1393                                     afu, &afu->native->psl_hwirq, &afu->native->psl_virq,
1394                                     afu->psl_irq_name))) {
1395                 kfree(afu->psl_irq_name);
1396                 afu->psl_irq_name = NULL;
1397         }
1398         return rc;
1399 }
1400
1401 void cxl_native_release_psl_irq(struct cxl_afu *afu)
1402 {
1403         if (afu->native->psl_virq == 0 ||
1404             afu->native->psl_virq !=
1405             irq_find_mapping(NULL, afu->native->psl_hwirq))
1406                 return;
1407
1408         cxl_unmap_irq(afu->native->psl_virq, afu);
1409         cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq);
1410         kfree(afu->psl_irq_name);
1411         afu->native->psl_virq = 0;
1412 }
1413
1414 static void recover_psl_err(struct cxl_afu *afu, u64 errstat)
1415 {
1416         u64 dsisr;
1417
1418         pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat);
1419
1420         /* Clear PSL_DSISR[PE] */
1421         dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1422         cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE);
1423
1424         /* Write 1s to clear error status bits */
1425         cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat);
1426 }
1427
1428 static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
1429 {
1430         trace_cxl_psl_irq_ack(ctx, tfc);
1431         if (tfc)
1432                 cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
1433         if (psl_reset_mask)
1434                 recover_psl_err(ctx->afu, psl_reset_mask);
1435
1436         return 0;
1437 }
1438
1439 int cxl_check_error(struct cxl_afu *afu)
1440 {
1441         return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
1442 }
1443
1444 static bool native_support_attributes(const char *attr_name,
1445                                       enum cxl_attrs type)
1446 {
1447         return true;
1448 }
1449
1450 static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out)
1451 {
1452         if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1453                 return -EIO;
1454         if (unlikely(off >= afu->crs_len))
1455                 return -ERANGE;
1456         *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset +
1457                 (cr * afu->crs_len) + off);
1458         return 0;
1459 }
1460
1461 static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out)
1462 {
1463         if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1464                 return -EIO;
1465         if (unlikely(off >= afu->crs_len))
1466                 return -ERANGE;
1467         *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset +
1468                 (cr * afu->crs_len) + off);
1469         return 0;
1470 }
1471
1472 static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out)
1473 {
1474         u64 aligned_off = off & ~0x3L;
1475         u32 val;
1476         int rc;
1477
1478         rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
1479         if (!rc)
1480                 *out = (val >> ((off & 0x3) * 8)) & 0xffff;
1481         return rc;
1482 }
1483
1484 static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out)
1485 {
1486         u64 aligned_off = off & ~0x3L;
1487         u32 val;
1488         int rc;
1489
1490         rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
1491         if (!rc)
1492                 *out = (val >> ((off & 0x3) * 8)) & 0xff;
1493         return rc;
1494 }
1495
1496 static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in)
1497 {
1498         if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1499                 return -EIO;
1500         if (unlikely(off >= afu->crs_len))
1501                 return -ERANGE;
1502         out_le32(afu->native->afu_desc_mmio + afu->crs_offset +
1503                 (cr * afu->crs_len) + off, in);
1504         return 0;
1505 }
1506
1507 static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in)
1508 {
1509         u64 aligned_off = off & ~0x3L;
1510         u32 val32, mask, shift;
1511         int rc;
1512
1513         rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
1514         if (rc)
1515                 return rc;
1516         shift = (off & 0x3) * 8;
1517         WARN_ON(shift == 24);
1518         mask = 0xffff << shift;
1519         val32 = (val32 & ~mask) | (in << shift);
1520
1521         rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
1522         return rc;
1523 }
1524
1525 static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in)
1526 {
1527         u64 aligned_off = off & ~0x3L;
1528         u32 val32, mask, shift;
1529         int rc;
1530
1531         rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
1532         if (rc)
1533                 return rc;
1534         shift = (off & 0x3) * 8;
1535         mask = 0xff << shift;
1536         val32 = (val32 & ~mask) | (in << shift);
1537
1538         rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
1539         return rc;
1540 }
1541
1542 const struct cxl_backend_ops cxl_native_ops = {
1543         .module = THIS_MODULE,
1544         .adapter_reset = cxl_pci_reset,
1545         .alloc_one_irq = cxl_pci_alloc_one_irq,
1546         .release_one_irq = cxl_pci_release_one_irq,
1547         .alloc_irq_ranges = cxl_pci_alloc_irq_ranges,
1548         .release_irq_ranges = cxl_pci_release_irq_ranges,
1549         .setup_irq = cxl_pci_setup_irq,
1550         .handle_psl_slice_error = native_handle_psl_slice_error,
1551         .psl_interrupt = NULL,
1552         .ack_irq = native_ack_irq,
1553         .irq_wait = native_irq_wait,
1554         .attach_process = native_attach_process,
1555         .detach_process = native_detach_process,
1556         .update_ivtes = native_update_ivtes,
1557         .support_attributes = native_support_attributes,
1558         .link_ok = cxl_adapter_link_ok,
1559         .release_afu = cxl_pci_release_afu,
1560         .afu_read_err_buffer = cxl_pci_afu_read_err_buffer,
1561         .afu_check_and_enable = native_afu_check_and_enable,
1562         .afu_activate_mode = native_afu_activate_mode,
1563         .afu_deactivate_mode = native_afu_deactivate_mode,
1564         .afu_reset = native_afu_reset,
1565         .afu_cr_read8 = native_afu_cr_read8,
1566         .afu_cr_read16 = native_afu_cr_read16,
1567         .afu_cr_read32 = native_afu_cr_read32,
1568         .afu_cr_read64 = native_afu_cr_read64,
1569         .afu_cr_write8 = native_afu_cr_write8,
1570         .afu_cr_write16 = native_afu_cr_write16,
1571         .afu_cr_write32 = native_afu_cr_write32,
1572         .read_adapter_vpd = cxl_pci_read_adapter_vpd,
1573 };