drivers/misc/cxl/pci.c

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #include <linux/pci_regs.h>
  11 #include <linux/pci_ids.h>
  12 #include <linux/device.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/sort.h>
  17 #include <linux/pci.h>
  18 #include <linux/of.h>
  19 #include <linux/delay.h>
  20 #include <asm/opal.h>
  21 #include <asm/msi_bitmap.h>
  22 #include <asm/pnv-pci.h>
  23 #include <asm/io.h>
  24 #include <asm/reg.h>
  25
  26 #include "cxl.h"
  27 #include <misc/cxl.h>
  28
  29
  30 #define CXL_PCI_VSEC_ID 0x1280
  31 #define CXL_VSEC_MIN_SIZE 0x80
  32
  33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest)                   \
  34         {                                                       \
  35                 pci_read_config_word(dev, vsec + 0x6, dest);    \
  36                 *dest >>= 4;                                    \
  37         }
  38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
  39         pci_read_config_byte(dev, vsec + 0x8, dest)
  40
  41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
  42         pci_read_config_byte(dev, vsec + 0x9, dest)
  43 #define CXL_STATUS_SECOND_PORT  0x80
  44 #define CXL_STATUS_MSI_X_FULL   0x40
  45 #define CXL_STATUS_MSI_X_SINGLE 0x20
  46 #define CXL_STATUS_FLASH_RW     0x08
  47 #define CXL_STATUS_FLASH_RO     0x04
  48 #define CXL_STATUS_LOADABLE_AFU 0x02
  49 #define CXL_STATUS_LOADABLE_PSL 0x01
  50 /* If we see these features we won't try to use the card */
  51 #define CXL_UNSUPPORTED_FEATURES \
  52         (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
  53
  54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
  55         pci_read_config_byte(dev, vsec + 0xa, dest)
  56 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
  57         pci_write_config_byte(dev, vsec + 0xa, val)
  58 #define CXL_VSEC_PROTOCOL_MASK   0xe0
  59 #define CXL_VSEC_PROTOCOL_1024TB 0x80
  60 #define CXL_VSEC_PROTOCOL_512TB  0x40
  61 #define CXL_VSEC_PROTOCOL_256TB  0x20 /* Power 8/9 uses this */
  62 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
  63
  64 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
  65         pci_read_config_word(dev, vsec + 0xc, dest)
  66 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
  67         pci_read_config_byte(dev, vsec + 0xe, dest)
  68 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
  69         pci_read_config_byte(dev, vsec + 0xf, dest)
  70 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
  71         pci_read_config_word(dev, vsec + 0x10, dest)
  72
  73 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
  74         pci_read_config_byte(dev, vsec + 0x13, dest)
  75 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
  76         pci_write_config_byte(dev, vsec + 0x13, val)
  77 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
  78 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
  79 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
  80
  81 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
  82         pci_read_config_dword(dev, vsec + 0x20, dest)
  83 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
  84         pci_read_config_dword(dev, vsec + 0x24, dest)
  85 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
  86         pci_read_config_dword(dev, vsec + 0x28, dest)
  87 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
  88         pci_read_config_dword(dev, vsec + 0x2c, dest)
  89
  90
  91 /* This works a little different than the p1/p2 register accesses to make it
  92  * easier to pull out individual fields */
  93 #define AFUD_READ(afu, off)             in_be64(afu->native->afu_desc_mmio + off)
  94 #define AFUD_READ_LE(afu, off)          in_le64(afu->native->afu_desc_mmio + off)
  95 #define EXTRACT_PPC_BIT(val, bit)       (!!(val & PPC_BIT(bit)))
  96 #define EXTRACT_PPC_BITS(val, bs, be)   ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
  97
  98 #define AFUD_READ_INFO(afu)             AFUD_READ(afu, 0x0)
  99 #define   AFUD_NUM_INTS_PER_PROC(val)   EXTRACT_PPC_BITS(val,  0, 15)
 100 #define   AFUD_NUM_PROCS(val)           EXTRACT_PPC_BITS(val, 16, 31)
 101 #define   AFUD_NUM_CRS(val)             EXTRACT_PPC_BITS(val, 32, 47)
 102 #define   AFUD_MULTIMODE(val)           EXTRACT_PPC_BIT(val, 48)
 103 #define   AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
 104 #define   AFUD_DEDICATED_PROCESS(val)   EXTRACT_PPC_BIT(val, 59)
 105 #define   AFUD_AFU_DIRECTED(val)        EXTRACT_PPC_BIT(val, 61)
 106 #define   AFUD_TIME_SLICED(val)         EXTRACT_PPC_BIT(val, 63)
 107 #define AFUD_READ_CR(afu)               AFUD_READ(afu, 0x20)
 108 #define   AFUD_CR_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
 109 #define AFUD_READ_CR_OFF(afu)           AFUD_READ(afu, 0x28)
 110 #define AFUD_READ_PPPSA(afu)            AFUD_READ(afu, 0x30)
 111 #define   AFUD_PPPSA_PP(val)            EXTRACT_PPC_BIT(val, 6)
 112 #define   AFUD_PPPSA_PSA(val)           EXTRACT_PPC_BIT(val, 7)
 113 #define   AFUD_PPPSA_LEN(val)           EXTRACT_PPC_BITS(val, 8, 63)
 114 #define AFUD_READ_PPPSA_OFF(afu)        AFUD_READ(afu, 0x38)
 115 #define AFUD_READ_EB(afu)               AFUD_READ(afu, 0x40)
 116 #define   AFUD_EB_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
 117 #define AFUD_READ_EB_OFF(afu)           AFUD_READ(afu, 0x48)
 118
 119 static const struct pci_device_id cxl_pci_tbl[] = {
 120         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
 121         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
 122         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
 123         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
 124         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
 125         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
 126         { }
 127 };
 128 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
 129
 130
 131 /*
 132  * Mostly using these wrappers to avoid confusion:
 133  * priv 1 is BAR2, while priv 2 is BAR0
 134  */
 135 static inline resource_size_t p1_base(struct pci_dev *dev)
 136 {
 137         return pci_resource_start(dev, 2);
 138 }
 139
 140 static inline resource_size_t p1_size(struct pci_dev *dev)
 141 {
 142         return pci_resource_len(dev, 2);
 143 }
 144
 145 static inline resource_size_t p2_base(struct pci_dev *dev)
 146 {
 147         return pci_resource_start(dev, 0);
 148 }
 149
 150 static inline resource_size_t p2_size(struct pci_dev *dev)
 151 {
 152         return pci_resource_len(dev, 0);
 153 }
 154
 155 static int find_cxl_vsec(struct pci_dev *dev)
 156 {
 157         int vsec = 0;
 158         u16 val;
 159
 160         while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
 161                 pci_read_config_word(dev, vsec + 0x4, &val);
 162                 if (val == CXL_PCI_VSEC_ID)
 163                         return vsec;
 164         }
 165         return 0;
 166
 167 }
 168
 169 static void dump_cxl_config_space(struct pci_dev *dev)
 170 {
 171         int vsec;
 172         u32 val;
 173
 174         dev_info(&dev->dev, "dump_cxl_config_space\n");
 175
 176         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
 177         dev_info(&dev->dev, "BAR0: %#.8x\n", val);
 178         pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
 179         dev_info(&dev->dev, "BAR1: %#.8x\n", val);
 180         pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
 181         dev_info(&dev->dev, "BAR2: %#.8x\n", val);
 182         pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
 183         dev_info(&dev->dev, "BAR3: %#.8x\n", val);
 184         pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
 185         dev_info(&dev->dev, "BAR4: %#.8x\n", val);
 186         pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
 187         dev_info(&dev->dev, "BAR5: %#.8x\n", val);
 188
 189         dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
 190                 p1_base(dev), p1_size(dev));
 191         dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
 192                 p2_base(dev), p2_size(dev));
 193         dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
 194                 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
 195
 196         if (!(vsec = find_cxl_vsec(dev)))
 197                 return;
 198
 199 #define show_reg(name, what) \
 200         dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
 201
 202         pci_read_config_dword(dev, vsec + 0x0, &val);
 203         show_reg("Cap ID", (val >> 0) & 0xffff);
 204         show_reg("Cap Ver", (val >> 16) & 0xf);
 205         show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
 206         pci_read_config_dword(dev, vsec + 0x4, &val);
 207         show_reg("VSEC ID", (val >> 0) & 0xffff);
 208         show_reg("VSEC Rev", (val >> 16) & 0xf);
 209         show_reg("VSEC Length", (val >> 20) & 0xfff);
 210         pci_read_config_dword(dev, vsec + 0x8, &val);
 211         show_reg("Num AFUs", (val >> 0) & 0xff);
 212         show_reg("Status", (val >> 8) & 0xff);
 213         show_reg("Mode Control", (val >> 16) & 0xff);
 214         show_reg("Reserved", (val >> 24) & 0xff);
 215         pci_read_config_dword(dev, vsec + 0xc, &val);
 216         show_reg("PSL Rev", (val >> 0) & 0xffff);
 217         show_reg("CAIA Ver", (val >> 16) & 0xffff);
 218         pci_read_config_dword(dev, vsec + 0x10, &val);
 219         show_reg("Base Image Rev", (val >> 0) & 0xffff);
 220         show_reg("Reserved", (val >> 16) & 0x0fff);
 221         show_reg("Image Control", (val >> 28) & 0x3);
 222         show_reg("Reserved", (val >> 30) & 0x1);
 223         show_reg("Image Loaded", (val >> 31) & 0x1);
 224
 225         pci_read_config_dword(dev, vsec + 0x14, &val);
 226         show_reg("Reserved", val);
 227         pci_read_config_dword(dev, vsec + 0x18, &val);
 228         show_reg("Reserved", val);
 229         pci_read_config_dword(dev, vsec + 0x1c, &val);
 230         show_reg("Reserved", val);
 231
 232         pci_read_config_dword(dev, vsec + 0x20, &val);
 233         show_reg("AFU Descriptor Offset", val);
 234         pci_read_config_dword(dev, vsec + 0x24, &val);
 235         show_reg("AFU Descriptor Size", val);
 236         pci_read_config_dword(dev, vsec + 0x28, &val);
 237         show_reg("Problem State Offset", val);
 238         pci_read_config_dword(dev, vsec + 0x2c, &val);
 239         show_reg("Problem State Size", val);
 240
 241         pci_read_config_dword(dev, vsec + 0x30, &val);
 242         show_reg("Reserved", val);
 243         pci_read_config_dword(dev, vsec + 0x34, &val);
 244         show_reg("Reserved", val);
 245         pci_read_config_dword(dev, vsec + 0x38, &val);
 246         show_reg("Reserved", val);
 247         pci_read_config_dword(dev, vsec + 0x3c, &val);
 248         show_reg("Reserved", val);
 249
 250         pci_read_config_dword(dev, vsec + 0x40, &val);
 251         show_reg("PSL Programming Port", val);
 252         pci_read_config_dword(dev, vsec + 0x44, &val);
 253         show_reg("PSL Programming Control", val);
 254
 255         pci_read_config_dword(dev, vsec + 0x48, &val);
 256         show_reg("Reserved", val);
 257         pci_read_config_dword(dev, vsec + 0x4c, &val);
 258         show_reg("Reserved", val);
 259
 260         pci_read_config_dword(dev, vsec + 0x50, &val);
 261         show_reg("Flash Address Register", val);
 262         pci_read_config_dword(dev, vsec + 0x54, &val);
 263         show_reg("Flash Size Register", val);
 264         pci_read_config_dword(dev, vsec + 0x58, &val);
 265         show_reg("Flash Status/Control Register", val);
 266         pci_read_config_dword(dev, vsec + 0x58, &val);
 267         show_reg("Flash Data Port", val);
 268
 269 #undef show_reg
 270 }
 271
 272 static void dump_afu_descriptor(struct cxl_afu *afu)
 273 {
 274         u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
 275         int i;
 276
 277 #define show_reg(name, what) \
 278         dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
 279
 280         val = AFUD_READ_INFO(afu);
 281         show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
 282         show_reg("num_of_processes", AFUD_NUM_PROCS(val));
 283         show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
 284         show_reg("req_prog_mode", val & 0xffffULL);
 285         afu_cr_num = AFUD_NUM_CRS(val);
 286
 287         val = AFUD_READ(afu, 0x8);
 288         show_reg("Reserved", val);
 289         val = AFUD_READ(afu, 0x10);
 290         show_reg("Reserved", val);
 291         val = AFUD_READ(afu, 0x18);
 292         show_reg("Reserved", val);
 293
 294         val = AFUD_READ_CR(afu);
 295         show_reg("Reserved", (val >> (63-7)) & 0xff);
 296         show_reg("AFU_CR_len", AFUD_CR_LEN(val));
 297         afu_cr_len = AFUD_CR_LEN(val) * 256;
 298
 299         val = AFUD_READ_CR_OFF(afu);
 300         afu_cr_off = val;
 301         show_reg("AFU_CR_offset", val);
 302
 303         val = AFUD_READ_PPPSA(afu);
 304         show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
 305         show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
 306
 307         val = AFUD_READ_PPPSA_OFF(afu);
 308         show_reg("PerProcessPSA_offset", val);
 309
 310         val = AFUD_READ_EB(afu);
 311         show_reg("Reserved", (val >> (63-7)) & 0xff);
 312         show_reg("AFU_EB_len", AFUD_EB_LEN(val));
 313
 314         val = AFUD_READ_EB_OFF(afu);
 315         show_reg("AFU_EB_offset", val);
 316
 317         for (i = 0; i < afu_cr_num; i++) {
 318                 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
 319                 show_reg("CR Vendor", val & 0xffff);
 320                 show_reg("CR Device", (val >> 16) & 0xffff);
 321         }
 322 #undef show_reg
 323 }
 324
 325 #define P8_CAPP_UNIT0_ID 0xBA
 326 #define P8_CAPP_UNIT1_ID 0XBE
 327 #define P9_CAPP_UNIT0_ID 0xC0
 328 #define P9_CAPP_UNIT1_ID 0xE0
 329
 330 static int get_phb_index(struct device_node *np, u32 *phb_index)
 331 {
 332         if (of_property_read_u32(np, "ibm,phb-index", phb_index))
 333                 return -ENODEV;
 334         return 0;
 335 }
 336
 337 static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
 338 {
 339         /*
 340          * POWER 8:
 341          *  - For chips other than POWER8NVL, we only have CAPP 0,
 342          *    irrespective of which PHB is used.
 343          *  - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
 344          *    CAPP 1 is attached to PHB1.
 345          */
 346         if (cxl_is_power8()) {
 347                 if (!pvr_version_is(PVR_POWER8NVL))
 348                         return P8_CAPP_UNIT0_ID;
 349
 350                 if (phb_index == 0)
 351                         return P8_CAPP_UNIT0_ID;
 352
 353                 if (phb_index == 1)
 354                         return P8_CAPP_UNIT1_ID;
 355         }
 356
 357         /*
 358          * POWER 9:
 359          *   PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
 360          *   PEC1 (PHB1 - PHB2). No capi mode
 361          *   PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
 362          */
 363         if (cxl_is_power9()) {
 364                 if (phb_index == 0)
 365                         return P9_CAPP_UNIT0_ID;
 366
 367                 if (phb_index == 3)
 368                         return P9_CAPP_UNIT1_ID;
 369         }
 370
 371         return 0;
 372 }
 373
 374 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
 375                              u32 *phb_index, u64 *capp_unit_id)
 376 {
 377         int rc;
 378         struct device_node *np;
 379         const __be32 *prop;
 380
 381         if (!(np = pnv_pci_get_phb_node(dev)))
 382                 return -ENODEV;
 383
 384         while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
 385                 np = of_get_next_parent(np);
 386         if (!np)
 387                 return -ENODEV;
 388
 389         *chipid = be32_to_cpup(prop);
 390
 391         rc = get_phb_index(np, phb_index);
 392         if (rc) {
 393                 pr_err("cxl: invalid phb index\n");
 394                 of_node_put(np);
 395                 return rc;
 396         }
 397
 398         *capp_unit_id = get_capp_unit_id(np, *phb_index);
 399         of_node_put(np);
 400         if (!*capp_unit_id) {
 401                 pr_err("cxl: No capp unit found for PHB[%lld,%d]. Make sure the adapter is on a capi-compatible slot\n",
 402                        *chipid, *phb_index);
 403                 return -ENODEV;
 404         }
 405
 406         return 0;
 407 }
 408
 409 static DEFINE_MUTEX(indications_mutex);
 410
 411 static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind,
 412                                u64 *nbwind)
 413 {
 414         static u64 nbw, asn, capi = 0;
 415         struct device_node *np;
 416         const __be32 *prop;
 417
 418         mutex_lock(&indications_mutex);
 419         if (!capi) {
 420                 if (!(np = pnv_pci_get_phb_node(dev))) {
 421                         mutex_unlock(&indications_mutex);
 422                         return -ENODEV;
 423                 }
 424
 425                 prop = of_get_property(np, "ibm,phb-indications", NULL);
 426                 if (!prop) {
 427                         nbw = 0x0300UL; /* legacy values */
 428                         asn = 0x0400UL;
 429                         capi = 0x0200UL;
 430                 } else {
 431                         nbw = (u64)be32_to_cpu(prop[2]);
 432                         asn = (u64)be32_to_cpu(prop[1]);
 433                         capi = (u64)be32_to_cpu(prop[0]);
 434                 }
 435                 of_node_put(np);
 436         }
 437         *capiind = capi;
 438         *asnind = asn;
 439         *nbwind = nbw;
 440         mutex_unlock(&indications_mutex);
 441         return 0;
 442 }
 443
 444 int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg)
 445 {
 446         u64 xsl_dsnctl;
 447         u64 capiind, asnind, nbwind;
 448
 449         /*
 450          * CAPI Identifier bits [0:7]
 451          * bit 61:60 MSI bits --> 0
 452          * bit 59 TVT selector --> 0
 453          */
 454         if (get_phb_indications(dev, &capiind, &asnind, &nbwind))
 455                 return -ENODEV;
 456
 457         /*
 458          * Tell XSL where to route data to.
 459          * The field chipid should match the PHB CAPI_CMPM register
 460          */
 461         xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */
 462         xsl_dsnctl |= (capp_unit_id << (63-15));
 463
 464         /* nMMU_ID Defaults to: b’000001001’*/
 465         xsl_dsnctl |= ((u64)0x09 << (63-28));
 466
 467         /*
 468          * Used to identify CAPI packets which should be sorted into
 469          * the Non-Blocking queues by the PHB. This field should match
 470          * the PHB PBL_NBW_CMPM register
 471          * nbwind=0x03, bits [57:58], must include capi indicator.
 472          * Not supported on P9 DD1.
 473          */
 474         xsl_dsnctl |= (nbwind << (63-55));
 475
 476         /*
 477          * Upper 16b address bits of ASB_Notify messages sent to the
 478          * system. Need to match the PHB’s ASN Compare/Mask Register.
 479          * Not supported on P9 DD1.
 480          */
 481         xsl_dsnctl |= asnind;
 482
 483         *reg = xsl_dsnctl;
 484         return 0;
 485 }
 486
 487 static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
 488                                                  struct pci_dev *dev)
 489 {
 490         u64 xsl_dsnctl, psl_fircntl;
 491         u64 chipid;
 492         u32 phb_index;
 493         u64 capp_unit_id;
 494         u64 psl_debug;
 495         int rc;
 496
 497         rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
 498         if (rc)
 499                 return rc;
 500
 501         rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl);
 502         if (rc)
 503                 return rc;
 504
 505         cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
 506
 507         /* Set fir_cntl to recommended value for production env */
 508         psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
 509         psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
 510         psl_fircntl |= 0x1ULL; /* ce_thresh */
 511         cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
 512
 513         /* Setup the PSL to transmit packets on the PCIe before the
 514          * CAPP is enabled. Make sure that CAPP virtual machines are disabled
 515          */
 516         cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000012A10ULL);
 517
 518         /*
 519          * A response to an ASB_Notify request is returned by the
 520          * system as an MMIO write to the address defined in
 521          * the PSL_TNR_ADDR register.
 522          * keep the Reset Value: 0x00020000E0000000
 523          */
 524
 525         /* Enable XSL rty limit */
 526         cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
 527
 528         /* Change XSL_INV dummy read threshold */
 529         cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
 530
 531         if (phb_index == 3) {
 532                 /* disable machines 31-47 and 20-27 for DMA */
 533                 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);
 534         }
 535
 536         /* Snoop machines */
 537         cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
 538
 539         /* Enable NORST and DD2 features */
 540         cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
 541
 542         /*
 543          * Check if PSL has data-cache. We need to flush adapter datacache
 544          * when as its about to be removed.
 545          */
 546         psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG);
 547         if (psl_debug & CXL_PSL_DEBUG_CDC) {
 548                 dev_dbg(&dev->dev, "No data-cache present\n");
 549                 adapter->native->no_data_cache = true;
 550         }
 551
 552         return 0;
 553 }
 554
 555 static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
 556 {
 557         u64 psl_dsnctl, psl_fircntl;
 558         u64 chipid;
 559         u32 phb_index;
 560         u64 capp_unit_id;
 561         int rc;
 562
 563         rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
 564         if (rc)
 565                 return rc;
 566
 567         psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
 568         psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
 569         /* Tell PSL where to route data to */
 570         psl_dsnctl |= (chipid << (63-5));
 571         psl_dsnctl |= (capp_unit_id << (63-13));
 572
 573         cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
 574         cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
 575         /* snoop write mask */
 576         cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
 577         /* set fir_cntl to recommended value for production env */
 578         psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
 579         psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
 580         psl_fircntl |= 0x1ULL; /* ce_thresh */
 581         cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
 582         /* for debugging with trace arrays */
 583         cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
 584
 585         return 0;
 586 }
 587
 588 /* PSL */
 589 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
 590 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
 591 /* For the PSL this is a multiple for 0 < n <= 7: */
 592 #define PSL_2048_250MHZ_CYCLES 1
 593
 594 static void write_timebase_ctrl_psl8(struct cxl *adapter)
 595 {
 596         cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
 597                      TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
 598 }
 599
 600 static u64 timebase_read_psl9(struct cxl *adapter)
 601 {
 602         return cxl_p1_read(adapter, CXL_PSL9_Timebase);
 603 }
 604
 605 static u64 timebase_read_psl8(struct cxl *adapter)
 606 {
 607         return cxl_p1_read(adapter, CXL_PSL_Timebase);
 608 }
 609
 610 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
 611 {
 612         struct device_node *np;
 613
 614         adapter->psl_timebase_synced = false;
 615
 616         if (!(np = pnv_pci_get_phb_node(dev)))
 617                 return;
 618
 619         /* Do not fail when CAPP timebase sync is not supported by OPAL */
 620         of_node_get(np);
 621         if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
 622                 of_node_put(np);
 623                 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
 624                 return;
 625         }
 626         of_node_put(np);
 627
 628         /*
 629          * Setup PSL Timebase Control and Status register
 630          * with the recommended Timebase Sync Count value
 631          */
 632         if (adapter->native->sl_ops->write_timebase_ctrl)
 633                 adapter->native->sl_ops->write_timebase_ctrl(adapter);
 634
 635         /* Enable PSL Timebase */
 636         cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
 637         cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
 638
 639         return;
 640 }
 641
 642 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
 643 {
 644         return 0;
 645 }
 646
 647 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
 648 {
 649         /* read/write masks for this slice */
 650         cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
 651         /* APC read/write masks for this slice */
 652         cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
 653         /* for debugging with trace arrays */
 654         cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
 655         cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
 656
 657         return 0;
 658 }
 659
 660 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
 661                 unsigned int virq)
 662 {
 663         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 664
 665         return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
 666 }
 667
 668 int cxl_update_image_control(struct cxl *adapter)
 669 {
 670         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 671         int rc;
 672         int vsec;
 673         u8 image_state;
 674
 675         if (!(vsec = find_cxl_vsec(dev))) {
 676                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
 677                 return -ENODEV;
 678         }
 679
 680         if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
 681                 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
 682                 return rc;
 683         }
 684
 685         if (adapter->perst_loads_image)
 686                 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
 687         else
 688                 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
 689
 690         if (adapter->perst_select_user)
 691                 image_state |= CXL_VSEC_PERST_SELECT_USER;
 692         else
 693                 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
 694
 695         if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
 696                 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
 697                 return rc;
 698         }
 699
 700         return 0;
 701 }
 702
 703 int cxl_pci_alloc_one_irq(struct cxl *adapter)
 704 {
 705         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 706
 707         return pnv_cxl_alloc_hwirqs(dev, 1);
 708 }
 709
 710 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
 711 {
 712         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 713
 714         return pnv_cxl_release_hwirqs(dev, hwirq, 1);
 715 }
 716
 717 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
 718                         struct cxl *adapter, unsigned int num)
 719 {
 720         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 721
 722         return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
 723 }
 724
 725 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
 726                                 struct cxl *adapter)
 727 {
 728         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 729
 730         pnv_cxl_release_hwirq_ranges(irqs, dev);
 731 }
 732
 733 static int setup_cxl_bars(struct pci_dev *dev)
 734 {
 735         /* Safety check in case we get backported to < 3.17 without M64 */
 736         if ((p1_base(dev) < 0x100000000ULL) ||
 737             (p2_base(dev) < 0x100000000ULL)) {
 738                 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
 739                 return -ENODEV;
 740         }
 741
 742         /*
 743          * BAR 4/5 has a special meaning for CXL and must be programmed with a
 744          * special value corresponding to the CXL protocol address range.
 745          * For POWER 8/9 that means bits 48:49 must be set to 10
 746          */
 747         pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
 748         pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
 749
 750         return 0;
 751 }
 752
 753 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
 754 static int switch_card_to_cxl(struct pci_dev *dev)
 755 {
 756         int vsec;
 757         u8 val;
 758         int rc;
 759
 760         dev_info(&dev->dev, "switch card to CXL\n");
 761
 762         if (!(vsec = find_cxl_vsec(dev))) {
 763                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
 764                 return -ENODEV;
 765         }
 766
 767         if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
 768                 dev_err(&dev->dev, "failed to read current mode control: %i", rc);
 769                 return rc;
 770         }
 771         val &= ~CXL_VSEC_PROTOCOL_MASK;
 772         val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
 773         if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
 774                 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
 775                 return rc;
 776         }
 777         /*
 778          * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
 779          * we must wait 100ms after this mode switch before touching
 780          * PCIe config space.
 781          */
 782         msleep(100);
 783
 784         return 0;
 785 }
 786
 787 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
 788 {
 789         u64 p1n_base, p2n_base, afu_desc;
 790         const u64 p1n_size = 0x100;
 791         const u64 p2n_size = 0x1000;
 792
 793         p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
 794         p2n_base = p2_base(dev) + (afu->slice * p2n_size);
 795         afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
 796         afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
 797
 798         if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
 799                 goto err;
 800         if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
 801                 goto err1;
 802         if (afu_desc) {
 803                 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
 804                         goto err2;
 805         }
 806
 807         return 0;
 808 err2:
 809         iounmap(afu->p2n_mmio);
 810 err1:
 811         iounmap(afu->native->p1n_mmio);
 812 err:
 813         dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
 814         return -ENOMEM;
 815 }
 816
 817 static void pci_unmap_slice_regs(struct cxl_afu *afu)
 818 {
 819         if (afu->p2n_mmio) {
 820                 iounmap(afu->p2n_mmio);
 821                 afu->p2n_mmio = NULL;
 822         }
 823         if (afu->native->p1n_mmio) {
 824                 iounmap(afu->native->p1n_mmio);
 825                 afu->native->p1n_mmio = NULL;
 826         }
 827         if (afu->native->afu_desc_mmio) {
 828                 iounmap(afu->native->afu_desc_mmio);
 829                 afu->native->afu_desc_mmio = NULL;
 830         }
 831 }
 832
 833 void cxl_pci_release_afu(struct device *dev)
 834 {
 835         struct cxl_afu *afu = to_cxl_afu(dev);
 836
 837         pr_devel("%s\n", __func__);
 838
 839         idr_destroy(&afu->contexts_idr);
 840         cxl_release_spa(afu);
 841
 842         kfree(afu->native);
 843         kfree(afu);
 844 }
 845
 846 /* Expects AFU struct to have recently been zeroed out */
 847 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
 848 {
 849         u64 val;
 850
 851         val = AFUD_READ_INFO(afu);
 852         afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
 853         afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
 854         afu->crs_num = AFUD_NUM_CRS(val);
 855
 856         if (AFUD_AFU_DIRECTED(val))
 857                 afu->modes_supported |= CXL_MODE_DIRECTED;
 858         if (AFUD_DEDICATED_PROCESS(val))
 859                 afu->modes_supported |= CXL_MODE_DEDICATED;
 860         if (AFUD_TIME_SLICED(val))
 861                 afu->modes_supported |= CXL_MODE_TIME_SLICED;
 862
 863         val = AFUD_READ_PPPSA(afu);
 864         afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
 865         afu->psa = AFUD_PPPSA_PSA(val);
 866         if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
 867                 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
 868
 869         val = AFUD_READ_CR(afu);
 870         afu->crs_len = AFUD_CR_LEN(val) * 256;
 871         afu->crs_offset = AFUD_READ_CR_OFF(afu);
 872
 873
 874         /* eb_len is in multiple of 4K */
 875         afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
 876         afu->eb_offset = AFUD_READ_EB_OFF(afu);
 877
 878         /* eb_off is 4K aligned so lower 12 bits are always zero */
 879         if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
 880                 dev_warn(&afu->dev,
 881                          "Invalid AFU error buffer offset %Lx\n",
 882                          afu->eb_offset);
 883                 dev_info(&afu->dev,
 884                          "Ignoring AFU error buffer in the descriptor\n");
 885                 /* indicate that no afu buffer exists */
 886                 afu->eb_len = 0;
 887         }
 888
 889         return 0;
 890 }
 891
 892 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
 893 {
 894         int i, rc;
 895         u32 val;
 896
 897         if (afu->psa && afu->adapter->ps_size <
 898                         (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
 899                 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
 900                 return -ENODEV;
 901         }
 902
 903         if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
 904                 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
 905
 906         for (i = 0; i < afu->crs_num; i++) {
 907                 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
 908                 if (rc || val == 0) {
 909                         dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
 910                         return -EINVAL;
 911                 }
 912         }
 913
 914         if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
 915                 /*
 916                  * We could also check this for the dedicated process model
 917                  * since the architecture indicates it should be set to 1, but
 918                  * in that case we ignore the value and I'd rather not risk
 919                  * breaking any existing dedicated process AFUs that left it as
 920                  * 0 (not that I'm aware of any). It is clearly an error for an
 921                  * AFU directed AFU to set this to 0, and would have previously
 922                  * triggered a bug resulting in the maximum not being enforced
 923                  * at all since idr_alloc treats 0 as no maximum.
 924                  */
 925                 dev_err(&afu->dev, "AFU does not support any processes\n");
 926                 return -EINVAL;
 927         }
 928
 929         return 0;
 930 }
 931
 932 static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
 933 {
 934         u64 reg;
 935
 936         /*
 937          * Clear out any regs that contain either an IVTE or address or may be
 938          * waiting on an acknowledgment to try to be a bit safer as we bring
 939          * it online
 940          */
 941         reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
 942         if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
 943                 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
 944                 if (cxl_ops->afu_reset(afu))
 945                         return -EIO;
 946                 if (cxl_afu_disable(afu))
 947                         return -EIO;
 948                 if (cxl_psl_purge(afu))
 949                         return -EIO;
 950         }
 951         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
 952         cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
 953         reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
 954         if (reg) {
 955                 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
 956                 if (reg & CXL_PSL9_DSISR_An_TF)
 957                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
 958                 else
 959                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
 960         }
 961         if (afu->adapter->native->sl_ops->register_serr_irq) {
 962                 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
 963                 if (reg) {
 964                         if (reg & ~0x000000007fffffff)
 965                                 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
 966                         cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
 967                 }
 968         }
 969         reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
 970         if (reg) {
 971                 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
 972                 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
 973         }
 974
 975         return 0;
 976 }
 977
 978 static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
 979 {
 980         u64 reg;
 981
 982         /*
 983          * Clear out any regs that contain either an IVTE or address or may be
 984          * waiting on an acknowledgement to try to be a bit safer as we bring
 985          * it online
 986          */
 987         reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
 988         if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
 989                 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
 990                 if (cxl_ops->afu_reset(afu))
 991                         return -EIO;
 992                 if (cxl_afu_disable(afu))
 993                         return -EIO;
 994                 if (cxl_psl_purge(afu))
 995                         return -EIO;
 996         }
 997         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
 998         cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
 999         cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
1000         cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1001         cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
1002         cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
1003         cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1004         cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1005         cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1006         cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1007         cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1008         reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1009         if (reg) {
1010                 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1011                 if (reg & CXL_PSL_DSISR_TRANS)
1012                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1013                 else
1014                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1015         }
1016         if (afu->adapter->native->sl_ops->register_serr_irq) {
1017                 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1018                 if (reg) {
1019                         if (reg & ~0xffff)
1020                                 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1021                         cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1022                 }
1023         }
1024         reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1025         if (reg) {
1026                 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1027                 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1028         }
1029
1030         return 0;
1031 }
1032
1033 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1034 /*
1035  * afu_eb_read:
1036  * Called from sysfs and reads the afu error info buffer. The h/w only supports
1037  * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1038  * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1039  */
1040 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1041                                 loff_t off, size_t count)
1042 {
1043         loff_t aligned_start, aligned_end;
1044         size_t aligned_length;
1045         void *tbuf;
1046         const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1047
1048         if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1049                 return 0;
1050
1051         /* calculate aligned read window */
1052         count = min((size_t)(afu->eb_len - off), count);
1053         aligned_start = round_down(off, 8);
1054         aligned_end = round_up(off + count, 8);
1055         aligned_length = aligned_end - aligned_start;
1056
1057         /* max we can copy in one read is PAGE_SIZE */
1058         if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1059                 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1060                 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1061         }
1062
1063         /* use bounce buffer for copy */
1064         tbuf = (void *)__get_free_page(GFP_KERNEL);
1065         if (!tbuf)
1066                 return -ENOMEM;
1067
1068         /* perform aligned read from the mmio region */
1069         memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1070         memcpy(buf, tbuf + (off & 0x7), count);
1071
1072         free_page((unsigned long)tbuf);
1073
1074         return count;
1075 }
1076
1077 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1078 {
1079         int rc;
1080
1081         if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1082                 return rc;
1083
1084         if (adapter->native->sl_ops->sanitise_afu_regs) {
1085                 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1086                 if (rc)
1087                         goto err1;
1088         }
1089
1090         /* We need to reset the AFU before we can read the AFU descriptor */
1091         if ((rc = cxl_ops->afu_reset(afu)))
1092                 goto err1;
1093
1094         if (cxl_verbose)
1095                 dump_afu_descriptor(afu);
1096
1097         if ((rc = cxl_read_afu_descriptor(afu)))
1098                 goto err1;
1099
1100         if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1101                 goto err1;
1102
1103         if (adapter->native->sl_ops->afu_regs_init)
1104                 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1105                         goto err1;
1106
1107         if (adapter->native->sl_ops->register_serr_irq)
1108                 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1109                         goto err1;
1110
1111         if ((rc = cxl_native_register_psl_irq(afu)))
1112                 goto err2;
1113
1114         atomic_set(&afu->configured_state, 0);
1115         return 0;
1116
1117 err2:
1118         if (adapter->native->sl_ops->release_serr_irq)
1119                 adapter->native->sl_ops->release_serr_irq(afu);
1120 err1:
1121         pci_unmap_slice_regs(afu);
1122         return rc;
1123 }
1124
1125 static void pci_deconfigure_afu(struct cxl_afu *afu)
1126 {
1127         /*
1128          * It's okay to deconfigure when AFU is already locked, otherwise wait
1129          * until there are no readers
1130          */
1131         if (atomic_read(&afu->configured_state) != -1) {
1132                 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1133                         schedule();
1134         }
1135         cxl_native_release_psl_irq(afu);
1136         if (afu->adapter->native->sl_ops->release_serr_irq)
1137                 afu->adapter->native->sl_ops->release_serr_irq(afu);
1138         pci_unmap_slice_regs(afu);
1139 }
1140
1141 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
1142 {
1143         struct cxl_afu *afu;
1144         int rc = -ENOMEM;
1145
1146         afu = cxl_alloc_afu(adapter, slice);
1147         if (!afu)
1148                 return -ENOMEM;
1149
1150         afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1151         if (!afu->native)
1152                 goto err_free_afu;
1153
1154         mutex_init(&afu->native->spa_mutex);
1155
1156         rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1157         if (rc)
1158                 goto err_free_native;
1159
1160         rc = pci_configure_afu(afu, adapter, dev);
1161         if (rc)
1162                 goto err_free_native;
1163
1164         /* Don't care if this fails */
1165         cxl_debugfs_afu_add(afu);
1166
1167         /*
1168          * After we call this function we must not free the afu directly, even
1169          * if it returns an error!
1170          */
1171         if ((rc = cxl_register_afu(afu)))
1172                 goto err_put_dev;
1173
1174         if ((rc = cxl_sysfs_afu_add(afu)))
1175                 goto err_del_dev;
1176
1177         adapter->afu[afu->slice] = afu;
1178
1179         if ((rc = cxl_pci_vphb_add(afu)))
1180                 dev_info(&afu->dev, "Can't register vPHB\n");
1181
1182         return 0;
1183
1184 err_del_dev:
1185         device_del(&afu->dev);
1186 err_put_dev:
1187         pci_deconfigure_afu(afu);
1188         cxl_debugfs_afu_remove(afu);
1189         put_device(&afu->dev);
1190         return rc;
1191
1192 err_free_native:
1193         kfree(afu->native);
1194 err_free_afu:
1195         kfree(afu);
1196         return rc;
1197
1198 }
1199
1200 static void cxl_pci_remove_afu(struct cxl_afu *afu)
1201 {
1202         pr_devel("%s\n", __func__);
1203
1204         if (!afu)
1205                 return;
1206
1207         cxl_pci_vphb_remove(afu);
1208         cxl_sysfs_afu_remove(afu);
1209         cxl_debugfs_afu_remove(afu);
1210
1211         spin_lock(&afu->adapter->afu_list_lock);
1212         afu->adapter->afu[afu->slice] = NULL;
1213         spin_unlock(&afu->adapter->afu_list_lock);
1214
1215         cxl_context_detach_all(afu);
1216         cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1217
1218         pci_deconfigure_afu(afu);
1219         device_unregister(&afu->dev);
1220 }
1221
1222 int cxl_pci_reset(struct cxl *adapter)
1223 {
1224         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1225         int rc;
1226
1227         if (adapter->perst_same_image) {
1228                 dev_warn(&dev->dev,
1229                          "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1230                 return -EINVAL;
1231         }
1232
1233         dev_info(&dev->dev, "CXL reset\n");
1234
1235         /*
1236          * The adapter is about to be reset, so ignore errors.
1237          */
1238         cxl_data_cache_flush(adapter);
1239
1240         /* pcie_warm_reset requests a fundamental pci reset which includes a
1241          * PERST assert/deassert.  PERST triggers a loading of the image
1242          * if "user" or "factory" is selected in sysfs */
1243         if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1244                 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1245                 return rc;
1246         }
1247
1248         return rc;
1249 }
1250
1251 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1252 {
1253         if (pci_request_region(dev, 2, "priv 2 regs"))
1254                 goto err1;
1255         if (pci_request_region(dev, 0, "priv 1 regs"))
1256                 goto err2;
1257
1258         pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
1259                         p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1260
1261         if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1262                 goto err3;
1263
1264         if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1265                 goto err4;
1266
1267         return 0;
1268
1269 err4:
1270         iounmap(adapter->native->p1_mmio);
1271         adapter->native->p1_mmio = NULL;
1272 err3:
1273         pci_release_region(dev, 0);
1274 err2:
1275         pci_release_region(dev, 2);
1276 err1:
1277         return -ENOMEM;
1278 }
1279
1280 static void cxl_unmap_adapter_regs(struct cxl *adapter)
1281 {
1282         if (adapter->native->p1_mmio) {
1283                 iounmap(adapter->native->p1_mmio);
1284                 adapter->native->p1_mmio = NULL;
1285                 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1286         }
1287         if (adapter->native->p2_mmio) {
1288                 iounmap(adapter->native->p2_mmio);
1289                 adapter->native->p2_mmio = NULL;
1290                 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1291         }
1292 }
1293
1294 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1295 {
1296         int vsec;
1297         u32 afu_desc_off, afu_desc_size;
1298         u32 ps_off, ps_size;
1299         u16 vseclen;
1300         u8 image_state;
1301
1302         if (!(vsec = find_cxl_vsec(dev))) {
1303                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1304                 return -ENODEV;
1305         }
1306
1307         CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1308         if (vseclen < CXL_VSEC_MIN_SIZE) {
1309                 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1310                 return -EINVAL;
1311         }
1312
1313         CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1314         CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1315         CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1316         CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1317         CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1318         CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1319         adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1320         adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1321         adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
1322
1323         CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1324         CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1325         CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1326         CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1327         CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1328
1329         /* Convert everything to bytes, because there is NO WAY I'd look at the
1330          * code a month later and forget what units these are in ;-) */
1331         adapter->native->ps_off = ps_off * 64 * 1024;
1332         adapter->ps_size = ps_size * 64 * 1024;
1333         adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1334         adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1335
1336         /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1337         adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1338
1339         return 0;
1340 }
1341
1342 /*
1343  * Workaround a PCIe Host Bridge defect on some cards, that can cause
1344  * malformed Transaction Layer Packet (TLP) errors to be erroneously
1345  * reported. Mask this error in the Uncorrectable Error Mask Register.
1346  *
1347  * The upper nibble of the PSL revision is used to distinguish between
1348  * different cards. The affected ones have it set to 0.
1349  */
1350 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1351 {
1352         int aer;
1353         u32 data;
1354
1355         if (adapter->psl_rev & 0xf000)
1356                 return;
1357         if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1358                 return;
1359         pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1360         if (data & PCI_ERR_UNC_MALF_TLP)
1361                 if (data & PCI_ERR_UNC_INTN)
1362                         return;
1363         data |= PCI_ERR_UNC_MALF_TLP;
1364         data |= PCI_ERR_UNC_INTN;
1365         pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1366 }
1367
1368 static bool cxl_compatible_caia_version(struct cxl *adapter)
1369 {
1370         if (cxl_is_power8() && (adapter->caia_major == 1))
1371                 return true;
1372
1373         if (cxl_is_power9() && (adapter->caia_major == 2))
1374                 return true;
1375
1376         return false;
1377 }
1378
1379 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1380 {
1381         if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1382                 return -EBUSY;
1383
1384         if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1385                 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1386                 return -EINVAL;
1387         }
1388
1389         if (!cxl_compatible_caia_version(adapter)) {
1390                 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1391                          adapter->caia_major);
1392                 return -ENODEV;
1393         }
1394
1395         if (!adapter->slices) {
1396                 /* Once we support dynamic reprogramming we can use the card if
1397                  * it supports loadable AFUs */
1398                 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1399                 return -EINVAL;
1400         }
1401
1402         if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1403                 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1404                 return -EINVAL;
1405         }
1406
1407         if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1408                 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1409                                    "available in BAR2: 0x%llx > 0x%llx\n",
1410                          adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1411                 return -EINVAL;
1412         }
1413
1414         return 0;
1415 }
1416
1417 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1418 {
1419         return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1420 }
1421
1422 static void cxl_release_adapter(struct device *dev)
1423 {
1424         struct cxl *adapter = to_cxl_adapter(dev);
1425
1426         pr_devel("cxl_release_adapter\n");
1427
1428         cxl_remove_adapter_nr(adapter);
1429
1430         kfree(adapter->native);
1431         kfree(adapter);
1432 }
1433
1434 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1435
1436 static int sanitise_adapter_regs(struct cxl *adapter)
1437 {
1438         int rc = 0;
1439
1440         /* Clear PSL tberror bit by writing 1 to it */
1441         cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1442
1443         if (adapter->native->sl_ops->invalidate_all) {
1444                 /* do not invalidate ERAT entries when not reloading on PERST */
1445                 if (cxl_is_power9() && (adapter->perst_loads_image))
1446                         return 0;
1447                 rc = adapter->native->sl_ops->invalidate_all(adapter);
1448         }
1449
1450         return rc;
1451 }
1452
1453 /* This should contain *only* operations that can safely be done in
1454  * both creation and recovery.
1455  */
1456 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1457 {
1458         int rc;
1459
1460         adapter->dev.parent = &dev->dev;
1461         adapter->dev.release = cxl_release_adapter;
1462         pci_set_drvdata(dev, adapter);
1463
1464         rc = pci_enable_device(dev);
1465         if (rc) {
1466                 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1467                 return rc;
1468         }
1469
1470         if ((rc = cxl_read_vsec(adapter, dev)))
1471                 return rc;
1472
1473         if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1474                 return rc;
1475
1476         cxl_fixup_malformed_tlp(adapter, dev);
1477
1478         if ((rc = setup_cxl_bars(dev)))
1479                 return rc;
1480
1481         if ((rc = switch_card_to_cxl(dev)))
1482                 return rc;
1483
1484         if ((rc = cxl_update_image_control(adapter)))
1485                 return rc;
1486
1487         if ((rc = cxl_map_adapter_regs(adapter, dev)))
1488                 return rc;
1489
1490         if ((rc = sanitise_adapter_regs(adapter)))
1491                 goto err;
1492
1493         if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1494                 goto err;
1495
1496         /* Required for devices using CAPP DMA mode, harmless for others */
1497         pci_set_master(dev);
1498
1499         adapter->tunneled_ops_supported = false;
1500
1501         if (cxl_is_power9()) {
1502                 if (pnv_pci_set_tunnel_bar(dev, 0x00020000E0000000ull, 1))
1503                         dev_info(&dev->dev, "Tunneled operations unsupported\n");
1504                 else
1505                         adapter->tunneled_ops_supported = true;
1506         }
1507
1508         if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1509                 goto err;
1510
1511         /* If recovery happened, the last step is to turn on snooping.
1512          * In the non-recovery case this has no effect */
1513         if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1514                 goto err;
1515
1516         /* Ignore error, adapter init is not dependant on timebase sync */
1517         cxl_setup_psl_timebase(adapter, dev);
1518
1519         if ((rc = cxl_native_register_psl_err_irq(adapter)))
1520                 goto err;
1521
1522         return 0;
1523
1524 err:
1525         cxl_unmap_adapter_regs(adapter);
1526         return rc;
1527
1528 }
1529
1530 static void cxl_deconfigure_adapter(struct cxl *adapter)
1531 {
1532         struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1533
1534         if (cxl_is_power9())
1535                 pnv_pci_set_tunnel_bar(pdev, 0x00020000E0000000ull, 0);
1536
1537         cxl_native_release_psl_err_irq(adapter);
1538         cxl_unmap_adapter_regs(adapter);
1539
1540         pci_disable_device(pdev);
1541 }
1542
1543 static void cxl_stop_trace_psl9(struct cxl *adapter)
1544 {
1545         int traceid;
1546         u64 trace_state, trace_mask;
1547         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1548
1549         /* read each tracearray state and issue mmio to stop them is needed */
1550         for (traceid = 0; traceid <= CXL_PSL9_TRACEID_MAX; ++traceid) {
1551                 trace_state = cxl_p1_read(adapter, CXL_PSL9_CTCCFG);
1552                 trace_mask = (0x3ULL << (62 - traceid * 2));
1553                 trace_state = (trace_state & trace_mask) >> (62 - traceid * 2);
1554                 dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n",
1555                         traceid, trace_state);
1556
1557                 /* issue mmio if the trace array isn't in FIN state */
1558                 if (trace_state != CXL_PSL9_TRACESTATE_FIN)
1559                         cxl_p1_write(adapter, CXL_PSL9_TRACECFG,
1560                                      0x8400000000000000ULL | traceid);
1561         }
1562 }
1563
1564 static void cxl_stop_trace_psl8(struct cxl *adapter)
1565 {
1566         int slice;
1567
1568         /* Stop the trace */
1569         cxl_p1_write(adapter, CXL_PSL_TRACE, 0x8000000000000017LL);
1570
1571         /* Stop the slice traces */
1572         spin_lock(&adapter->afu_list_lock);
1573         for (slice = 0; slice < adapter->slices; slice++) {
1574                 if (adapter->afu[slice])
1575                         cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
1576                                       0x8000000000000000LL);
1577         }
1578         spin_unlock(&adapter->afu_list_lock);
1579 }
1580
1581 static const struct cxl_service_layer_ops psl9_ops = {
1582         .adapter_regs_init = init_implementation_adapter_regs_psl9,
1583         .invalidate_all = cxl_invalidate_all_psl9,
1584         .afu_regs_init = init_implementation_afu_regs_psl9,
1585         .sanitise_afu_regs = sanitise_afu_regs_psl9,
1586         .register_serr_irq = cxl_native_register_serr_irq,
1587         .release_serr_irq = cxl_native_release_serr_irq,
1588         .handle_interrupt = cxl_irq_psl9,
1589         .fail_irq = cxl_fail_irq_psl,
1590         .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1591         .attach_afu_directed = cxl_attach_afu_directed_psl9,
1592         .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1593         .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1594         .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1595         .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1596         .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
1597         .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
1598         .debugfs_stop_trace = cxl_stop_trace_psl9,
1599         .timebase_read = timebase_read_psl9,
1600         .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1601         .needs_reset_before_disable = true,
1602 };
1603
1604 static const struct cxl_service_layer_ops psl8_ops = {
1605         .adapter_regs_init = init_implementation_adapter_regs_psl8,
1606         .invalidate_all = cxl_invalidate_all_psl8,
1607         .afu_regs_init = init_implementation_afu_regs_psl8,
1608         .sanitise_afu_regs = sanitise_afu_regs_psl8,
1609         .register_serr_irq = cxl_native_register_serr_irq,
1610         .release_serr_irq = cxl_native_release_serr_irq,
1611         .handle_interrupt = cxl_irq_psl8,
1612         .fail_irq = cxl_fail_irq_psl,
1613         .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1614         .attach_afu_directed = cxl_attach_afu_directed_psl8,
1615         .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1616         .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1617         .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1618         .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1619         .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
1620         .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl8,
1621         .debugfs_stop_trace = cxl_stop_trace_psl8,
1622         .write_timebase_ctrl = write_timebase_ctrl_psl8,
1623         .timebase_read = timebase_read_psl8,
1624         .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1625         .needs_reset_before_disable = true,
1626 };
1627
1628 static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1629 {
1630         if (cxl_is_power8()) {
1631                 dev_info(&dev->dev, "Device uses a PSL8\n");
1632                 adapter->native->sl_ops = &psl8_ops;
1633         } else {
1634                 dev_info(&dev->dev, "Device uses a PSL9\n");
1635                 adapter->native->sl_ops = &psl9_ops;
1636         }
1637 }
1638
1639
1640 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
1641 {
1642         struct cxl *adapter;
1643         int rc;
1644
1645         adapter = cxl_alloc_adapter();
1646         if (!adapter)
1647                 return ERR_PTR(-ENOMEM);
1648
1649         adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1650         if (!adapter->native) {
1651                 rc = -ENOMEM;
1652                 goto err_release;
1653         }
1654
1655         set_sl_ops(adapter, dev);
1656
1657         /* Set defaults for parameters which need to persist over
1658          * configure/reconfigure
1659          */
1660         adapter->perst_loads_image = true;
1661         adapter->perst_same_image = false;
1662
1663         rc = cxl_configure_adapter(adapter, dev);
1664         if (rc) {
1665                 pci_disable_device(dev);
1666                 goto err_release;
1667         }
1668
1669         /* Don't care if this one fails: */
1670         cxl_debugfs_adapter_add(adapter);
1671
1672         /*
1673          * After we call this function we must not free the adapter directly,
1674          * even if it returns an error!
1675          */
1676         if ((rc = cxl_register_adapter(adapter)))
1677                 goto err_put_dev;
1678
1679         if ((rc = cxl_sysfs_adapter_add(adapter)))
1680                 goto err_del_dev;
1681
1682         /* Release the context lock as adapter is configured */
1683         cxl_adapter_context_unlock(adapter);
1684
1685         return adapter;
1686
1687 err_del_dev:
1688         device_del(&adapter->dev);
1689 err_put_dev:
1690         /* This should mirror cxl_remove_adapter, except without the
1691          * sysfs parts
1692          */
1693         cxl_debugfs_adapter_remove(adapter);
1694         cxl_deconfigure_adapter(adapter);
1695         put_device(&adapter->dev);
1696         return ERR_PTR(rc);
1697
1698 err_release:
1699         cxl_release_adapter(&adapter->dev);
1700         return ERR_PTR(rc);
1701 }
1702
1703 static void cxl_pci_remove_adapter(struct cxl *adapter)
1704 {
1705         pr_devel("cxl_remove_adapter\n");
1706
1707         cxl_sysfs_adapter_remove(adapter);
1708         cxl_debugfs_adapter_remove(adapter);
1709
1710         /*
1711          * Flush adapter datacache as its about to be removed.
1712          */
1713         cxl_data_cache_flush(adapter);
1714
1715         cxl_deconfigure_adapter(adapter);
1716
1717         device_unregister(&adapter->dev);
1718 }
1719
1720 #define CXL_MAX_PCIEX_PARENT 2
1721
1722 int cxl_slot_is_switched(struct pci_dev *dev)
1723 {
1724         struct device_node *np;
1725         int depth = 0;
1726         const __be32 *prop;
1727
1728         if (!(np = pci_device_to_OF_node(dev))) {
1729                 pr_err("cxl: np = NULL\n");
1730                 return -ENODEV;
1731         }
1732         of_node_get(np);
1733         while (np) {
1734                 np = of_get_next_parent(np);
1735                 prop = of_get_property(np, "device_type", NULL);
1736                 if (!prop || strcmp((char *)prop, "pciex"))
1737                         break;
1738                 depth++;
1739         }
1740         of_node_put(np);
1741         return (depth > CXL_MAX_PCIEX_PARENT);
1742 }
1743
1744 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1745 {
1746         struct cxl *adapter;
1747         int slice;
1748         int rc;
1749
1750         if (cxl_pci_is_vphb_device(dev)) {
1751                 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1752                 return -ENODEV;
1753         }
1754
1755         if (cxl_slot_is_switched(dev)) {
1756                 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1757                 return -ENODEV;
1758         }
1759
1760         if (cxl_is_power9() && !radix_enabled()) {
1761                 dev_info(&dev->dev, "Only Radix mode supported\n");
1762                 return -ENODEV;
1763         }
1764
1765         if (cxl_verbose)
1766                 dump_cxl_config_space(dev);
1767
1768         adapter = cxl_pci_init_adapter(dev);
1769         if (IS_ERR(adapter)) {
1770                 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1771                 return PTR_ERR(adapter);
1772         }
1773
1774         for (slice = 0; slice < adapter->slices; slice++) {
1775                 if ((rc = pci_init_afu(adapter, slice, dev))) {
1776                         dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1777                         continue;
1778                 }
1779
1780                 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1781                 if (rc)
1782                         dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
1783         }
1784
1785         return 0;
1786 }
1787
1788 static void cxl_remove(struct pci_dev *dev)
1789 {
1790         struct cxl *adapter = pci_get_drvdata(dev);
1791         struct cxl_afu *afu;
1792         int i;
1793
1794         /*
1795          * Lock to prevent someone grabbing a ref through the adapter list as
1796          * we are removing it
1797          */
1798         for (i = 0; i < adapter->slices; i++) {
1799                 afu = adapter->afu[i];
1800                 cxl_pci_remove_afu(afu);
1801         }
1802         cxl_pci_remove_adapter(adapter);
1803 }
1804
1805 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
1806                                                 pci_channel_state_t state)
1807 {
1808         struct pci_dev *afu_dev;
1809         pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1810         pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
1811
1812         /* There should only be one entry, but go through the list
1813          * anyway
1814          */
1815         if (afu == NULL || afu->phb == NULL)
1816                 return result;
1817
1818         list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1819                 if (!afu_dev->driver)
1820                         continue;
1821
1822                 afu_dev->error_state = state;
1823
1824                 if (afu_dev->driver->err_handler)
1825                         afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
1826                                                                                   state);
1827                 /* Disconnect trumps all, NONE trumps NEED_RESET */
1828                 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1829                         result = PCI_ERS_RESULT_DISCONNECT;
1830                 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1831                          (result == PCI_ERS_RESULT_NEED_RESET))
1832                         result = PCI_ERS_RESULT_NONE;
1833         }
1834         return result;
1835 }
1836
1837 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
1838                                                pci_channel_state_t state)
1839 {
1840         struct cxl *adapter = pci_get_drvdata(pdev);
1841         struct cxl_afu *afu;
1842         pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1843         pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
1844         int i;
1845
1846         /* At this point, we could still have an interrupt pending.
1847          * Let's try to get them out of the way before they do
1848          * anything we don't like.
1849          */
1850         schedule();
1851
1852         /* If we're permanently dead, give up. */
1853         if (state == pci_channel_io_perm_failure) {
1854                 spin_lock(&adapter->afu_list_lock);
1855                 for (i = 0; i < adapter->slices; i++) {
1856                         afu = adapter->afu[i];
1857                         /*
1858                          * Tell the AFU drivers; but we don't care what they
1859                          * say, we're going away.
1860                          */
1861                         cxl_vphb_error_detected(afu, state);
1862                 }
1863                 spin_unlock(&adapter->afu_list_lock);
1864                 return PCI_ERS_RESULT_DISCONNECT;
1865         }
1866
1867         /* Are we reflashing?
1868          *
1869          * If we reflash, we could come back as something entirely
1870          * different, including a non-CAPI card. As such, by default
1871          * we don't participate in the process. We'll be unbound and
1872          * the slot re-probed. (TODO: check EEH doesn't blindly rebind
1873          * us!)
1874          *
1875          * However, this isn't the entire story: for reliablity
1876          * reasons, we usually want to reflash the FPGA on PERST in
1877          * order to get back to a more reliable known-good state.
1878          *
1879          * This causes us a bit of a problem: if we reflash we can't
1880          * trust that we'll come back the same - we could have a new
1881          * image and been PERSTed in order to load that
1882          * image. However, most of the time we actually *will* come
1883          * back the same - for example a regular EEH event.
1884          *
1885          * Therefore, we allow the user to assert that the image is
1886          * indeed the same and that we should continue on into EEH
1887          * anyway.
1888          */
1889         if (adapter->perst_loads_image && !adapter->perst_same_image) {
1890                 /* TODO take the PHB out of CXL mode */
1891                 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
1892                 return PCI_ERS_RESULT_NONE;
1893         }
1894
1895         /*
1896          * At this point, we want to try to recover.  We'll always
1897          * need a complete slot reset: we don't trust any other reset.
1898          *
1899          * Now, we go through each AFU:
1900          *  - We send the driver, if bound, an error_detected callback.
1901          *    We expect it to clean up, but it can also tell us to give
1902          *    up and permanently detach the card. To simplify things, if
1903          *    any bound AFU driver doesn't support EEH, we give up on EEH.
1904          *
1905          *  - We detach all contexts associated with the AFU. This
1906          *    does not free them, but puts them into a CLOSED state
1907          *    which causes any the associated files to return useful
1908          *    errors to userland. It also unmaps, but does not free,
1909          *    any IRQs.
1910          *
1911          *  - We clean up our side: releasing and unmapping resources we hold
1912          *    so we can wire them up again when the hardware comes back up.
1913          *
1914          * Driver authors should note:
1915          *
1916          *  - Any contexts you create in your kernel driver (except
1917          *    those associated with anonymous file descriptors) are
1918          *    your responsibility to free and recreate. Likewise with
1919          *    any attached resources.
1920          *
1921          *  - We will take responsibility for re-initialising the
1922          *    device context (the one set up for you in
1923          *    cxl_pci_enable_device_hook and accessed through
1924          *    cxl_get_context). If you've attached IRQs or other
1925          *    resources to it, they remains yours to free.
1926          *
1927          * You can call the same functions to release resources as you
1928          * normally would: we make sure that these functions continue
1929          * to work when the hardware is down.
1930          *
1931          * Two examples:
1932          *
1933          * 1) If you normally free all your resources at the end of
1934          *    each request, or if you use anonymous FDs, your
1935          *    error_detected callback can simply set a flag to tell
1936          *    your driver not to start any new calls. You can then
1937          *    clear the flag in the resume callback.
1938          *
1939          * 2) If you normally allocate your resources on startup:
1940          *     * Set a flag in error_detected as above.
1941          *     * Let CXL detach your contexts.
1942          *     * In slot_reset, free the old resources and allocate new ones.
1943          *     * In resume, clear the flag to allow things to start.
1944          */
1945
1946         /* Make sure no one else changes the afu list */
1947         spin_lock(&adapter->afu_list_lock);
1948
1949         for (i = 0; i < adapter->slices; i++) {
1950                 afu = adapter->afu[i];
1951
1952                 if (afu == NULL)
1953                         continue;
1954
1955                 afu_result = cxl_vphb_error_detected(afu, state);
1956                 cxl_context_detach_all(afu);
1957                 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1958                 pci_deconfigure_afu(afu);
1959
1960                 /* Disconnect trumps all, NONE trumps NEED_RESET */
1961                 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1962                         result = PCI_ERS_RESULT_DISCONNECT;
1963                 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1964                          (result == PCI_ERS_RESULT_NEED_RESET))
1965                         result = PCI_ERS_RESULT_NONE;
1966         }
1967         spin_unlock(&adapter->afu_list_lock);
1968
1969         /* should take the context lock here */
1970         if (cxl_adapter_context_lock(adapter) != 0)
1971                 dev_warn(&adapter->dev,
1972                          "Couldn't take context lock with %d active-contexts\n",
1973                          atomic_read(&adapter->contexts_num));
1974
1975         cxl_deconfigure_adapter(adapter);
1976
1977         return result;
1978 }
1979
1980 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
1981 {
1982         struct cxl *adapter = pci_get_drvdata(pdev);
1983         struct cxl_afu *afu;
1984         struct cxl_context *ctx;
1985         struct pci_dev *afu_dev;
1986         pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
1987         pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1988         int i;
1989
1990         if (cxl_configure_adapter(adapter, pdev))
1991                 goto err;
1992
1993         /*
1994          * Unlock context activation for the adapter. Ideally this should be
1995          * done in cxl_pci_resume but cxlflash module tries to activate the
1996          * master context as part of slot_reset callback.
1997          */
1998         cxl_adapter_context_unlock(adapter);
1999
2000         spin_lock(&adapter->afu_list_lock);
2001         for (i = 0; i < adapter->slices; i++) {
2002                 afu = adapter->afu[i];
2003
2004                 if (afu == NULL)
2005                         continue;
2006
2007                 if (pci_configure_afu(afu, adapter, pdev))
2008                         goto err_unlock;
2009
2010                 if (cxl_afu_select_best_mode(afu))
2011                         goto err_unlock;
2012
2013                 if (afu->phb == NULL)
2014                         continue;
2015
2016                 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2017                         /* Reset the device context.
2018                          * TODO: make this less disruptive
2019                          */
2020                         ctx = cxl_get_context(afu_dev);
2021
2022                         if (ctx && cxl_release_context(ctx))
2023                                 goto err_unlock;
2024
2025                         ctx = cxl_dev_context_init(afu_dev);
2026                         if (IS_ERR(ctx))
2027                                 goto err_unlock;
2028
2029                         afu_dev->dev.archdata.cxl_ctx = ctx;
2030
2031                         if (cxl_ops->afu_check_and_enable(afu))
2032                                 goto err_unlock;
2033
2034                         afu_dev->error_state = pci_channel_io_normal;
2035
2036                         /* If there's a driver attached, allow it to
2037                          * chime in on recovery. Drivers should check
2038                          * if everything has come back OK, but
2039                          * shouldn't start new work until we call
2040                          * their resume function.
2041                          */
2042                         if (!afu_dev->driver)
2043                                 continue;
2044
2045                         if (afu_dev->driver->err_handler &&
2046                             afu_dev->driver->err_handler->slot_reset)
2047                                 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
2048
2049                         if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2050                                 result = PCI_ERS_RESULT_DISCONNECT;
2051                 }
2052         }
2053
2054         spin_unlock(&adapter->afu_list_lock);
2055         return result;
2056
2057 err_unlock:
2058         spin_unlock(&adapter->afu_list_lock);
2059
2060 err:
2061         /* All the bits that happen in both error_detected and cxl_remove
2062          * should be idempotent, so we don't need to worry about leaving a mix
2063          * of unconfigured and reconfigured resources.
2064          */
2065         dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2066         return PCI_ERS_RESULT_DISCONNECT;
2067 }
2068
2069 static void cxl_pci_resume(struct pci_dev *pdev)
2070 {
2071         struct cxl *adapter = pci_get_drvdata(pdev);
2072         struct cxl_afu *afu;
2073         struct pci_dev *afu_dev;
2074         int i;
2075
2076         /* Everything is back now. Drivers should restart work now.
2077          * This is not the place to be checking if everything came back up
2078          * properly, because there's no return value: do that in slot_reset.
2079          */
2080         spin_lock(&adapter->afu_list_lock);
2081         for (i = 0; i < adapter->slices; i++) {
2082                 afu = adapter->afu[i];
2083
2084                 if (afu == NULL || afu->phb == NULL)
2085                         continue;
2086
2087                 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2088                         if (afu_dev->driver && afu_dev->driver->err_handler &&
2089                             afu_dev->driver->err_handler->resume)
2090                                 afu_dev->driver->err_handler->resume(afu_dev);
2091                 }
2092         }
2093         spin_unlock(&adapter->afu_list_lock);
2094 }
2095
2096 static const struct pci_error_handlers cxl_err_handler = {
2097         .error_detected = cxl_pci_error_detected,
2098         .slot_reset = cxl_pci_slot_reset,
2099         .resume = cxl_pci_resume,
2100 };
2101
2102 struct pci_driver cxl_pci_driver = {
2103         .name = "cxl-pci",
2104         .id_table = cxl_pci_tbl,
2105         .probe = cxl_probe,
2106         .remove = cxl_remove,
2107         .shutdown = cxl_remove,
2108         .err_handler = &cxl_err_handler,
2109 };