drivers/mmc/host/bfin_sdh.c

   1 /*
   2  * bfin_sdh.c - Analog Devices Blackfin SDH Controller
   3  *
   4  * Copyright (C) 2007-2009 Analog Device Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #define DRIVER_NAME     "bfin-sdh"
  10
  11 #include <linux/module.h>
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/mmc/host.h>
  19 #include <linux/proc_fs.h>
  20 #include <linux/gfp.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/dma.h>
  24 #include <asm/portmux.h>
  25 #include <asm/bfin_sdh.h>
  26
  27 #if defined(CONFIG_BF51x) || defined(__ADSPBF60x__)
  28 #define bfin_read_SDH_CLK_CTL           bfin_read_RSI_CLK_CTL
  29 #define bfin_write_SDH_CLK_CTL          bfin_write_RSI_CLK_CTL
  30 #define bfin_write_SDH_ARGUMENT         bfin_write_RSI_ARGUMENT
  31 #define bfin_write_SDH_COMMAND          bfin_write_RSI_COMMAND
  32 #define bfin_write_SDH_DATA_TIMER       bfin_write_RSI_DATA_TIMER
  33 #define bfin_read_SDH_RESPONSE0         bfin_read_RSI_RESPONSE0
  34 #define bfin_read_SDH_RESPONSE1         bfin_read_RSI_RESPONSE1
  35 #define bfin_read_SDH_RESPONSE2         bfin_read_RSI_RESPONSE2
  36 #define bfin_read_SDH_RESPONSE3         bfin_read_RSI_RESPONSE3
  37 #define bfin_write_SDH_DATA_LGTH        bfin_write_RSI_DATA_LGTH
  38 #define bfin_read_SDH_DATA_CTL          bfin_read_RSI_DATA_CTL
  39 #define bfin_write_SDH_DATA_CTL         bfin_write_RSI_DATA_CTL
  40 #define bfin_read_SDH_DATA_CNT          bfin_read_RSI_DATA_CNT
  41 #define bfin_write_SDH_STATUS_CLR       bfin_write_RSI_STATUS_CLR
  42 #define bfin_read_SDH_E_STATUS          bfin_read_RSI_E_STATUS
  43 #define bfin_write_SDH_E_STATUS         bfin_write_RSI_E_STATUS
  44 #define bfin_read_SDH_STATUS            bfin_read_RSI_STATUS
  45 #define bfin_write_SDH_MASK0            bfin_write_RSI_MASK0
  46 #define bfin_write_SDH_E_MASK           bfin_write_RSI_E_MASK
  47 #define bfin_read_SDH_CFG               bfin_read_RSI_CFG
  48 #define bfin_write_SDH_CFG              bfin_write_RSI_CFG
  49 # if defined(__ADSPBF60x__)
  50 #  define bfin_read_SDH_BLK_SIZE        bfin_read_RSI_BLKSZ
  51 #  define bfin_write_SDH_BLK_SIZE       bfin_write_RSI_BLKSZ
  52 # else
  53 #  define bfin_read_SDH_PWR_CTL         bfin_read_RSI_PWR_CTL
  54 #  define bfin_write_SDH_PWR_CTL        bfin_write_RSI_PWR_CTL
  55 # endif
  56 #endif
  57
  58 struct sdh_host {
  59         struct mmc_host         *mmc;
  60         spinlock_t              lock;
  61         struct resource         *res;
  62         void __iomem            *base;
  63         int                     irq;
  64         int                     stat_irq;
  65         int                     dma_ch;
  66         int                     dma_dir;
  67         struct dma_desc_array   *sg_cpu;
  68         dma_addr_t              sg_dma;
  69         int                     dma_len;
  70
  71         unsigned long           sclk;
  72         unsigned int            imask;
  73         unsigned int            power_mode;
  74         unsigned int            clk_div;
  75
  76         struct mmc_request      *mrq;
  77         struct mmc_command      *cmd;
  78         struct mmc_data         *data;
  79 };
  80
  81 static struct bfin_sd_host *get_sdh_data(struct platform_device *pdev)
  82 {
  83         return pdev->dev.platform_data;
  84 }
  85
  86 static void sdh_stop_clock(struct sdh_host *host)
  87 {
  88         bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E);
  89         SSYNC();
  90 }
  91
  92 static void sdh_enable_stat_irq(struct sdh_host *host, unsigned int mask)
  93 {
  94         unsigned long flags;
  95
  96         spin_lock_irqsave(&host->lock, flags);
  97         host->imask |= mask;
  98         bfin_write_SDH_MASK0(mask);
  99         SSYNC();
 100         spin_unlock_irqrestore(&host->lock, flags);
 101 }
 102
 103 static void sdh_disable_stat_irq(struct sdh_host *host, unsigned int mask)
 104 {
 105         unsigned long flags;
 106
 107         spin_lock_irqsave(&host->lock, flags);
 108         host->imask &= ~mask;
 109         bfin_write_SDH_MASK0(host->imask);
 110         SSYNC();
 111         spin_unlock_irqrestore(&host->lock, flags);
 112 }
 113
 114 static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
 115 {
 116         unsigned int length;
 117         unsigned int data_ctl;
 118         unsigned int dma_cfg;
 119         unsigned int cycle_ns, timeout;
 120
 121         dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags);
 122         host->data = data;
 123         data_ctl = 0;
 124         dma_cfg = 0;
 125
 126         length = data->blksz * data->blocks;
 127         bfin_write_SDH_DATA_LGTH(length);
 128
 129         if (data->flags & MMC_DATA_READ)
 130                 data_ctl |= DTX_DIR;
 131         /* Only supports power-of-2 block size */
 132         if (data->blksz & (data->blksz - 1))
 133                 return -EINVAL;
 134 #ifndef RSI_BLKSZ
 135         data_ctl |= ((ffs(data->blksz) - 1) << 4);
 136 #else
 137         bfin_write_SDH_BLK_SIZE(data->blksz);
 138 #endif
 139
 140         bfin_write_SDH_DATA_CTL(data_ctl);
 141         /* the time of a host clock period in ns */
 142         cycle_ns = 1000000000 / (host->sclk / (2 * (host->clk_div + 1)));
 143         timeout = data->timeout_ns / cycle_ns;
 144         timeout += data->timeout_clks;
 145         bfin_write_SDH_DATA_TIMER(timeout);
 146         SSYNC();
 147
 148         if (data->flags & MMC_DATA_READ) {
 149                 host->dma_dir = DMA_FROM_DEVICE;
 150                 dma_cfg |= WNR;
 151         } else
 152                 host->dma_dir = DMA_TO_DEVICE;
 153
 154         sdh_enable_stat_irq(host, (DAT_CRC_FAIL | DAT_TIME_OUT | DAT_END));
 155         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
 156 #if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
 157         dma_cfg |= DMAFLOW_ARRAY | RESTART | WDSIZE_32 | DMAEN;
 158 # ifdef RSI_BLKSZ
 159         dma_cfg |= PSIZE_32 | NDSIZE_3;
 160 # else
 161         dma_cfg |= NDSIZE_5;
 162 # endif
 163         {
 164                 struct scatterlist *sg;
 165                 int i;
 166                 for_each_sg(data->sg, sg, host->dma_len, i) {
 167                         host->sg_cpu[i].start_addr = sg_dma_address(sg);
 168                         host->sg_cpu[i].cfg = dma_cfg;
 169                         host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
 170                         host->sg_cpu[i].x_modify = 4;
 171                         dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
 172                                 "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
 173                                 i, host->sg_cpu[i].start_addr,
 174                                 host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
 175                                 host->sg_cpu[i].x_modify);
 176                 }
 177         }
 178         flush_dcache_range((unsigned int)host->sg_cpu,
 179                 (unsigned int)host->sg_cpu +
 180                         host->dma_len * sizeof(struct dma_desc_array));
 181         /* Set the last descriptor to stop mode */
 182         host->sg_cpu[host->dma_len - 1].cfg &= ~(DMAFLOW | NDSIZE);
 183         host->sg_cpu[host->dma_len - 1].cfg |= DI_EN;
 184
 185         set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
 186         set_dma_x_count(host->dma_ch, 0);
 187         set_dma_x_modify(host->dma_ch, 0);
 188         SSYNC();
 189         set_dma_config(host->dma_ch, dma_cfg);
 190 #elif defined(CONFIG_BF51x)
 191         /* RSI DMA doesn't work in array mode */
 192         dma_cfg |= WDSIZE_32 | DMAEN;
 193         set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
 194         set_dma_x_count(host->dma_ch, length / 4);
 195         set_dma_x_modify(host->dma_ch, 4);
 196         SSYNC();
 197         set_dma_config(host->dma_ch, dma_cfg);
 198 #endif
 199         bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
 200
 201         SSYNC();
 202
 203         dev_dbg(mmc_dev(host->mmc), "%s exit\n", __func__);
 204         return 0;
 205 }
 206
 207 static void sdh_start_cmd(struct sdh_host *host, struct mmc_command *cmd)
 208 {
 209         unsigned int sdh_cmd;
 210         unsigned int stat_mask;
 211
 212         dev_dbg(mmc_dev(host->mmc), "%s enter cmd: 0x%p\n", __func__, cmd);
 213         WARN_ON(host->cmd != NULL);
 214         host->cmd = cmd;
 215
 216         sdh_cmd = 0;
 217         stat_mask = 0;
 218
 219         sdh_cmd |= cmd->opcode;
 220
 221         if (cmd->flags & MMC_RSP_PRESENT) {
 222                 sdh_cmd |= CMD_RSP;
 223                 stat_mask |= CMD_RESP_END;
 224         } else {
 225                 stat_mask |= CMD_SENT;
 226         }
 227
 228         if (cmd->flags & MMC_RSP_136)
 229                 sdh_cmd |= CMD_L_RSP;
 230
 231         stat_mask |= CMD_CRC_FAIL | CMD_TIME_OUT;
 232
 233         sdh_enable_stat_irq(host, stat_mask);
 234
 235         bfin_write_SDH_ARGUMENT(cmd->arg);
 236         bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
 237         bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() | CLK_E);
 238         SSYNC();
 239 }
 240
 241 static void sdh_finish_request(struct sdh_host *host, struct mmc_request *mrq)
 242 {
 243         dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
 244         host->mrq = NULL;
 245         host->cmd = NULL;
 246         host->data = NULL;
 247         mmc_request_done(host->mmc, mrq);
 248 }
 249
 250 static int sdh_cmd_done(struct sdh_host *host, unsigned int stat)
 251 {
 252         struct mmc_command *cmd = host->cmd;
 253         int ret = 0;
 254
 255         dev_dbg(mmc_dev(host->mmc), "%s enter cmd: %p\n", __func__, cmd);
 256         if (!cmd)
 257                 return 0;
 258
 259         host->cmd = NULL;
 260
 261         if (cmd->flags & MMC_RSP_PRESENT) {
 262                 cmd->resp[0] = bfin_read_SDH_RESPONSE0();
 263                 if (cmd->flags & MMC_RSP_136) {
 264                         cmd->resp[1] = bfin_read_SDH_RESPONSE1();
 265                         cmd->resp[2] = bfin_read_SDH_RESPONSE2();
 266                         cmd->resp[3] = bfin_read_SDH_RESPONSE3();
 267                 }
 268         }
 269         if (stat & CMD_TIME_OUT)
 270                 cmd->error = -ETIMEDOUT;
 271         else if (stat & CMD_CRC_FAIL && cmd->flags & MMC_RSP_CRC)
 272                 cmd->error = -EILSEQ;
 273
 274         sdh_disable_stat_irq(host, (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL));
 275
 276         if (host->data && !cmd->error) {
 277                 if (host->data->flags & MMC_DATA_WRITE) {
 278                         ret = sdh_setup_data(host, host->data);
 279                         if (ret)
 280                                 return 0;
 281                 }
 282
 283                 sdh_enable_stat_irq(host, DAT_END | RX_OVERRUN | TX_UNDERRUN | DAT_TIME_OUT);
 284         } else
 285                 sdh_finish_request(host, host->mrq);
 286
 287         return 1;
 288 }
 289
 290 static int sdh_data_done(struct sdh_host *host, unsigned int stat)
 291 {
 292         struct mmc_data *data = host->data;
 293
 294         dev_dbg(mmc_dev(host->mmc), "%s enter stat: 0x%x\n", __func__, stat);
 295         if (!data)
 296                 return 0;
 297
 298         disable_dma(host->dma_ch);
 299         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 300                      host->dma_dir);
 301
 302         if (stat & DAT_TIME_OUT)
 303                 data->error = -ETIMEDOUT;
 304         else if (stat & DAT_CRC_FAIL)
 305                 data->error = -EILSEQ;
 306         else if (stat & (RX_OVERRUN | TX_UNDERRUN))
 307                 data->error = -EIO;
 308
 309         if (!data->error)
 310                 data->bytes_xfered = data->blocks * data->blksz;
 311         else
 312                 data->bytes_xfered = 0;
 313
 314         bfin_write_SDH_STATUS_CLR(DAT_END_STAT | DAT_TIMEOUT_STAT | \
 315                         DAT_CRC_FAIL_STAT | DAT_BLK_END_STAT | RX_OVERRUN | TX_UNDERRUN);
 316         bfin_write_SDH_DATA_CTL(0);
 317         SSYNC();
 318
 319         host->data = NULL;
 320         if (host->mrq->stop) {
 321                 sdh_stop_clock(host);
 322                 sdh_start_cmd(host, host->mrq->stop);
 323         } else {
 324                 sdh_finish_request(host, host->mrq);
 325         }
 326
 327         return 1;
 328 }
 329
 330 static void sdh_request(struct mmc_host *mmc, struct mmc_request *mrq)
 331 {
 332         struct sdh_host *host = mmc_priv(mmc);
 333         int ret = 0;
 334
 335         dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
 336         WARN_ON(host->mrq != NULL);
 337
 338         spin_lock(&host->lock);
 339         host->mrq = mrq;
 340         host->data = mrq->data;
 341
 342         if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
 343                 ret = sdh_setup_data(host, mrq->data);
 344                 if (ret)
 345                         goto data_err;
 346         }
 347
 348         sdh_start_cmd(host, mrq->cmd);
 349 data_err:
 350         spin_unlock(&host->lock);
 351 }
 352
 353 static void sdh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 354 {
 355         struct sdh_host *host;
 356         u16 clk_ctl = 0;
 357 #ifndef RSI_BLKSZ
 358         u16 pwr_ctl = 0;
 359 #endif
 360         u16 cfg;
 361         host = mmc_priv(mmc);
 362
 363         spin_lock(&host->lock);
 364
 365         cfg = bfin_read_SDH_CFG();
 366         cfg |= MWE;
 367         switch (ios->bus_width) {
 368         case MMC_BUS_WIDTH_4:
 369 #ifndef RSI_BLKSZ
 370                 cfg &= ~PD_SDDAT3;
 371 #endif
 372                 cfg |= PUP_SDDAT3;
 373                 /* Enable 4 bit SDIO */
 374                 cfg |= SD4E;
 375                 clk_ctl |= WIDE_BUS_4;
 376                 break;
 377         case MMC_BUS_WIDTH_8:
 378 #ifndef RSI_BLKSZ
 379                 cfg &= ~PD_SDDAT3;
 380 #endif
 381                 cfg |= PUP_SDDAT3;
 382                 /* Disable 4 bit SDIO */
 383                 cfg &= ~SD4E;
 384                 clk_ctl |= BYTE_BUS_8;
 385                 break;
 386         default:
 387                 cfg &= ~PUP_SDDAT3;
 388                 /* Disable 4 bit SDIO */
 389                 cfg &= ~SD4E;
 390         }
 391         bfin_write_SDH_CFG(cfg);
 392
 393         host->power_mode = ios->power_mode;
 394 #ifndef RSI_BLKSZ
 395         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
 396                 pwr_ctl |= ROD_CTL;
 397 # ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
 398                 pwr_ctl |= SD_CMD_OD;
 399 # endif
 400         }
 401
 402         if (ios->power_mode != MMC_POWER_OFF)
 403                 pwr_ctl |= PWR_ON;
 404         else
 405                 pwr_ctl &= ~PWR_ON;
 406
 407         bfin_write_SDH_PWR_CTL(pwr_ctl);
 408 #else
 409 # ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
 410         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 411                 cfg |= SD_CMD_OD;
 412         else
 413                 cfg &= ~SD_CMD_OD;
 414 # endif
 415
 416         if (ios->power_mode != MMC_POWER_OFF)
 417                 cfg |= PWR_ON;
 418         else
 419                 cfg &= ~PWR_ON;
 420
 421         bfin_write_SDH_CFG(cfg);
 422 #endif
 423         SSYNC();
 424
 425         if (ios->power_mode == MMC_POWER_ON && ios->clock) {
 426                 unsigned char clk_div;
 427                 clk_div = (get_sclk() / ios->clock - 1) / 2;
 428                 clk_div = min_t(unsigned char, clk_div, 0xFF);
 429                 clk_ctl |= clk_div;
 430                 clk_ctl |= CLK_E;
 431                 host->clk_div = clk_div;
 432                 bfin_write_SDH_CLK_CTL(clk_ctl);
 433         } else
 434                 sdh_stop_clock(host);
 435
 436         /* set up sdh interrupt mask*/
 437         if (ios->power_mode == MMC_POWER_ON)
 438                 bfin_write_SDH_MASK0(DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
 439                         RX_OVERRUN | TX_UNDERRUN | CMD_SENT | CMD_RESP_END |
 440                         CMD_TIME_OUT | CMD_CRC_FAIL);
 441         else
 442                 bfin_write_SDH_MASK0(0);
 443         SSYNC();
 444
 445         spin_unlock(&host->lock);
 446
 447         dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
 448                 host->clk_div,
 449                 host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0,
 450                 ios->clock);
 451 }
 452
 453 static const struct mmc_host_ops sdh_ops = {
 454         .request        = sdh_request,
 455         .set_ios        = sdh_set_ios,
 456 };
 457
 458 static irqreturn_t sdh_dma_irq(int irq, void *devid)
 459 {
 460         struct sdh_host *host = devid;
 461
 462         dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04lx\n", __func__,
 463                 get_dma_curr_irqstat(host->dma_ch));
 464         clear_dma_irqstat(host->dma_ch);
 465         SSYNC();
 466
 467         return IRQ_HANDLED;
 468 }
 469
 470 static irqreturn_t sdh_stat_irq(int irq, void *devid)
 471 {
 472         struct sdh_host *host = devid;
 473         unsigned int status;
 474         int handled = 0;
 475
 476         dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
 477
 478         spin_lock(&host->lock);
 479
 480         status = bfin_read_SDH_E_STATUS();
 481         if (status & SD_CARD_DET) {
 482                 mmc_detect_change(host->mmc, 0);
 483                 bfin_write_SDH_E_STATUS(SD_CARD_DET);
 484         }
 485         status = bfin_read_SDH_STATUS();
 486         if (status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL)) {
 487                 handled |= sdh_cmd_done(host, status);
 488                 bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | \
 489                                 CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
 490                 SSYNC();
 491         }
 492
 493         status = bfin_read_SDH_STATUS();
 494         if (status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN))
 495                 handled |= sdh_data_done(host, status);
 496
 497         spin_unlock(&host->lock);
 498
 499         dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);
 500
 501         return IRQ_RETVAL(handled);
 502 }
 503
 504 static void sdh_reset(void)
 505 {
 506 #if defined(CONFIG_BF54x)
 507         /* Secure Digital Host shares DMA with Nand controller */
 508         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
 509 #endif
 510
 511         bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
 512         SSYNC();
 513
 514         /* Disable card inserting detection pin. set MMC_CAP_NEEDS_POLL, and
 515          * mmc stack will do the detection.
 516          */
 517         bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
 518         SSYNC();
 519 }
 520
 521 static int sdh_probe(struct platform_device *pdev)
 522 {
 523         struct mmc_host *mmc;
 524         struct sdh_host *host;
 525         struct bfin_sd_host *drv_data = get_sdh_data(pdev);
 526         int ret;
 527
 528         if (!drv_data) {
 529                 dev_err(&pdev->dev, "missing platform driver data\n");
 530                 ret = -EINVAL;
 531                 goto out;
 532         }
 533
 534         mmc = mmc_alloc_host(sizeof(struct sdh_host), &pdev->dev);
 535         if (!mmc) {
 536                 ret = -ENOMEM;
 537                 goto out;
 538         }
 539
 540         mmc->ops = &sdh_ops;
 541 #if defined(CONFIG_BF51x)
 542         mmc->max_segs = 1;
 543 #else
 544         mmc->max_segs = PAGE_SIZE / sizeof(struct dma_desc_array);
 545 #endif
 546 #ifdef RSI_BLKSZ
 547         mmc->max_seg_size = -1;
 548 #else
 549         mmc->max_seg_size = 1 << 16;
 550 #endif
 551         mmc->max_blk_size = 1 << 11;
 552         mmc->max_blk_count = 1 << 11;
 553         mmc->max_req_size = PAGE_SIZE;
 554         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 555         mmc->f_max = get_sclk();
 556         mmc->f_min = mmc->f_max >> 9;
 557         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL;
 558         host = mmc_priv(mmc);
 559         host->mmc = mmc;
 560         host->sclk = get_sclk();
 561
 562         spin_lock_init(&host->lock);
 563         host->irq = drv_data->irq_int0;
 564         host->dma_ch = drv_data->dma_chan;
 565
 566         ret = request_dma(host->dma_ch, DRIVER_NAME "DMA");
 567         if (ret) {
 568                 dev_err(&pdev->dev, "unable to request DMA channel\n");
 569                 goto out1;
 570         }
 571
 572         ret = set_dma_callback(host->dma_ch, sdh_dma_irq, host);
 573         if (ret) {
 574                 dev_err(&pdev->dev, "unable to request DMA irq\n");
 575                 goto out2;
 576         }
 577
 578         host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
 579         if (host->sg_cpu == NULL) {
 580                 ret = -ENOMEM;
 581                 goto out2;
 582         }
 583
 584         platform_set_drvdata(pdev, mmc);
 585
 586         ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
 587         if (ret) {
 588                 dev_err(&pdev->dev, "unable to request status irq\n");
 589                 goto out3;
 590         }
 591
 592         ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
 593         if (ret) {
 594                 dev_err(&pdev->dev, "unable to request peripheral pins\n");
 595                 goto out4;
 596         }
 597
 598         sdh_reset();
 599
 600         mmc_add_host(mmc);
 601         return 0;
 602
 603 out4:
 604         free_irq(host->irq, host);
 605 out3:
 606         mmc_remove_host(mmc);
 607         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 608 out2:
 609         free_dma(host->dma_ch);
 610 out1:
 611         mmc_free_host(mmc);
 612  out:
 613         return ret;
 614 }
 615
 616 static int sdh_remove(struct platform_device *pdev)
 617 {
 618         struct mmc_host *mmc = platform_get_drvdata(pdev);
 619
 620         if (mmc) {
 621                 struct sdh_host *host = mmc_priv(mmc);
 622
 623                 mmc_remove_host(mmc);
 624
 625                 sdh_stop_clock(host);
 626                 free_irq(host->irq, host);
 627                 free_dma(host->dma_ch);
 628                 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 629
 630                 mmc_free_host(mmc);
 631         }
 632
 633         return 0;
 634 }
 635
 636 #ifdef CONFIG_PM
 637 static int sdh_suspend(struct platform_device *dev, pm_message_t state)
 638 {
 639         struct bfin_sd_host *drv_data = get_sdh_data(dev);
 640
 641         peripheral_free_list(drv_data->pin_req);
 642
 643         return 0;
 644 }
 645
 646 static int sdh_resume(struct platform_device *dev)
 647 {
 648         struct bfin_sd_host *drv_data = get_sdh_data(dev);
 649         int ret = 0;
 650
 651         ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
 652         if (ret) {
 653                 dev_err(&dev->dev, "unable to request peripheral pins\n");
 654                 return ret;
 655         }
 656
 657         sdh_reset();
 658         return ret;
 659 }
 660 #else
 661 # define sdh_suspend NULL
 662 # define sdh_resume  NULL
 663 #endif
 664
 665 static struct platform_driver sdh_driver = {
 666         .probe   = sdh_probe,
 667         .remove  = sdh_remove,
 668         .suspend = sdh_suspend,
 669         .resume  = sdh_resume,
 670         .driver  = {
 671                 .name = DRIVER_NAME,
 672         },
 673 };
 674
 675 module_platform_driver(sdh_driver);
 676
 677 MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
 678 MODULE_AUTHOR("Cliff Cai, Roy Huang");
 679 MODULE_LICENSE("GPL");