2 * meson-mx-sdio.c - Meson6, Meson8 and Meson8b SDIO/MMC Host Controller
4 * Copyright (C) 2015 Endless Mobile, Inc.
5 * Author: Carlo Caione <carlo@endlessm.com>
6 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or (at
11 * your option) any later version.
14 #include <linux/bitfield.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/module.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_platform.h>
25 #include <linux/timer.h>
26 #include <linux/types.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/mmc.h>
30 #include <linux/mmc/sdio.h>
31 #include <linux/mmc/slot-gpio.h>
33 #define MESON_MX_SDIO_ARGU 0x00
35 #define MESON_MX_SDIO_SEND 0x04
36 #define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK GENMASK(7, 0)
37 #define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK GENMASK(15, 8)
38 #define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7 BIT(16)
39 #define MESON_MX_SDIO_SEND_RESP_HAS_DATA BIT(17)
40 #define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8 BIT(18)
41 #define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY BIT(19)
42 #define MESON_MX_SDIO_SEND_DATA BIT(20)
43 #define MESON_MX_SDIO_SEND_USE_INT_WINDOW BIT(21)
44 #define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK GENMASK(31, 24)
46 #define MESON_MX_SDIO_CONF 0x08
47 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT 0
48 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH 10
49 #define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC BIT(10)
50 #define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11)
51 #define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK GENMASK(17, 12)
52 #define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE BIT(18)
53 #define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE BIT(19)
54 #define MESON_MX_SDIO_CONF_BUS_WIDTH BIT(20)
55 #define MESON_MX_SDIO_CONF_M_ENDIAN_MASK GENMASK(22, 21)
56 #define MESON_MX_SDIO_CONF_WRITE_NWR_MASK GENMASK(28, 23)
57 #define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29)
59 #define MESON_MX_SDIO_IRQS 0x0c
60 #define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK GENMASK(3, 0)
61 #define MESON_MX_SDIO_IRQS_CMD_BUSY BIT(4)
62 #define MESON_MX_SDIO_IRQS_RESP_CRC7_OK BIT(5)
63 #define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK BIT(6)
64 #define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK BIT(7)
65 #define MESON_MX_SDIO_IRQS_IF_INT BIT(8)
66 #define MESON_MX_SDIO_IRQS_CMD_INT BIT(9)
67 #define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK GENMASK(15, 12)
68 #define MESON_MX_SDIO_IRQS_TIMING_OUT_INT BIT(16)
69 #define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17)
70 #define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN BIT(18)
71 #define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK GENMASK(31, 19)
73 #define MESON_MX_SDIO_IRQC 0x10
74 #define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN BIT(3)
75 #define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN BIT(4)
76 #define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK GENMASK(7, 6)
77 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK BIT(8)
78 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD BIT(9)
79 #define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK GENMASK(13, 10)
80 #define MESON_MX_SDIO_IRQC_SOFT_RESET BIT(15)
81 #define MESON_MX_SDIO_IRQC_FORCE_HALT BIT(30)
82 #define MESON_MX_SDIO_IRQC_HALT_HOLE BIT(31)
84 #define MESON_MX_SDIO_MULT 0x14
85 #define MESON_MX_SDIO_MULT_PORT_SEL_MASK GENMASK(1, 0)
86 #define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE BIT(2)
87 #define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3)
88 #define MESON_MX_SDIO_MULT_STREAM_ENABLE BIT(4)
89 #define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE BIT(5)
90 #define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX BIT(8)
91 #define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED BIT(10)
92 #define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED BIT(11)
93 #define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK GENMASK(15, 12)
95 #define MESON_MX_SDIO_ADDR 0x18
97 #define MESON_MX_SDIO_EXT 0x1c
98 #define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK GENMASK(29, 16)
100 #define MESON_MX_SDIO_BOUNCE_REQ_SIZE (128 * 1024)
101 #define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1)
102 #define MESON_MX_SDIO_MAX_SLOTS 3
104 struct meson_mx_mmc_host {
105 struct device *controller_dev;
107 struct clk *parent_clk;
108 struct clk *core_clk;
109 struct clk_divider cfg_div;
110 struct clk *cfg_div_clk;
111 struct clk_fixed_factor fixed_factor;
112 struct clk *fixed_factor_clk;
118 struct timer_list cmd_timeout;
120 unsigned int slot_id;
121 struct mmc_host *mmc;
123 struct mmc_request *mrq;
124 struct mmc_command *cmd;
128 static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask,
131 struct meson_mx_mmc_host *host = mmc_priv(mmc);
134 regval = readl(host->base + reg);
136 regval |= (val & mask);
138 writel(regval, host->base + reg);
141 static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host *host)
143 writel(MESON_MX_SDIO_IRQC_SOFT_RESET, host->base + MESON_MX_SDIO_IRQC);
147 static struct mmc_command *meson_mx_mmc_get_next_cmd(struct mmc_command *cmd)
149 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
150 return cmd->mrq->cmd;
151 else if (mmc_op_multi(cmd->opcode) &&
152 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
153 return cmd->mrq->stop;
158 static void meson_mx_mmc_start_cmd(struct mmc_host *mmc,
159 struct mmc_command *cmd)
161 struct meson_mx_mmc_host *host = mmc_priv(mmc);
162 unsigned int pack_size;
163 unsigned long irqflags, timeout;
164 u32 mult, send = 0, ext = 0;
168 if (cmd->busy_timeout)
169 timeout = msecs_to_jiffies(cmd->busy_timeout);
171 timeout = msecs_to_jiffies(1000);
173 switch (mmc_resp_type(cmd)) {
177 /* 7 (CMD) + 32 (response) + 7 (CRC) -1 */
178 send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 45);
181 /* 7 (CMD) + 120 (response) + 7 (CRC) -1 */
182 send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 133);
183 send |= MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8;
189 if (!(cmd->flags & MMC_RSP_CRC))
190 send |= MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7;
192 if (cmd->flags & MMC_RSP_BUSY)
193 send |= MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY;
196 send |= FIELD_PREP(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK,
197 (cmd->data->blocks - 1));
199 pack_size = cmd->data->blksz * BITS_PER_BYTE;
200 if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
201 pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 4;
203 pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 1;
205 ext |= FIELD_PREP(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK,
208 if (cmd->data->flags & MMC_DATA_WRITE)
209 send |= MESON_MX_SDIO_SEND_DATA;
211 send |= MESON_MX_SDIO_SEND_RESP_HAS_DATA;
213 cmd->data->bytes_xfered = 0;
216 send |= FIELD_PREP(MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK,
217 (0x40 | cmd->opcode));
219 spin_lock_irqsave(&host->irq_lock, irqflags);
221 mult = readl(host->base + MESON_MX_SDIO_MULT);
222 mult &= ~MESON_MX_SDIO_MULT_PORT_SEL_MASK;
223 mult |= FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK, host->slot_id);
225 writel(mult, host->base + MESON_MX_SDIO_MULT);
227 /* enable the CMD done interrupt */
228 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQC,
229 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN,
230 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN);
232 /* clear pending interrupts */
233 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQS,
234 MESON_MX_SDIO_IRQS_CMD_INT,
235 MESON_MX_SDIO_IRQS_CMD_INT);
237 writel(cmd->arg, host->base + MESON_MX_SDIO_ARGU);
238 writel(ext, host->base + MESON_MX_SDIO_EXT);
239 writel(send, host->base + MESON_MX_SDIO_SEND);
241 spin_unlock_irqrestore(&host->irq_lock, irqflags);
243 mod_timer(&host->cmd_timeout, jiffies + timeout);
246 static void meson_mx_mmc_request_done(struct meson_mx_mmc_host *host)
248 struct mmc_request *mrq;
252 if (host->cmd->error)
253 meson_mx_mmc_soft_reset(host);
258 mmc_request_done(host->mmc, mrq);
261 static void meson_mx_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
263 struct meson_mx_mmc_host *host = mmc_priv(mmc);
264 unsigned short vdd = ios->vdd;
265 unsigned long clk_rate = ios->clock;
267 switch (ios->bus_width) {
268 case MMC_BUS_WIDTH_1:
269 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF,
270 MESON_MX_SDIO_CONF_BUS_WIDTH, 0);
273 case MMC_BUS_WIDTH_4:
274 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF,
275 MESON_MX_SDIO_CONF_BUS_WIDTH,
276 MESON_MX_SDIO_CONF_BUS_WIDTH);
279 case MMC_BUS_WIDTH_8:
281 dev_err(mmc_dev(mmc), "unsupported bus width: %d\n",
283 host->error = -EINVAL;
287 host->error = clk_set_rate(host->cfg_div_clk, ios->clock);
289 dev_warn(mmc_dev(mmc),
290 "failed to set MMC clock to %lu: %d\n",
291 clk_rate, host->error);
295 mmc->actual_clock = clk_get_rate(host->cfg_div_clk);
297 switch (ios->power_mode) {
302 if (!IS_ERR(mmc->supply.vmmc)) {
303 host->error = mmc_regulator_set_ocr(mmc,
313 static int meson_mx_mmc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq)
315 struct mmc_data *data = mrq->data;
317 struct scatterlist *sg;
323 if (sg->offset & 3 || sg->length & 3) {
324 dev_err(mmc_dev(mmc),
325 "unaligned scatterlist: offset %x length %d\n",
326 sg->offset, sg->length);
330 dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
331 mmc_get_dma_dir(data));
333 dev_err(mmc_dev(mmc), "dma_map_sg failed\n");
340 static void meson_mx_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
342 struct meson_mx_mmc_host *host = mmc_priv(mmc);
343 struct mmc_command *cmd = mrq->cmd;
346 host->error = meson_mx_mmc_map_dma(mmc, mrq);
349 cmd->error = host->error;
350 mmc_request_done(mmc, mrq);
357 writel(sg_dma_address(mrq->data->sg),
358 host->base + MESON_MX_SDIO_ADDR);
361 meson_mx_mmc_start_cmd(mmc, mrq->sbc);
363 meson_mx_mmc_start_cmd(mmc, mrq->cmd);
366 static void meson_mx_mmc_read_response(struct mmc_host *mmc,
367 struct mmc_command *cmd)
369 struct meson_mx_mmc_host *host = mmc_priv(mmc);
373 mult = readl(host->base + MESON_MX_SDIO_MULT);
374 mult |= MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX;
375 mult &= ~MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK;
376 mult |= FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK, 0);
377 writel(mult, host->base + MESON_MX_SDIO_MULT);
379 if (cmd->flags & MMC_RSP_136) {
380 for (i = 0; i <= 3; i++)
381 resp[3 - i] = readl(host->base + MESON_MX_SDIO_ARGU);
382 cmd->resp[0] = (resp[0] << 8) | ((resp[1] >> 24) & 0xff);
383 cmd->resp[1] = (resp[1] << 8) | ((resp[2] >> 24) & 0xff);
384 cmd->resp[2] = (resp[2] << 8) | ((resp[3] >> 24) & 0xff);
385 cmd->resp[3] = (resp[3] << 8);
386 } else if (cmd->flags & MMC_RSP_PRESENT) {
387 cmd->resp[0] = readl(host->base + MESON_MX_SDIO_ARGU);
391 static irqreturn_t meson_mx_mmc_process_cmd_irq(struct meson_mx_mmc_host *host,
394 struct mmc_command *cmd = host->cmd;
397 * NOTE: even though it shouldn't happen we sometimes get command
398 * interrupts twice (at least this is what it looks like). Ideally
399 * we find out why this happens and warn here as soon as it occurs.
405 meson_mx_mmc_read_response(host->mmc, cmd);
408 if (!((irqs & MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK) ||
409 (irqs & MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK)))
410 cmd->error = -EILSEQ;
412 if (!((irqs & MESON_MX_SDIO_IRQS_RESP_CRC7_OK) ||
413 (send & MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7)))
414 cmd->error = -EILSEQ;
417 return IRQ_WAKE_THREAD;
420 static irqreturn_t meson_mx_mmc_irq(int irq, void *data)
422 struct meson_mx_mmc_host *host = (void *) data;
424 unsigned long irqflags;
427 spin_lock_irqsave(&host->irq_lock, irqflags);
429 irqs = readl(host->base + MESON_MX_SDIO_IRQS);
430 send = readl(host->base + MESON_MX_SDIO_SEND);
432 if (irqs & MESON_MX_SDIO_IRQS_CMD_INT)
433 ret = meson_mx_mmc_process_cmd_irq(host, irqs, send);
437 /* finally ACK all pending interrupts */
438 writel(irqs, host->base + MESON_MX_SDIO_IRQS);
440 spin_unlock_irqrestore(&host->irq_lock, irqflags);
445 static irqreturn_t meson_mx_mmc_irq_thread(int irq, void *irq_data)
447 struct meson_mx_mmc_host *host = (void *) irq_data;
448 struct mmc_command *cmd = host->cmd, *next_cmd;
453 del_timer_sync(&host->cmd_timeout);
456 dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg,
458 mmc_get_dma_dir(cmd->data));
460 cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks;
463 next_cmd = meson_mx_mmc_get_next_cmd(cmd);
465 meson_mx_mmc_start_cmd(host->mmc, next_cmd);
467 meson_mx_mmc_request_done(host);
472 static void meson_mx_mmc_timeout(struct timer_list *t)
474 struct meson_mx_mmc_host *host = from_timer(host, t, cmd_timeout);
475 unsigned long irqflags;
478 spin_lock_irqsave(&host->irq_lock, irqflags);
480 /* disable the CMD interrupt */
481 irqc = readl(host->base + MESON_MX_SDIO_IRQC);
482 irqc &= ~MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN;
483 writel(irqc, host->base + MESON_MX_SDIO_IRQC);
485 spin_unlock_irqrestore(&host->irq_lock, irqflags);
488 * skip the timeout handling if the interrupt handler already processed
494 dev_dbg(mmc_dev(host->mmc),
495 "Timeout on CMD%u (IRQS = 0x%08x, ARGU = 0x%08x)\n",
496 host->cmd->opcode, readl(host->base + MESON_MX_SDIO_IRQS),
497 readl(host->base + MESON_MX_SDIO_ARGU));
499 host->cmd->error = -ETIMEDOUT;
501 meson_mx_mmc_request_done(host);
504 static struct mmc_host_ops meson_mx_mmc_ops = {
505 .request = meson_mx_mmc_request,
506 .set_ios = meson_mx_mmc_set_ios,
507 .get_cd = mmc_gpio_get_cd,
508 .get_ro = mmc_gpio_get_ro,
511 static struct platform_device *meson_mx_mmc_slot_pdev(struct device *parent)
513 struct device_node *slot_node;
514 struct platform_device *pdev;
517 * TODO: the MMC core framework currently does not support
518 * controllers with multiple slots properly. So we only register
519 * the first slot for now
521 slot_node = of_get_compatible_child(parent->of_node, "mmc-slot");
523 dev_warn(parent, "no 'mmc-slot' sub-node found\n");
524 return ERR_PTR(-ENOENT);
527 pdev = of_platform_device_create(slot_node, NULL, parent);
528 of_node_put(slot_node);
533 static int meson_mx_mmc_add_host(struct meson_mx_mmc_host *host)
535 struct mmc_host *mmc = host->mmc;
536 struct device *slot_dev = mmc_dev(mmc);
539 if (of_property_read_u32(slot_dev->of_node, "reg", &host->slot_id)) {
540 dev_err(slot_dev, "missing 'reg' property\n");
544 if (host->slot_id >= MESON_MX_SDIO_MAX_SLOTS) {
545 dev_err(slot_dev, "invalid 'reg' property value %d\n",
550 /* Get regulators and the supported OCR mask */
551 ret = mmc_regulator_get_supply(mmc);
555 mmc->max_req_size = MESON_MX_SDIO_BOUNCE_REQ_SIZE;
556 mmc->max_seg_size = mmc->max_req_size;
558 FIELD_GET(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK,
560 mmc->max_blk_size = FIELD_GET(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK,
562 mmc->max_blk_size -= (4 * MESON_MX_SDIO_RESPONSE_CRC16_BITS);
563 mmc->max_blk_size /= BITS_PER_BYTE;
565 /* Get the min and max supported clock rates */
566 mmc->f_min = clk_round_rate(host->cfg_div_clk, 1);
567 mmc->f_max = clk_round_rate(host->cfg_div_clk,
568 clk_get_rate(host->parent_clk));
570 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY;
571 mmc->ops = &meson_mx_mmc_ops;
573 ret = mmc_of_parse(mmc);
577 ret = mmc_add_host(mmc);
584 static int meson_mx_mmc_register_clks(struct meson_mx_mmc_host *host)
586 struct clk_init_data init;
587 const char *clk_div_parent, *clk_fixed_factor_parent;
589 clk_fixed_factor_parent = __clk_get_name(host->parent_clk);
590 init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL,
592 dev_name(host->controller_dev));
596 init.ops = &clk_fixed_factor_ops;
598 init.parent_names = &clk_fixed_factor_parent;
599 init.num_parents = 1;
600 host->fixed_factor.div = 2;
601 host->fixed_factor.mult = 1;
602 host->fixed_factor.hw.init = &init;
604 host->fixed_factor_clk = devm_clk_register(host->controller_dev,
605 &host->fixed_factor.hw);
606 if (WARN_ON(IS_ERR(host->fixed_factor_clk)))
607 return PTR_ERR(host->fixed_factor_clk);
609 clk_div_parent = __clk_get_name(host->fixed_factor_clk);
610 init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL,
611 "%s#div", dev_name(host->controller_dev));
615 init.ops = &clk_divider_ops;
616 init.flags = CLK_SET_RATE_PARENT;
617 init.parent_names = &clk_div_parent;
618 init.num_parents = 1;
619 host->cfg_div.reg = host->base + MESON_MX_SDIO_CONF;
620 host->cfg_div.shift = MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT;
621 host->cfg_div.width = MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH;
622 host->cfg_div.hw.init = &init;
623 host->cfg_div.flags = CLK_DIVIDER_ALLOW_ZERO;
625 host->cfg_div_clk = devm_clk_register(host->controller_dev,
627 if (WARN_ON(IS_ERR(host->cfg_div_clk)))
628 return PTR_ERR(host->cfg_div_clk);
633 static int meson_mx_mmc_probe(struct platform_device *pdev)
635 struct platform_device *slot_pdev;
636 struct mmc_host *mmc;
637 struct meson_mx_mmc_host *host;
638 struct resource *res;
642 slot_pdev = meson_mx_mmc_slot_pdev(&pdev->dev);
645 else if (IS_ERR(slot_pdev))
646 return PTR_ERR(slot_pdev);
648 mmc = mmc_alloc_host(sizeof(*host), &slot_pdev->dev);
651 goto error_unregister_slot_pdev;
654 host = mmc_priv(mmc);
656 host->controller_dev = &pdev->dev;
658 spin_lock_init(&host->irq_lock);
659 timer_setup(&host->cmd_timeout, meson_mx_mmc_timeout, 0);
661 platform_set_drvdata(pdev, host);
663 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
664 host->base = devm_ioremap_resource(host->controller_dev, res);
665 if (IS_ERR(host->base)) {
666 ret = PTR_ERR(host->base);
670 irq = platform_get_irq(pdev, 0);
676 ret = devm_request_threaded_irq(host->controller_dev, irq,
678 meson_mx_mmc_irq_thread, IRQF_ONESHOT,
683 host->core_clk = devm_clk_get(host->controller_dev, "core");
684 if (IS_ERR(host->core_clk)) {
685 ret = PTR_ERR(host->core_clk);
689 host->parent_clk = devm_clk_get(host->controller_dev, "clkin");
690 if (IS_ERR(host->parent_clk)) {
691 ret = PTR_ERR(host->parent_clk);
695 ret = meson_mx_mmc_register_clks(host);
699 ret = clk_prepare_enable(host->core_clk);
701 dev_err(host->controller_dev, "Failed to enable core clock\n");
705 ret = clk_prepare_enable(host->cfg_div_clk);
707 dev_err(host->controller_dev, "Failed to enable MMC clock\n");
708 goto error_disable_core_clk;
712 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK, 39);
713 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_M_ENDIAN_MASK, 0x3);
714 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_NWR_MASK, 0x2);
715 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK, 0x2);
716 writel(conf, host->base + MESON_MX_SDIO_CONF);
718 meson_mx_mmc_soft_reset(host);
720 ret = meson_mx_mmc_add_host(host);
722 goto error_disable_clks;
727 clk_disable_unprepare(host->cfg_div_clk);
728 error_disable_core_clk:
729 clk_disable_unprepare(host->core_clk);
732 error_unregister_slot_pdev:
733 of_platform_device_destroy(&slot_pdev->dev, NULL);
737 static int meson_mx_mmc_remove(struct platform_device *pdev)
739 struct meson_mx_mmc_host *host = platform_get_drvdata(pdev);
740 struct device *slot_dev = mmc_dev(host->mmc);
742 del_timer_sync(&host->cmd_timeout);
744 mmc_remove_host(host->mmc);
746 of_platform_device_destroy(slot_dev, NULL);
748 clk_disable_unprepare(host->cfg_div_clk);
749 clk_disable_unprepare(host->core_clk);
751 mmc_free_host(host->mmc);
756 static const struct of_device_id meson_mx_mmc_of_match[] = {
757 { .compatible = "amlogic,meson8-sdio", },
758 { .compatible = "amlogic,meson8b-sdio", },
761 MODULE_DEVICE_TABLE(of, meson_mx_mmc_of_match);
763 static struct platform_driver meson_mx_mmc_driver = {
764 .probe = meson_mx_mmc_probe,
765 .remove = meson_mx_mmc_remove,
767 .name = "meson-mx-sdio",
768 .of_match_table = of_match_ptr(meson_mx_mmc_of_match),
772 module_platform_driver(meson_mx_mmc_driver);
774 MODULE_DESCRIPTION("Meson6, Meson8 and Meson8b SDIO/MMC Host Driver");
775 MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
776 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
777 MODULE_LICENSE("GPL v2");