drivers/mmc/host/rtsx_pci_sdmmc.c

   1 /* Realtek PCI-Express SD/MMC Card Interface driver
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <linux/highmem.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/sd.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/card.h>
  33 #include <linux/mfd/rtsx_pci.h>
  34 #include <asm/unaligned.h>
  35
  36 struct realtek_pci_sdmmc {
  37         struct platform_device  *pdev;
  38         struct rtsx_pcr         *pcr;
  39         struct mmc_host         *mmc;
  40         struct mmc_request      *mrq;
  41 #define SDMMC_WORKQ_NAME        "rtsx_pci_sdmmc_workq"
  42
  43         struct work_struct      work;
  44         struct mutex            host_mutex;
  45
  46         u8                      ssc_depth;
  47         unsigned int            clock;
  48         bool                    vpclk;
  49         bool                    double_clk;
  50         bool                    eject;
  51         bool                    initial_mode;
  52         int                     prev_power_state;
  53         int                     sg_count;
  54         s32                     cookie;
  55         int                     cookie_sg_count;
  56         bool                    using_cookie;
  57 };
  58
  59 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
  60 {
  61         return &(host->pdev->dev);
  62 }
  63
  64 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
  65 {
  66         rtsx_pci_write_register(host->pcr, CARD_STOP,
  67                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
  68 }
  69
  70 #ifdef DEBUG
  71 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
  72 {
  73         u16 len = end - start + 1;
  74         int i;
  75         u8 data[8];
  76
  77         for (i = 0; i < len; i += 8) {
  78                 int j;
  79                 int n = min(8, len - i);
  80
  81                 memset(&data, 0, sizeof(data));
  82                 for (j = 0; j < n; j++)
  83                         rtsx_pci_read_register(host->pcr, start + i + j,
  84                                 data + j);
  85                 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
  86                         start + i, n, data);
  87         }
  88 }
  89
  90 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
  91 {
  92         dump_reg_range(host, 0xFDA0, 0xFDB3);
  93         dump_reg_range(host, 0xFD52, 0xFD69);
  94 }
  95 #else
  96 #define sd_print_debug_regs(host)
  97 #endif /* DEBUG */
  98
  99 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
 100 {
 101         return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
 102 }
 103
 104 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
 105 {
 106         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
 107                 SD_CMD_START | cmd->opcode);
 108         rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
 109 }
 110
 111 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
 112 {
 113         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
 114         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
 115         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
 116         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
 117 }
 118
 119 static int sd_response_type(struct mmc_command *cmd)
 120 {
 121         switch (mmc_resp_type(cmd)) {
 122         case MMC_RSP_NONE:
 123                 return SD_RSP_TYPE_R0;
 124         case MMC_RSP_R1:
 125                 return SD_RSP_TYPE_R1;
 126         case MMC_RSP_R1_NO_CRC:
 127                 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
 128         case MMC_RSP_R1B:
 129                 return SD_RSP_TYPE_R1b;
 130         case MMC_RSP_R2:
 131                 return SD_RSP_TYPE_R2;
 132         case MMC_RSP_R3:
 133                 return SD_RSP_TYPE_R3;
 134         default:
 135                 return -EINVAL;
 136         }
 137 }
 138
 139 static int sd_status_index(int resp_type)
 140 {
 141         if (resp_type == SD_RSP_TYPE_R0)
 142                 return 0;
 143         else if (resp_type == SD_RSP_TYPE_R2)
 144                 return 16;
 145
 146         return 5;
 147 }
 148 /*
 149  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
 150  *
 151  * @pre: if called in pre_req()
 152  * return:
 153  *      0 - do dma_map_sg()
 154  *      1 - using cookie
 155  */
 156 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
 157                 struct mmc_data *data, bool pre)
 158 {
 159         struct rtsx_pcr *pcr = host->pcr;
 160         int read = data->flags & MMC_DATA_READ;
 161         int count = 0;
 162         int using_cookie = 0;
 163
 164         if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
 165                 dev_err(sdmmc_dev(host),
 166                         "error: data->host_cookie = %d, host->cookie = %d\n",
 167                         data->host_cookie, host->cookie);
 168                 data->host_cookie = 0;
 169         }
 170
 171         if (pre || data->host_cookie != host->cookie) {
 172                 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
 173         } else {
 174                 count = host->cookie_sg_count;
 175                 using_cookie = 1;
 176         }
 177
 178         if (pre) {
 179                 host->cookie_sg_count = count;
 180                 if (++host->cookie < 0)
 181                         host->cookie = 1;
 182                 data->host_cookie = host->cookie;
 183         } else {
 184                 host->sg_count = count;
 185         }
 186
 187         return using_cookie;
 188 }
 189
 190 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
 191                 bool is_first_req)
 192 {
 193         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 194         struct mmc_data *data = mrq->data;
 195
 196         if (data->host_cookie) {
 197                 dev_err(sdmmc_dev(host),
 198                         "error: reset data->host_cookie = %d\n",
 199                         data->host_cookie);
 200                 data->host_cookie = 0;
 201         }
 202
 203         sd_pre_dma_transfer(host, data, true);
 204         dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
 205 }
 206
 207 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 208                 int err)
 209 {
 210         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 211         struct rtsx_pcr *pcr = host->pcr;
 212         struct mmc_data *data = mrq->data;
 213         int read = data->flags & MMC_DATA_READ;
 214
 215         rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
 216         data->host_cookie = 0;
 217 }
 218
 219 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
 220                 struct mmc_command *cmd)
 221 {
 222         struct rtsx_pcr *pcr = host->pcr;
 223         u8 cmd_idx = (u8)cmd->opcode;
 224         u32 arg = cmd->arg;
 225         int err = 0;
 226         int timeout = 100;
 227         int i;
 228         u8 *ptr;
 229         int rsp_type;
 230         int stat_idx;
 231         bool clock_toggled = false;
 232
 233         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 234                         __func__, cmd_idx, arg);
 235
 236         rsp_type = sd_response_type(cmd);
 237         if (rsp_type < 0)
 238                 goto out;
 239
 240         stat_idx = sd_status_index(rsp_type);
 241
 242         if (rsp_type == SD_RSP_TYPE_R1b)
 243                 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
 244
 245         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 246                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
 247                                 0xFF, SD_CLK_TOGGLE_EN);
 248                 if (err < 0)
 249                         goto out;
 250
 251                 clock_toggled = true;
 252         }
 253
 254         rtsx_pci_init_cmd(pcr);
 255         sd_cmd_set_sd_cmd(pcr, cmd);
 256         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 257         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 258                         0x01, PINGPONG_BUFFER);
 259         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 260                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 261         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 262                      SD_TRANSFER_END | SD_STAT_IDLE,
 263                      SD_TRANSFER_END | SD_STAT_IDLE);
 264
 265         if (rsp_type == SD_RSP_TYPE_R2) {
 266                 /* Read data from ping-pong buffer */
 267                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
 268                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 269         } else if (rsp_type != SD_RSP_TYPE_R0) {
 270                 /* Read data from SD_CMDx registers */
 271                 for (i = SD_CMD0; i <= SD_CMD4; i++)
 272                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 273         }
 274
 275         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
 276
 277         err = rtsx_pci_send_cmd(pcr, timeout);
 278         if (err < 0) {
 279                 sd_print_debug_regs(host);
 280                 sd_clear_error(host);
 281                 dev_dbg(sdmmc_dev(host),
 282                         "rtsx_pci_send_cmd error (err = %d)\n", err);
 283                 goto out;
 284         }
 285
 286         if (rsp_type == SD_RSP_TYPE_R0) {
 287                 err = 0;
 288                 goto out;
 289         }
 290
 291         /* Eliminate returned value of CHECK_REG_CMD */
 292         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
 293
 294         /* Check (Start,Transmission) bit of Response */
 295         if ((ptr[0] & 0xC0) != 0) {
 296                 err = -EILSEQ;
 297                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
 298                 goto out;
 299         }
 300
 301         /* Check CRC7 */
 302         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 303                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 304                         err = -EILSEQ;
 305                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
 306                         goto out;
 307                 }
 308         }
 309
 310         if (rsp_type == SD_RSP_TYPE_R2) {
 311                 /*
 312                  * The controller offloads the last byte {CRC-7, end bit 1'b1}
 313                  * of response type R2. Assign dummy CRC, 0, and end bit to the
 314                  * byte(ptr[16], goes into the LSB of resp[3] later).
 315                  */
 316                 ptr[16] = 1;
 317
 318                 for (i = 0; i < 4; i++) {
 319                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
 320                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
 321                                         i, cmd->resp[i]);
 322                 }
 323         } else {
 324                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
 325                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
 326                                 cmd->resp[0]);
 327         }
 328
 329 out:
 330         cmd->error = err;
 331
 332         if (err && clock_toggled)
 333                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
 334                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 335 }
 336
 337 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
 338         u16 byte_cnt, u8 *buf, int buf_len, int timeout)
 339 {
 340         struct rtsx_pcr *pcr = host->pcr;
 341         int err;
 342         u8 trans_mode;
 343
 344         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 345                 __func__, cmd->opcode, cmd->arg);
 346
 347         if (!buf)
 348                 buf_len = 0;
 349
 350         if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
 351                 trans_mode = SD_TM_AUTO_TUNING;
 352         else
 353                 trans_mode = SD_TM_NORMAL_READ;
 354
 355         rtsx_pci_init_cmd(pcr);
 356         sd_cmd_set_sd_cmd(pcr, cmd);
 357         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 358         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 359                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 360                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 361         if (trans_mode != SD_TM_AUTO_TUNING)
 362                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 363                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 364
 365         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 366                         0xFF, trans_mode | SD_TRANSFER_START);
 367         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 368                         SD_TRANSFER_END, SD_TRANSFER_END);
 369
 370         err = rtsx_pci_send_cmd(pcr, timeout);
 371         if (err < 0) {
 372                 sd_print_debug_regs(host);
 373                 dev_dbg(sdmmc_dev(host),
 374                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 375                 return err;
 376         }
 377
 378         if (buf && buf_len) {
 379                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
 380                 if (err < 0) {
 381                         dev_dbg(sdmmc_dev(host),
 382                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
 383                         return err;
 384                 }
 385         }
 386
 387         return 0;
 388 }
 389
 390 static int sd_write_data(struct realtek_pci_sdmmc *host,
 391         struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
 392         int timeout)
 393 {
 394         struct rtsx_pcr *pcr = host->pcr;
 395         int err;
 396
 397         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 398                 __func__, cmd->opcode, cmd->arg);
 399
 400         if (!buf)
 401                 buf_len = 0;
 402
 403         sd_send_cmd_get_rsp(host, cmd);
 404         if (cmd->error)
 405                 return cmd->error;
 406
 407         if (buf && buf_len) {
 408                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
 409                 if (err < 0) {
 410                         dev_dbg(sdmmc_dev(host),
 411                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
 412                         return err;
 413                 }
 414         }
 415
 416         rtsx_pci_init_cmd(pcr);
 417         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 418         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 419                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 420                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
 421         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 422                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 423         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 424                         SD_TRANSFER_END, SD_TRANSFER_END);
 425
 426         err = rtsx_pci_send_cmd(pcr, timeout);
 427         if (err < 0) {
 428                 sd_print_debug_regs(host);
 429                 dev_dbg(sdmmc_dev(host),
 430                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 431                 return err;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
 438         struct mmc_request *mrq)
 439 {
 440         struct rtsx_pcr *pcr = host->pcr;
 441         struct mmc_host *mmc = host->mmc;
 442         struct mmc_card *card = mmc->card;
 443         struct mmc_command *cmd = mrq->cmd;
 444         struct mmc_data *data = mrq->data;
 445         int uhs = mmc_card_uhs(card);
 446         u8 cfg2 = 0;
 447         int err;
 448         int resp_type;
 449         size_t data_len = data->blksz * data->blocks;
 450
 451         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 452                 __func__, cmd->opcode, cmd->arg);
 453
 454         resp_type = sd_response_type(cmd);
 455         if (resp_type < 0)
 456                 return resp_type;
 457
 458         if (!uhs)
 459                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 460
 461         rtsx_pci_init_cmd(pcr);
 462         sd_cmd_set_sd_cmd(pcr, cmd);
 463         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 464         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 465                         DMA_DONE_INT, DMA_DONE_INT);
 466         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 467                 0xFF, (u8)(data_len >> 24));
 468         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 469                 0xFF, (u8)(data_len >> 16));
 470         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 471                 0xFF, (u8)(data_len >> 8));
 472         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 473         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 474                 0x03 | DMA_PACK_SIZE_MASK,
 475                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
 476         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 477                         0x01, RING_BUFFER);
 478         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
 479         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 480                         SD_TRANSFER_START | SD_TM_AUTO_READ_2);
 481         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 482                         SD_TRANSFER_END, SD_TRANSFER_END);
 483         rtsx_pci_send_cmd_no_wait(pcr);
 484
 485         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
 486         if (err < 0) {
 487                 sd_print_debug_regs(host);
 488                 sd_clear_error(host);
 489                 return err;
 490         }
 491
 492         return 0;
 493 }
 494
 495 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
 496         struct mmc_request *mrq)
 497 {
 498         struct rtsx_pcr *pcr = host->pcr;
 499         struct mmc_host *mmc = host->mmc;
 500         struct mmc_card *card = mmc->card;
 501         struct mmc_command *cmd = mrq->cmd;
 502         struct mmc_data *data = mrq->data;
 503         int uhs = mmc_card_uhs(card);
 504         u8 cfg2;
 505         int err;
 506         size_t data_len = data->blksz * data->blocks;
 507
 508         sd_send_cmd_get_rsp(host, cmd);
 509         if (cmd->error)
 510                 return cmd->error;
 511
 512         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 513                 __func__, cmd->opcode, cmd->arg);
 514
 515         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 516                 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
 517
 518         if (!uhs)
 519                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 520
 521         rtsx_pci_init_cmd(pcr);
 522         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 523         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 524                         DMA_DONE_INT, DMA_DONE_INT);
 525         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 526                 0xFF, (u8)(data_len >> 24));
 527         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 528                 0xFF, (u8)(data_len >> 16));
 529         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 530                 0xFF, (u8)(data_len >> 8));
 531         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 532         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 533                 0x03 | DMA_PACK_SIZE_MASK,
 534                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
 535         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 536                         0x01, RING_BUFFER);
 537         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 538         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 539                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 540         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 541                         SD_TRANSFER_END, SD_TRANSFER_END);
 542         rtsx_pci_send_cmd_no_wait(pcr);
 543         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
 544         if (err < 0) {
 545                 sd_clear_error(host);
 546                 return err;
 547         }
 548
 549         return 0;
 550 }
 551
 552 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
 553 {
 554         rtsx_pci_write_register(host->pcr, SD_CFG1,
 555                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
 556 }
 557
 558 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
 559 {
 560         rtsx_pci_write_register(host->pcr, SD_CFG1,
 561                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
 562 }
 563
 564 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 565 {
 566         struct mmc_data *data = mrq->data;
 567         int err;
 568
 569         if (host->sg_count < 0) {
 570                 data->error = host->sg_count;
 571                 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
 572                         __func__, host->sg_count);
 573                 return data->error;
 574         }
 575
 576         if (data->flags & MMC_DATA_READ) {
 577                 if (host->initial_mode)
 578                         sd_disable_initial_mode(host);
 579
 580                 err = sd_read_long_data(host, mrq);
 581
 582                 if (host->initial_mode)
 583                         sd_enable_initial_mode(host);
 584
 585                 return err;
 586         }
 587
 588         return sd_write_long_data(host, mrq);
 589 }
 590
 591 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
 592                 struct mmc_request *mrq)
 593 {
 594         struct mmc_command *cmd = mrq->cmd;
 595         struct mmc_data *data = mrq->data;
 596         u8 *buf;
 597
 598         buf = kzalloc(data->blksz, GFP_NOIO);
 599         if (!buf) {
 600                 cmd->error = -ENOMEM;
 601                 return;
 602         }
 603
 604         if (data->flags & MMC_DATA_READ) {
 605                 if (host->initial_mode)
 606                         sd_disable_initial_mode(host);
 607
 608                 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
 609                                 data->blksz, 200);
 610
 611                 if (host->initial_mode)
 612                         sd_enable_initial_mode(host);
 613
 614                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
 615         } else {
 616                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
 617
 618                 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
 619                                 data->blksz, 200);
 620         }
 621
 622         kfree(buf);
 623 }
 624
 625 static int sd_change_phase(struct realtek_pci_sdmmc *host,
 626                 u8 sample_point, bool rx)
 627 {
 628         struct rtsx_pcr *pcr = host->pcr;
 629         int err;
 630
 631         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
 632                         __func__, rx ? "RX" : "TX", sample_point);
 633
 634         rtsx_pci_init_cmd(pcr);
 635
 636         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 637         if (rx)
 638                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 639                                 SD_VPRX_CTL, 0x1F, sample_point);
 640         else
 641                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 642                                 SD_VPTX_CTL, 0x1F, sample_point);
 643         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 644         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 645                         PHASE_NOT_RESET, PHASE_NOT_RESET);
 646         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
 647         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 648
 649         err = rtsx_pci_send_cmd(pcr, 100);
 650         if (err < 0)
 651                 return err;
 652
 653         return 0;
 654 }
 655
 656 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
 657 {
 658         bit %= RTSX_PHASE_MAX;
 659         return phase_map & (1 << bit);
 660 }
 661
 662 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
 663 {
 664         int i;
 665
 666         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 667                 if (test_phase_bit(phase_map, start_bit + i) == 0)
 668                         return i;
 669         }
 670         return RTSX_PHASE_MAX;
 671 }
 672
 673 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
 674 {
 675         int start = 0, len = 0;
 676         int start_final = 0, len_final = 0;
 677         u8 final_phase = 0xFF;
 678
 679         if (phase_map == 0) {
 680                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
 681                 return final_phase;
 682         }
 683
 684         while (start < RTSX_PHASE_MAX) {
 685                 len = sd_get_phase_len(phase_map, start);
 686                 if (len_final < len) {
 687                         start_final = start;
 688                         len_final = len;
 689                 }
 690                 start += len ? len : 1;
 691         }
 692
 693         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
 694         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 695                 phase_map, len_final, final_phase);
 696
 697         return final_phase;
 698 }
 699
 700 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
 701 {
 702         int err, i;
 703         u8 val = 0;
 704
 705         for (i = 0; i < 100; i++) {
 706                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
 707                 if (val & SD_DATA_IDLE)
 708                         return;
 709
 710                 udelay(100);
 711         }
 712 }
 713
 714 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
 715                 u8 opcode, u8 sample_point)
 716 {
 717         int err;
 718         struct mmc_command cmd = {0};
 719
 720         err = sd_change_phase(host, sample_point, true);
 721         if (err < 0)
 722                 return err;
 723
 724         cmd.opcode = opcode;
 725         err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
 726         if (err < 0) {
 727                 /* Wait till SD DATA IDLE */
 728                 sd_wait_data_idle(host);
 729                 sd_clear_error(host);
 730                 return err;
 731         }
 732
 733         return 0;
 734 }
 735
 736 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
 737                 u8 opcode, u32 *phase_map)
 738 {
 739         int err, i;
 740         u32 raw_phase_map = 0;
 741
 742         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 743                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
 744                 if (err == 0)
 745                         raw_phase_map |= 1 << i;
 746         }
 747
 748         if (phase_map)
 749                 *phase_map = raw_phase_map;
 750
 751         return 0;
 752 }
 753
 754 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
 755 {
 756         int err, i;
 757         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
 758         u8 final_phase;
 759
 760         for (i = 0; i < RX_TUNING_CNT; i++) {
 761                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
 762                 if (err < 0)
 763                         return err;
 764
 765                 if (raw_phase_map[i] == 0)
 766                         break;
 767         }
 768
 769         phase_map = 0xFFFFFFFF;
 770         for (i = 0; i < RX_TUNING_CNT; i++) {
 771                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
 772                                 i, raw_phase_map[i]);
 773                 phase_map &= raw_phase_map[i];
 774         }
 775         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
 776
 777         if (phase_map) {
 778                 final_phase = sd_search_final_phase(host, phase_map);
 779                 if (final_phase == 0xFF)
 780                         return -EINVAL;
 781
 782                 err = sd_change_phase(host, final_phase, true);
 783                 if (err < 0)
 784                         return err;
 785         } else {
 786                 return -EINVAL;
 787         }
 788
 789         return 0;
 790 }
 791
 792 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
 793         struct mmc_data *data)
 794 {
 795         return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
 796 }
 797
 798 static inline int sd_rw_cmd(struct mmc_command *cmd)
 799 {
 800         return mmc_op_multi(cmd->opcode) ||
 801                 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
 802                 (cmd->opcode == MMC_WRITE_BLOCK);
 803 }
 804
 805 static void sd_request(struct work_struct *work)
 806 {
 807         struct realtek_pci_sdmmc *host = container_of(work,
 808                         struct realtek_pci_sdmmc, work);
 809         struct rtsx_pcr *pcr = host->pcr;
 810
 811         struct mmc_host *mmc = host->mmc;
 812         struct mmc_request *mrq = host->mrq;
 813         struct mmc_command *cmd = mrq->cmd;
 814         struct mmc_data *data = mrq->data;
 815
 816         unsigned int data_size = 0;
 817         int err;
 818
 819         if (host->eject || !sd_get_cd_int(host)) {
 820                 cmd->error = -ENOMEDIUM;
 821                 goto finish;
 822         }
 823
 824         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
 825         if (err) {
 826                 cmd->error = err;
 827                 goto finish;
 828         }
 829
 830         mutex_lock(&pcr->pcr_mutex);
 831
 832         rtsx_pci_start_run(pcr);
 833
 834         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
 835                         host->initial_mode, host->double_clk, host->vpclk);
 836         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
 837         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
 838                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 839
 840         mutex_lock(&host->host_mutex);
 841         host->mrq = mrq;
 842         mutex_unlock(&host->host_mutex);
 843
 844         if (mrq->data)
 845                 data_size = data->blocks * data->blksz;
 846
 847         if (!data_size) {
 848                 sd_send_cmd_get_rsp(host, cmd);
 849         } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
 850                 cmd->error = sd_rw_multi(host, mrq);
 851                 if (!host->using_cookie)
 852                         sdmmc_post_req(host->mmc, host->mrq, 0);
 853
 854                 if (mmc_op_multi(cmd->opcode) && mrq->stop)
 855                         sd_send_cmd_get_rsp(host, mrq->stop);
 856         } else {
 857                 sd_normal_rw(host, mrq);
 858         }
 859
 860         if (mrq->data) {
 861                 if (cmd->error || data->error)
 862                         data->bytes_xfered = 0;
 863                 else
 864                         data->bytes_xfered = data->blocks * data->blksz;
 865         }
 866
 867         mutex_unlock(&pcr->pcr_mutex);
 868
 869 finish:
 870         if (cmd->error) {
 871                 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
 872                         cmd->opcode, cmd->arg, cmd->error);
 873         }
 874
 875         mutex_lock(&host->host_mutex);
 876         host->mrq = NULL;
 877         mutex_unlock(&host->host_mutex);
 878
 879         mmc_request_done(mmc, mrq);
 880 }
 881
 882 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 883 {
 884         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 885         struct mmc_data *data = mrq->data;
 886
 887         mutex_lock(&host->host_mutex);
 888         host->mrq = mrq;
 889         mutex_unlock(&host->host_mutex);
 890
 891         if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
 892                 host->using_cookie = sd_pre_dma_transfer(host, data, false);
 893
 894         schedule_work(&host->work);
 895 }
 896
 897 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
 898                 unsigned char bus_width)
 899 {
 900         int err = 0;
 901         u8 width[] = {
 902                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
 903                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
 904                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
 905         };
 906
 907         if (bus_width <= MMC_BUS_WIDTH_8)
 908                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
 909                                 0x03, width[bus_width]);
 910
 911         return err;
 912 }
 913
 914 static int sd_power_on(struct realtek_pci_sdmmc *host, unsigned char power_mode)
 915 {
 916         struct rtsx_pcr *pcr = host->pcr;
 917         int err;
 918
 919         if (host->prev_power_state == MMC_POWER_ON)
 920                 return 0;
 921
 922         if (host->prev_power_state == MMC_POWER_UP) {
 923                 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);
 924                 goto finish;
 925         }
 926
 927         msleep(100);
 928
 929         rtsx_pci_init_cmd(pcr);
 930         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
 931         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
 932                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 933         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
 934                         SD_CLK_EN, SD_CLK_EN);
 935         err = rtsx_pci_send_cmd(pcr, 100);
 936         if (err < 0)
 937                 return err;
 938
 939         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
 940         if (err < 0)
 941                 return err;
 942
 943         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
 944         if (err < 0)
 945                 return err;
 946
 947         mdelay(1);
 948
 949         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
 950         if (err < 0)
 951                 return err;
 952
 953         /* send at least 74 clocks */
 954         rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
 955
 956 finish:
 957         host->prev_power_state = power_mode;
 958         return 0;
 959 }
 960
 961 static int sd_power_off(struct realtek_pci_sdmmc *host)
 962 {
 963         struct rtsx_pcr *pcr = host->pcr;
 964         int err;
 965
 966         host->prev_power_state = MMC_POWER_OFF;
 967
 968         rtsx_pci_init_cmd(pcr);
 969
 970         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 971         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 972
 973         err = rtsx_pci_send_cmd(pcr, 100);
 974         if (err < 0)
 975                 return err;
 976
 977         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 978         if (err < 0)
 979                 return err;
 980
 981         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
 982 }
 983
 984 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
 985                 unsigned char power_mode)
 986 {
 987         int err;
 988
 989         if (power_mode == MMC_POWER_OFF)
 990                 err = sd_power_off(host);
 991         else
 992                 err = sd_power_on(host, power_mode);
 993
 994         return err;
 995 }
 996
 997 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
 998 {
 999         struct rtsx_pcr *pcr = host->pcr;
1000         int err = 0;
1001
1002         rtsx_pci_init_cmd(pcr);
1003
1004         switch (timing) {
1005         case MMC_TIMING_UHS_SDR104:
1006         case MMC_TIMING_UHS_SDR50:
1007                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1008                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
1009                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
1010                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1011                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1012                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1013                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1014                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1015                 break;
1016
1017         case MMC_TIMING_MMC_DDR52:
1018         case MMC_TIMING_UHS_DDR50:
1019                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1020                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
1021                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1022                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1023                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1024                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1025                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1026                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1027                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1028                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1029                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1030                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1031                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1032                 break;
1033
1034         case MMC_TIMING_MMC_HS:
1035         case MMC_TIMING_SD_HS:
1036                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1037                                 0x0C, SD_20_MODE);
1038                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1039                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1040                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1041                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1042                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1043                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1044                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1045                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1046                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1047                 break;
1048
1049         default:
1050                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1051                                 SD_CFG1, 0x0C, SD_20_MODE);
1052                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1053                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1054                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1055                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1056                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1057                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1058                                 SD_PUSH_POINT_CTL, 0xFF, 0);
1059                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1060                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1061                 break;
1062         }
1063
1064         err = rtsx_pci_send_cmd(pcr, 100);
1065
1066         return err;
1067 }
1068
1069 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1070 {
1071         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1072         struct rtsx_pcr *pcr = host->pcr;
1073
1074         if (host->eject)
1075                 return;
1076
1077         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1078                 return;
1079
1080         mutex_lock(&pcr->pcr_mutex);
1081
1082         rtsx_pci_start_run(pcr);
1083
1084         sd_set_bus_width(host, ios->bus_width);
1085         sd_set_power_mode(host, ios->power_mode);
1086         sd_set_timing(host, ios->timing);
1087
1088         host->vpclk = false;
1089         host->double_clk = true;
1090
1091         switch (ios->timing) {
1092         case MMC_TIMING_UHS_SDR104:
1093         case MMC_TIMING_UHS_SDR50:
1094                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1095                 host->vpclk = true;
1096                 host->double_clk = false;
1097                 break;
1098         case MMC_TIMING_MMC_DDR52:
1099         case MMC_TIMING_UHS_DDR50:
1100         case MMC_TIMING_UHS_SDR25:
1101                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1102                 break;
1103         default:
1104                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1105                 break;
1106         }
1107
1108         host->initial_mode = (ios->clock <= 1000000) ? true : false;
1109
1110         host->clock = ios->clock;
1111         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1112                         host->initial_mode, host->double_clk, host->vpclk);
1113
1114         mutex_unlock(&pcr->pcr_mutex);
1115 }
1116
1117 static int sdmmc_get_ro(struct mmc_host *mmc)
1118 {
1119         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1120         struct rtsx_pcr *pcr = host->pcr;
1121         int ro = 0;
1122         u32 val;
1123
1124         if (host->eject)
1125                 return -ENOMEDIUM;
1126
1127         mutex_lock(&pcr->pcr_mutex);
1128
1129         rtsx_pci_start_run(pcr);
1130
1131         /* Check SD mechanical write-protect switch */
1132         val = rtsx_pci_readl(pcr, RTSX_BIPR);
1133         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1134         if (val & SD_WRITE_PROTECT)
1135                 ro = 1;
1136
1137         mutex_unlock(&pcr->pcr_mutex);
1138
1139         return ro;
1140 }
1141
1142 static int sdmmc_get_cd(struct mmc_host *mmc)
1143 {
1144         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1145         struct rtsx_pcr *pcr = host->pcr;
1146         int cd = 0;
1147         u32 val;
1148
1149         if (host->eject)
1150                 return cd;
1151
1152         mutex_lock(&pcr->pcr_mutex);
1153
1154         rtsx_pci_start_run(pcr);
1155
1156         /* Check SD card detect */
1157         val = rtsx_pci_card_exist(pcr);
1158         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1159         if (val & SD_EXIST)
1160                 cd = 1;
1161
1162         mutex_unlock(&pcr->pcr_mutex);
1163
1164         return cd;
1165 }
1166
1167 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1168 {
1169         struct rtsx_pcr *pcr = host->pcr;
1170         int err;
1171         u8 stat;
1172
1173         /* Reference to Signal Voltage Switch Sequence in SD spec.
1174          * Wait for a period of time so that the card can drive SD_CMD and
1175          * SD_DAT[3:0] to low after sending back CMD11 response.
1176          */
1177         mdelay(1);
1178
1179         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1180          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1181          * abort the voltage switch sequence;
1182          */
1183         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1184         if (err < 0)
1185                 return err;
1186
1187         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1188                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1189                 return -EINVAL;
1190
1191         /* Stop toggle SD clock */
1192         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1193                         0xFF, SD_CLK_FORCE_STOP);
1194         if (err < 0)
1195                 return err;
1196
1197         return 0;
1198 }
1199
1200 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1201 {
1202         struct rtsx_pcr *pcr = host->pcr;
1203         int err;
1204         u8 stat, mask, val;
1205
1206         /* Wait 1.8V output of voltage regulator in card stable */
1207         msleep(50);
1208
1209         /* Toggle SD clock again */
1210         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1211         if (err < 0)
1212                 return err;
1213
1214         /* Wait for a period of time so that the card can drive
1215          * SD_DAT[3:0] to high at 1.8V
1216          */
1217         msleep(20);
1218
1219         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1220         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1221         if (err < 0)
1222                 return err;
1223
1224         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1225                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1226         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1227                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1228         if ((stat & mask) != val) {
1229                 dev_dbg(sdmmc_dev(host),
1230                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1231                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1232                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1233                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1234                 return -EINVAL;
1235         }
1236
1237         return 0;
1238 }
1239
1240 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1241 {
1242         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1243         struct rtsx_pcr *pcr = host->pcr;
1244         int err = 0;
1245         u8 voltage;
1246
1247         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1248                         __func__, ios->signal_voltage);
1249
1250         if (host->eject)
1251                 return -ENOMEDIUM;
1252
1253         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1254         if (err)
1255                 return err;
1256
1257         mutex_lock(&pcr->pcr_mutex);
1258
1259         rtsx_pci_start_run(pcr);
1260
1261         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1262                 voltage = OUTPUT_3V3;
1263         else
1264                 voltage = OUTPUT_1V8;
1265
1266         if (voltage == OUTPUT_1V8) {
1267                 err = sd_wait_voltage_stable_1(host);
1268                 if (err < 0)
1269                         goto out;
1270         }
1271
1272         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1273         if (err < 0)
1274                 goto out;
1275
1276         if (voltage == OUTPUT_1V8) {
1277                 err = sd_wait_voltage_stable_2(host);
1278                 if (err < 0)
1279                         goto out;
1280         }
1281
1282 out:
1283         /* Stop toggle SD clock in idle */
1284         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1285                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1286
1287         mutex_unlock(&pcr->pcr_mutex);
1288
1289         return err;
1290 }
1291
1292 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1293 {
1294         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1295         struct rtsx_pcr *pcr = host->pcr;
1296         int err = 0;
1297
1298         if (host->eject)
1299                 return -ENOMEDIUM;
1300
1301         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1302         if (err)
1303                 return err;
1304
1305         mutex_lock(&pcr->pcr_mutex);
1306
1307         rtsx_pci_start_run(pcr);
1308
1309         /* Set initial TX phase */
1310         switch (mmc->ios.timing) {
1311         case MMC_TIMING_UHS_SDR104:
1312                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1313                 break;
1314
1315         case MMC_TIMING_UHS_SDR50:
1316                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1317                 break;
1318
1319         case MMC_TIMING_UHS_DDR50:
1320                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1321                 break;
1322
1323         default:
1324                 err = 0;
1325         }
1326
1327         if (err)
1328                 goto out;
1329
1330         /* Tuning RX phase */
1331         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1332                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1333                 err = sd_tuning_rx(host, opcode);
1334         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1335                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1336
1337 out:
1338         mutex_unlock(&pcr->pcr_mutex);
1339
1340         return err;
1341 }
1342
1343 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1344         .pre_req = sdmmc_pre_req,
1345         .post_req = sdmmc_post_req,
1346         .request = sdmmc_request,
1347         .set_ios = sdmmc_set_ios,
1348         .get_ro = sdmmc_get_ro,
1349         .get_cd = sdmmc_get_cd,
1350         .start_signal_voltage_switch = sdmmc_switch_voltage,
1351         .execute_tuning = sdmmc_execute_tuning,
1352 };
1353
1354 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1355 {
1356         struct mmc_host *mmc = host->mmc;
1357         struct rtsx_pcr *pcr = host->pcr;
1358
1359         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1360
1361         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1362                 mmc->caps |= MMC_CAP_UHS_SDR50;
1363         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1364                 mmc->caps |= MMC_CAP_UHS_SDR104;
1365         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1366                 mmc->caps |= MMC_CAP_UHS_DDR50;
1367         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1368                 mmc->caps |= MMC_CAP_1_8V_DDR;
1369         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1370                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1371 }
1372
1373 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1374 {
1375         struct mmc_host *mmc = host->mmc;
1376
1377         mmc->f_min = 250000;
1378         mmc->f_max = 208000000;
1379         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1380         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1381                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1382                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1383         mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1384         mmc->max_current_330 = 400;
1385         mmc->max_current_180 = 800;
1386         mmc->ops = &realtek_pci_sdmmc_ops;
1387
1388         init_extra_caps(host);
1389
1390         mmc->max_segs = 256;
1391         mmc->max_seg_size = 65536;
1392         mmc->max_blk_size = 512;
1393         mmc->max_blk_count = 65535;
1394         mmc->max_req_size = 524288;
1395 }
1396
1397 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1398 {
1399         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1400
1401         host->cookie = -1;
1402         mmc_detect_change(host->mmc, 0);
1403 }
1404
1405 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1406 {
1407         struct mmc_host *mmc;
1408         struct realtek_pci_sdmmc *host;
1409         struct rtsx_pcr *pcr;
1410         struct pcr_handle *handle = pdev->dev.platform_data;
1411
1412         if (!handle)
1413                 return -ENXIO;
1414
1415         pcr = handle->pcr;
1416         if (!pcr)
1417                 return -ENXIO;
1418
1419         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1420
1421         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1422         if (!mmc)
1423                 return -ENOMEM;
1424
1425         host = mmc_priv(mmc);
1426         host->pcr = pcr;
1427         host->mmc = mmc;
1428         host->pdev = pdev;
1429         host->cookie = -1;
1430         host->prev_power_state = MMC_POWER_OFF;
1431         INIT_WORK(&host->work, sd_request);
1432         platform_set_drvdata(pdev, host);
1433         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1434         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1435
1436         mutex_init(&host->host_mutex);
1437
1438         realtek_init_host(host);
1439
1440         mmc_add_host(mmc);
1441
1442         return 0;
1443 }
1444
1445 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1446 {
1447         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1448         struct rtsx_pcr *pcr;
1449         struct mmc_host *mmc;
1450
1451         if (!host)
1452                 return 0;
1453
1454         pcr = host->pcr;
1455         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1456         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1457         mmc = host->mmc;
1458
1459         cancel_work_sync(&host->work);
1460
1461         mutex_lock(&host->host_mutex);
1462         if (host->mrq) {
1463                 dev_dbg(&(pdev->dev),
1464                         "%s: Controller removed during transfer\n",
1465                         mmc_hostname(mmc));
1466
1467                 rtsx_pci_complete_unfinished_transfer(pcr);
1468
1469                 host->mrq->cmd->error = -ENOMEDIUM;
1470                 if (host->mrq->stop)
1471                         host->mrq->stop->error = -ENOMEDIUM;
1472                 mmc_request_done(mmc, host->mrq);
1473         }
1474         mutex_unlock(&host->host_mutex);
1475
1476         mmc_remove_host(mmc);
1477         host->eject = true;
1478
1479         flush_work(&host->work);
1480
1481         mmc_free_host(mmc);
1482
1483         dev_dbg(&(pdev->dev),
1484                 ": Realtek PCI-E SDMMC controller has been removed\n");
1485
1486         return 0;
1487 }
1488
1489 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1490         {
1491                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1492         }, {
1493                 /* sentinel */
1494         }
1495 };
1496 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1497
1498 static struct platform_driver rtsx_pci_sdmmc_driver = {
1499         .probe          = rtsx_pci_sdmmc_drv_probe,
1500         .remove         = rtsx_pci_sdmmc_drv_remove,
1501         .id_table       = rtsx_pci_sdmmc_ids,
1502         .driver         = {
1503                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1504         },
1505 };
1506 module_platform_driver(rtsx_pci_sdmmc_driver);
1507
1508 MODULE_LICENSE("GPL");
1509 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1510 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");