drivers/mmc/host/rtsx_pci_sdmmc.c

   1 /* Realtek PCI-Express SD/MMC Card Interface driver
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <linux/highmem.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/sd.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/card.h>
  33 #include <linux/mfd/rtsx_pci.h>
  34 #include <asm/unaligned.h>
  35
  36 struct realtek_pci_sdmmc {
  37         struct platform_device  *pdev;
  38         struct rtsx_pcr         *pcr;
  39         struct mmc_host         *mmc;
  40         struct mmc_request      *mrq;
  41 #define SDMMC_WORKQ_NAME        "rtsx_pci_sdmmc_workq"
  42
  43         struct work_struct      work;
  44         struct mutex            host_mutex;
  45
  46         u8                      ssc_depth;
  47         unsigned int            clock;
  48         bool                    vpclk;
  49         bool                    double_clk;
  50         bool                    eject;
  51         bool                    initial_mode;
  52         int                     power_state;
  53 #define SDMMC_POWER_ON          1
  54 #define SDMMC_POWER_OFF         0
  55
  56         int                     sg_count;
  57         s32                     cookie;
  58         int                     cookie_sg_count;
  59         bool                    using_cookie;
  60 };
  61
  62 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
  63 {
  64         return &(host->pdev->dev);
  65 }
  66
  67 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
  68 {
  69         rtsx_pci_write_register(host->pcr, CARD_STOP,
  70                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
  71 }
  72
  73 #ifdef DEBUG
  74 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
  75 {
  76         u16 len = end - start + 1;
  77         int i;
  78         u8 data[8];
  79
  80         for (i = 0; i < len; i += 8) {
  81                 int j;
  82                 int n = min(8, len - i);
  83
  84                 memset(&data, 0, sizeof(data));
  85                 for (j = 0; j < n; j++)
  86                         rtsx_pci_read_register(host->pcr, start + i + j,
  87                                 data + j);
  88                 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
  89                         start + i, n, data);
  90         }
  91 }
  92
  93 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
  94 {
  95         dump_reg_range(host, 0xFDA0, 0xFDB3);
  96         dump_reg_range(host, 0xFD52, 0xFD69);
  97 }
  98 #else
  99 #define sd_print_debug_regs(host)
 100 #endif /* DEBUG */
 101
 102 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
 103 {
 104         return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
 105 }
 106
 107 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
 108 {
 109         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
 110                 SD_CMD_START | cmd->opcode);
 111         rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
 112 }
 113
 114 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
 115 {
 116         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
 117         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
 118         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
 119         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
 120 }
 121
 122 static int sd_response_type(struct mmc_command *cmd)
 123 {
 124         switch (mmc_resp_type(cmd)) {
 125         case MMC_RSP_NONE:
 126                 return SD_RSP_TYPE_R0;
 127         case MMC_RSP_R1:
 128                 return SD_RSP_TYPE_R1;
 129         case MMC_RSP_R1_NO_CRC:
 130                 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
 131         case MMC_RSP_R1B:
 132                 return SD_RSP_TYPE_R1b;
 133         case MMC_RSP_R2:
 134                 return SD_RSP_TYPE_R2;
 135         case MMC_RSP_R3:
 136                 return SD_RSP_TYPE_R3;
 137         default:
 138                 return -EINVAL;
 139         }
 140 }
 141
 142 static int sd_status_index(int resp_type)
 143 {
 144         if (resp_type == SD_RSP_TYPE_R0)
 145                 return 0;
 146         else if (resp_type == SD_RSP_TYPE_R2)
 147                 return 16;
 148
 149         return 5;
 150 }
 151 /*
 152  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
 153  *
 154  * @pre: if called in pre_req()
 155  * return:
 156  *      0 - do dma_map_sg()
 157  *      1 - using cookie
 158  */
 159 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
 160                 struct mmc_data *data, bool pre)
 161 {
 162         struct rtsx_pcr *pcr = host->pcr;
 163         int read = data->flags & MMC_DATA_READ;
 164         int count = 0;
 165         int using_cookie = 0;
 166
 167         if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
 168                 dev_err(sdmmc_dev(host),
 169                         "error: data->host_cookie = %d, host->cookie = %d\n",
 170                         data->host_cookie, host->cookie);
 171                 data->host_cookie = 0;
 172         }
 173
 174         if (pre || data->host_cookie != host->cookie) {
 175                 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
 176         } else {
 177                 count = host->cookie_sg_count;
 178                 using_cookie = 1;
 179         }
 180
 181         if (pre) {
 182                 host->cookie_sg_count = count;
 183                 if (++host->cookie < 0)
 184                         host->cookie = 1;
 185                 data->host_cookie = host->cookie;
 186         } else {
 187                 host->sg_count = count;
 188         }
 189
 190         return using_cookie;
 191 }
 192
 193 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
 194 {
 195         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 196         struct mmc_data *data = mrq->data;
 197
 198         if (data->host_cookie) {
 199                 dev_err(sdmmc_dev(host),
 200                         "error: reset data->host_cookie = %d\n",
 201                         data->host_cookie);
 202                 data->host_cookie = 0;
 203         }
 204
 205         sd_pre_dma_transfer(host, data, true);
 206         dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
 207 }
 208
 209 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 210                 int err)
 211 {
 212         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 213         struct rtsx_pcr *pcr = host->pcr;
 214         struct mmc_data *data = mrq->data;
 215         int read = data->flags & MMC_DATA_READ;
 216
 217         rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
 218         data->host_cookie = 0;
 219 }
 220
 221 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
 222                 struct mmc_command *cmd)
 223 {
 224         struct rtsx_pcr *pcr = host->pcr;
 225         u8 cmd_idx = (u8)cmd->opcode;
 226         u32 arg = cmd->arg;
 227         int err = 0;
 228         int timeout = 100;
 229         int i;
 230         u8 *ptr;
 231         int rsp_type;
 232         int stat_idx;
 233         bool clock_toggled = false;
 234
 235         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 236                         __func__, cmd_idx, arg);
 237
 238         rsp_type = sd_response_type(cmd);
 239         if (rsp_type < 0)
 240                 goto out;
 241
 242         stat_idx = sd_status_index(rsp_type);
 243
 244         if (rsp_type == SD_RSP_TYPE_R1b)
 245                 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
 246
 247         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 248                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
 249                                 0xFF, SD_CLK_TOGGLE_EN);
 250                 if (err < 0)
 251                         goto out;
 252
 253                 clock_toggled = true;
 254         }
 255
 256         rtsx_pci_init_cmd(pcr);
 257         sd_cmd_set_sd_cmd(pcr, cmd);
 258         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 259         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 260                         0x01, PINGPONG_BUFFER);
 261         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 262                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 263         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 264                      SD_TRANSFER_END | SD_STAT_IDLE,
 265                      SD_TRANSFER_END | SD_STAT_IDLE);
 266
 267         if (rsp_type == SD_RSP_TYPE_R2) {
 268                 /* Read data from ping-pong buffer */
 269                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
 270                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 271         } else if (rsp_type != SD_RSP_TYPE_R0) {
 272                 /* Read data from SD_CMDx registers */
 273                 for (i = SD_CMD0; i <= SD_CMD4; i++)
 274                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 275         }
 276
 277         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
 278
 279         err = rtsx_pci_send_cmd(pcr, timeout);
 280         if (err < 0) {
 281                 sd_print_debug_regs(host);
 282                 sd_clear_error(host);
 283                 dev_dbg(sdmmc_dev(host),
 284                         "rtsx_pci_send_cmd error (err = %d)\n", err);
 285                 goto out;
 286         }
 287
 288         if (rsp_type == SD_RSP_TYPE_R0) {
 289                 err = 0;
 290                 goto out;
 291         }
 292
 293         /* Eliminate returned value of CHECK_REG_CMD */
 294         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
 295
 296         /* Check (Start,Transmission) bit of Response */
 297         if ((ptr[0] & 0xC0) != 0) {
 298                 err = -EILSEQ;
 299                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
 300                 goto out;
 301         }
 302
 303         /* Check CRC7 */
 304         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 305                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 306                         err = -EILSEQ;
 307                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
 308                         goto out;
 309                 }
 310         }
 311
 312         if (rsp_type == SD_RSP_TYPE_R2) {
 313                 /*
 314                  * The controller offloads the last byte {CRC-7, end bit 1'b1}
 315                  * of response type R2. Assign dummy CRC, 0, and end bit to the
 316                  * byte(ptr[16], goes into the LSB of resp[3] later).
 317                  */
 318                 ptr[16] = 1;
 319
 320                 for (i = 0; i < 4; i++) {
 321                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
 322                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
 323                                         i, cmd->resp[i]);
 324                 }
 325         } else {
 326                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
 327                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
 328                                 cmd->resp[0]);
 329         }
 330
 331 out:
 332         cmd->error = err;
 333
 334         if (err && clock_toggled)
 335                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
 336                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 337 }
 338
 339 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
 340         u16 byte_cnt, u8 *buf, int buf_len, int timeout)
 341 {
 342         struct rtsx_pcr *pcr = host->pcr;
 343         int err;
 344         u8 trans_mode;
 345
 346         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 347                 __func__, cmd->opcode, cmd->arg);
 348
 349         if (!buf)
 350                 buf_len = 0;
 351
 352         if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
 353                 trans_mode = SD_TM_AUTO_TUNING;
 354         else
 355                 trans_mode = SD_TM_NORMAL_READ;
 356
 357         rtsx_pci_init_cmd(pcr);
 358         sd_cmd_set_sd_cmd(pcr, cmd);
 359         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 360         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 361                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 362                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 363         if (trans_mode != SD_TM_AUTO_TUNING)
 364                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 365                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 366
 367         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 368                         0xFF, trans_mode | SD_TRANSFER_START);
 369         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 370                         SD_TRANSFER_END, SD_TRANSFER_END);
 371
 372         err = rtsx_pci_send_cmd(pcr, timeout);
 373         if (err < 0) {
 374                 sd_print_debug_regs(host);
 375                 dev_dbg(sdmmc_dev(host),
 376                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 377                 return err;
 378         }
 379
 380         if (buf && buf_len) {
 381                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
 382                 if (err < 0) {
 383                         dev_dbg(sdmmc_dev(host),
 384                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
 385                         return err;
 386                 }
 387         }
 388
 389         return 0;
 390 }
 391
 392 static int sd_write_data(struct realtek_pci_sdmmc *host,
 393         struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
 394         int timeout)
 395 {
 396         struct rtsx_pcr *pcr = host->pcr;
 397         int err;
 398
 399         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 400                 __func__, cmd->opcode, cmd->arg);
 401
 402         if (!buf)
 403                 buf_len = 0;
 404
 405         sd_send_cmd_get_rsp(host, cmd);
 406         if (cmd->error)
 407                 return cmd->error;
 408
 409         if (buf && buf_len) {
 410                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
 411                 if (err < 0) {
 412                         dev_dbg(sdmmc_dev(host),
 413                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
 414                         return err;
 415                 }
 416         }
 417
 418         rtsx_pci_init_cmd(pcr);
 419         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 420         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 421                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 422                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
 423         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 424                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 425         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 426                         SD_TRANSFER_END, SD_TRANSFER_END);
 427
 428         err = rtsx_pci_send_cmd(pcr, timeout);
 429         if (err < 0) {
 430                 sd_print_debug_regs(host);
 431                 dev_dbg(sdmmc_dev(host),
 432                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 433                 return err;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
 440         struct mmc_request *mrq)
 441 {
 442         struct rtsx_pcr *pcr = host->pcr;
 443         struct mmc_host *mmc = host->mmc;
 444         struct mmc_card *card = mmc->card;
 445         struct mmc_command *cmd = mrq->cmd;
 446         struct mmc_data *data = mrq->data;
 447         int uhs = mmc_card_uhs(card);
 448         u8 cfg2 = 0;
 449         int err;
 450         int resp_type;
 451         size_t data_len = data->blksz * data->blocks;
 452
 453         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 454                 __func__, cmd->opcode, cmd->arg);
 455
 456         resp_type = sd_response_type(cmd);
 457         if (resp_type < 0)
 458                 return resp_type;
 459
 460         if (!uhs)
 461                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 462
 463         rtsx_pci_init_cmd(pcr);
 464         sd_cmd_set_sd_cmd(pcr, cmd);
 465         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 466         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 467                         DMA_DONE_INT, DMA_DONE_INT);
 468         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 469                 0xFF, (u8)(data_len >> 24));
 470         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 471                 0xFF, (u8)(data_len >> 16));
 472         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 473                 0xFF, (u8)(data_len >> 8));
 474         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 475         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 476                 0x03 | DMA_PACK_SIZE_MASK,
 477                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
 478         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 479                         0x01, RING_BUFFER);
 480         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
 481         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 482                         SD_TRANSFER_START | SD_TM_AUTO_READ_2);
 483         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 484                         SD_TRANSFER_END, SD_TRANSFER_END);
 485         rtsx_pci_send_cmd_no_wait(pcr);
 486
 487         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
 488         if (err < 0) {
 489                 sd_print_debug_regs(host);
 490                 sd_clear_error(host);
 491                 return err;
 492         }
 493
 494         return 0;
 495 }
 496
 497 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
 498         struct mmc_request *mrq)
 499 {
 500         struct rtsx_pcr *pcr = host->pcr;
 501         struct mmc_host *mmc = host->mmc;
 502         struct mmc_card *card = mmc->card;
 503         struct mmc_command *cmd = mrq->cmd;
 504         struct mmc_data *data = mrq->data;
 505         int uhs = mmc_card_uhs(card);
 506         u8 cfg2;
 507         int err;
 508         size_t data_len = data->blksz * data->blocks;
 509
 510         sd_send_cmd_get_rsp(host, cmd);
 511         if (cmd->error)
 512                 return cmd->error;
 513
 514         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 515                 __func__, cmd->opcode, cmd->arg);
 516
 517         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 518                 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
 519
 520         if (!uhs)
 521                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 522
 523         rtsx_pci_init_cmd(pcr);
 524         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 525         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 526                         DMA_DONE_INT, DMA_DONE_INT);
 527         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 528                 0xFF, (u8)(data_len >> 24));
 529         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 530                 0xFF, (u8)(data_len >> 16));
 531         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 532                 0xFF, (u8)(data_len >> 8));
 533         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 534         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 535                 0x03 | DMA_PACK_SIZE_MASK,
 536                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
 537         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 538                         0x01, RING_BUFFER);
 539         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 540         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 541                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 542         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 543                         SD_TRANSFER_END, SD_TRANSFER_END);
 544         rtsx_pci_send_cmd_no_wait(pcr);
 545         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
 546         if (err < 0) {
 547                 sd_clear_error(host);
 548                 return err;
 549         }
 550
 551         return 0;
 552 }
 553
 554 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
 555 {
 556         rtsx_pci_write_register(host->pcr, SD_CFG1,
 557                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
 558 }
 559
 560 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
 561 {
 562         rtsx_pci_write_register(host->pcr, SD_CFG1,
 563                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
 564 }
 565
 566 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 567 {
 568         struct mmc_data *data = mrq->data;
 569         int err;
 570
 571         if (host->sg_count < 0) {
 572                 data->error = host->sg_count;
 573                 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
 574                         __func__, host->sg_count);
 575                 return data->error;
 576         }
 577
 578         if (data->flags & MMC_DATA_READ) {
 579                 if (host->initial_mode)
 580                         sd_disable_initial_mode(host);
 581
 582                 err = sd_read_long_data(host, mrq);
 583
 584                 if (host->initial_mode)
 585                         sd_enable_initial_mode(host);
 586
 587                 return err;
 588         }
 589
 590         return sd_write_long_data(host, mrq);
 591 }
 592
 593 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
 594                 struct mmc_request *mrq)
 595 {
 596         struct mmc_command *cmd = mrq->cmd;
 597         struct mmc_data *data = mrq->data;
 598         u8 *buf;
 599
 600         buf = kzalloc(data->blksz, GFP_NOIO);
 601         if (!buf) {
 602                 cmd->error = -ENOMEM;
 603                 return;
 604         }
 605
 606         if (data->flags & MMC_DATA_READ) {
 607                 if (host->initial_mode)
 608                         sd_disable_initial_mode(host);
 609
 610                 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
 611                                 data->blksz, 200);
 612
 613                 if (host->initial_mode)
 614                         sd_enable_initial_mode(host);
 615
 616                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
 617         } else {
 618                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
 619
 620                 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
 621                                 data->blksz, 200);
 622         }
 623
 624         kfree(buf);
 625 }
 626
 627 static int sd_change_phase(struct realtek_pci_sdmmc *host,
 628                 u8 sample_point, bool rx)
 629 {
 630         struct rtsx_pcr *pcr = host->pcr;
 631         int err;
 632
 633         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
 634                         __func__, rx ? "RX" : "TX", sample_point);
 635
 636         rtsx_pci_init_cmd(pcr);
 637
 638         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 639         if (rx)
 640                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 641                                 SD_VPRX_CTL, 0x1F, sample_point);
 642         else
 643                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 644                                 SD_VPTX_CTL, 0x1F, sample_point);
 645         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 646         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 647                         PHASE_NOT_RESET, PHASE_NOT_RESET);
 648         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
 649         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 650
 651         err = rtsx_pci_send_cmd(pcr, 100);
 652         if (err < 0)
 653                 return err;
 654
 655         return 0;
 656 }
 657
 658 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
 659 {
 660         bit %= RTSX_PHASE_MAX;
 661         return phase_map & (1 << bit);
 662 }
 663
 664 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
 665 {
 666         int i;
 667
 668         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 669                 if (test_phase_bit(phase_map, start_bit + i) == 0)
 670                         return i;
 671         }
 672         return RTSX_PHASE_MAX;
 673 }
 674
 675 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
 676 {
 677         int start = 0, len = 0;
 678         int start_final = 0, len_final = 0;
 679         u8 final_phase = 0xFF;
 680
 681         if (phase_map == 0) {
 682                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
 683                 return final_phase;
 684         }
 685
 686         while (start < RTSX_PHASE_MAX) {
 687                 len = sd_get_phase_len(phase_map, start);
 688                 if (len_final < len) {
 689                         start_final = start;
 690                         len_final = len;
 691                 }
 692                 start += len ? len : 1;
 693         }
 694
 695         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
 696         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 697                 phase_map, len_final, final_phase);
 698
 699         return final_phase;
 700 }
 701
 702 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
 703 {
 704         int err, i;
 705         u8 val = 0;
 706
 707         for (i = 0; i < 100; i++) {
 708                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
 709                 if (val & SD_DATA_IDLE)
 710                         return;
 711
 712                 udelay(100);
 713         }
 714 }
 715
 716 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
 717                 u8 opcode, u8 sample_point)
 718 {
 719         int err;
 720         struct mmc_command cmd = {};
 721
 722         err = sd_change_phase(host, sample_point, true);
 723         if (err < 0)
 724                 return err;
 725
 726         cmd.opcode = opcode;
 727         err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
 728         if (err < 0) {
 729                 /* Wait till SD DATA IDLE */
 730                 sd_wait_data_idle(host);
 731                 sd_clear_error(host);
 732                 return err;
 733         }
 734
 735         return 0;
 736 }
 737
 738 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
 739                 u8 opcode, u32 *phase_map)
 740 {
 741         int err, i;
 742         u32 raw_phase_map = 0;
 743
 744         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 745                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
 746                 if (err == 0)
 747                         raw_phase_map |= 1 << i;
 748         }
 749
 750         if (phase_map)
 751                 *phase_map = raw_phase_map;
 752
 753         return 0;
 754 }
 755
 756 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
 757 {
 758         int err, i;
 759         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
 760         u8 final_phase;
 761
 762         for (i = 0; i < RX_TUNING_CNT; i++) {
 763                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
 764                 if (err < 0)
 765                         return err;
 766
 767                 if (raw_phase_map[i] == 0)
 768                         break;
 769         }
 770
 771         phase_map = 0xFFFFFFFF;
 772         for (i = 0; i < RX_TUNING_CNT; i++) {
 773                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
 774                                 i, raw_phase_map[i]);
 775                 phase_map &= raw_phase_map[i];
 776         }
 777         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
 778
 779         if (phase_map) {
 780                 final_phase = sd_search_final_phase(host, phase_map);
 781                 if (final_phase == 0xFF)
 782                         return -EINVAL;
 783
 784                 err = sd_change_phase(host, final_phase, true);
 785                 if (err < 0)
 786                         return err;
 787         } else {
 788                 return -EINVAL;
 789         }
 790
 791         return 0;
 792 }
 793
 794 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
 795         struct mmc_data *data)
 796 {
 797         return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
 798 }
 799
 800 static inline int sd_rw_cmd(struct mmc_command *cmd)
 801 {
 802         return mmc_op_multi(cmd->opcode) ||
 803                 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
 804                 (cmd->opcode == MMC_WRITE_BLOCK);
 805 }
 806
 807 static void sd_request(struct work_struct *work)
 808 {
 809         struct realtek_pci_sdmmc *host = container_of(work,
 810                         struct realtek_pci_sdmmc, work);
 811         struct rtsx_pcr *pcr = host->pcr;
 812
 813         struct mmc_host *mmc = host->mmc;
 814         struct mmc_request *mrq = host->mrq;
 815         struct mmc_command *cmd = mrq->cmd;
 816         struct mmc_data *data = mrq->data;
 817
 818         unsigned int data_size = 0;
 819         int err;
 820
 821         if (host->eject || !sd_get_cd_int(host)) {
 822                 cmd->error = -ENOMEDIUM;
 823                 goto finish;
 824         }
 825
 826         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
 827         if (err) {
 828                 cmd->error = err;
 829                 goto finish;
 830         }
 831
 832         mutex_lock(&pcr->pcr_mutex);
 833
 834         rtsx_pci_start_run(pcr);
 835
 836         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
 837                         host->initial_mode, host->double_clk, host->vpclk);
 838         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
 839         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
 840                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 841
 842         mutex_lock(&host->host_mutex);
 843         host->mrq = mrq;
 844         mutex_unlock(&host->host_mutex);
 845
 846         if (mrq->data)
 847                 data_size = data->blocks * data->blksz;
 848
 849         if (!data_size) {
 850                 sd_send_cmd_get_rsp(host, cmd);
 851         } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
 852                 cmd->error = sd_rw_multi(host, mrq);
 853                 if (!host->using_cookie)
 854                         sdmmc_post_req(host->mmc, host->mrq, 0);
 855
 856                 if (mmc_op_multi(cmd->opcode) && mrq->stop)
 857                         sd_send_cmd_get_rsp(host, mrq->stop);
 858         } else {
 859                 sd_normal_rw(host, mrq);
 860         }
 861
 862         if (mrq->data) {
 863                 if (cmd->error || data->error)
 864                         data->bytes_xfered = 0;
 865                 else
 866                         data->bytes_xfered = data->blocks * data->blksz;
 867         }
 868
 869         mutex_unlock(&pcr->pcr_mutex);
 870
 871 finish:
 872         if (cmd->error) {
 873                 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
 874                         cmd->opcode, cmd->arg, cmd->error);
 875         }
 876
 877         mutex_lock(&host->host_mutex);
 878         host->mrq = NULL;
 879         mutex_unlock(&host->host_mutex);
 880
 881         mmc_request_done(mmc, mrq);
 882 }
 883
 884 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 885 {
 886         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 887         struct mmc_data *data = mrq->data;
 888
 889         mutex_lock(&host->host_mutex);
 890         host->mrq = mrq;
 891         mutex_unlock(&host->host_mutex);
 892
 893         if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
 894                 host->using_cookie = sd_pre_dma_transfer(host, data, false);
 895
 896         schedule_work(&host->work);
 897 }
 898
 899 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
 900                 unsigned char bus_width)
 901 {
 902         int err = 0;
 903         u8 width[] = {
 904                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
 905                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
 906                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
 907         };
 908
 909         if (bus_width <= MMC_BUS_WIDTH_8)
 910                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
 911                                 0x03, width[bus_width]);
 912
 913         return err;
 914 }
 915
 916 static int sd_power_on(struct realtek_pci_sdmmc *host)
 917 {
 918         struct rtsx_pcr *pcr = host->pcr;
 919         int err;
 920
 921         if (host->power_state == SDMMC_POWER_ON)
 922                 return 0;
 923
 924         rtsx_pci_init_cmd(pcr);
 925         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
 926         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
 927                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 928         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
 929                         SD_CLK_EN, SD_CLK_EN);
 930         err = rtsx_pci_send_cmd(pcr, 100);
 931         if (err < 0)
 932                 return err;
 933
 934         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
 935         if (err < 0)
 936                 return err;
 937
 938         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
 939         if (err < 0)
 940                 return err;
 941
 942         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
 943         if (err < 0)
 944                 return err;
 945
 946         host->power_state = SDMMC_POWER_ON;
 947         return 0;
 948 }
 949
 950 static int sd_power_off(struct realtek_pci_sdmmc *host)
 951 {
 952         struct rtsx_pcr *pcr = host->pcr;
 953         int err;
 954
 955         host->power_state = SDMMC_POWER_OFF;
 956
 957         rtsx_pci_init_cmd(pcr);
 958
 959         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 960         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 961
 962         err = rtsx_pci_send_cmd(pcr, 100);
 963         if (err < 0)
 964                 return err;
 965
 966         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 967         if (err < 0)
 968                 return err;
 969
 970         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
 971 }
 972
 973 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
 974                 unsigned char power_mode)
 975 {
 976         int err;
 977
 978         if (power_mode == MMC_POWER_OFF)
 979                 err = sd_power_off(host);
 980         else
 981                 err = sd_power_on(host);
 982
 983         return err;
 984 }
 985
 986 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
 987 {
 988         struct rtsx_pcr *pcr = host->pcr;
 989         int err = 0;
 990
 991         rtsx_pci_init_cmd(pcr);
 992
 993         switch (timing) {
 994         case MMC_TIMING_UHS_SDR104:
 995         case MMC_TIMING_UHS_SDR50:
 996                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 997                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 998                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 999                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1000                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1001                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1002                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1003                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1004                 break;
1005
1006         case MMC_TIMING_MMC_DDR52:
1007         case MMC_TIMING_UHS_DDR50:
1008                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1009                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
1010                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1011                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1012                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1013                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1014                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1015                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1016                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1017                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1018                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1019                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1020                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1021                 break;
1022
1023         case MMC_TIMING_MMC_HS:
1024         case MMC_TIMING_SD_HS:
1025                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1026                                 0x0C, SD_20_MODE);
1027                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1028                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1029                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1030                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1031                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1032                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1033                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1034                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1035                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1036                 break;
1037
1038         default:
1039                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1040                                 SD_CFG1, 0x0C, SD_20_MODE);
1041                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1042                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1043                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1044                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1045                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1046                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1047                                 SD_PUSH_POINT_CTL, 0xFF, 0);
1048                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1049                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1050                 break;
1051         }
1052
1053         err = rtsx_pci_send_cmd(pcr, 100);
1054
1055         return err;
1056 }
1057
1058 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1059 {
1060         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1061         struct rtsx_pcr *pcr = host->pcr;
1062
1063         if (host->eject)
1064                 return;
1065
1066         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1067                 return;
1068
1069         mutex_lock(&pcr->pcr_mutex);
1070
1071         rtsx_pci_start_run(pcr);
1072
1073         sd_set_bus_width(host, ios->bus_width);
1074         sd_set_power_mode(host, ios->power_mode);
1075         sd_set_timing(host, ios->timing);
1076
1077         host->vpclk = false;
1078         host->double_clk = true;
1079
1080         switch (ios->timing) {
1081         case MMC_TIMING_UHS_SDR104:
1082         case MMC_TIMING_UHS_SDR50:
1083                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1084                 host->vpclk = true;
1085                 host->double_clk = false;
1086                 break;
1087         case MMC_TIMING_MMC_DDR52:
1088         case MMC_TIMING_UHS_DDR50:
1089         case MMC_TIMING_UHS_SDR25:
1090                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1091                 break;
1092         default:
1093                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1094                 break;
1095         }
1096
1097         host->initial_mode = (ios->clock <= 1000000) ? true : false;
1098
1099         host->clock = ios->clock;
1100         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1101                         host->initial_mode, host->double_clk, host->vpclk);
1102
1103         mutex_unlock(&pcr->pcr_mutex);
1104 }
1105
1106 static int sdmmc_get_ro(struct mmc_host *mmc)
1107 {
1108         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1109         struct rtsx_pcr *pcr = host->pcr;
1110         int ro = 0;
1111         u32 val;
1112
1113         if (host->eject)
1114                 return -ENOMEDIUM;
1115
1116         mutex_lock(&pcr->pcr_mutex);
1117
1118         rtsx_pci_start_run(pcr);
1119
1120         /* Check SD mechanical write-protect switch */
1121         val = rtsx_pci_readl(pcr, RTSX_BIPR);
1122         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1123         if (val & SD_WRITE_PROTECT)
1124                 ro = 1;
1125
1126         mutex_unlock(&pcr->pcr_mutex);
1127
1128         return ro;
1129 }
1130
1131 static int sdmmc_get_cd(struct mmc_host *mmc)
1132 {
1133         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1134         struct rtsx_pcr *pcr = host->pcr;
1135         int cd = 0;
1136         u32 val;
1137
1138         if (host->eject)
1139                 return cd;
1140
1141         mutex_lock(&pcr->pcr_mutex);
1142
1143         rtsx_pci_start_run(pcr);
1144
1145         /* Check SD card detect */
1146         val = rtsx_pci_card_exist(pcr);
1147         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1148         if (val & SD_EXIST)
1149                 cd = 1;
1150
1151         mutex_unlock(&pcr->pcr_mutex);
1152
1153         return cd;
1154 }
1155
1156 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1157 {
1158         struct rtsx_pcr *pcr = host->pcr;
1159         int err;
1160         u8 stat;
1161
1162         /* Reference to Signal Voltage Switch Sequence in SD spec.
1163          * Wait for a period of time so that the card can drive SD_CMD and
1164          * SD_DAT[3:0] to low after sending back CMD11 response.
1165          */
1166         mdelay(1);
1167
1168         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1169          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1170          * abort the voltage switch sequence;
1171          */
1172         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1173         if (err < 0)
1174                 return err;
1175
1176         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1177                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1178                 return -EINVAL;
1179
1180         /* Stop toggle SD clock */
1181         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1182                         0xFF, SD_CLK_FORCE_STOP);
1183         if (err < 0)
1184                 return err;
1185
1186         return 0;
1187 }
1188
1189 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1190 {
1191         struct rtsx_pcr *pcr = host->pcr;
1192         int err;
1193         u8 stat, mask, val;
1194
1195         /* Wait 1.8V output of voltage regulator in card stable */
1196         msleep(50);
1197
1198         /* Toggle SD clock again */
1199         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1200         if (err < 0)
1201                 return err;
1202
1203         /* Wait for a period of time so that the card can drive
1204          * SD_DAT[3:0] to high at 1.8V
1205          */
1206         msleep(20);
1207
1208         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1209         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1210         if (err < 0)
1211                 return err;
1212
1213         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1214                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1215         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1216                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1217         if ((stat & mask) != val) {
1218                 dev_dbg(sdmmc_dev(host),
1219                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1220                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1221                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1222                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1223                 return -EINVAL;
1224         }
1225
1226         return 0;
1227 }
1228
1229 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1230 {
1231         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1232         struct rtsx_pcr *pcr = host->pcr;
1233         int err = 0;
1234         u8 voltage;
1235
1236         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1237                         __func__, ios->signal_voltage);
1238
1239         if (host->eject)
1240                 return -ENOMEDIUM;
1241
1242         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1243         if (err)
1244                 return err;
1245
1246         mutex_lock(&pcr->pcr_mutex);
1247
1248         rtsx_pci_start_run(pcr);
1249
1250         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1251                 voltage = OUTPUT_3V3;
1252         else
1253                 voltage = OUTPUT_1V8;
1254
1255         if (voltage == OUTPUT_1V8) {
1256                 err = sd_wait_voltage_stable_1(host);
1257                 if (err < 0)
1258                         goto out;
1259         }
1260
1261         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1262         if (err < 0)
1263                 goto out;
1264
1265         if (voltage == OUTPUT_1V8) {
1266                 err = sd_wait_voltage_stable_2(host);
1267                 if (err < 0)
1268                         goto out;
1269         }
1270
1271 out:
1272         /* Stop toggle SD clock in idle */
1273         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1274                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1275
1276         mutex_unlock(&pcr->pcr_mutex);
1277
1278         return err;
1279 }
1280
1281 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1282 {
1283         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1284         struct rtsx_pcr *pcr = host->pcr;
1285         int err = 0;
1286
1287         if (host->eject)
1288                 return -ENOMEDIUM;
1289
1290         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1291         if (err)
1292                 return err;
1293
1294         mutex_lock(&pcr->pcr_mutex);
1295
1296         rtsx_pci_start_run(pcr);
1297
1298         /* Set initial TX phase */
1299         switch (mmc->ios.timing) {
1300         case MMC_TIMING_UHS_SDR104:
1301                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1302                 break;
1303
1304         case MMC_TIMING_UHS_SDR50:
1305                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1306                 break;
1307
1308         case MMC_TIMING_UHS_DDR50:
1309                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1310                 break;
1311
1312         default:
1313                 err = 0;
1314         }
1315
1316         if (err)
1317                 goto out;
1318
1319         /* Tuning RX phase */
1320         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1321                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1322                 err = sd_tuning_rx(host, opcode);
1323         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1324                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1325
1326 out:
1327         mutex_unlock(&pcr->pcr_mutex);
1328
1329         return err;
1330 }
1331
1332 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1333         .pre_req = sdmmc_pre_req,
1334         .post_req = sdmmc_post_req,
1335         .request = sdmmc_request,
1336         .set_ios = sdmmc_set_ios,
1337         .get_ro = sdmmc_get_ro,
1338         .get_cd = sdmmc_get_cd,
1339         .start_signal_voltage_switch = sdmmc_switch_voltage,
1340         .execute_tuning = sdmmc_execute_tuning,
1341 };
1342
1343 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1344 {
1345         struct mmc_host *mmc = host->mmc;
1346         struct rtsx_pcr *pcr = host->pcr;
1347
1348         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1349
1350         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1351                 mmc->caps |= MMC_CAP_UHS_SDR50;
1352         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1353                 mmc->caps |= MMC_CAP_UHS_SDR104;
1354         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1355                 mmc->caps |= MMC_CAP_UHS_DDR50;
1356         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1357                 mmc->caps |= MMC_CAP_1_8V_DDR;
1358         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1359                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1360 }
1361
1362 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1363 {
1364         struct mmc_host *mmc = host->mmc;
1365
1366         mmc->f_min = 250000;
1367         mmc->f_max = 208000000;
1368         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1369         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1370                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1371                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1372         mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1373         mmc->max_current_330 = 400;
1374         mmc->max_current_180 = 800;
1375         mmc->ops = &realtek_pci_sdmmc_ops;
1376
1377         init_extra_caps(host);
1378
1379         mmc->max_segs = 256;
1380         mmc->max_seg_size = 65536;
1381         mmc->max_blk_size = 512;
1382         mmc->max_blk_count = 65535;
1383         mmc->max_req_size = 524288;
1384 }
1385
1386 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1387 {
1388         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1389
1390         host->cookie = -1;
1391         mmc_detect_change(host->mmc, 0);
1392 }
1393
1394 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1395 {
1396         struct mmc_host *mmc;
1397         struct realtek_pci_sdmmc *host;
1398         struct rtsx_pcr *pcr;
1399         struct pcr_handle *handle = pdev->dev.platform_data;
1400
1401         if (!handle)
1402                 return -ENXIO;
1403
1404         pcr = handle->pcr;
1405         if (!pcr)
1406                 return -ENXIO;
1407
1408         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1409
1410         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1411         if (!mmc)
1412                 return -ENOMEM;
1413
1414         host = mmc_priv(mmc);
1415         host->pcr = pcr;
1416         host->mmc = mmc;
1417         host->pdev = pdev;
1418         host->cookie = -1;
1419         host->power_state = SDMMC_POWER_OFF;
1420         INIT_WORK(&host->work, sd_request);
1421         platform_set_drvdata(pdev, host);
1422         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1423         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1424
1425         mutex_init(&host->host_mutex);
1426
1427         realtek_init_host(host);
1428
1429         mmc_add_host(mmc);
1430
1431         return 0;
1432 }
1433
1434 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1435 {
1436         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1437         struct rtsx_pcr *pcr;
1438         struct mmc_host *mmc;
1439
1440         if (!host)
1441                 return 0;
1442
1443         pcr = host->pcr;
1444         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1445         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1446         mmc = host->mmc;
1447
1448         cancel_work_sync(&host->work);
1449
1450         mutex_lock(&host->host_mutex);
1451         if (host->mrq) {
1452                 dev_dbg(&(pdev->dev),
1453                         "%s: Controller removed during transfer\n",
1454                         mmc_hostname(mmc));
1455
1456                 rtsx_pci_complete_unfinished_transfer(pcr);
1457
1458                 host->mrq->cmd->error = -ENOMEDIUM;
1459                 if (host->mrq->stop)
1460                         host->mrq->stop->error = -ENOMEDIUM;
1461                 mmc_request_done(mmc, host->mrq);
1462         }
1463         mutex_unlock(&host->host_mutex);
1464
1465         mmc_remove_host(mmc);
1466         host->eject = true;
1467
1468         flush_work(&host->work);
1469
1470         mmc_free_host(mmc);
1471
1472         dev_dbg(&(pdev->dev),
1473                 ": Realtek PCI-E SDMMC controller has been removed\n");
1474
1475         return 0;
1476 }
1477
1478 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1479         {
1480                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1481         }, {
1482                 /* sentinel */
1483         }
1484 };
1485 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1486
1487 static struct platform_driver rtsx_pci_sdmmc_driver = {
1488         .probe          = rtsx_pci_sdmmc_drv_probe,
1489         .remove         = rtsx_pci_sdmmc_drv_remove,
1490         .id_table       = rtsx_pci_sdmmc_ids,
1491         .driver         = {
1492                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1493         },
1494 };
1495 module_platform_driver(rtsx_pci_sdmmc_driver);
1496
1497 MODULE_LICENSE("GPL");
1498 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1499 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");