drivers/mmc/host/sdhci-esdhc-imx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Freescale eSDHC i.MX controller driver for the platform bus.
   4  *
   5  * derived from the OF-version.
   6  *
   7  * Copyright (c) 2010 Pengutronix e.K.
   8  *   Author: Wolfram Sang <kernel@pengutronix.de>
   9  */
  10
  11 #include <linux/io.h>
  12 #include <linux/delay.h>
  13 #include <linux/err.h>
  14 #include <linux/clk.h>
  15 #include <linux/gpio.h>
  16 #include <linux/module.h>
  17 #include <linux/slab.h>
  18 #include <linux/mmc/host.h>
  19 #include <linux/mmc/mmc.h>
  20 #include <linux/mmc/sdio.h>
  21 #include <linux/mmc/slot-gpio.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_gpio.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/platform_data/mmc-esdhc-imx.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/iopoll.h>
  29 #include "sdhci-pltfm.h"
  30 #include "sdhci-esdhc.h"
  31
  32 #define ESDHC_SYS_CTRL_DTOCV_MASK       0x0f
  33 #define ESDHC_CTRL_D3CD                 0x08
  34 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
  35 /* VENDOR SPEC register */
  36 #define ESDHC_VENDOR_SPEC               0xc0
  37 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  38 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  39 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  40 #define ESDHC_WTMK_LVL                  0x44
  41 #define  ESDHC_WTMK_DEFAULT_VAL         0x10401040
  42 #define  ESDHC_WTMK_LVL_RD_WML_MASK     0x000000FF
  43 #define  ESDHC_WTMK_LVL_RD_WML_SHIFT    0
  44 #define  ESDHC_WTMK_LVL_WR_WML_MASK     0x00FF0000
  45 #define  ESDHC_WTMK_LVL_WR_WML_SHIFT    16
  46 #define  ESDHC_WTMK_LVL_WML_VAL_DEF     64
  47 #define  ESDHC_WTMK_LVL_WML_VAL_MAX     128
  48 #define ESDHC_MIX_CTRL                  0x48
  49 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  50 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  51 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  52 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  53 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN    (1 << 24)
  54 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  55 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
  56 /* Bits 3 and 6 are not SDHCI standard definitions */
  57 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  58 /* Tuning bits */
  59 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  60
  61 /* dll control register */
  62 #define ESDHC_DLL_CTRL                  0x60
  63 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  64 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  65
  66 /* tune control register */
  67 #define ESDHC_TUNE_CTRL_STATUS          0x68
  68 #define  ESDHC_TUNE_CTRL_STEP           1
  69 #define  ESDHC_TUNE_CTRL_MIN            0
  70 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  71
  72 /* strobe dll register */
  73 #define ESDHC_STROBE_DLL_CTRL           0x70
  74 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
  75 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
  76 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
  77
  78 #define ESDHC_STROBE_DLL_STATUS         0x74
  79 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
  80 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
  81
  82 #define ESDHC_TUNING_CTRL               0xcc
  83 #define ESDHC_STD_TUNING_EN             (1 << 24)
  84 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  85 #define ESDHC_TUNING_START_TAP_DEFAULT  0x1
  86 #define ESDHC_TUNING_START_TAP_MASK     0x7f
  87 #define ESDHC_TUNING_STEP_MASK          0x00070000
  88 #define ESDHC_TUNING_STEP_SHIFT         16
  89
  90 /* pinctrl state */
  91 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
  92 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
  93
  94 /*
  95  * Our interpretation of the SDHCI_HOST_CONTROL register
  96  */
  97 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
  98 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
  99 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
 100
 101 /*
 102  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
 103  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 104  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 105  * Define this macro DMA error INT for fsl eSDHC
 106  */
 107 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
 108
 109 /*
 110  * The CMDTYPE of the CMD register (offset 0xE) should be set to
 111  * "11" when the STOP CMD12 is issued on imx53 to abort one
 112  * open ended multi-blk IO. Otherwise the TC INT wouldn't
 113  * be generated.
 114  * In exact block transfer, the controller doesn't complete the
 115  * operations automatically as required at the end of the
 116  * transfer and remains on hold if the abort command is not sent.
 117  * As a result, the TC flag is not asserted and SW received timeout
 118  * exception. Bit1 of Vendor Spec register is used to fix it.
 119  */
 120 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 121 /*
 122  * The flag tells that the ESDHC controller is an USDHC block that is
 123  * integrated on the i.MX6 series.
 124  */
 125 #define ESDHC_FLAG_USDHC                BIT(3)
 126 /* The IP supports manual tuning process */
 127 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 128 /* The IP supports standard tuning process */
 129 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 130 /* The IP has SDHCI_CAPABILITIES_1 register */
 131 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 132 /*
 133  * The IP has erratum ERR004536
 134  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
 135  * when reading data from the card
 136  * This flag is also set for i.MX25 and i.MX35 in order to get
 137  * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
 138  */
 139 #define ESDHC_FLAG_ERR004536            BIT(7)
 140 /* The IP supports HS200 mode */
 141 #define ESDHC_FLAG_HS200                BIT(8)
 142 /* The IP supports HS400 mode */
 143 #define ESDHC_FLAG_HS400                BIT(9)
 144
 145 /* A clock frequency higher than this rate requires strobe dll control */
 146 #define ESDHC_STROBE_DLL_CLK_FREQ       100000000
 147
 148 struct esdhc_soc_data {
 149         u32 flags;
 150 };
 151
 152 static struct esdhc_soc_data esdhc_imx25_data = {
 153         .flags = ESDHC_FLAG_ERR004536,
 154 };
 155
 156 static struct esdhc_soc_data esdhc_imx35_data = {
 157         .flags = ESDHC_FLAG_ERR004536,
 158 };
 159
 160 static struct esdhc_soc_data esdhc_imx51_data = {
 161         .flags = 0,
 162 };
 163
 164 static struct esdhc_soc_data esdhc_imx53_data = {
 165         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 166 };
 167
 168 static struct esdhc_soc_data usdhc_imx6q_data = {
 169         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
 170 };
 171
 172 static struct esdhc_soc_data usdhc_imx6sl_data = {
 173         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 174                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
 175                         | ESDHC_FLAG_HS200,
 176 };
 177
 178 static struct esdhc_soc_data usdhc_imx6sx_data = {
 179         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 180                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
 181 };
 182
 183 static struct esdhc_soc_data usdhc_imx7d_data = {
 184         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 185                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 186                         | ESDHC_FLAG_HS400,
 187 };
 188
 189 struct pltfm_imx_data {
 190         u32 scratchpad;
 191         struct pinctrl *pinctrl;
 192         struct pinctrl_state *pins_default;
 193         struct pinctrl_state *pins_100mhz;
 194         struct pinctrl_state *pins_200mhz;
 195         const struct esdhc_soc_data *socdata;
 196         struct esdhc_platform_data boarddata;
 197         struct clk *clk_ipg;
 198         struct clk *clk_ahb;
 199         struct clk *clk_per;
 200         unsigned int actual_clock;
 201         enum {
 202                 NO_CMD_PENDING,      /* no multiblock command pending */
 203                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 204                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 205         } multiblock_status;
 206         u32 is_ddr;
 207 };
 208
 209 static const struct platform_device_id imx_esdhc_devtype[] = {
 210         {
 211                 .name = "sdhci-esdhc-imx25",
 212                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
 213         }, {
 214                 .name = "sdhci-esdhc-imx35",
 215                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
 216         }, {
 217                 .name = "sdhci-esdhc-imx51",
 218                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
 219         }, {
 220                 /* sentinel */
 221         }
 222 };
 223 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
 224
 225 static const struct of_device_id imx_esdhc_dt_ids[] = {
 226         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 227         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 228         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 229         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 230         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
 231         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 232         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 233         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
 234         { /* sentinel */ }
 235 };
 236 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 237
 238 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 239 {
 240         return data->socdata == &esdhc_imx25_data;
 241 }
 242
 243 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 244 {
 245         return data->socdata == &esdhc_imx53_data;
 246 }
 247
 248 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
 249 {
 250         return data->socdata == &usdhc_imx6q_data;
 251 }
 252
 253 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 254 {
 255         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 256 }
 257
 258 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 259 {
 260         void __iomem *base = host->ioaddr + (reg & ~0x3);
 261         u32 shift = (reg & 0x3) * 8;
 262
 263         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 264 }
 265
 266 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 267 {
 268         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 269         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 270         u32 val = readl(host->ioaddr + reg);
 271
 272         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 273                 u32 fsl_prss = val;
 274                 /* save the least 20 bits */
 275                 val = fsl_prss & 0x000FFFFF;
 276                 /* move dat[0-3] bits */
 277                 val |= (fsl_prss & 0x0F000000) >> 4;
 278                 /* move cmd line bit */
 279                 val |= (fsl_prss & 0x00800000) << 1;
 280         }
 281
 282         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 283                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 284                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 285                         val &= 0xffff0000;
 286
 287                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 288                  * ADMA2 capability of esdhc, but this bit is messed up on
 289                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 290                  * don't actually support ADMA2). So set the BROKEN_ADMA
 291                  * quirk on MX25/35 platforms.
 292                  */
 293
 294                 if (val & SDHCI_CAN_DO_ADMA1) {
 295                         val &= ~SDHCI_CAN_DO_ADMA1;
 296                         val |= SDHCI_CAN_DO_ADMA2;
 297                 }
 298         }
 299
 300         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 301                 if (esdhc_is_usdhc(imx_data)) {
 302                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 303                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 304                         else
 305                                 /* imx6q/dl does not have cap_1 register, fake one */
 306                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 307                                         | SDHCI_SUPPORT_SDR50
 308                                         | SDHCI_USE_SDR50_TUNING
 309                                         | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
 310
 311                         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
 312                                 val |= SDHCI_SUPPORT_HS400;
 313
 314                         /*
 315                          * Do not advertise faster UHS modes if there are no
 316                          * pinctrl states for 100MHz/200MHz.
 317                          */
 318                         if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
 319                             IS_ERR_OR_NULL(imx_data->pins_200mhz))
 320                                 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
 321                                          | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
 322                 }
 323         }
 324
 325         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 326                 val = 0;
 327                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
 328                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
 329                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
 330         }
 331
 332         if (unlikely(reg == SDHCI_INT_STATUS)) {
 333                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 334                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 335                         val |= SDHCI_INT_ADMA_ERROR;
 336                 }
 337
 338                 /*
 339                  * mask off the interrupt we get in response to the manually
 340                  * sent CMD12
 341                  */
 342                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 343                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 344                         val &= ~SDHCI_INT_RESPONSE;
 345                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 346                                                    SDHCI_INT_STATUS);
 347                         imx_data->multiblock_status = NO_CMD_PENDING;
 348                 }
 349         }
 350
 351         return val;
 352 }
 353
 354 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 355 {
 356         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 357         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 358         u32 data;
 359
 360         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
 361                         reg == SDHCI_INT_STATUS)) {
 362                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
 363                         /*
 364                          * Clear and then set D3CD bit to avoid missing the
 365                          * card interrupt. This is an eSDHC controller problem
 366                          * so we need to apply the following workaround: clear
 367                          * and set D3CD bit will make eSDHC re-sample the card
 368                          * interrupt. In case a card interrupt was lost,
 369                          * re-sample it by the following steps.
 370                          */
 371                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 372                         data &= ~ESDHC_CTRL_D3CD;
 373                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 374                         data |= ESDHC_CTRL_D3CD;
 375                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 376                 }
 377
 378                 if (val & SDHCI_INT_ADMA_ERROR) {
 379                         val &= ~SDHCI_INT_ADMA_ERROR;
 380                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 381                 }
 382         }
 383
 384         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 385                                 && (reg == SDHCI_INT_STATUS)
 386                                 && (val & SDHCI_INT_DATA_END))) {
 387                         u32 v;
 388                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 389                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 390                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 391
 392                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 393                         {
 394                                 /* send a manual CMD12 with RESPTYP=none */
 395                                 data = MMC_STOP_TRANSMISSION << 24 |
 396                                        SDHCI_CMD_ABORTCMD << 16;
 397                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 398                                 imx_data->multiblock_status = WAIT_FOR_INT;
 399                         }
 400         }
 401
 402         writel(val, host->ioaddr + reg);
 403 }
 404
 405 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 406 {
 407         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 408         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 409         u16 ret = 0;
 410         u32 val;
 411
 412         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 413                 reg ^= 2;
 414                 if (esdhc_is_usdhc(imx_data)) {
 415                         /*
 416                          * The usdhc register returns a wrong host version.
 417                          * Correct it here.
 418                          */
 419                         return SDHCI_SPEC_300;
 420                 }
 421         }
 422
 423         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 424                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 425                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 426                         ret |= SDHCI_CTRL_VDD_180;
 427
 428                 if (esdhc_is_usdhc(imx_data)) {
 429                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 430                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 431                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 432                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 433                                 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 434                 }
 435
 436                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 437                         ret |= SDHCI_CTRL_EXEC_TUNING;
 438                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 439                         ret |= SDHCI_CTRL_TUNED_CLK;
 440
 441                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 442
 443                 return ret;
 444         }
 445
 446         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 447                 if (esdhc_is_usdhc(imx_data)) {
 448                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 449                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 450                         /* Swap AC23 bit */
 451                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 452                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 453                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 454                         }
 455                 } else {
 456                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 457                 }
 458
 459                 return ret;
 460         }
 461
 462         return readw(host->ioaddr + reg);
 463 }
 464
 465 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 466 {
 467         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 468         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 469         u32 new_val = 0;
 470
 471         switch (reg) {
 472         case SDHCI_CLOCK_CONTROL:
 473                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 474                 if (val & SDHCI_CLOCK_CARD_EN)
 475                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 476                 else
 477                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 478                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 479                 return;
 480         case SDHCI_HOST_CONTROL2:
 481                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 482                 if (val & SDHCI_CTRL_VDD_180)
 483                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 484                 else
 485                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 486                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 487                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 488                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 489                         if (val & SDHCI_CTRL_TUNED_CLK) {
 490                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 491                                 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 492                         } else {
 493                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 494                                 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 495                         }
 496                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 497                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 498                         u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 499                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 500                         if (val & SDHCI_CTRL_TUNED_CLK) {
 501                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 502                         } else {
 503                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 504                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 505                                 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 506                         }
 507
 508                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 509                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 510                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 511                                 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 512                         } else {
 513                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 514                         }
 515
 516                         writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 517                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 518                 }
 519                 return;
 520         case SDHCI_TRANSFER_MODE:
 521                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 522                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 523                                 && (host->cmd->data->blocks > 1)
 524                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 525                         u32 v;
 526                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 527                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 528                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 529                 }
 530
 531                 if (esdhc_is_usdhc(imx_data)) {
 532                         u32 wml;
 533                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 534                         /* Swap AC23 bit */
 535                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 536                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 537                                 val |= ESDHC_MIX_CTRL_AC23EN;
 538                         }
 539                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 540                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 541
 542                         /* Set watermark levels for PIO access to maximum value
 543                          * (128 words) to accommodate full 512 bytes buffer.
 544                          * For DMA access restore the levels to default value.
 545                          */
 546                         m = readl(host->ioaddr + ESDHC_WTMK_LVL);
 547                         if (val & SDHCI_TRNS_DMA)
 548                                 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
 549                         else
 550                                 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
 551                         m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
 552                                ESDHC_WTMK_LVL_WR_WML_MASK);
 553                         m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
 554                              (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
 555                         writel(m, host->ioaddr + ESDHC_WTMK_LVL);
 556                 } else {
 557                         /*
 558                          * Postpone this write, we must do it together with a
 559                          * command write that is down below.
 560                          */
 561                         imx_data->scratchpad = val;
 562                 }
 563                 return;
 564         case SDHCI_COMMAND:
 565                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 566                         val |= SDHCI_CMD_ABORTCMD;
 567
 568                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 569                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 570                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 571
 572                 if (esdhc_is_usdhc(imx_data))
 573                         writel(val << 16,
 574                                host->ioaddr + SDHCI_TRANSFER_MODE);
 575                 else
 576                         writel(val << 16 | imx_data->scratchpad,
 577                                host->ioaddr + SDHCI_TRANSFER_MODE);
 578                 return;
 579         case SDHCI_BLOCK_SIZE:
 580                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 581                 break;
 582         }
 583         esdhc_clrset_le(host, 0xffff, val, reg);
 584 }
 585
 586 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
 587 {
 588         u8 ret;
 589         u32 val;
 590
 591         switch (reg) {
 592         case SDHCI_HOST_CONTROL:
 593                 val = readl(host->ioaddr + reg);
 594
 595                 ret = val & SDHCI_CTRL_LED;
 596                 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
 597                 ret |= (val & ESDHC_CTRL_4BITBUS);
 598                 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
 599                 return ret;
 600         }
 601
 602         return readb(host->ioaddr + reg);
 603 }
 604
 605 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 606 {
 607         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 608         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 609         u32 new_val = 0;
 610         u32 mask;
 611
 612         switch (reg) {
 613         case SDHCI_POWER_CONTROL:
 614                 /*
 615                  * FSL put some DMA bits here
 616                  * If your board has a regulator, code should be here
 617                  */
 618                 return;
 619         case SDHCI_HOST_CONTROL:
 620                 /* FSL messed up here, so we need to manually compose it. */
 621                 new_val = val & SDHCI_CTRL_LED;
 622                 /* ensure the endianness */
 623                 new_val |= ESDHC_HOST_CONTROL_LE;
 624                 /* bits 8&9 are reserved on mx25 */
 625                 if (!is_imx25_esdhc(imx_data)) {
 626                         /* DMA mode bits are shifted */
 627                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 628                 }
 629
 630                 /*
 631                  * Do not touch buswidth bits here. This is done in
 632                  * esdhc_pltfm_bus_width.
 633                  * Do not touch the D3CD bit either which is used for the
 634                  * SDIO interrupt erratum workaround.
 635                  */
 636                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 637
 638                 esdhc_clrset_le(host, mask, new_val, reg);
 639                 return;
 640         case SDHCI_SOFTWARE_RESET:
 641                 if (val & SDHCI_RESET_DATA)
 642                         new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 643                 break;
 644         }
 645         esdhc_clrset_le(host, 0xff, val, reg);
 646
 647         if (reg == SDHCI_SOFTWARE_RESET) {
 648                 if (val & SDHCI_RESET_ALL) {
 649                         /*
 650                          * The esdhc has a design violation to SDHC spec which
 651                          * tells that software reset should not affect card
 652                          * detection circuit. But esdhc clears its SYSCTL
 653                          * register bits [0..2] during the software reset. This
 654                          * will stop those clocks that card detection circuit
 655                          * relies on. To work around it, we turn the clocks on
 656                          * back to keep card detection circuit functional.
 657                          */
 658                         esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 659                         /*
 660                          * The reset on usdhc fails to clear MIX_CTRL register.
 661                          * Do it manually here.
 662                          */
 663                         if (esdhc_is_usdhc(imx_data)) {
 664                                 /*
 665                                  * the tuning bits should be kept during reset
 666                                  */
 667                                 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 668                                 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 669                                                 host->ioaddr + ESDHC_MIX_CTRL);
 670                                 imx_data->is_ddr = 0;
 671                         }
 672                 } else if (val & SDHCI_RESET_DATA) {
 673                         /*
 674                          * The eSDHC DAT line software reset clears at least the
 675                          * data transfer width on i.MX25, so make sure that the
 676                          * Host Control register is unaffected.
 677                          */
 678                         esdhc_clrset_le(host, 0xff, new_val,
 679                                         SDHCI_HOST_CONTROL);
 680                 }
 681         }
 682 }
 683
 684 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 685 {
 686         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 687
 688         return pltfm_host->clock;
 689 }
 690
 691 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 692 {
 693         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 694
 695         return pltfm_host->clock / 256 / 16;
 696 }
 697
 698 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 699                                          unsigned int clock)
 700 {
 701         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 702         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 703         unsigned int host_clock = pltfm_host->clock;
 704         int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
 705         int pre_div = 1;
 706         int div = 1;
 707         u32 temp, val;
 708
 709         if (esdhc_is_usdhc(imx_data)) {
 710                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 711                 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 712                         host->ioaddr + ESDHC_VENDOR_SPEC);
 713         }
 714
 715         if (clock == 0) {
 716                 host->mmc->actual_clock = 0;
 717                 return;
 718         }
 719
 720         /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
 721         if (is_imx53_esdhc(imx_data)) {
 722                 /*
 723                  * According to the i.MX53 reference manual, if DLLCTRL[10] can
 724                  * be set, then the controller is eSDHCv3, else it is eSDHCv2.
 725                  */
 726                 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
 727                 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
 728                 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
 729                 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
 730                 if (temp & BIT(10))
 731                         pre_div = 2;
 732         }
 733
 734         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 735         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 736                 | ESDHC_CLOCK_MASK);
 737         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 738
 739         while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
 740                         pre_div < 256)
 741                 pre_div *= 2;
 742
 743         while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
 744                 div++;
 745
 746         host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
 747         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 748                 clock, host->mmc->actual_clock);
 749
 750         pre_div >>= 1;
 751         div--;
 752
 753         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 754         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 755                 | (div << ESDHC_DIVIDER_SHIFT)
 756                 | (pre_div << ESDHC_PREDIV_SHIFT));
 757         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 758
 759         if (esdhc_is_usdhc(imx_data)) {
 760                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 761                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 762                         host->ioaddr + ESDHC_VENDOR_SPEC);
 763         }
 764
 765         mdelay(1);
 766 }
 767
 768 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 769 {
 770         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 771         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 772         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 773
 774         switch (boarddata->wp_type) {
 775         case ESDHC_WP_GPIO:
 776                 return mmc_gpio_get_ro(host->mmc);
 777         case ESDHC_WP_CONTROLLER:
 778                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 779                                SDHCI_WRITE_PROTECT);
 780         case ESDHC_WP_NONE:
 781                 break;
 782         }
 783
 784         return -ENOSYS;
 785 }
 786
 787 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 788 {
 789         u32 ctrl;
 790
 791         switch (width) {
 792         case MMC_BUS_WIDTH_8:
 793                 ctrl = ESDHC_CTRL_8BITBUS;
 794                 break;
 795         case MMC_BUS_WIDTH_4:
 796                 ctrl = ESDHC_CTRL_4BITBUS;
 797                 break;
 798         default:
 799                 ctrl = 0;
 800                 break;
 801         }
 802
 803         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 804                         SDHCI_HOST_CONTROL);
 805 }
 806
 807 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 808 {
 809         u32 reg;
 810
 811         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 812         mdelay(1);
 813
 814         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 815         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 816                         ESDHC_MIX_CTRL_FBCLK_SEL;
 817         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 818         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 819         dev_dbg(mmc_dev(host->mmc),
 820                 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 821                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 822 }
 823
 824 static void esdhc_post_tuning(struct sdhci_host *host)
 825 {
 826         u32 reg;
 827
 828         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 829         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 830         reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 831         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 832 }
 833
 834 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
 835 {
 836         int min, max, avg, ret;
 837
 838         /* find the mininum delay first which can pass tuning */
 839         min = ESDHC_TUNE_CTRL_MIN;
 840         while (min < ESDHC_TUNE_CTRL_MAX) {
 841                 esdhc_prepare_tuning(host, min);
 842                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
 843                         break;
 844                 min += ESDHC_TUNE_CTRL_STEP;
 845         }
 846
 847         /* find the maxinum delay which can not pass tuning */
 848         max = min + ESDHC_TUNE_CTRL_STEP;
 849         while (max < ESDHC_TUNE_CTRL_MAX) {
 850                 esdhc_prepare_tuning(host, max);
 851                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
 852                         max -= ESDHC_TUNE_CTRL_STEP;
 853                         break;
 854                 }
 855                 max += ESDHC_TUNE_CTRL_STEP;
 856         }
 857
 858         /* use average delay to get the best timing */
 859         avg = (min + max) / 2;
 860         esdhc_prepare_tuning(host, avg);
 861         ret = mmc_send_tuning(host->mmc, opcode, NULL);
 862         esdhc_post_tuning(host);
 863
 864         dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
 865                 ret ? "failed" : "passed", avg, ret);
 866
 867         return ret;
 868 }
 869
 870 static int esdhc_change_pinstate(struct sdhci_host *host,
 871                                                 unsigned int uhs)
 872 {
 873         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 874         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 875         struct pinctrl_state *pinctrl;
 876
 877         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
 878
 879         if (IS_ERR(imx_data->pinctrl) ||
 880                 IS_ERR(imx_data->pins_default) ||
 881                 IS_ERR(imx_data->pins_100mhz) ||
 882                 IS_ERR(imx_data->pins_200mhz))
 883                 return -EINVAL;
 884
 885         switch (uhs) {
 886         case MMC_TIMING_UHS_SDR50:
 887         case MMC_TIMING_UHS_DDR50:
 888                 pinctrl = imx_data->pins_100mhz;
 889                 break;
 890         case MMC_TIMING_UHS_SDR104:
 891         case MMC_TIMING_MMC_HS200:
 892         case MMC_TIMING_MMC_HS400:
 893                 pinctrl = imx_data->pins_200mhz;
 894                 break;
 895         default:
 896                 /* back to default state for other legacy timing */
 897                 pinctrl = imx_data->pins_default;
 898         }
 899
 900         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
 901 }
 902
 903 /*
 904  * For HS400 eMMC, there is a data_strobe line. This signal is generated
 905  * by the device and used for data output and CRC status response output
 906  * in HS400 mode. The frequency of this signal follows the frequency of
 907  * CLK generated by host. The host receives the data which is aligned to the
 908  * edge of data_strobe line. Due to the time delay between CLK line and
 909  * data_strobe line, if the delay time is larger than one clock cycle,
 910  * then CLK and data_strobe line will be misaligned, read error shows up.
 911  * So when the CLK is higher than 100MHz, each clock cycle is short enough,
 912  * host should configure the delay target.
 913  */
 914 static void esdhc_set_strobe_dll(struct sdhci_host *host)
 915 {
 916         u32 v;
 917
 918         if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
 919                 /* disable clock before enabling strobe dll */
 920                 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
 921                        ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 922                        host->ioaddr + ESDHC_VENDOR_SPEC);
 923
 924                 /* force a reset on strobe dll */
 925                 writel(ESDHC_STROBE_DLL_CTRL_RESET,
 926                         host->ioaddr + ESDHC_STROBE_DLL_CTRL);
 927                 /*
 928                  * enable strobe dll ctrl and adjust the delay target
 929                  * for the uSDHC loopback read clock
 930                  */
 931                 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
 932                         (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
 933                 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
 934                 /* wait 1us to make sure strobe dll status register stable */
 935                 udelay(1);
 936                 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
 937                 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
 938                         dev_warn(mmc_dev(host->mmc),
 939                                 "warning! HS400 strobe DLL status REF not lock!\n");
 940                 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
 941                         dev_warn(mmc_dev(host->mmc),
 942                                 "warning! HS400 strobe DLL status SLV not lock!\n");
 943         }
 944 }
 945
 946 static void esdhc_reset_tuning(struct sdhci_host *host)
 947 {
 948         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 949         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 950         u32 ctrl;
 951         int ret;
 952
 953         /* Reset the tuning circuit */
 954         if (esdhc_is_usdhc(imx_data)) {
 955                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 956                         ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
 957                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 958                         ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 959                         writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
 960                         writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 961                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 962                         ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 963                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 964                         ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 965                         writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 966                         /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
 967                         ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
 968                                 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
 969                         if (ret == -ETIMEDOUT)
 970                                 dev_warn(mmc_dev(host->mmc),
 971                                  "Warning! clear execute tuning bit failed\n");
 972                         /*
 973                          * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
 974                          * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
 975                          * will finally make sure the normal data transfer logic correct.
 976                          */
 977                         ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
 978                         ctrl |= SDHCI_INT_DATA_AVAIL;
 979                         writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
 980                 }
 981         }
 982 }
 983
 984 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
 985 {
 986         u32 m;
 987         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 988         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 989         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 990
 991         /* disable ddr mode and disable HS400 mode */
 992         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 993         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
 994         imx_data->is_ddr = 0;
 995
 996         switch (timing) {
 997         case MMC_TIMING_UHS_SDR12:
 998         case MMC_TIMING_UHS_SDR25:
 999         case MMC_TIMING_UHS_SDR50:
1000         case MMC_TIMING_UHS_SDR104:
1001         case MMC_TIMING_MMC_HS:
1002         case MMC_TIMING_MMC_HS200:
1003                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1004                 break;
1005         case MMC_TIMING_UHS_DDR50:
1006         case MMC_TIMING_MMC_DDR52:
1007                 m |= ESDHC_MIX_CTRL_DDREN;
1008                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1009                 imx_data->is_ddr = 1;
1010                 if (boarddata->delay_line) {
1011                         u32 v;
1012                         v = boarddata->delay_line <<
1013                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1014                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1015                         if (is_imx53_esdhc(imx_data))
1016                                 v <<= 1;
1017                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1018                 }
1019                 break;
1020         case MMC_TIMING_MMC_HS400:
1021                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1022                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1023                 imx_data->is_ddr = 1;
1024                 /* update clock after enable DDR for strobe DLL lock */
1025                 host->ops->set_clock(host, host->clock);
1026                 esdhc_set_strobe_dll(host);
1027                 break;
1028         case MMC_TIMING_LEGACY:
1029         default:
1030                 esdhc_reset_tuning(host);
1031                 break;
1032         }
1033
1034         esdhc_change_pinstate(host, timing);
1035 }
1036
1037 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1038 {
1039         sdhci_reset(host, mask);
1040
1041         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1042         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1043 }
1044
1045 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1046 {
1047         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1048         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1049
1050         /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1051         return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1052 }
1053
1054 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1055 {
1056         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1057         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1058
1059         /* use maximum timeout counter */
1060         esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1061                         esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1062                         SDHCI_TIMEOUT_CONTROL);
1063 }
1064
1065 static struct sdhci_ops sdhci_esdhc_ops = {
1066         .read_l = esdhc_readl_le,
1067         .read_w = esdhc_readw_le,
1068         .read_b = esdhc_readb_le,
1069         .write_l = esdhc_writel_le,
1070         .write_w = esdhc_writew_le,
1071         .write_b = esdhc_writeb_le,
1072         .set_clock = esdhc_pltfm_set_clock,
1073         .get_max_clock = esdhc_pltfm_get_max_clock,
1074         .get_min_clock = esdhc_pltfm_get_min_clock,
1075         .get_max_timeout_count = esdhc_get_max_timeout_count,
1076         .get_ro = esdhc_pltfm_get_ro,
1077         .set_timeout = esdhc_set_timeout,
1078         .set_bus_width = esdhc_pltfm_set_bus_width,
1079         .set_uhs_signaling = esdhc_set_uhs_signaling,
1080         .reset = esdhc_reset,
1081 };
1082
1083 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1084         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1085                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1086                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1087                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1088         .ops = &sdhci_esdhc_ops,
1089 };
1090
1091 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1092 {
1093         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1094         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1095         int tmp;
1096
1097         if (esdhc_is_usdhc(imx_data)) {
1098                 /*
1099                  * The imx6q ROM code will change the default watermark
1100                  * level setting to something insane.  Change it back here.
1101                  */
1102                 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1103
1104                 /*
1105                  * ROM code will change the bit burst_length_enable setting
1106                  * to zero if this usdhc is chosen to boot system. Change
1107                  * it back here, otherwise it will impact the performance a
1108                  * lot. This bit is used to enable/disable the burst length
1109                  * for the external AHB2AXI bridge. It's useful especially
1110                  * for INCR transfer because without burst length indicator,
1111                  * the AHB2AXI bridge does not know the burst length in
1112                  * advance. And without burst length indicator, AHB INCR
1113                  * transfer can only be converted to singles on the AXI side.
1114                  */
1115                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1116                         | ESDHC_BURST_LEN_EN_INCR,
1117                         host->ioaddr + SDHCI_HOST_CONTROL);
1118
1119                 /*
1120                  * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1121                  * TO1.1, it's harmless for MX6SL
1122                  */
1123                 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1124                         host->ioaddr + 0x6c);
1125
1126                 /* disable DLL_CTRL delay line settings */
1127                 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1128
1129                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1130                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1131                         tmp |= ESDHC_STD_TUNING_EN |
1132                                 ESDHC_TUNING_START_TAP_DEFAULT;
1133                         if (imx_data->boarddata.tuning_start_tap) {
1134                                 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1135                                 tmp |= imx_data->boarddata.tuning_start_tap;
1136                         }
1137
1138                         if (imx_data->boarddata.tuning_step) {
1139                                 tmp &= ~ESDHC_TUNING_STEP_MASK;
1140                                 tmp |= imx_data->boarddata.tuning_step
1141                                         << ESDHC_TUNING_STEP_SHIFT;
1142                         }
1143                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1144                 }
1145         }
1146 }
1147
1148 #ifdef CONFIG_OF
1149 static int
1150 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1151                          struct sdhci_host *host,
1152                          struct pltfm_imx_data *imx_data)
1153 {
1154         struct device_node *np = pdev->dev.of_node;
1155         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1156         int ret;
1157
1158         if (of_get_property(np, "fsl,wp-controller", NULL))
1159                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1160
1161         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1162         if (gpio_is_valid(boarddata->wp_gpio))
1163                 boarddata->wp_type = ESDHC_WP_GPIO;
1164
1165         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1166         of_property_read_u32(np, "fsl,tuning-start-tap",
1167                              &boarddata->tuning_start_tap);
1168
1169         if (of_find_property(np, "no-1-8-v", NULL))
1170                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1171
1172         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1173                 boarddata->delay_line = 0;
1174
1175         mmc_of_parse_voltage(np, &host->ocr_mask);
1176
1177         if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pins_default)) {
1178                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1179                                                 ESDHC_PINCTRL_STATE_100MHZ);
1180                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1181                                                 ESDHC_PINCTRL_STATE_200MHZ);
1182         }
1183
1184         /* call to generic mmc_of_parse to support additional capabilities */
1185         ret = mmc_of_parse(host->mmc);
1186         if (ret)
1187                 return ret;
1188
1189         if (mmc_gpio_get_cd(host->mmc) >= 0)
1190                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1191
1192         return 0;
1193 }
1194 #else
1195 static inline int
1196 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1197                          struct sdhci_host *host,
1198                          struct pltfm_imx_data *imx_data)
1199 {
1200         return -ENODEV;
1201 }
1202 #endif
1203
1204 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1205                          struct sdhci_host *host,
1206                          struct pltfm_imx_data *imx_data)
1207 {
1208         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1209         int err;
1210
1211         if (!host->mmc->parent->platform_data) {
1212                 dev_err(mmc_dev(host->mmc), "no board data!\n");
1213                 return -EINVAL;
1214         }
1215
1216         imx_data->boarddata = *((struct esdhc_platform_data *)
1217                                 host->mmc->parent->platform_data);
1218         /* write_protect */
1219         if (boarddata->wp_type == ESDHC_WP_GPIO) {
1220                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1221                 if (err) {
1222                         dev_err(mmc_dev(host->mmc),
1223                                 "failed to request write-protect gpio!\n");
1224                         return err;
1225                 }
1226                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1227         }
1228
1229         /* card_detect */
1230         switch (boarddata->cd_type) {
1231         case ESDHC_CD_GPIO:
1232                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1233                 if (err) {
1234                         dev_err(mmc_dev(host->mmc),
1235                                 "failed to request card-detect gpio!\n");
1236                         return err;
1237                 }
1238                 /* fall through */
1239
1240         case ESDHC_CD_CONTROLLER:
1241                 /* we have a working card_detect back */
1242                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1243                 break;
1244
1245         case ESDHC_CD_PERMANENT:
1246                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1247                 break;
1248
1249         case ESDHC_CD_NONE:
1250                 break;
1251         }
1252
1253         switch (boarddata->max_bus_width) {
1254         case 8:
1255                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1256                 break;
1257         case 4:
1258                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1259                 break;
1260         case 1:
1261         default:
1262                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1263                 break;
1264         }
1265
1266         return 0;
1267 }
1268
1269 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1270 {
1271         const struct of_device_id *of_id =
1272                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1273         struct sdhci_pltfm_host *pltfm_host;
1274         struct sdhci_host *host;
1275         int err;
1276         struct pltfm_imx_data *imx_data;
1277
1278         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1279                                 sizeof(*imx_data));
1280         if (IS_ERR(host))
1281                 return PTR_ERR(host);
1282
1283         pltfm_host = sdhci_priv(host);
1284
1285         imx_data = sdhci_pltfm_priv(pltfm_host);
1286
1287         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1288                                                   pdev->id_entry->driver_data;
1289
1290         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1291         if (IS_ERR(imx_data->clk_ipg)) {
1292                 err = PTR_ERR(imx_data->clk_ipg);
1293                 goto free_sdhci;
1294         }
1295
1296         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1297         if (IS_ERR(imx_data->clk_ahb)) {
1298                 err = PTR_ERR(imx_data->clk_ahb);
1299                 goto free_sdhci;
1300         }
1301
1302         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1303         if (IS_ERR(imx_data->clk_per)) {
1304                 err = PTR_ERR(imx_data->clk_per);
1305                 goto free_sdhci;
1306         }
1307
1308         pltfm_host->clk = imx_data->clk_per;
1309         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1310         err = clk_prepare_enable(imx_data->clk_per);
1311         if (err)
1312                 goto free_sdhci;
1313         err = clk_prepare_enable(imx_data->clk_ipg);
1314         if (err)
1315                 goto disable_per_clk;
1316         err = clk_prepare_enable(imx_data->clk_ahb);
1317         if (err)
1318                 goto disable_ipg_clk;
1319
1320         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1321         if (IS_ERR(imx_data->pinctrl)) {
1322                 err = PTR_ERR(imx_data->pinctrl);
1323                 goto disable_ahb_clk;
1324         }
1325
1326         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1327                                                 PINCTRL_STATE_DEFAULT);
1328         if (IS_ERR(imx_data->pins_default))
1329                 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1330
1331         if (esdhc_is_usdhc(imx_data)) {
1332                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1333                 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1334                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1335                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1336
1337                 /* clear tuning bits in case ROM has set it already */
1338                 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1339                 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1340                 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1341         }
1342
1343         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1344                 sdhci_esdhc_ops.platform_execute_tuning =
1345                                         esdhc_executing_tuning;
1346
1347         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1348                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1349
1350         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1351                 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1352
1353         if (of_id)
1354                 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1355         else
1356                 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1357         if (err)
1358                 goto disable_ahb_clk;
1359
1360         sdhci_esdhc_imx_hwinit(host);
1361
1362         err = sdhci_add_host(host);
1363         if (err)
1364                 goto disable_ahb_clk;
1365
1366         pm_runtime_set_active(&pdev->dev);
1367         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1368         pm_runtime_use_autosuspend(&pdev->dev);
1369         pm_suspend_ignore_children(&pdev->dev, 1);
1370         pm_runtime_enable(&pdev->dev);
1371
1372         return 0;
1373
1374 disable_ahb_clk:
1375         clk_disable_unprepare(imx_data->clk_ahb);
1376 disable_ipg_clk:
1377         clk_disable_unprepare(imx_data->clk_ipg);
1378 disable_per_clk:
1379         clk_disable_unprepare(imx_data->clk_per);
1380 free_sdhci:
1381         sdhci_pltfm_free(pdev);
1382         return err;
1383 }
1384
1385 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1386 {
1387         struct sdhci_host *host = platform_get_drvdata(pdev);
1388         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1389         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1390         int dead;
1391
1392         pm_runtime_get_sync(&pdev->dev);
1393         dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1394         pm_runtime_disable(&pdev->dev);
1395         pm_runtime_put_noidle(&pdev->dev);
1396
1397         sdhci_remove_host(host, dead);
1398
1399         clk_disable_unprepare(imx_data->clk_per);
1400         clk_disable_unprepare(imx_data->clk_ipg);
1401         clk_disable_unprepare(imx_data->clk_ahb);
1402
1403         sdhci_pltfm_free(pdev);
1404
1405         return 0;
1406 }
1407
1408 #ifdef CONFIG_PM_SLEEP
1409 static int sdhci_esdhc_suspend(struct device *dev)
1410 {
1411         struct sdhci_host *host = dev_get_drvdata(dev);
1412
1413         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1414                 mmc_retune_needed(host->mmc);
1415
1416         return sdhci_suspend_host(host);
1417 }
1418
1419 static int sdhci_esdhc_resume(struct device *dev)
1420 {
1421         struct sdhci_host *host = dev_get_drvdata(dev);
1422
1423         /* re-initialize hw state in case it's lost in low power mode */
1424         sdhci_esdhc_imx_hwinit(host);
1425
1426         return sdhci_resume_host(host);
1427 }
1428 #endif
1429
1430 #ifdef CONFIG_PM
1431 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1432 {
1433         struct sdhci_host *host = dev_get_drvdata(dev);
1434         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1435         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1436         int ret;
1437
1438         ret = sdhci_runtime_suspend_host(host);
1439         if (ret)
1440                 return ret;
1441
1442         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1443                 mmc_retune_needed(host->mmc);
1444
1445         if (!sdhci_sdio_irq_enabled(host)) {
1446                 imx_data->actual_clock = host->mmc->actual_clock;
1447                 esdhc_pltfm_set_clock(host, 0);
1448                 clk_disable_unprepare(imx_data->clk_per);
1449                 clk_disable_unprepare(imx_data->clk_ipg);
1450         }
1451         clk_disable_unprepare(imx_data->clk_ahb);
1452
1453         return ret;
1454 }
1455
1456 static int sdhci_esdhc_runtime_resume(struct device *dev)
1457 {
1458         struct sdhci_host *host = dev_get_drvdata(dev);
1459         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1460         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1461         int err;
1462
1463         err = clk_prepare_enable(imx_data->clk_ahb);
1464         if (err)
1465                 return err;
1466
1467         if (!sdhci_sdio_irq_enabled(host)) {
1468                 err = clk_prepare_enable(imx_data->clk_per);
1469                 if (err)
1470                         goto disable_ahb_clk;
1471                 err = clk_prepare_enable(imx_data->clk_ipg);
1472                 if (err)
1473                         goto disable_per_clk;
1474                 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1475         }
1476
1477         err = sdhci_runtime_resume_host(host);
1478         if (err)
1479                 goto disable_ipg_clk;
1480
1481         return 0;
1482
1483 disable_ipg_clk:
1484         if (!sdhci_sdio_irq_enabled(host))
1485                 clk_disable_unprepare(imx_data->clk_ipg);
1486 disable_per_clk:
1487         if (!sdhci_sdio_irq_enabled(host))
1488                 clk_disable_unprepare(imx_data->clk_per);
1489 disable_ahb_clk:
1490         clk_disable_unprepare(imx_data->clk_ahb);
1491         return err;
1492 }
1493 #endif
1494
1495 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1496         SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1497         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1498                                 sdhci_esdhc_runtime_resume, NULL)
1499 };
1500
1501 static struct platform_driver sdhci_esdhc_imx_driver = {
1502         .driver         = {
1503                 .name   = "sdhci-esdhc-imx",
1504                 .of_match_table = imx_esdhc_dt_ids,
1505                 .pm     = &sdhci_esdhc_pmops,
1506         },
1507         .id_table       = imx_esdhc_devtype,
1508         .probe          = sdhci_esdhc_imx_probe,
1509         .remove         = sdhci_esdhc_imx_remove,
1510 };
1511
1512 module_platform_driver(sdhci_esdhc_imx_driver);
1513
1514 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1515 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1516 MODULE_LICENSE("GPL v2");