2 * Copyright (C) 2014 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 * iProc SDHCI platform driver
18 #include <linux/delay.h>
19 #include <linux/module.h>
20 #include <linux/mmc/host.h>
22 #include <linux/of_device.h>
23 #include "sdhci-pltfm.h"
25 struct sdhci_iproc_data {
26 const struct sdhci_pltfm_data *pdata;
31 struct sdhci_iproc_host {
32 const struct sdhci_iproc_data *data;
39 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
41 static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
43 u32 val = readl(host->ioaddr + reg);
45 pr_debug("%s: readl [0x%02x] 0x%08x\n",
46 mmc_hostname(host->mmc), reg, val);
50 static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
52 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
53 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
57 if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
58 /* Get the saved transfer mode */
59 val = iproc_host->shadow_cmd;
60 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
61 iproc_host->is_blk_shadowed) {
62 /* Get the saved block info */
63 val = iproc_host->shadow_blk;
65 val = sdhci_iproc_readl(host, (reg & ~3));
67 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
71 static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
73 u32 val = sdhci_iproc_readl(host, (reg & ~3));
74 u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
78 static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
80 pr_debug("%s: writel [0x%02x] 0x%08x\n",
81 mmc_hostname(host->mmc), reg, val);
83 writel(val, host->ioaddr + reg);
85 if (host->clock <= 400000) {
86 /* Round up to micro-second four SD clock delay */
88 udelay((4 * 1000000 + host->clock - 1) / host->clock);
95 * The Arasan has a bugette whereby it may lose the content of successive
96 * writes to the same register that are within two SD-card clock cycles of
97 * each other (a clock domain crossing problem). The data
98 * register does not have this problem, which is just as well - otherwise we'd
99 * have to nobble the DMA engine too.
101 * This wouldn't be a problem with the code except that we can only write the
102 * controller with 32-bit writes. So two different 16-bit registers are
103 * written back to back creates the problem.
105 * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
106 * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
107 * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
108 * the work around can be further optimized. We can keep shadow values of
109 * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
110 * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
111 * by the TRANSFER+COMMAND in another 32-bit write.
113 static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
115 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
116 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
117 u32 word_shift = REG_OFFSET_IN_BITS(reg);
118 u32 mask = 0xffff << word_shift;
121 if (reg == SDHCI_COMMAND) {
122 /* Write the block now as we are issuing a command */
123 if (iproc_host->is_blk_shadowed) {
124 sdhci_iproc_writel(host, iproc_host->shadow_blk,
126 iproc_host->is_blk_shadowed = false;
128 oldval = iproc_host->shadow_cmd;
129 iproc_host->is_cmd_shadowed = false;
130 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
131 iproc_host->is_blk_shadowed) {
132 /* Block size and count are stored in shadow reg */
133 oldval = iproc_host->shadow_blk;
135 /* Read reg, all other registers are not shadowed */
136 oldval = sdhci_iproc_readl(host, (reg & ~3));
138 newval = (oldval & ~mask) | (val << word_shift);
140 if (reg == SDHCI_TRANSFER_MODE) {
141 /* Save the transfer mode until the command is issued */
142 iproc_host->shadow_cmd = newval;
143 iproc_host->is_cmd_shadowed = true;
144 } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
145 /* Save the block info until the command is issued */
146 iproc_host->shadow_blk = newval;
147 iproc_host->is_blk_shadowed = true;
149 /* Command or other regular 32-bit write */
150 sdhci_iproc_writel(host, newval, reg & ~3);
154 static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
156 u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
157 u32 byte_shift = REG_OFFSET_IN_BITS(reg);
158 u32 mask = 0xff << byte_shift;
159 u32 newval = (oldval & ~mask) | (val << byte_shift);
161 sdhci_iproc_writel(host, newval, reg & ~3);
164 static const struct sdhci_ops sdhci_iproc_ops = {
165 .read_l = sdhci_iproc_readl,
166 .read_w = sdhci_iproc_readw,
167 .read_b = sdhci_iproc_readb,
168 .write_l = sdhci_iproc_writel,
169 .write_w = sdhci_iproc_writew,
170 .write_b = sdhci_iproc_writeb,
171 .set_clock = sdhci_set_clock,
172 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
173 .set_bus_width = sdhci_set_bus_width,
174 .reset = sdhci_reset,
175 .set_uhs_signaling = sdhci_set_uhs_signaling,
178 static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
179 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
180 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
181 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
182 .ops = &sdhci_iproc_ops,
185 static const struct sdhci_iproc_data iproc_data = {
186 .pdata = &sdhci_iproc_pltfm_data,
191 static const struct of_device_id sdhci_iproc_of_match[] = {
192 { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_data },
195 MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
197 static int sdhci_iproc_probe(struct platform_device *pdev)
199 const struct of_device_id *match;
200 const struct sdhci_iproc_data *iproc_data;
201 struct sdhci_host *host;
202 struct sdhci_iproc_host *iproc_host;
203 struct sdhci_pltfm_host *pltfm_host;
206 match = of_match_device(sdhci_iproc_of_match, &pdev->dev);
209 iproc_data = match->data;
211 host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
213 return PTR_ERR(host);
215 pltfm_host = sdhci_priv(host);
216 iproc_host = sdhci_pltfm_priv(pltfm_host);
218 iproc_host->data = iproc_data;
220 ret = mmc_of_parse(host->mmc);
224 sdhci_get_of_property(pdev);
226 /* Enable EMMC 1/8V DDR capable */
227 host->mmc->caps |= MMC_CAP_1_8V_DDR;
229 pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
230 if (IS_ERR(pltfm_host->clk)) {
231 ret = PTR_ERR(pltfm_host->clk);
235 if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
236 host->caps = iproc_host->data->caps;
237 host->caps1 = iproc_host->data->caps1;
240 return sdhci_add_host(host);
243 sdhci_pltfm_free(pdev);
247 static int sdhci_iproc_remove(struct platform_device *pdev)
249 return sdhci_pltfm_unregister(pdev);
252 static struct platform_driver sdhci_iproc_driver = {
254 .name = "sdhci-iproc",
255 .of_match_table = sdhci_iproc_of_match,
256 .pm = SDHCI_PLTFM_PMOPS,
258 .probe = sdhci_iproc_probe,
259 .remove = sdhci_iproc_remove,
261 module_platform_driver(sdhci_iproc_driver);
263 MODULE_AUTHOR("Broadcom");
264 MODULE_DESCRIPTION("IPROC SDHCI driver");
265 MODULE_LICENSE("GPL v2");