2 * Arasan Secure Digital Host Controller Interface.
3 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (c) 2012 Wind River Systems, Inc.
5 * Copyright (C) 2013 Pengutronix e.K.
6 * Copyright (C) 2013 Xilinx Inc.
8 * Based on sdhci-of-esdhc.c
10 * Copyright (c) 2007 Freescale Semiconductor, Inc.
11 * Copyright (c) 2009 MontaVista Software, Inc.
13 * Authors: Xiaobo Xie <X.Xie@freescale.com>
14 * Anton Vorontsov <avorontsov@ru.mvista.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or (at
19 * your option) any later version.
22 #include <linux/clk-provider.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/phy/phy.h>
27 #include <linux/regmap.h>
28 #include "sdhci-pltfm.h"
31 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78
33 #define VENDOR_ENHANCED_STROBE BIT(0)
35 #define PHY_CLK_TOO_SLOW_HZ 400000
38 * On some SoCs the syscon area has a feature where the upper 16-bits of
39 * each 32-bit register act as a write mask for the lower 16-bits. This allows
40 * atomic updates of the register without locking. This macro is used on SoCs
41 * that have that feature.
43 #define HIWORD_UPDATE(val, mask, shift) \
44 ((val) << (shift) | (mask) << ((shift) + 16))
47 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
49 * @reg: Offset within the syscon of the register containing this field
50 * @width: Number of bits for this field
51 * @shift: Bit offset within @reg of this field (or -1 if not avail)
53 struct sdhci_arasan_soc_ctl_field {
60 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
62 * It's up to the licensee of the Arsan IP block to make these available
63 * somewhere if needed. Presumably these will be scattered somewhere that's
64 * accessible via the syscon API.
66 * @baseclkfreq: Where to find corecfg_baseclkfreq
67 * @clockmultiplier: Where to find corecfg_clockmultiplier
68 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
70 struct sdhci_arasan_soc_ctl_map {
71 struct sdhci_arasan_soc_ctl_field baseclkfreq;
72 struct sdhci_arasan_soc_ctl_field clockmultiplier;
77 * struct sdhci_arasan_data
78 * @host: Pointer to the main SDHCI host structure.
79 * @clk_ahb: Pointer to the AHB clock
80 * @phy: Pointer to the generic phy
81 * @is_phy_on: True if the PHY is on; false if not.
82 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
83 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
84 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
85 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
87 struct sdhci_arasan_data {
88 struct sdhci_host *host;
93 struct clk_hw sdcardclk_hw;
94 struct clk *sdcardclk;
96 struct regmap *soc_ctl_base;
97 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
98 unsigned int quirks; /* Arasan deviations from spec */
100 /* Controller does not have CD wired and will not function normally without */
101 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
104 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
105 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
106 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
107 .hiword_update = true,
111 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
113 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
114 * Note that if a field is specified as not available (shift < 0) then
115 * this function will silently return an error code. It will be noisy
116 * and print errors for any other (unexpected) errors.
118 * @host: The sdhci_host
119 * @fld: The field to write to
120 * @val: The value to write
122 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
123 const struct sdhci_arasan_soc_ctl_field *fld,
126 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
127 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
128 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
130 u16 width = fld->width;
131 s16 shift = fld->shift;
135 * Silently return errors for shift < 0 so caller doesn't have
136 * to check for fields which are optional. For fields that
137 * are required then caller needs to do something special
143 if (sdhci_arasan->soc_ctl_map->hiword_update)
144 ret = regmap_write(soc_ctl_base, reg,
145 HIWORD_UPDATE(val, GENMASK(width, 0),
148 ret = regmap_update_bits(soc_ctl_base, reg,
149 GENMASK(shift + width, shift),
152 /* Yell about (unexpected) regmap errors */
154 pr_warn("%s: Regmap write fail: %d\n",
155 mmc_hostname(host->mmc), ret);
160 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
162 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
163 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
164 bool ctrl_phy = false;
166 if (!IS_ERR(sdhci_arasan->phy)) {
167 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
169 * If PHY off, set clock to max speed and power PHY on.
171 * Although PHY docs apparently suggest power cycling
172 * when changing the clock the PHY doesn't like to be
173 * powered on while at low speeds like those used in ID
174 * mode. Even worse is powering the PHY on while the
177 * To workaround the PHY limitations, the best we can
178 * do is to power it on at a faster speed and then slam
179 * through low speeds without power cycling.
181 sdhci_set_clock(host, host->max_clk);
182 if (phy_power_on(sdhci_arasan->phy)) {
183 pr_err("%s: Cannot power on phy.\n",
184 mmc_hostname(host->mmc));
188 sdhci_arasan->is_phy_on = true;
191 * We'll now fall through to the below case with
192 * ctrl_phy = false (so we won't turn off/on). The
193 * sdhci_set_clock() will set the real clock.
195 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
197 * At higher clock speeds the PHY is fine being power
198 * cycled and docs say you _should_ power cycle when
199 * changing clock speeds.
205 if (ctrl_phy && sdhci_arasan->is_phy_on) {
206 phy_power_off(sdhci_arasan->phy);
207 sdhci_arasan->is_phy_on = false;
210 sdhci_set_clock(host, clock);
213 if (phy_power_on(sdhci_arasan->phy)) {
214 pr_err("%s: Cannot power on phy.\n",
215 mmc_hostname(host->mmc));
219 sdhci_arasan->is_phy_on = true;
223 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
227 struct sdhci_host *host = mmc_priv(mmc);
229 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
230 if (ios->enhanced_strobe)
231 vendor |= VENDOR_ENHANCED_STROBE;
233 vendor &= ~VENDOR_ENHANCED_STROBE;
235 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
238 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
241 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
242 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
244 sdhci_reset(host, mask);
246 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
247 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
248 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
249 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
253 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
256 switch (ios->signal_voltage) {
257 case MMC_SIGNAL_VOLTAGE_180:
259 * Plese don't switch to 1V8 as arasan,5.1 doesn't
260 * actually refer to this setting to indicate the
261 * signal voltage and the state machine will be broken
262 * actually if we force to enable 1V8. That's something
263 * like broken quirk but we could work around here.
266 case MMC_SIGNAL_VOLTAGE_330:
267 case MMC_SIGNAL_VOLTAGE_120:
268 /* We don't support 3V3 and 1V2 */
275 static const struct sdhci_ops sdhci_arasan_ops = {
276 .set_clock = sdhci_arasan_set_clock,
277 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
278 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
279 .set_bus_width = sdhci_set_bus_width,
280 .reset = sdhci_arasan_reset,
281 .set_uhs_signaling = sdhci_set_uhs_signaling,
284 static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
285 .ops = &sdhci_arasan_ops,
286 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
287 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
288 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
291 #ifdef CONFIG_PM_SLEEP
293 * sdhci_arasan_suspend - Suspend method for the driver
294 * @dev: Address of the device structure
295 * Returns 0 on success and error value on error
297 * Put the device in a low power state.
299 static int sdhci_arasan_suspend(struct device *dev)
301 struct platform_device *pdev = to_platform_device(dev);
302 struct sdhci_host *host = platform_get_drvdata(pdev);
303 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
304 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
307 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
308 mmc_retune_needed(host->mmc);
310 ret = sdhci_suspend_host(host);
314 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
315 ret = phy_power_off(sdhci_arasan->phy);
317 dev_err(dev, "Cannot power off phy.\n");
318 if (sdhci_resume_host(host))
319 dev_err(dev, "Cannot resume host.\n");
323 sdhci_arasan->is_phy_on = false;
326 clk_disable(pltfm_host->clk);
327 clk_disable(sdhci_arasan->clk_ahb);
333 * sdhci_arasan_resume - Resume method for the driver
334 * @dev: Address of the device structure
335 * Returns 0 on success and error value on error
337 * Resume operation after suspend
339 static int sdhci_arasan_resume(struct device *dev)
341 struct platform_device *pdev = to_platform_device(dev);
342 struct sdhci_host *host = platform_get_drvdata(pdev);
343 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
344 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
347 ret = clk_enable(sdhci_arasan->clk_ahb);
349 dev_err(dev, "Cannot enable AHB clock.\n");
353 ret = clk_enable(pltfm_host->clk);
355 dev_err(dev, "Cannot enable SD clock.\n");
359 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
360 ret = phy_power_on(sdhci_arasan->phy);
362 dev_err(dev, "Cannot power on phy.\n");
365 sdhci_arasan->is_phy_on = true;
368 return sdhci_resume_host(host);
370 #endif /* ! CONFIG_PM_SLEEP */
372 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
373 sdhci_arasan_resume);
375 static const struct of_device_id sdhci_arasan_of_match[] = {
376 /* SoC-specific compatible strings w/ soc_ctl_map */
378 .compatible = "rockchip,rk3399-sdhci-5.1",
379 .data = &rk3399_soc_ctl_map,
382 /* Generic compatible below here */
383 { .compatible = "arasan,sdhci-8.9a" },
384 { .compatible = "arasan,sdhci-5.1" },
385 { .compatible = "arasan,sdhci-4.9a" },
389 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
392 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
394 * Return the current actual rate of the SD card clock. This can be used
395 * to communicate with out PHY.
397 * @hw: Pointer to the hardware clock structure.
398 * @parent_rate The parent rate (should be rate of clk_xin).
399 * Returns the card clock rate.
401 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
402 unsigned long parent_rate)
405 struct sdhci_arasan_data *sdhci_arasan =
406 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
407 struct sdhci_host *host = sdhci_arasan->host;
409 return host->mmc->actual_clock;
412 static const struct clk_ops arasan_sdcardclk_ops = {
413 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
417 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
419 * The corecfg_clockmultiplier is supposed to contain clock multiplier
420 * value of programmable clock generator.
423 * - Many existing devices don't seem to do this and work fine. To keep
424 * compatibility for old hardware where the device tree doesn't provide a
425 * register map, this function is a noop if a soc_ctl_map hasn't been provided
427 * - The value of corecfg_clockmultiplier should sync with that of corresponding
428 * value reading from sdhci_capability_register. So this function is called
429 * once at probe time and never called again.
431 * @host: The sdhci_host
433 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
436 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
437 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
438 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
439 sdhci_arasan->soc_ctl_map;
441 /* Having a map is optional */
445 /* If we have a map, we expect to have a syscon */
446 if (!sdhci_arasan->soc_ctl_base) {
447 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
448 mmc_hostname(host->mmc));
452 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
456 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
458 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
459 * function can be used to make that happen.
462 * - Many existing devices don't seem to do this and work fine. To keep
463 * compatibility for old hardware where the device tree doesn't provide a
464 * register map, this function is a noop if a soc_ctl_map hasn't been provided
466 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
467 * to achieve lower clock rates. That means that this function is called once
468 * at probe time and never called again.
470 * @host: The sdhci_host
472 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
474 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
475 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
476 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
477 sdhci_arasan->soc_ctl_map;
478 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
480 /* Having a map is optional */
484 /* If we have a map, we expect to have a syscon */
485 if (!sdhci_arasan->soc_ctl_base) {
486 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
487 mmc_hostname(host->mmc));
491 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
495 * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
497 * Some PHY devices need to know what the actual card clock is. In order for
498 * them to find out, we'll provide a clock through the common clock framework
501 * Note: without seriously re-architecting SDHCI's clock code and testing on
502 * all platforms, there's no way to create a totally beautiful clock here
503 * with all clock ops implemented. Instead, we'll just create a clock that can
504 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
505 * framework that we're doing things behind its back. This should be sufficient
506 * to create nice clean device tree bindings and later (if needed) we can try
507 * re-architecting SDHCI if we see some benefit to it.
509 * @sdhci_arasan: Our private data structure.
510 * @clk_xin: Pointer to the functional clock
511 * @dev: Pointer to our struct device.
512 * Returns 0 on success and error value on error
514 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
518 struct device_node *np = dev->of_node;
519 struct clk_init_data sdcardclk_init;
520 const char *parent_clk_name;
523 /* Providing a clock to the PHY is optional; no error if missing */
524 if (!of_find_property(np, "#clock-cells", NULL))
527 ret = of_property_read_string_index(np, "clock-output-names", 0,
528 &sdcardclk_init.name);
530 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
534 parent_clk_name = __clk_get_name(clk_xin);
535 sdcardclk_init.parent_names = &parent_clk_name;
536 sdcardclk_init.num_parents = 1;
537 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
538 sdcardclk_init.ops = &arasan_sdcardclk_ops;
540 sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
541 sdhci_arasan->sdcardclk =
542 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
543 sdhci_arasan->sdcardclk_hw.init = NULL;
545 ret = of_clk_add_provider(np, of_clk_src_simple_get,
546 sdhci_arasan->sdcardclk);
548 dev_err(dev, "Failed to add clock provider\n");
554 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
556 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
559 * @dev: Pointer to our struct device.
561 static void sdhci_arasan_unregister_sdclk(struct device *dev)
563 struct device_node *np = dev->of_node;
565 if (!of_find_property(np, "#clock-cells", NULL))
568 of_clk_del_provider(dev->of_node);
571 static int sdhci_arasan_probe(struct platform_device *pdev)
574 const struct of_device_id *match;
575 struct device_node *node;
577 struct sdhci_host *host;
578 struct sdhci_pltfm_host *pltfm_host;
579 struct sdhci_arasan_data *sdhci_arasan;
580 struct device_node *np = pdev->dev.of_node;
582 host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata,
583 sizeof(*sdhci_arasan));
585 return PTR_ERR(host);
587 pltfm_host = sdhci_priv(host);
588 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
589 sdhci_arasan->host = host;
591 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
592 sdhci_arasan->soc_ctl_map = match->data;
594 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
596 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
599 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
600 ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
601 if (ret != -EPROBE_DEFER)
602 dev_err(&pdev->dev, "Can't get syscon: %d\n",
608 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
609 if (IS_ERR(sdhci_arasan->clk_ahb)) {
610 dev_err(&pdev->dev, "clk_ahb clock not found.\n");
611 ret = PTR_ERR(sdhci_arasan->clk_ahb);
615 clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
616 if (IS_ERR(clk_xin)) {
617 dev_err(&pdev->dev, "clk_xin clock not found.\n");
618 ret = PTR_ERR(clk_xin);
622 ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
624 dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
628 ret = clk_prepare_enable(clk_xin);
630 dev_err(&pdev->dev, "Unable to enable SD clock.\n");
634 sdhci_get_of_property(pdev);
636 if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
637 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
639 pltfm_host->clk = clk_xin;
641 if (of_device_is_compatible(pdev->dev.of_node,
642 "rockchip,rk3399-sdhci-5.1"))
643 sdhci_arasan_update_clockmultiplier(host, 0x0);
645 sdhci_arasan_update_baseclkfreq(host);
647 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
649 goto clk_disable_all;
651 ret = mmc_of_parse(host->mmc);
653 if (ret != -EPROBE_DEFER)
654 dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);
658 sdhci_arasan->phy = ERR_PTR(-ENODEV);
659 if (of_device_is_compatible(pdev->dev.of_node,
660 "arasan,sdhci-5.1")) {
661 sdhci_arasan->phy = devm_phy_get(&pdev->dev,
663 if (IS_ERR(sdhci_arasan->phy)) {
664 ret = PTR_ERR(sdhci_arasan->phy);
665 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
669 ret = phy_init(sdhci_arasan->phy);
671 dev_err(&pdev->dev, "phy_init err.\n");
675 host->mmc_host_ops.hs400_enhanced_strobe =
676 sdhci_arasan_hs400_enhanced_strobe;
677 host->mmc_host_ops.start_signal_voltage_switch =
678 sdhci_arasan_voltage_switch;
681 ret = sdhci_add_host(host);
688 if (!IS_ERR(sdhci_arasan->phy))
689 phy_exit(sdhci_arasan->phy);
691 sdhci_arasan_unregister_sdclk(&pdev->dev);
693 clk_disable_unprepare(clk_xin);
695 clk_disable_unprepare(sdhci_arasan->clk_ahb);
697 sdhci_pltfm_free(pdev);
701 static int sdhci_arasan_remove(struct platform_device *pdev)
704 struct sdhci_host *host = platform_get_drvdata(pdev);
705 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
706 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
707 struct clk *clk_ahb = sdhci_arasan->clk_ahb;
709 if (!IS_ERR(sdhci_arasan->phy)) {
710 if (sdhci_arasan->is_phy_on)
711 phy_power_off(sdhci_arasan->phy);
712 phy_exit(sdhci_arasan->phy);
715 sdhci_arasan_unregister_sdclk(&pdev->dev);
717 ret = sdhci_pltfm_unregister(pdev);
719 clk_disable_unprepare(clk_ahb);
724 static struct platform_driver sdhci_arasan_driver = {
726 .name = "sdhci-arasan",
727 .of_match_table = sdhci_arasan_of_match,
728 .pm = &sdhci_arasan_dev_pm_ops,
730 .probe = sdhci_arasan_probe,
731 .remove = sdhci_arasan_remove,
734 module_platform_driver(sdhci_arasan_driver);
736 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
737 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
738 MODULE_LICENSE("GPL");