2 * Arasan Secure Digital Host Controller Interface.
3 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (c) 2012 Wind River Systems, Inc.
5 * Copyright (C) 2013 Pengutronix e.K.
6 * Copyright (C) 2013 Xilinx Inc.
8 * Based on sdhci-of-esdhc.c
10 * Copyright (c) 2007 Freescale Semiconductor, Inc.
11 * Copyright (c) 2009 MontaVista Software, Inc.
13 * Authors: Xiaobo Xie <X.Xie@freescale.com>
14 * Anton Vorontsov <avorontsov@ru.mvista.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or (at
19 * your option) any later version.
22 #include <linux/clk-provider.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/phy/phy.h>
27 #include <linux/regmap.h>
31 #include "sdhci-pltfm.h"
33 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78
34 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
35 #define VENDOR_ENHANCED_STROBE BIT(0)
37 #define PHY_CLK_TOO_SLOW_HZ 400000
40 * On some SoCs the syscon area has a feature where the upper 16-bits of
41 * each 32-bit register act as a write mask for the lower 16-bits. This allows
42 * atomic updates of the register without locking. This macro is used on SoCs
43 * that have that feature.
45 #define HIWORD_UPDATE(val, mask, shift) \
46 ((val) << (shift) | (mask) << ((shift) + 16))
49 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
51 * @reg: Offset within the syscon of the register containing this field
52 * @width: Number of bits for this field
53 * @shift: Bit offset within @reg of this field (or -1 if not avail)
55 struct sdhci_arasan_soc_ctl_field {
62 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
64 * It's up to the licensee of the Arsan IP block to make these available
65 * somewhere if needed. Presumably these will be scattered somewhere that's
66 * accessible via the syscon API.
68 * @baseclkfreq: Where to find corecfg_baseclkfreq
69 * @clockmultiplier: Where to find corecfg_clockmultiplier
70 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
72 struct sdhci_arasan_soc_ctl_map {
73 struct sdhci_arasan_soc_ctl_field baseclkfreq;
74 struct sdhci_arasan_soc_ctl_field clockmultiplier;
79 * struct sdhci_arasan_data
80 * @host: Pointer to the main SDHCI host structure.
81 * @clk_ahb: Pointer to the AHB clock
82 * @phy: Pointer to the generic phy
83 * @is_phy_on: True if the PHY is on; false if not.
84 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
85 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
86 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
87 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
89 struct sdhci_arasan_data {
90 struct sdhci_host *host;
96 struct clk_hw sdcardclk_hw;
97 struct clk *sdcardclk;
99 struct regmap *soc_ctl_base;
100 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
101 unsigned int quirks; /* Arasan deviations from spec */
103 /* Controller does not have CD wired and will not function normally without */
104 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
105 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
106 * internal clock even when the clock isn't stable */
107 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
110 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
111 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
112 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
113 .hiword_update = true,
117 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
119 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
120 * Note that if a field is specified as not available (shift < 0) then
121 * this function will silently return an error code. It will be noisy
122 * and print errors for any other (unexpected) errors.
124 * @host: The sdhci_host
125 * @fld: The field to write to
126 * @val: The value to write
128 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
129 const struct sdhci_arasan_soc_ctl_field *fld,
132 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
133 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
134 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
136 u16 width = fld->width;
137 s16 shift = fld->shift;
141 * Silently return errors for shift < 0 so caller doesn't have
142 * to check for fields which are optional. For fields that
143 * are required then caller needs to do something special
149 if (sdhci_arasan->soc_ctl_map->hiword_update)
150 ret = regmap_write(soc_ctl_base, reg,
151 HIWORD_UPDATE(val, GENMASK(width, 0),
154 ret = regmap_update_bits(soc_ctl_base, reg,
155 GENMASK(shift + width, shift),
158 /* Yell about (unexpected) regmap errors */
160 pr_warn("%s: Regmap write fail: %d\n",
161 mmc_hostname(host->mmc), ret);
166 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
169 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
170 bool ctrl_phy = false;
172 if (!IS_ERR(sdhci_arasan->phy)) {
173 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
175 * If PHY off, set clock to max speed and power PHY on.
177 * Although PHY docs apparently suggest power cycling
178 * when changing the clock the PHY doesn't like to be
179 * powered on while at low speeds like those used in ID
180 * mode. Even worse is powering the PHY on while the
183 * To workaround the PHY limitations, the best we can
184 * do is to power it on at a faster speed and then slam
185 * through low speeds without power cycling.
187 sdhci_set_clock(host, host->max_clk);
188 if (phy_power_on(sdhci_arasan->phy)) {
189 pr_err("%s: Cannot power on phy.\n",
190 mmc_hostname(host->mmc));
194 sdhci_arasan->is_phy_on = true;
197 * We'll now fall through to the below case with
198 * ctrl_phy = false (so we won't turn off/on). The
199 * sdhci_set_clock() will set the real clock.
201 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
203 * At higher clock speeds the PHY is fine being power
204 * cycled and docs say you _should_ power cycle when
205 * changing clock speeds.
211 if (ctrl_phy && sdhci_arasan->is_phy_on) {
212 phy_power_off(sdhci_arasan->phy);
213 sdhci_arasan->is_phy_on = false;
216 sdhci_set_clock(host, clock);
218 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
220 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
221 * after enabling the clock even though the clock is not
222 * stable. Trying to use a clock without waiting here results
223 * in EILSEQ while detecting some older/slower cards. The
224 * chosen delay is the maximum delay from sdhci_set_clock.
229 if (phy_power_on(sdhci_arasan->phy)) {
230 pr_err("%s: Cannot power on phy.\n",
231 mmc_hostname(host->mmc));
235 sdhci_arasan->is_phy_on = true;
239 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
243 struct sdhci_host *host = mmc_priv(mmc);
245 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
246 if (ios->enhanced_strobe)
247 vendor |= VENDOR_ENHANCED_STROBE;
249 vendor &= ~VENDOR_ENHANCED_STROBE;
251 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
254 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
257 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
258 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
260 sdhci_reset(host, mask);
262 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
263 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
264 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
265 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
269 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
272 switch (ios->signal_voltage) {
273 case MMC_SIGNAL_VOLTAGE_180:
275 * Plese don't switch to 1V8 as arasan,5.1 doesn't
276 * actually refer to this setting to indicate the
277 * signal voltage and the state machine will be broken
278 * actually if we force to enable 1V8. That's something
279 * like broken quirk but we could work around here.
282 case MMC_SIGNAL_VOLTAGE_330:
283 case MMC_SIGNAL_VOLTAGE_120:
284 /* We don't support 3V3 and 1V2 */
291 static void sdhci_arasan_set_power(struct sdhci_host *host, unsigned char mode,
294 if (!IS_ERR(host->mmc->supply.vmmc)) {
295 struct mmc_host *mmc = host->mmc;
297 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
299 sdhci_set_power_noreg(host, mode, vdd);
302 static const struct sdhci_ops sdhci_arasan_ops = {
303 .set_clock = sdhci_arasan_set_clock,
304 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
305 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
306 .set_bus_width = sdhci_set_bus_width,
307 .reset = sdhci_arasan_reset,
308 .set_uhs_signaling = sdhci_set_uhs_signaling,
309 .set_power = sdhci_arasan_set_power,
312 static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
313 .ops = &sdhci_arasan_ops,
314 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
315 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
316 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
317 SDHCI_QUIRK2_STOP_WITH_TC,
320 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
325 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
328 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
333 static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
335 sdhci_dumpregs(mmc_priv(mmc));
338 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
340 struct sdhci_host *host = mmc_priv(mmc);
343 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
344 while (reg & SDHCI_DATA_AVAILABLE) {
345 sdhci_readl(host, SDHCI_BUFFER);
346 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
349 sdhci_cqe_enable(mmc);
352 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
353 .enable = sdhci_arasan_cqe_enable,
354 .disable = sdhci_cqe_disable,
355 .dumpregs = sdhci_arasan_dumpregs,
358 static const struct sdhci_ops sdhci_arasan_cqe_ops = {
359 .set_clock = sdhci_arasan_set_clock,
360 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
361 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
362 .set_bus_width = sdhci_set_bus_width,
363 .reset = sdhci_arasan_reset,
364 .set_uhs_signaling = sdhci_set_uhs_signaling,
365 .set_power = sdhci_arasan_set_power,
366 .irq = sdhci_arasan_cqhci_irq,
369 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
370 .ops = &sdhci_arasan_cqe_ops,
371 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
372 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
373 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
376 #ifdef CONFIG_PM_SLEEP
378 * sdhci_arasan_suspend - Suspend method for the driver
379 * @dev: Address of the device structure
380 * Returns 0 on success and error value on error
382 * Put the device in a low power state.
384 static int sdhci_arasan_suspend(struct device *dev)
386 struct sdhci_host *host = dev_get_drvdata(dev);
387 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
388 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
391 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
392 mmc_retune_needed(host->mmc);
394 if (sdhci_arasan->has_cqe) {
395 ret = cqhci_suspend(host->mmc);
400 ret = sdhci_suspend_host(host);
404 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
405 ret = phy_power_off(sdhci_arasan->phy);
407 dev_err(dev, "Cannot power off phy.\n");
408 if (sdhci_resume_host(host))
409 dev_err(dev, "Cannot resume host.\n");
413 sdhci_arasan->is_phy_on = false;
416 clk_disable(pltfm_host->clk);
417 clk_disable(sdhci_arasan->clk_ahb);
423 * sdhci_arasan_resume - Resume method for the driver
424 * @dev: Address of the device structure
425 * Returns 0 on success and error value on error
427 * Resume operation after suspend
429 static int sdhci_arasan_resume(struct device *dev)
431 struct sdhci_host *host = dev_get_drvdata(dev);
432 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
433 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
436 ret = clk_enable(sdhci_arasan->clk_ahb);
438 dev_err(dev, "Cannot enable AHB clock.\n");
442 ret = clk_enable(pltfm_host->clk);
444 dev_err(dev, "Cannot enable SD clock.\n");
448 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
449 ret = phy_power_on(sdhci_arasan->phy);
451 dev_err(dev, "Cannot power on phy.\n");
454 sdhci_arasan->is_phy_on = true;
457 ret = sdhci_resume_host(host);
459 dev_err(dev, "Cannot resume host.\n");
463 if (sdhci_arasan->has_cqe)
464 return cqhci_resume(host->mmc);
468 #endif /* ! CONFIG_PM_SLEEP */
470 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
471 sdhci_arasan_resume);
473 static const struct of_device_id sdhci_arasan_of_match[] = {
474 /* SoC-specific compatible strings w/ soc_ctl_map */
476 .compatible = "rockchip,rk3399-sdhci-5.1",
477 .data = &rk3399_soc_ctl_map,
480 /* Generic compatible below here */
481 { .compatible = "arasan,sdhci-8.9a" },
482 { .compatible = "arasan,sdhci-5.1" },
483 { .compatible = "arasan,sdhci-4.9a" },
487 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
490 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
492 * Return the current actual rate of the SD card clock. This can be used
493 * to communicate with out PHY.
495 * @hw: Pointer to the hardware clock structure.
496 * @parent_rate The parent rate (should be rate of clk_xin).
497 * Returns the card clock rate.
499 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
500 unsigned long parent_rate)
503 struct sdhci_arasan_data *sdhci_arasan =
504 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
505 struct sdhci_host *host = sdhci_arasan->host;
507 return host->mmc->actual_clock;
510 static const struct clk_ops arasan_sdcardclk_ops = {
511 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
515 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
517 * The corecfg_clockmultiplier is supposed to contain clock multiplier
518 * value of programmable clock generator.
521 * - Many existing devices don't seem to do this and work fine. To keep
522 * compatibility for old hardware where the device tree doesn't provide a
523 * register map, this function is a noop if a soc_ctl_map hasn't been provided
525 * - The value of corecfg_clockmultiplier should sync with that of corresponding
526 * value reading from sdhci_capability_register. So this function is called
527 * once at probe time and never called again.
529 * @host: The sdhci_host
531 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
534 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
535 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
536 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
537 sdhci_arasan->soc_ctl_map;
539 /* Having a map is optional */
543 /* If we have a map, we expect to have a syscon */
544 if (!sdhci_arasan->soc_ctl_base) {
545 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
546 mmc_hostname(host->mmc));
550 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
554 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
556 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
557 * function can be used to make that happen.
560 * - Many existing devices don't seem to do this and work fine. To keep
561 * compatibility for old hardware where the device tree doesn't provide a
562 * register map, this function is a noop if a soc_ctl_map hasn't been provided
564 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
565 * to achieve lower clock rates. That means that this function is called once
566 * at probe time and never called again.
568 * @host: The sdhci_host
570 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
572 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
573 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
574 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
575 sdhci_arasan->soc_ctl_map;
576 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
578 /* Having a map is optional */
582 /* If we have a map, we expect to have a syscon */
583 if (!sdhci_arasan->soc_ctl_base) {
584 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
585 mmc_hostname(host->mmc));
589 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
593 * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
595 * Some PHY devices need to know what the actual card clock is. In order for
596 * them to find out, we'll provide a clock through the common clock framework
599 * Note: without seriously re-architecting SDHCI's clock code and testing on
600 * all platforms, there's no way to create a totally beautiful clock here
601 * with all clock ops implemented. Instead, we'll just create a clock that can
602 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
603 * framework that we're doing things behind its back. This should be sufficient
604 * to create nice clean device tree bindings and later (if needed) we can try
605 * re-architecting SDHCI if we see some benefit to it.
607 * @sdhci_arasan: Our private data structure.
608 * @clk_xin: Pointer to the functional clock
609 * @dev: Pointer to our struct device.
610 * Returns 0 on success and error value on error
612 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
616 struct device_node *np = dev->of_node;
617 struct clk_init_data sdcardclk_init;
618 const char *parent_clk_name;
621 /* Providing a clock to the PHY is optional; no error if missing */
622 if (!of_find_property(np, "#clock-cells", NULL))
625 ret = of_property_read_string_index(np, "clock-output-names", 0,
626 &sdcardclk_init.name);
628 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
632 parent_clk_name = __clk_get_name(clk_xin);
633 sdcardclk_init.parent_names = &parent_clk_name;
634 sdcardclk_init.num_parents = 1;
635 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
636 sdcardclk_init.ops = &arasan_sdcardclk_ops;
638 sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
639 sdhci_arasan->sdcardclk =
640 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
641 sdhci_arasan->sdcardclk_hw.init = NULL;
643 ret = of_clk_add_provider(np, of_clk_src_simple_get,
644 sdhci_arasan->sdcardclk);
646 dev_err(dev, "Failed to add clock provider\n");
652 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
654 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
657 * @dev: Pointer to our struct device.
659 static void sdhci_arasan_unregister_sdclk(struct device *dev)
661 struct device_node *np = dev->of_node;
663 if (!of_find_property(np, "#clock-cells", NULL))
666 of_clk_del_provider(dev->of_node);
669 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
671 struct sdhci_host *host = sdhci_arasan->host;
672 struct cqhci_host *cq_host;
676 if (!sdhci_arasan->has_cqe)
677 return sdhci_add_host(host);
679 ret = sdhci_setup_host(host);
683 cq_host = devm_kzalloc(host->mmc->parent,
684 sizeof(*cq_host), GFP_KERNEL);
690 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
691 cq_host->ops = &sdhci_arasan_cqhci_ops;
693 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
695 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
697 ret = cqhci_init(cq_host, host->mmc, dma64);
701 ret = __sdhci_add_host(host);
708 sdhci_cleanup_host(host);
712 static int sdhci_arasan_probe(struct platform_device *pdev)
715 const struct of_device_id *match;
716 struct device_node *node;
718 struct sdhci_host *host;
719 struct sdhci_pltfm_host *pltfm_host;
720 struct sdhci_arasan_data *sdhci_arasan;
721 struct device_node *np = pdev->dev.of_node;
722 const struct sdhci_pltfm_data *pdata;
724 if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-5.1"))
725 pdata = &sdhci_arasan_cqe_pdata;
727 pdata = &sdhci_arasan_pdata;
729 host = sdhci_pltfm_init(pdev, pdata, sizeof(*sdhci_arasan));
732 return PTR_ERR(host);
734 pltfm_host = sdhci_priv(host);
735 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
736 sdhci_arasan->host = host;
738 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
739 sdhci_arasan->soc_ctl_map = match->data;
741 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
743 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
746 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
747 ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
748 if (ret != -EPROBE_DEFER)
749 dev_err(&pdev->dev, "Can't get syscon: %d\n",
755 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
756 if (IS_ERR(sdhci_arasan->clk_ahb)) {
757 dev_err(&pdev->dev, "clk_ahb clock not found.\n");
758 ret = PTR_ERR(sdhci_arasan->clk_ahb);
762 clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
763 if (IS_ERR(clk_xin)) {
764 dev_err(&pdev->dev, "clk_xin clock not found.\n");
765 ret = PTR_ERR(clk_xin);
769 ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
771 dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
775 ret = clk_prepare_enable(clk_xin);
777 dev_err(&pdev->dev, "Unable to enable SD clock.\n");
781 sdhci_get_of_property(pdev);
783 if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
784 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
786 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
787 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
789 pltfm_host->clk = clk_xin;
791 if (of_device_is_compatible(pdev->dev.of_node,
792 "rockchip,rk3399-sdhci-5.1"))
793 sdhci_arasan_update_clockmultiplier(host, 0x0);
795 sdhci_arasan_update_baseclkfreq(host);
797 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
799 goto clk_disable_all;
801 ret = mmc_of_parse(host->mmc);
803 if (ret != -EPROBE_DEFER)
804 dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);
808 sdhci_arasan->phy = ERR_PTR(-ENODEV);
809 if (of_device_is_compatible(pdev->dev.of_node,
810 "arasan,sdhci-5.1")) {
811 sdhci_arasan->phy = devm_phy_get(&pdev->dev,
813 if (IS_ERR(sdhci_arasan->phy)) {
814 ret = PTR_ERR(sdhci_arasan->phy);
815 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
819 ret = phy_init(sdhci_arasan->phy);
821 dev_err(&pdev->dev, "phy_init err.\n");
825 host->mmc_host_ops.hs400_enhanced_strobe =
826 sdhci_arasan_hs400_enhanced_strobe;
827 host->mmc_host_ops.start_signal_voltage_switch =
828 sdhci_arasan_voltage_switch;
829 sdhci_arasan->has_cqe = true;
830 host->mmc->caps2 |= MMC_CAP2_CQE;
832 if (!of_property_read_bool(np, "disable-cqe-dcmd"))
833 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
836 ret = sdhci_arasan_add_host(sdhci_arasan);
843 if (!IS_ERR(sdhci_arasan->phy))
844 phy_exit(sdhci_arasan->phy);
846 sdhci_arasan_unregister_sdclk(&pdev->dev);
848 clk_disable_unprepare(clk_xin);
850 clk_disable_unprepare(sdhci_arasan->clk_ahb);
852 sdhci_pltfm_free(pdev);
856 static int sdhci_arasan_remove(struct platform_device *pdev)
859 struct sdhci_host *host = platform_get_drvdata(pdev);
860 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
861 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
862 struct clk *clk_ahb = sdhci_arasan->clk_ahb;
864 if (!IS_ERR(sdhci_arasan->phy)) {
865 if (sdhci_arasan->is_phy_on)
866 phy_power_off(sdhci_arasan->phy);
867 phy_exit(sdhci_arasan->phy);
870 sdhci_arasan_unregister_sdclk(&pdev->dev);
872 ret = sdhci_pltfm_unregister(pdev);
874 clk_disable_unprepare(clk_ahb);
879 static struct platform_driver sdhci_arasan_driver = {
881 .name = "sdhci-arasan",
882 .of_match_table = sdhci_arasan_of_match,
883 .pm = &sdhci_arasan_dev_pm_ops,
885 .probe = sdhci_arasan_probe,
886 .remove = sdhci_arasan_remove,
889 module_platform_driver(sdhci_arasan_driver);
891 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
892 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
893 MODULE_LICENSE("GPL");