2 * Atmel SDMMC controller driver.
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/module.h>
26 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
30 #include "sdhci-pltfm.h"
32 #define SDMMC_MC1R 0x204
33 #define SDMMC_MC1R_DDR BIT(3)
34 #define SDMMC_MC1R_FCD BIT(7)
35 #define SDMMC_CACR 0x230
36 #define SDMMC_CACR_CAPWREN BIT(0)
37 #define SDMMC_CACR_KEY (0x46 << 8)
39 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
41 struct sdhci_at91_priv {
48 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
52 mc1r = readb(host->ioaddr + SDMMC_MC1R);
53 mc1r |= SDMMC_MC1R_FCD;
54 writeb(mc1r, host->ioaddr + SDMMC_MC1R);
57 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
60 unsigned long timeout;
62 host->mmc->actual_clock = 0;
65 * There is no requirement to disable the internal clock before
66 * changing the SD clock configuration. Moreover, disabling the
67 * internal clock, changing the configuration and re-enabling the
68 * internal clock causes some bugs. It can prevent to get the internal
69 * clock stable flag ready and an unexpected switch to the base clock
72 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
73 clk &= SDHCI_CLOCK_INT_EN;
74 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
79 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
81 clk |= SDHCI_CLOCK_INT_EN;
82 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
86 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
87 & SDHCI_CLOCK_INT_STABLE)) {
89 pr_err("%s: Internal clock never stabilised.\n",
90 mmc_hostname(host->mmc));
97 clk |= SDHCI_CLOCK_CARD_EN;
98 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
102 * In this specific implementation of the SDHCI controller, the power register
103 * needs to have a valid voltage set even when the power supply is managed by
104 * an external regulator.
106 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
109 if (!IS_ERR(host->mmc->supply.vmmc)) {
110 struct mmc_host *mmc = host->mmc;
112 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
114 sdhci_set_power_noreg(host, mode, vdd);
117 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
122 if (timing == MMC_TIMING_MMC_DDR52) {
123 mc1r = sdhci_readb(host, SDMMC_MC1R);
124 mc1r |= SDMMC_MC1R_DDR;
125 sdhci_writeb(host, mc1r, SDMMC_MC1R);
127 sdhci_set_uhs_signaling(host, timing);
130 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
132 sdhci_reset(host, mask);
134 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
135 || mmc_gpio_get_cd(host->mmc) >= 0)
136 sdhci_at91_set_force_card_detect(host);
139 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
140 .set_clock = sdhci_at91_set_clock,
141 .set_bus_width = sdhci_set_bus_width,
142 .reset = sdhci_at91_reset,
143 .set_uhs_signaling = sdhci_at91_set_uhs_signaling,
144 .set_power = sdhci_at91_set_power,
147 static const struct sdhci_pltfm_data soc_data_sama5d2 = {
148 .ops = &sdhci_at91_sama5d2_ops,
151 static const struct of_device_id sdhci_at91_dt_match[] = {
152 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
155 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
157 static int sdhci_at91_set_clks_presets(struct device *dev)
159 struct sdhci_host *host = dev_get_drvdata(dev);
160 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
161 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
163 unsigned int caps0, caps1;
164 unsigned int clk_base, clk_mul;
165 unsigned int gck_rate, real_gck_rate;
166 unsigned int preset_div;
169 * The mult clock is provided by as a generated clock by the PMC
170 * controller. In order to set the rate of gck, we have to get the
171 * base clock rate and the clock mult from capabilities.
173 clk_prepare_enable(priv->hclock);
174 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
175 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
176 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
177 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
178 gck_rate = clk_base * 1000000 * (clk_mul + 1);
179 ret = clk_set_rate(priv->gck, gck_rate);
181 dev_err(dev, "failed to set gck");
182 clk_disable_unprepare(priv->hclock);
186 * We need to check if we have the requested rate for gck because in
187 * some cases this rate could be not supported. If it happens, the rate
188 * is the closest one gck can provide. We have to update the value
191 real_gck_rate = clk_get_rate(priv->gck);
192 if (real_gck_rate != gck_rate) {
193 clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
194 caps1 &= (~SDHCI_CLOCK_MUL_MASK);
195 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) &
196 SDHCI_CLOCK_MUL_MASK);
197 /* Set capabilities in r/w mode. */
198 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN,
199 host->ioaddr + SDMMC_CACR);
200 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
201 /* Set capabilities in ro mode. */
202 writel(0, host->ioaddr + SDMMC_CACR);
203 dev_info(dev, "update clk mul to %u as gck rate is %u Hz\n",
204 clk_mul, real_gck_rate);
208 * We have to set preset values because it depends on the clk_mul
209 * value. Moreover, SDR104 is supported in a degraded mode since the
210 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
211 * reason, we need to use presets to support SDR104.
213 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
214 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
215 host->ioaddr + SDHCI_PRESET_FOR_SDR12);
216 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
217 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
218 host->ioaddr + SDHCI_PRESET_FOR_SDR25);
219 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
220 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
221 host->ioaddr + SDHCI_PRESET_FOR_SDR50);
222 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
223 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
224 host->ioaddr + SDHCI_PRESET_FOR_SDR104);
225 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
226 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
227 host->ioaddr + SDHCI_PRESET_FOR_DDR50);
229 clk_prepare_enable(priv->mainck);
230 clk_prepare_enable(priv->gck);
235 #ifdef CONFIG_PM_SLEEP
236 static int sdhci_at91_suspend(struct device *dev)
238 struct sdhci_host *host = dev_get_drvdata(dev);
239 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
240 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
243 ret = pm_runtime_force_suspend(dev);
245 priv->restore_needed = true;
249 #endif /* CONFIG_PM_SLEEP */
252 static int sdhci_at91_runtime_suspend(struct device *dev)
254 struct sdhci_host *host = dev_get_drvdata(dev);
255 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
256 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
259 ret = sdhci_runtime_suspend_host(host);
261 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
262 mmc_retune_needed(host->mmc);
264 clk_disable_unprepare(priv->gck);
265 clk_disable_unprepare(priv->hclock);
266 clk_disable_unprepare(priv->mainck);
271 static int sdhci_at91_runtime_resume(struct device *dev)
273 struct sdhci_host *host = dev_get_drvdata(dev);
274 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
275 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
278 if (priv->restore_needed) {
279 ret = sdhci_at91_set_clks_presets(dev);
283 priv->restore_needed = false;
287 ret = clk_prepare_enable(priv->mainck);
289 dev_err(dev, "can't enable mainck\n");
293 ret = clk_prepare_enable(priv->hclock);
295 dev_err(dev, "can't enable hclock\n");
299 ret = clk_prepare_enable(priv->gck);
301 dev_err(dev, "can't enable gck\n");
306 return sdhci_runtime_resume_host(host);
308 #endif /* CONFIG_PM */
310 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
311 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
312 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
313 sdhci_at91_runtime_resume,
317 static int sdhci_at91_probe(struct platform_device *pdev)
319 const struct of_device_id *match;
320 const struct sdhci_pltfm_data *soc_data;
321 struct sdhci_host *host;
322 struct sdhci_pltfm_host *pltfm_host;
323 struct sdhci_at91_priv *priv;
326 match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
329 soc_data = match->data;
331 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
333 return PTR_ERR(host);
335 pltfm_host = sdhci_priv(host);
336 priv = sdhci_pltfm_priv(pltfm_host);
338 priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
339 if (IS_ERR(priv->mainck)) {
340 dev_err(&pdev->dev, "failed to get baseclk\n");
341 ret = PTR_ERR(priv->mainck);
342 goto sdhci_pltfm_free;
345 priv->hclock = devm_clk_get(&pdev->dev, "hclock");
346 if (IS_ERR(priv->hclock)) {
347 dev_err(&pdev->dev, "failed to get hclock\n");
348 ret = PTR_ERR(priv->hclock);
349 goto sdhci_pltfm_free;
352 priv->gck = devm_clk_get(&pdev->dev, "multclk");
353 if (IS_ERR(priv->gck)) {
354 dev_err(&pdev->dev, "failed to get multclk\n");
355 ret = PTR_ERR(priv->gck);
356 goto sdhci_pltfm_free;
359 ret = sdhci_at91_set_clks_presets(&pdev->dev);
361 goto sdhci_pltfm_free;
363 priv->restore_needed = false;
365 ret = mmc_of_parse(host->mmc);
367 goto clocks_disable_unprepare;
369 sdhci_get_of_property(pdev);
371 pm_runtime_get_noresume(&pdev->dev);
372 pm_runtime_set_active(&pdev->dev);
373 pm_runtime_enable(&pdev->dev);
374 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
375 pm_runtime_use_autosuspend(&pdev->dev);
377 /* HS200 is broken at this moment */
378 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
380 ret = sdhci_add_host(host);
382 goto pm_runtime_disable;
385 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
386 * the assumption that all the clocks of the controller are disabled.
387 * It means we can't get irq from it when it is runtime suspended.
388 * For that reason, it is not planned to wake-up on a card detect irq
389 * from the controller.
390 * If we want to use runtime PM and to be able to wake-up on card
391 * insertion, we have to use a GPIO for the card detection or we can
392 * use polling. Be aware that using polling will resume/suspend the
393 * controller between each attempt.
394 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
395 * to enable polling via device tree with broken-cd property.
397 if (mmc_card_is_removable(host->mmc) &&
398 mmc_gpio_get_cd(host->mmc) < 0) {
399 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
400 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
404 * If the device attached to the MMC bus is not removable, it is safer
405 * to set the Force Card Detect bit. People often don't connect the
406 * card detect signal and use this pin for another purpose. If the card
407 * detect pin is not muxed to SDHCI controller, a default value is
408 * used. This value can be different from a SoC revision to another
409 * one. Problems come when this default value is not card present. To
410 * avoid this case, if the device is non removable then the card
411 * detection procedure using the SDMCC_CD signal is bypassed.
412 * This bit is reset when a software reset for all command is performed
413 * so we need to implement our own reset function to set back this bit.
415 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
417 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
418 || mmc_gpio_get_cd(host->mmc) >= 0)
419 sdhci_at91_set_force_card_detect(host);
421 pm_runtime_put_autosuspend(&pdev->dev);
426 pm_runtime_disable(&pdev->dev);
427 pm_runtime_set_suspended(&pdev->dev);
428 pm_runtime_put_noidle(&pdev->dev);
429 clocks_disable_unprepare:
430 clk_disable_unprepare(priv->gck);
431 clk_disable_unprepare(priv->mainck);
432 clk_disable_unprepare(priv->hclock);
434 sdhci_pltfm_free(pdev);
438 static int sdhci_at91_remove(struct platform_device *pdev)
440 struct sdhci_host *host = platform_get_drvdata(pdev);
441 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
442 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
443 struct clk *gck = priv->gck;
444 struct clk *hclock = priv->hclock;
445 struct clk *mainck = priv->mainck;
447 pm_runtime_get_sync(&pdev->dev);
448 pm_runtime_disable(&pdev->dev);
449 pm_runtime_put_noidle(&pdev->dev);
451 sdhci_pltfm_unregister(pdev);
453 clk_disable_unprepare(gck);
454 clk_disable_unprepare(hclock);
455 clk_disable_unprepare(mainck);
460 static struct platform_driver sdhci_at91_driver = {
462 .name = "sdhci-at91",
463 .of_match_table = sdhci_at91_dt_match,
464 .pm = &sdhci_at91_dev_pm_ops,
466 .probe = sdhci_at91_probe,
467 .remove = sdhci_at91_remove,
470 module_platform_driver(sdhci_at91_driver);
472 MODULE_DESCRIPTION("SDHCI driver for at91");
473 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
474 MODULE_LICENSE("GPL v2");