drivers/mmc/host/sdhci-omap.c

   1 /**
   2  * SDHCI Controller driver for TI's OMAP SoCs
   3  *
   4  * Copyright (C) 2017 Texas Instruments
   5  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 of
   9  * the License as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/mmc/slot-gpio.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/sys_soc.h>
  30 #include <linux/thermal.h>
  31
  32 #include "sdhci-pltfm.h"
  33
  34 #define SDHCI_OMAP_CON          0x12c
  35 #define CON_DW8                 BIT(5)
  36 #define CON_DMA_MASTER          BIT(20)
  37 #define CON_DDR                 BIT(19)
  38 #define CON_CLKEXTFREE          BIT(16)
  39 #define CON_PADEN               BIT(15)
  40 #define CON_CTPL                BIT(11)
  41 #define CON_INIT                BIT(1)
  42 #define CON_OD                  BIT(0)
  43
  44 #define SDHCI_OMAP_DLL          0x0134
  45 #define DLL_SWT                 BIT(20)
  46 #define DLL_FORCE_SR_C_SHIFT    13
  47 #define DLL_FORCE_SR_C_MASK     (0x7f << DLL_FORCE_SR_C_SHIFT)
  48 #define DLL_FORCE_VALUE         BIT(12)
  49 #define DLL_CALIB               BIT(1)
  50
  51 #define SDHCI_OMAP_CMD          0x20c
  52
  53 #define SDHCI_OMAP_PSTATE       0x0224
  54 #define PSTATE_DLEV_DAT0        BIT(20)
  55 #define PSTATE_DATI             BIT(1)
  56
  57 #define SDHCI_OMAP_HCTL         0x228
  58 #define HCTL_SDBP               BIT(8)
  59 #define HCTL_SDVS_SHIFT         9
  60 #define HCTL_SDVS_MASK          (0x7 << HCTL_SDVS_SHIFT)
  61 #define HCTL_SDVS_33            (0x7 << HCTL_SDVS_SHIFT)
  62 #define HCTL_SDVS_30            (0x6 << HCTL_SDVS_SHIFT)
  63 #define HCTL_SDVS_18            (0x5 << HCTL_SDVS_SHIFT)
  64
  65 #define SDHCI_OMAP_SYSCTL       0x22c
  66 #define SYSCTL_CEN              BIT(2)
  67 #define SYSCTL_CLKD_SHIFT       6
  68 #define SYSCTL_CLKD_MASK        0x3ff
  69
  70 #define SDHCI_OMAP_STAT         0x230
  71
  72 #define SDHCI_OMAP_IE           0x234
  73 #define INT_CC_EN               BIT(0)
  74
  75 #define SDHCI_OMAP_AC12         0x23c
  76 #define AC12_V1V8_SIGEN         BIT(19)
  77 #define AC12_SCLK_SEL           BIT(23)
  78
  79 #define SDHCI_OMAP_CAPA         0x240
  80 #define CAPA_VS33               BIT(24)
  81 #define CAPA_VS30               BIT(25)
  82 #define CAPA_VS18               BIT(26)
  83
  84 #define SDHCI_OMAP_CAPA2        0x0244
  85 #define CAPA2_TSDR50            BIT(13)
  86
  87 #define SDHCI_OMAP_TIMEOUT      1               /* 1 msec */
  88
  89 #define SYSCTL_CLKD_MAX         0x3FF
  90
  91 #define IOV_1V8                 1800000         /* 180000 uV */
  92 #define IOV_3V0                 3000000         /* 300000 uV */
  93 #define IOV_3V3                 3300000         /* 330000 uV */
  94
  95 #define MAX_PHASE_DELAY         0x7C
  96
  97 /* sdhci-omap controller flags */
  98 #define SDHCI_OMAP_REQUIRE_IODELAY      BIT(0)
  99
 100 struct sdhci_omap_data {
 101         u32 offset;
 102         u8 flags;
 103 };
 104
 105 struct sdhci_omap_host {
 106         char                    *version;
 107         void __iomem            *base;
 108         struct device           *dev;
 109         struct  regulator       *pbias;
 110         bool                    pbias_enabled;
 111         struct sdhci_host       *host;
 112         u8                      bus_mode;
 113         u8                      power_mode;
 114         u8                      timing;
 115         u8                      flags;
 116
 117         struct pinctrl          *pinctrl;
 118         struct pinctrl_state    **pinctrl_state;
 119         bool                    is_tuning;
 120 };
 121
 122 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
 123 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
 124
 125 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
 126                                    unsigned int offset)
 127 {
 128         return readl(host->base + offset);
 129 }
 130
 131 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
 132                                      unsigned int offset, u32 data)
 133 {
 134         writel(data, host->base + offset);
 135 }
 136
 137 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
 138                                 bool power_on, unsigned int iov)
 139 {
 140         int ret;
 141         struct device *dev = omap_host->dev;
 142
 143         if (IS_ERR(omap_host->pbias))
 144                 return 0;
 145
 146         if (power_on) {
 147                 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
 148                 if (ret) {
 149                         dev_err(dev, "pbias set voltage failed\n");
 150                         return ret;
 151                 }
 152
 153                 if (omap_host->pbias_enabled)
 154                         return 0;
 155
 156                 ret = regulator_enable(omap_host->pbias);
 157                 if (ret) {
 158                         dev_err(dev, "pbias reg enable fail\n");
 159                         return ret;
 160                 }
 161
 162                 omap_host->pbias_enabled = true;
 163         } else {
 164                 if (!omap_host->pbias_enabled)
 165                         return 0;
 166
 167                 ret = regulator_disable(omap_host->pbias);
 168                 if (ret) {
 169                         dev_err(dev, "pbias reg disable fail\n");
 170                         return ret;
 171                 }
 172                 omap_host->pbias_enabled = false;
 173         }
 174
 175         return 0;
 176 }
 177
 178 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
 179                                  unsigned int iov)
 180 {
 181         int ret;
 182         struct sdhci_host *host = omap_host->host;
 183         struct mmc_host *mmc = host->mmc;
 184
 185         ret = sdhci_omap_set_pbias(omap_host, false, 0);
 186         if (ret)
 187                 return ret;
 188
 189         if (!IS_ERR(mmc->supply.vqmmc)) {
 190                 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
 191                 if (ret) {
 192                         dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
 193                         return ret;
 194                 }
 195         }
 196
 197         ret = sdhci_omap_set_pbias(omap_host, true, iov);
 198         if (ret)
 199                 return ret;
 200
 201         return 0;
 202 }
 203
 204 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
 205                                       unsigned char signal_voltage)
 206 {
 207         u32 reg;
 208         ktime_t timeout;
 209
 210         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
 211         reg &= ~HCTL_SDVS_MASK;
 212
 213         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 214                 reg |= HCTL_SDVS_33;
 215         else
 216                 reg |= HCTL_SDVS_18;
 217
 218         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 219
 220         reg |= HCTL_SDBP;
 221         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 222
 223         /* wait 1ms */
 224         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 225         while (1) {
 226                 bool timedout = ktime_after(ktime_get(), timeout);
 227
 228                 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)
 229                         break;
 230                 if (WARN_ON(timedout))
 231                         return;
 232                 usleep_range(5, 10);
 233         }
 234 }
 235
 236 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
 237 {
 238         struct sdhci_host *host = mmc_priv(mmc);
 239         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 240         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 241         u32 reg;
 242
 243         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 244         if (enable)
 245                 reg |= (CON_CTPL | CON_CLKEXTFREE);
 246         else
 247                 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
 248         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 249
 250         sdhci_enable_sdio_irq(mmc, enable);
 251 }
 252
 253 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
 254                                       int count)
 255 {
 256         int i;
 257         u32 reg;
 258
 259         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 260         reg |= DLL_FORCE_VALUE;
 261         reg &= ~DLL_FORCE_SR_C_MASK;
 262         reg |= (count << DLL_FORCE_SR_C_SHIFT);
 263         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 264
 265         reg |= DLL_CALIB;
 266         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 267         for (i = 0; i < 1000; i++) {
 268                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 269                 if (reg & DLL_CALIB)
 270                         break;
 271         }
 272         reg &= ~DLL_CALIB;
 273         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 274 }
 275
 276 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
 277 {
 278         u32 reg;
 279
 280         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 281         reg &= ~AC12_SCLK_SEL;
 282         sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 283
 284         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 285         reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
 286         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 287 }
 288
 289 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
 290 {
 291         struct sdhci_host *host = mmc_priv(mmc);
 292         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 293         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 294         struct thermal_zone_device *thermal_dev;
 295         struct device *dev = omap_host->dev;
 296         struct mmc_ios *ios = &mmc->ios;
 297         u32 start_window = 0, max_window = 0;
 298         bool single_point_failure = false;
 299         bool dcrc_was_enabled = false;
 300         u8 cur_match, prev_match = 0;
 301         u32 length = 0, max_len = 0;
 302         u32 phase_delay = 0;
 303         int temperature;
 304         int ret = 0;
 305         u32 reg;
 306         int i;
 307
 308         pltfm_host = sdhci_priv(host);
 309         omap_host = sdhci_pltfm_priv(pltfm_host);
 310         dev = omap_host->dev;
 311
 312         /* clock tuning is not needed for upto 52MHz */
 313         if (ios->clock <= 52000000)
 314                 return 0;
 315
 316         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
 317         if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
 318                 return 0;
 319
 320         thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal");
 321         if (IS_ERR(thermal_dev)) {
 322                 dev_err(dev, "Unable to get thermal zone for tuning\n");
 323                 return PTR_ERR(thermal_dev);
 324         }
 325
 326         ret = thermal_zone_get_temp(thermal_dev, &temperature);
 327         if (ret)
 328                 return ret;
 329
 330         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 331         reg |= DLL_SWT;
 332         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 333
 334         /*
 335          * OMAP5/DRA74X/DRA72x Errata i802:
 336          * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
 337          * during the tuning procedure. So disable it during the
 338          * tuning procedure.
 339          */
 340         if (host->ier & SDHCI_INT_DATA_CRC) {
 341                 host->ier &= ~SDHCI_INT_DATA_CRC;
 342                 dcrc_was_enabled = true;
 343         }
 344
 345         omap_host->is_tuning = true;
 346
 347         /*
 348          * Stage 1: Search for a maximum pass window ignoring any
 349          * any single point failures. If the tuning value ends up
 350          * near it, move away from it in stage 2 below
 351          */
 352         while (phase_delay <= MAX_PHASE_DELAY) {
 353                 sdhci_omap_set_dll(omap_host, phase_delay);
 354
 355                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 356                 if (cur_match) {
 357                         if (prev_match) {
 358                                 length++;
 359                         } else if (single_point_failure) {
 360                                 /* ignore single point failure */
 361                                 length++;
 362                         } else {
 363                                 start_window = phase_delay;
 364                                 length = 1;
 365                         }
 366                 } else {
 367                         single_point_failure = prev_match;
 368                 }
 369
 370                 if (length > max_len) {
 371                         max_window = start_window;
 372                         max_len = length;
 373                 }
 374
 375                 prev_match = cur_match;
 376                 phase_delay += 4;
 377         }
 378
 379         if (!max_len) {
 380                 dev_err(dev, "Unable to find match\n");
 381                 ret = -EIO;
 382                 goto tuning_error;
 383         }
 384
 385         /*
 386          * Assign tuning value as a ratio of maximum pass window based
 387          * on temperature
 388          */
 389         if (temperature < -20000)
 390                 phase_delay = min(max_window + 4 * (max_len - 1) - 24,
 391                                   max_window +
 392                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 393         else if (temperature < 20000)
 394                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 395         else if (temperature < 40000)
 396                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 397         else if (temperature < 70000)
 398                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 399         else if (temperature < 90000)
 400                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 401         else if (temperature < 120000)
 402                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 403         else
 404                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 405
 406         /*
 407          * Stage 2: Search for a single point failure near the chosen tuning
 408          * value in two steps. First in the +3 to +10 range and then in the
 409          * +2 to -10 range. If found, move away from it in the appropriate
 410          * direction by the appropriate amount depending on the temperature.
 411          */
 412         for (i = 3; i <= 10; i++) {
 413                 sdhci_omap_set_dll(omap_host, phase_delay + i);
 414
 415                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 416                         if (temperature < 10000)
 417                                 phase_delay += i + 6;
 418                         else if (temperature < 20000)
 419                                 phase_delay += i - 12;
 420                         else if (temperature < 70000)
 421                                 phase_delay += i - 8;
 422                         else
 423                                 phase_delay += i - 6;
 424
 425                         goto single_failure_found;
 426                 }
 427         }
 428
 429         for (i = 2; i >= -10; i--) {
 430                 sdhci_omap_set_dll(omap_host, phase_delay + i);
 431
 432                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 433                         if (temperature < 10000)
 434                                 phase_delay += i + 12;
 435                         else if (temperature < 20000)
 436                                 phase_delay += i + 8;
 437                         else if (temperature < 70000)
 438                                 phase_delay += i + 8;
 439                         else if (temperature < 90000)
 440                                 phase_delay += i + 10;
 441                         else
 442                                 phase_delay += i + 12;
 443
 444                         goto single_failure_found;
 445                 }
 446         }
 447
 448 single_failure_found:
 449         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 450         if (!(reg & AC12_SCLK_SEL)) {
 451                 ret = -EIO;
 452                 goto tuning_error;
 453         }
 454
 455         sdhci_omap_set_dll(omap_host, phase_delay);
 456
 457         omap_host->is_tuning = false;
 458
 459         goto ret;
 460
 461 tuning_error:
 462         omap_host->is_tuning = false;
 463         dev_err(dev, "Tuning failed\n");
 464         sdhci_omap_disable_tuning(omap_host);
 465
 466 ret:
 467         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 468         /* Reenable forbidden interrupt */
 469         if (dcrc_was_enabled)
 470                 host->ier |= SDHCI_INT_DATA_CRC;
 471         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 472         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 473         return ret;
 474 }
 475
 476 static int sdhci_omap_card_busy(struct mmc_host *mmc)
 477 {
 478         u32 reg, ac12;
 479         int ret = false;
 480         struct sdhci_host *host = mmc_priv(mmc);
 481         struct sdhci_pltfm_host *pltfm_host;
 482         struct sdhci_omap_host *omap_host;
 483         u32 ier = host->ier;
 484
 485         pltfm_host = sdhci_priv(host);
 486         omap_host = sdhci_pltfm_priv(pltfm_host);
 487
 488         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 489         ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 490         reg &= ~CON_CLKEXTFREE;
 491         if (ac12 & AC12_V1V8_SIGEN)
 492                 reg |= CON_CLKEXTFREE;
 493         reg |= CON_PADEN;
 494         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 495
 496         disable_irq(host->irq);
 497         ier |= SDHCI_INT_CARD_INT;
 498         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 499         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 500
 501         /*
 502          * Delay is required for PSTATE to correctly reflect
 503          * DLEV/CLEV values after PADEN is set.
 504          */
 505         usleep_range(50, 100);
 506         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
 507         if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
 508                 ret = true;
 509
 510         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 511         reg &= ~(CON_CLKEXTFREE | CON_PADEN);
 512         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 513
 514         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 515         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 516         enable_irq(host->irq);
 517
 518         return ret;
 519 }
 520
 521 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
 522                                                   struct mmc_ios *ios)
 523 {
 524         u32 reg;
 525         int ret;
 526         unsigned int iov;
 527         struct sdhci_host *host = mmc_priv(mmc);
 528         struct sdhci_pltfm_host *pltfm_host;
 529         struct sdhci_omap_host *omap_host;
 530         struct device *dev;
 531
 532         pltfm_host = sdhci_priv(host);
 533         omap_host = sdhci_pltfm_priv(pltfm_host);
 534         dev = omap_host->dev;
 535
 536         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 537                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 538                 if (!(reg & CAPA_VS33))
 539                         return -EOPNOTSUPP;
 540
 541                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 542
 543                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 544                 reg &= ~AC12_V1V8_SIGEN;
 545                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 546
 547                 iov = IOV_3V3;
 548         } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 549                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 550                 if (!(reg & CAPA_VS18))
 551                         return -EOPNOTSUPP;
 552
 553                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 554
 555                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 556                 reg |= AC12_V1V8_SIGEN;
 557                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 558
 559                 iov = IOV_1V8;
 560         } else {
 561                 return -EOPNOTSUPP;
 562         }
 563
 564         ret = sdhci_omap_enable_iov(omap_host, iov);
 565         if (ret) {
 566                 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
 567                 return ret;
 568         }
 569
 570         dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
 571         return 0;
 572 }
 573
 574 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
 575 {
 576         int ret;
 577         struct pinctrl_state *pinctrl_state;
 578         struct device *dev = omap_host->dev;
 579
 580         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 581                 return;
 582
 583         if (omap_host->timing == timing)
 584                 return;
 585
 586         sdhci_omap_stop_clock(omap_host);
 587
 588         pinctrl_state = omap_host->pinctrl_state[timing];
 589         ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
 590         if (ret) {
 591                 dev_err(dev, "failed to select pinctrl state\n");
 592                 return;
 593         }
 594
 595         sdhci_omap_start_clock(omap_host);
 596         omap_host->timing = timing;
 597 }
 598
 599 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
 600                                       u8 power_mode)
 601 {
 602         if (omap_host->bus_mode == MMC_POWER_OFF)
 603                 sdhci_omap_disable_tuning(omap_host);
 604         omap_host->power_mode = power_mode;
 605 }
 606
 607 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
 608                                     unsigned int mode)
 609 {
 610         u32 reg;
 611
 612         if (omap_host->bus_mode == mode)
 613                 return;
 614
 615         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 616         if (mode == MMC_BUSMODE_OPENDRAIN)
 617                 reg |= CON_OD;
 618         else
 619                 reg &= ~CON_OD;
 620         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 621
 622         omap_host->bus_mode = mode;
 623 }
 624
 625 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 626 {
 627         struct sdhci_host *host = mmc_priv(mmc);
 628         struct sdhci_pltfm_host *pltfm_host;
 629         struct sdhci_omap_host *omap_host;
 630
 631         pltfm_host = sdhci_priv(host);
 632         omap_host = sdhci_pltfm_priv(pltfm_host);
 633
 634         sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
 635         sdhci_omap_set_timing(omap_host, ios->timing);
 636         sdhci_set_ios(mmc, ios);
 637         sdhci_omap_set_power_mode(omap_host, ios->power_mode);
 638 }
 639
 640 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
 641                                    unsigned int clock)
 642 {
 643         u16 dsor;
 644
 645         dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
 646         if (dsor > SYSCTL_CLKD_MAX)
 647                 dsor = SYSCTL_CLKD_MAX;
 648
 649         return dsor;
 650 }
 651
 652 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
 653 {
 654         u32 reg;
 655
 656         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 657         reg |= SYSCTL_CEN;
 658         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 659 }
 660
 661 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
 662 {
 663         u32 reg;
 664
 665         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 666         reg &= ~SYSCTL_CEN;
 667         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 668 }
 669
 670 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
 671 {
 672         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 673         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 674         unsigned long clkdiv;
 675
 676         sdhci_omap_stop_clock(omap_host);
 677
 678         if (!clock)
 679                 return;
 680
 681         clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
 682         clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
 683         sdhci_enable_clk(host, clkdiv);
 684
 685         sdhci_omap_start_clock(omap_host);
 686 }
 687
 688 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
 689                           unsigned short vdd)
 690 {
 691         struct mmc_host *mmc = host->mmc;
 692
 693         if (!IS_ERR(mmc->supply.vmmc))
 694                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 695 }
 696
 697 static int sdhci_omap_enable_dma(struct sdhci_host *host)
 698 {
 699         u32 reg;
 700         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 701         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 702
 703         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 704         reg |= CON_DMA_MASTER;
 705         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 706
 707         return 0;
 708 }
 709
 710 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
 711 {
 712         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 713
 714         return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
 715 }
 716
 717 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
 718 {
 719         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 720         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 721         u32 reg;
 722
 723         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 724         if (width == MMC_BUS_WIDTH_8)
 725                 reg |= CON_DW8;
 726         else
 727                 reg &= ~CON_DW8;
 728         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 729
 730         sdhci_set_bus_width(host, width);
 731 }
 732
 733 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 734 {
 735         u32 reg;
 736         ktime_t timeout;
 737         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 738         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 739
 740         if (omap_host->power_mode == power_mode)
 741                 return;
 742
 743         if (power_mode != MMC_POWER_ON)
 744                 return;
 745
 746         disable_irq(host->irq);
 747
 748         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 749         reg |= CON_INIT;
 750         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 751         sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
 752
 753         /* wait 1ms */
 754         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 755         while (1) {
 756                 bool timedout = ktime_after(ktime_get(), timeout);
 757
 758                 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)
 759                         break;
 760                 if (WARN_ON(timedout))
 761                         return;
 762                 usleep_range(5, 10);
 763         }
 764
 765         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 766         reg &= ~CON_INIT;
 767         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 768         sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
 769
 770         enable_irq(host->irq);
 771 }
 772
 773 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
 774                                          unsigned int timing)
 775 {
 776         u32 reg;
 777         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 778         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 779
 780         sdhci_omap_stop_clock(omap_host);
 781
 782         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 783         if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
 784                 reg |= CON_DDR;
 785         else
 786                 reg &= ~CON_DDR;
 787         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 788
 789         sdhci_set_uhs_signaling(host, timing);
 790         sdhci_omap_start_clock(omap_host);
 791 }
 792
 793 void sdhci_omap_reset(struct sdhci_host *host, u8 mask)
 794 {
 795         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 796         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 797
 798         /* Don't reset data lines during tuning operation */
 799         if (omap_host->is_tuning)
 800                 mask &= ~SDHCI_RESET_DATA;
 801
 802         sdhci_reset(host, mask);
 803 }
 804
 805 #define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\
 806                       SDHCI_INT_TIMEOUT)
 807 #define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE)
 808
 809 static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask)
 810 {
 811         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 812         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 813
 814         if (omap_host->is_tuning && host->cmd && !host->data_early &&
 815             (intmask & CMD_ERR_MASK)) {
 816
 817                 /*
 818                  * Since we are not resetting data lines during tuning
 819                  * operation, data error or data complete interrupts
 820                  * might still arrive. Mark this request as a failure
 821                  * but still wait for the data interrupt
 822                  */
 823                 if (intmask & SDHCI_INT_TIMEOUT)
 824                         host->cmd->error = -ETIMEDOUT;
 825                 else
 826                         host->cmd->error = -EILSEQ;
 827
 828                 host->cmd = NULL;
 829
 830                 /*
 831                  * Sometimes command error interrupts and command complete
 832                  * interrupt will arrive together. Clear all command related
 833                  * interrupts here.
 834                  */
 835                 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS);
 836                 intmask &= ~CMD_MASK;
 837         }
 838
 839         return intmask;
 840 }
 841
 842 static struct sdhci_ops sdhci_omap_ops = {
 843         .set_clock = sdhci_omap_set_clock,
 844         .set_power = sdhci_omap_set_power,
 845         .enable_dma = sdhci_omap_enable_dma,
 846         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 847         .get_min_clock = sdhci_omap_get_min_clock,
 848         .set_bus_width = sdhci_omap_set_bus_width,
 849         .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
 850         .reset = sdhci_omap_reset,
 851         .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
 852         .irq = sdhci_omap_irq,
 853 };
 854
 855 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
 856 {
 857         u32 reg;
 858         int ret = 0;
 859         struct device *dev = omap_host->dev;
 860         struct regulator *vqmmc;
 861
 862         vqmmc = regulator_get(dev, "vqmmc");
 863         if (IS_ERR(vqmmc)) {
 864                 ret = PTR_ERR(vqmmc);
 865                 goto reg_put;
 866         }
 867
 868         /* voltage capabilities might be set by boot loader, clear it */
 869         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 870         reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
 871
 872         if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
 873                 reg |= CAPA_VS33;
 874         if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
 875                 reg |= CAPA_VS18;
 876
 877         sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
 878
 879 reg_put:
 880         regulator_put(vqmmc);
 881
 882         return ret;
 883 }
 884
 885 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
 886         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 887                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 888                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 889                   SDHCI_QUIRK_NO_HISPD_BIT |
 890                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
 891         .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
 892                    SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 893                    SDHCI_QUIRK2_RSP_136_HAS_CRC |
 894                    SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
 895         .ops = &sdhci_omap_ops,
 896 };
 897
 898 static const struct sdhci_omap_data k2g_data = {
 899         .offset = 0x200,
 900 };
 901
 902 static const struct sdhci_omap_data dra7_data = {
 903         .offset = 0x200,
 904         .flags  = SDHCI_OMAP_REQUIRE_IODELAY,
 905 };
 906
 907 static const struct of_device_id omap_sdhci_match[] = {
 908         { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
 909         { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
 910         {},
 911 };
 912 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
 913
 914 static struct pinctrl_state
 915 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
 916                                   u32 *caps, u32 capmask)
 917 {
 918         struct device *dev = omap_host->dev;
 919         char *version = omap_host->version;
 920         struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
 921         char str[20];
 922
 923         if (!(*caps & capmask))
 924                 goto ret;
 925
 926         if (version) {
 927                 snprintf(str, 20, "%s-%s", mode, version);
 928                 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
 929         }
 930
 931         if (IS_ERR(pinctrl_state))
 932                 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
 933
 934         if (IS_ERR(pinctrl_state)) {
 935                 dev_err(dev, "no pinctrl state for %s mode", mode);
 936                 *caps &= ~capmask;
 937         }
 938
 939 ret:
 940         return pinctrl_state;
 941 }
 942
 943 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
 944                                                    *omap_host)
 945 {
 946         struct device *dev = omap_host->dev;
 947         struct sdhci_host *host = omap_host->host;
 948         struct mmc_host *mmc = host->mmc;
 949         u32 *caps = &mmc->caps;
 950         u32 *caps2 = &mmc->caps2;
 951         struct pinctrl_state *state;
 952         struct pinctrl_state **pinctrl_state;
 953
 954         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 955                 return 0;
 956
 957         pinctrl_state = devm_kcalloc(dev,
 958                                      MMC_TIMING_MMC_HS200 + 1,
 959                                      sizeof(*pinctrl_state),
 960                                      GFP_KERNEL);
 961         if (!pinctrl_state)
 962                 return -ENOMEM;
 963
 964         omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
 965         if (IS_ERR(omap_host->pinctrl)) {
 966                 dev_err(dev, "Cannot get pinctrl\n");
 967                 return PTR_ERR(omap_host->pinctrl);
 968         }
 969
 970         state = pinctrl_lookup_state(omap_host->pinctrl, "default");
 971         if (IS_ERR(state)) {
 972                 dev_err(dev, "no pinctrl state for default mode\n");
 973                 return PTR_ERR(state);
 974         }
 975         pinctrl_state[MMC_TIMING_LEGACY] = state;
 976
 977         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
 978                                                  MMC_CAP_UHS_SDR104);
 979         if (!IS_ERR(state))
 980                 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
 981
 982         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
 983                                                  MMC_CAP_UHS_DDR50);
 984         if (!IS_ERR(state))
 985                 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
 986
 987         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
 988                                                  MMC_CAP_UHS_SDR50);
 989         if (!IS_ERR(state))
 990                 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
 991
 992         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
 993                                                  MMC_CAP_UHS_SDR25);
 994         if (!IS_ERR(state))
 995                 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
 996
 997         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
 998                                                  MMC_CAP_UHS_SDR12);
 999         if (!IS_ERR(state))
1000                 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
1001
1002         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
1003                                                  MMC_CAP_1_8V_DDR);
1004         if (!IS_ERR(state)) {
1005                 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1006         } else {
1007                 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1008                                                          caps,
1009                                                          MMC_CAP_3_3V_DDR);
1010                 if (!IS_ERR(state))
1011                         pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1012         }
1013
1014         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1015                                                  MMC_CAP_SD_HIGHSPEED);
1016         if (!IS_ERR(state))
1017                 pinctrl_state[MMC_TIMING_SD_HS] = state;
1018
1019         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1020                                                  MMC_CAP_MMC_HIGHSPEED);
1021         if (!IS_ERR(state))
1022                 pinctrl_state[MMC_TIMING_MMC_HS] = state;
1023
1024         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1025                                                  MMC_CAP2_HS200_1_8V_SDR);
1026         if (!IS_ERR(state))
1027                 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
1028
1029         omap_host->pinctrl_state = pinctrl_state;
1030
1031         return 0;
1032 }
1033
1034 static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
1035         {
1036                 .machine = "DRA7[45]*",
1037                 .revision = "ES1.[01]",
1038         },
1039         {
1040                 /* sentinel */
1041         }
1042 };
1043
1044 static int sdhci_omap_probe(struct platform_device *pdev)
1045 {
1046         int ret;
1047         u32 offset;
1048         struct device *dev = &pdev->dev;
1049         struct sdhci_host *host;
1050         struct sdhci_pltfm_host *pltfm_host;
1051         struct sdhci_omap_host *omap_host;
1052         struct mmc_host *mmc;
1053         const struct of_device_id *match;
1054         struct sdhci_omap_data *data;
1055         const struct soc_device_attribute *soc;
1056
1057         match = of_match_device(omap_sdhci_match, dev);
1058         if (!match)
1059                 return -EINVAL;
1060
1061         data = (struct sdhci_omap_data *)match->data;
1062         if (!data) {
1063                 dev_err(dev, "no sdhci omap data\n");
1064                 return -EINVAL;
1065         }
1066         offset = data->offset;
1067
1068         host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
1069                                 sizeof(*omap_host));
1070         if (IS_ERR(host)) {
1071                 dev_err(dev, "Failed sdhci_pltfm_init\n");
1072                 return PTR_ERR(host);
1073         }
1074
1075         pltfm_host = sdhci_priv(host);
1076         omap_host = sdhci_pltfm_priv(pltfm_host);
1077         omap_host->host = host;
1078         omap_host->base = host->ioaddr;
1079         omap_host->dev = dev;
1080         omap_host->power_mode = MMC_POWER_UNDEFINED;
1081         omap_host->timing = MMC_TIMING_LEGACY;
1082         omap_host->flags = data->flags;
1083         host->ioaddr += offset;
1084
1085         mmc = host->mmc;
1086         sdhci_get_of_property(pdev);
1087         ret = mmc_of_parse(mmc);
1088         if (ret)
1089                 goto err_pltfm_free;
1090
1091         soc = soc_device_match(sdhci_omap_soc_devices);
1092         if (soc) {
1093                 omap_host->version = "rev11";
1094                 if (!strcmp(dev_name(dev), "4809c000.mmc"))
1095                         mmc->f_max = 96000000;
1096                 if (!strcmp(dev_name(dev), "480b4000.mmc"))
1097                         mmc->f_max = 48000000;
1098                 if (!strcmp(dev_name(dev), "480ad000.mmc"))
1099                         mmc->f_max = 48000000;
1100         }
1101
1102         pltfm_host->clk = devm_clk_get(dev, "fck");
1103         if (IS_ERR(pltfm_host->clk)) {
1104                 ret = PTR_ERR(pltfm_host->clk);
1105                 goto err_pltfm_free;
1106         }
1107
1108         ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
1109         if (ret) {
1110                 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
1111                 goto err_pltfm_free;
1112         }
1113
1114         omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
1115         if (IS_ERR(omap_host->pbias)) {
1116                 ret = PTR_ERR(omap_host->pbias);
1117                 if (ret != -ENODEV)
1118                         goto err_pltfm_free;
1119                 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
1120         }
1121         omap_host->pbias_enabled = false;
1122
1123         /*
1124          * omap_device_pm_domain has callbacks to enable the main
1125          * functional clock, interface clock and also configure the
1126          * SYSCONFIG register of omap devices. The callback will be invoked
1127          * as part of pm_runtime_get_sync.
1128          */
1129         pm_runtime_enable(dev);
1130         ret = pm_runtime_get_sync(dev);
1131         if (ret < 0) {
1132                 dev_err(dev, "pm_runtime_get_sync failed\n");
1133                 pm_runtime_put_noidle(dev);
1134                 goto err_rpm_disable;
1135         }
1136
1137         ret = sdhci_omap_set_capabilities(omap_host);
1138         if (ret) {
1139                 dev_err(dev, "failed to set system capabilities\n");
1140                 goto err_put_sync;
1141         }
1142
1143         host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
1144         host->mmc_host_ops.start_signal_voltage_switch =
1145                                         sdhci_omap_start_signal_voltage_switch;
1146         host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
1147         host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
1148         host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
1149         host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
1150
1151         /* R1B responses is required to properly manage HW busy detection. */
1152         mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
1153
1154         ret = sdhci_setup_host(host);
1155         if (ret)
1156                 goto err_put_sync;
1157
1158         ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1159         if (ret)
1160                 goto err_cleanup_host;
1161
1162         ret = __sdhci_add_host(host);
1163         if (ret)
1164                 goto err_cleanup_host;
1165
1166         return 0;
1167
1168 err_cleanup_host:
1169         sdhci_cleanup_host(host);
1170
1171 err_put_sync:
1172         pm_runtime_put_sync(dev);
1173
1174 err_rpm_disable:
1175         pm_runtime_disable(dev);
1176
1177 err_pltfm_free:
1178         sdhci_pltfm_free(pdev);
1179         return ret;
1180 }
1181
1182 static int sdhci_omap_remove(struct platform_device *pdev)
1183 {
1184         struct device *dev = &pdev->dev;
1185         struct sdhci_host *host = platform_get_drvdata(pdev);
1186
1187         sdhci_remove_host(host, true);
1188         pm_runtime_put_sync(dev);
1189         pm_runtime_disable(dev);
1190         sdhci_pltfm_free(pdev);
1191
1192         return 0;
1193 }
1194
1195 static struct platform_driver sdhci_omap_driver = {
1196         .probe = sdhci_omap_probe,
1197         .remove = sdhci_omap_remove,
1198         .driver = {
1199                    .name = "sdhci-omap",
1200                    .of_match_table = omap_sdhci_match,
1201                   },
1202 };
1203
1204 module_platform_driver(sdhci_omap_driver);
1205
1206 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1207 MODULE_AUTHOR("Texas Instruments Inc.");
1208 MODULE_LICENSE("GPL v2");
1209 MODULE_ALIAS("platform:sdhci_omap");