drivers/mmc/host/sdhci-pci-o2micro.c

   1 /*
   2  * Copyright (C) 2013 BayHub Technology Ltd.
   3  *
   4  * Authors: Peter Guo <peter.guo@bayhubtech.com>
   5  *          Adam Lee <adam.lee@canonical.com>
   6  *          Ernest Zhang <ernest.zhang@bayhubtech.com>
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/pci.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/mmc.h>
  22 #include <linux/delay.h>
  23
  24 #include "sdhci.h"
  25 #include "sdhci-pci.h"
  26
  27 /*
  28  * O2Micro device registers
  29  */
  30
  31 #define O2_SD_MISC_REG5         0x64
  32 #define O2_SD_LD0_CTRL          0x68
  33 #define O2_SD_DEV_CTRL          0x88
  34 #define O2_SD_LOCK_WP           0xD3
  35 #define O2_SD_TEST_REG          0xD4
  36 #define O2_SD_FUNC_REG0         0xDC
  37 #define O2_SD_MULTI_VCC3V       0xEE
  38 #define O2_SD_CLKREQ            0xEC
  39 #define O2_SD_CAPS              0xE0
  40 #define O2_SD_ADMA1             0xE2
  41 #define O2_SD_ADMA2             0xE7
  42 #define O2_SD_INF_MOD           0xF1
  43 #define O2_SD_MISC_CTRL4        0xFC
  44 #define O2_SD_TUNING_CTRL       0x300
  45 #define O2_SD_PLL_SETTING       0x304
  46 #define O2_SD_MISC_SETTING      0x308
  47 #define O2_SD_CLK_SETTING       0x328
  48 #define O2_SD_CAP_REG2          0x330
  49 #define O2_SD_CAP_REG0          0x334
  50 #define O2_SD_UHS1_CAP_SETTING  0x33C
  51 #define O2_SD_DELAY_CTRL        0x350
  52 #define O2_SD_UHS2_L1_CTRL      0x35C
  53 #define O2_SD_FUNC_REG3         0x3E0
  54 #define O2_SD_FUNC_REG4         0x3E4
  55 #define O2_SD_LED_ENABLE        BIT(6)
  56 #define O2_SD_FREG0_LEDOFF      BIT(13)
  57 #define O2_SD_FREG4_ENABLE_CLK_SET      BIT(22)
  58
  59 #define O2_SD_VENDOR_SETTING    0x110
  60 #define O2_SD_VENDOR_SETTING2   0x1C8
  61 #define O2_SD_HW_TUNING_DISABLE BIT(4)
  62
  63 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
  64 {
  65         u16 reg;
  66
  67         /* enable hardware tuning */
  68         reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
  69         reg &= ~O2_SD_HW_TUNING_DISABLE;
  70         sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
  71 }
  72
  73 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
  74 {
  75         int i;
  76
  77         sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200);
  78
  79         for (i = 0; i < 150; i++) {
  80                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  81
  82                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
  83                         if (ctrl & SDHCI_CTRL_TUNED_CLK) {
  84                                 host->tuning_done = true;
  85                                 return;
  86                         }
  87                         pr_warn("%s: HW tuning failed !\n",
  88                                 mmc_hostname(host->mmc));
  89                         break;
  90                 }
  91
  92                 mdelay(1);
  93         }
  94
  95         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
  96                 mmc_hostname(host->mmc));
  97         sdhci_reset_tuning(host);
  98 }
  99
 100 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
 101 {
 102         struct sdhci_host *host = mmc_priv(mmc);
 103         int current_bus_width = 0;
 104
 105         /*
 106          * This handler only implements the eMMC tuning that is specific to
 107          * this controller.  Fall back to the standard method for other TIMING.
 108          */
 109         if (host->timing != MMC_TIMING_MMC_HS200)
 110                 return sdhci_execute_tuning(mmc, opcode);
 111
 112         if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
 113                 return -EINVAL;
 114
 115         /*
 116          * o2 sdhci host didn't support 8bit emmc tuning
 117          */
 118         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
 119                 current_bus_width = mmc->ios.bus_width;
 120                 mmc->ios.bus_width = MMC_BUS_WIDTH_4;
 121                 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
 122         }
 123
 124         sdhci_o2_set_tuning_mode(host);
 125
 126         sdhci_start_tuning(host);
 127
 128         __sdhci_o2_execute_tuning(host, opcode);
 129
 130         sdhci_end_tuning(host);
 131
 132         if (current_bus_width == MMC_BUS_WIDTH_8) {
 133                 mmc->ios.bus_width = MMC_BUS_WIDTH_8;
 134                 sdhci_set_bus_width(host, current_bus_width);
 135         }
 136
 137         host->flags &= ~SDHCI_HS400_TUNING;
 138         return 0;
 139 }
 140
 141 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
 142 {
 143         u32 scratch_32;
 144         pci_read_config_dword(chip->pdev,
 145                               O2_SD_PLL_SETTING, &scratch_32);
 146
 147         scratch_32 &= 0x0000FFFF;
 148         scratch_32 |= value;
 149
 150         pci_write_config_dword(chip->pdev,
 151                                O2_SD_PLL_SETTING, scratch_32);
 152 }
 153
 154 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
 155 {
 156         int ret;
 157         u32 scratch_32;
 158
 159         /* Set led of SD host function enable */
 160         ret = pci_read_config_dword(chip->pdev,
 161                                     O2_SD_FUNC_REG0, &scratch_32);
 162         if (ret)
 163                 return;
 164
 165         scratch_32 &= ~O2_SD_FREG0_LEDOFF;
 166         pci_write_config_dword(chip->pdev,
 167                                O2_SD_FUNC_REG0, scratch_32);
 168
 169         ret = pci_read_config_dword(chip->pdev,
 170                                     O2_SD_TEST_REG, &scratch_32);
 171         if (ret)
 172                 return;
 173
 174         scratch_32 |= O2_SD_LED_ENABLE;
 175         pci_write_config_dword(chip->pdev,
 176                                O2_SD_TEST_REG, scratch_32);
 177
 178 }
 179
 180 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
 181 {
 182         u32 scratch_32;
 183         int ret;
 184         /* Improve write performance for SD3.0 */
 185         ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
 186         if (ret)
 187                 return;
 188         scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
 189         pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
 190
 191         /* Enable Link abnormal reset generating Reset */
 192         ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
 193         if (ret)
 194                 return;
 195         scratch_32 &= ~((1 << 19) | (1 << 11));
 196         scratch_32 |= (1 << 10);
 197         pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
 198
 199         /* set card power over current protection */
 200         ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
 201         if (ret)
 202                 return;
 203         scratch_32 |= (1 << 4);
 204         pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
 205
 206         /* adjust the output delay for SD mode */
 207         pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
 208
 209         /* Set the output voltage setting of Aux 1.2v LDO */
 210         ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
 211         if (ret)
 212                 return;
 213         scratch_32 &= ~(3 << 12);
 214         pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
 215
 216         /* Set Max power supply capability of SD host */
 217         ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
 218         if (ret)
 219                 return;
 220         scratch_32 &= ~(0x01FE);
 221         scratch_32 |= 0x00CC;
 222         pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
 223         /* Set DLL Tuning Window */
 224         ret = pci_read_config_dword(chip->pdev,
 225                                     O2_SD_TUNING_CTRL, &scratch_32);
 226         if (ret)
 227                 return;
 228         scratch_32 &= ~(0x000000FF);
 229         scratch_32 |= 0x00000066;
 230         pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
 231
 232         /* Set UHS2 T_EIDLE */
 233         ret = pci_read_config_dword(chip->pdev,
 234                                     O2_SD_UHS2_L1_CTRL, &scratch_32);
 235         if (ret)
 236                 return;
 237         scratch_32 &= ~(0x000000FC);
 238         scratch_32 |= 0x00000084;
 239         pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
 240
 241         /* Set UHS2 Termination */
 242         ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
 243         if (ret)
 244                 return;
 245         scratch_32 &= ~((1 << 21) | (1 << 30));
 246
 247         pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
 248
 249         /* Set L1 Entrance Timer */
 250         ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
 251         if (ret)
 252                 return;
 253         scratch_32 &= ~(0xf0000000);
 254         scratch_32 |= 0x30000000;
 255         pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
 256
 257         ret = pci_read_config_dword(chip->pdev,
 258                                     O2_SD_MISC_CTRL4, &scratch_32);
 259         if (ret)
 260                 return;
 261         scratch_32 &= ~(0x000f0000);
 262         scratch_32 |= 0x00080000;
 263         pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
 264 }
 265
 266 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
 267                                     struct sdhci_host *host)
 268 {
 269         int ret;
 270
 271         ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
 272         if (!ret) {
 273                 pr_info("%s: unsupport msi, use INTx irq\n",
 274                         mmc_hostname(host->mmc));
 275                 return;
 276         }
 277
 278         ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
 279                                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
 280         if (ret < 0) {
 281                 pr_err("%s: enable PCI MSI failed, err=%d\n",
 282                        mmc_hostname(host->mmc), ret);
 283                 return;
 284         }
 285
 286         host->irq = pci_irq_vector(chip->pdev, 0);
 287 }
 288
 289 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
 290 {
 291         struct sdhci_pci_chip *chip;
 292         struct sdhci_host *host;
 293         u32 reg, caps;
 294         int ret;
 295
 296         chip = slot->chip;
 297         host = slot->host;
 298
 299         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 300
 301         /*
 302          * mmc_select_bus_width() will test the bus to determine the actual bus
 303          * width.
 304          */
 305         if (caps & SDHCI_CAN_DO_8BIT)
 306                 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 307
 308         switch (chip->pdev->device) {
 309         case PCI_DEVICE_ID_O2_SDS0:
 310         case PCI_DEVICE_ID_O2_SEABIRD0:
 311         case PCI_DEVICE_ID_O2_SEABIRD1:
 312         case PCI_DEVICE_ID_O2_SDS1:
 313         case PCI_DEVICE_ID_O2_FUJIN2:
 314                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
 315                 if (reg & 0x1)
 316                         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 317
 318                 sdhci_pci_o2_enable_msi(chip, host);
 319
 320                 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
 321                         ret = pci_read_config_dword(chip->pdev,
 322                                                     O2_SD_MISC_SETTING, &reg);
 323                         if (ret)
 324                                 return -EIO;
 325                         if (reg & (1 << 4)) {
 326                                 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
 327                                         mmc_hostname(host->mmc));
 328                                 host->flags &= ~SDHCI_SIGNALING_330;
 329                                 host->flags |= SDHCI_SIGNALING_180;
 330                                 host->mmc->caps2 |= MMC_CAP2_NO_SD;
 331                                 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 332                         }
 333                 }
 334
 335                 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
 336
 337                 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
 338                         break;
 339                 /* set dll watch dog timer */
 340                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
 341                 reg |= (1 << 12);
 342                 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
 343
 344                 break;
 345         default:
 346                 break;
 347         }
 348
 349         return 0;
 350 }
 351
 352 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
 353 {
 354         int ret;
 355         u8 scratch;
 356         u32 scratch_32;
 357
 358         switch (chip->pdev->device) {
 359         case PCI_DEVICE_ID_O2_8220:
 360         case PCI_DEVICE_ID_O2_8221:
 361         case PCI_DEVICE_ID_O2_8320:
 362         case PCI_DEVICE_ID_O2_8321:
 363                 /* This extra setup is required due to broken ADMA. */
 364                 ret = pci_read_config_byte(chip->pdev,
 365                                 O2_SD_LOCK_WP, &scratch);
 366                 if (ret)
 367                         return ret;
 368                 scratch &= 0x7f;
 369                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 370
 371                 /* Set Multi 3 to VCC3V# */
 372                 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
 373
 374                 /* Disable CLK_REQ# support after media DET */
 375                 ret = pci_read_config_byte(chip->pdev,
 376                                 O2_SD_CLKREQ, &scratch);
 377                 if (ret)
 378                         return ret;
 379                 scratch |= 0x20;
 380                 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
 381
 382                 /* Choose capabilities, enable SDMA.  We have to write 0x01
 383                  * to the capabilities register first to unlock it.
 384                  */
 385                 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
 386                 if (ret)
 387                         return ret;
 388                 scratch |= 0x01;
 389                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
 390                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
 391
 392                 /* Disable ADMA1/2 */
 393                 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
 394                 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
 395
 396                 /* Disable the infinite transfer mode */
 397                 ret = pci_read_config_byte(chip->pdev,
 398                                 O2_SD_INF_MOD, &scratch);
 399                 if (ret)
 400                         return ret;
 401                 scratch |= 0x08;
 402                 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
 403
 404                 /* Lock WP */
 405                 ret = pci_read_config_byte(chip->pdev,
 406                                 O2_SD_LOCK_WP, &scratch);
 407                 if (ret)
 408                         return ret;
 409                 scratch |= 0x80;
 410                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 411                 break;
 412         case PCI_DEVICE_ID_O2_SDS0:
 413         case PCI_DEVICE_ID_O2_SDS1:
 414         case PCI_DEVICE_ID_O2_FUJIN2:
 415                 /* UnLock WP */
 416                 ret = pci_read_config_byte(chip->pdev,
 417                                 O2_SD_LOCK_WP, &scratch);
 418                 if (ret)
 419                         return ret;
 420
 421                 scratch &= 0x7f;
 422                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 423
 424                 /* DevId=8520 subId= 0x11 or 0x12  Type Chip support */
 425                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
 426                         ret = pci_read_config_dword(chip->pdev,
 427                                                     O2_SD_FUNC_REG0,
 428                                                     &scratch_32);
 429                         scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
 430
 431                         /* Check Whether subId is 0x11 or 0x12 */
 432                         if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
 433                                 scratch_32 = 0x25100000;
 434
 435                                 o2_pci_set_baseclk(chip, scratch_32);
 436                                 ret = pci_read_config_dword(chip->pdev,
 437                                                             O2_SD_FUNC_REG4,
 438                                                             &scratch_32);
 439
 440                                 /* Enable Base Clk setting change */
 441                                 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
 442                                 pci_write_config_dword(chip->pdev,
 443                                                        O2_SD_FUNC_REG4,
 444                                                        scratch_32);
 445
 446                                 /* Set Tuning Window to 4 */
 447                                 pci_write_config_byte(chip->pdev,
 448                                                       O2_SD_TUNING_CTRL, 0x44);
 449
 450                                 break;
 451                         }
 452                 }
 453
 454                 /* Enable 8520 led function */
 455                 o2_pci_led_enable(chip);
 456
 457                 /* Set timeout CLK */
 458                 ret = pci_read_config_dword(chip->pdev,
 459                                             O2_SD_CLK_SETTING, &scratch_32);
 460                 if (ret)
 461                         return ret;
 462
 463                 scratch_32 &= ~(0xFF00);
 464                 scratch_32 |= 0x07E0C800;
 465                 pci_write_config_dword(chip->pdev,
 466                                        O2_SD_CLK_SETTING, scratch_32);
 467
 468                 ret = pci_read_config_dword(chip->pdev,
 469                                             O2_SD_CLKREQ, &scratch_32);
 470                 if (ret)
 471                         return ret;
 472                 scratch_32 |= 0x3;
 473                 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
 474
 475                 ret = pci_read_config_dword(chip->pdev,
 476                                             O2_SD_PLL_SETTING, &scratch_32);
 477                 if (ret)
 478                         return ret;
 479
 480                 scratch_32 &= ~(0x1F3F070E);
 481                 scratch_32 |= 0x18270106;
 482                 pci_write_config_dword(chip->pdev,
 483                                        O2_SD_PLL_SETTING, scratch_32);
 484
 485                 /* Disable UHS1 funciton */
 486                 ret = pci_read_config_dword(chip->pdev,
 487                                             O2_SD_CAP_REG2, &scratch_32);
 488                 if (ret)
 489                         return ret;
 490                 scratch_32 &= ~(0xE0);
 491                 pci_write_config_dword(chip->pdev,
 492                                        O2_SD_CAP_REG2, scratch_32);
 493
 494                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
 495                         sdhci_pci_o2_fujin2_pci_init(chip);
 496
 497                 /* Lock WP */
 498                 ret = pci_read_config_byte(chip->pdev,
 499                                            O2_SD_LOCK_WP, &scratch);
 500                 if (ret)
 501                         return ret;
 502                 scratch |= 0x80;
 503                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 504                 break;
 505         case PCI_DEVICE_ID_O2_SEABIRD0:
 506                 if (chip->pdev->revision == 0x01)
 507                         chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
 508                 /* fall through */
 509         case PCI_DEVICE_ID_O2_SEABIRD1:
 510                 /* UnLock WP */
 511                 ret = pci_read_config_byte(chip->pdev,
 512                                 O2_SD_LOCK_WP, &scratch);
 513                 if (ret)
 514                         return ret;
 515
 516                 scratch &= 0x7f;
 517                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 518
 519                 ret = pci_read_config_dword(chip->pdev,
 520                                             O2_SD_PLL_SETTING, &scratch_32);
 521
 522                 if ((scratch_32 & 0xff000000) == 0x01000000) {
 523                         scratch_32 &= 0x0000FFFF;
 524                         scratch_32 |= 0x1F340000;
 525
 526                         pci_write_config_dword(chip->pdev,
 527                                                O2_SD_PLL_SETTING, scratch_32);
 528                 } else {
 529                         scratch_32 &= 0x0000FFFF;
 530                         scratch_32 |= 0x25100000;
 531
 532                         pci_write_config_dword(chip->pdev,
 533                                                O2_SD_PLL_SETTING, scratch_32);
 534
 535                         ret = pci_read_config_dword(chip->pdev,
 536                                                     O2_SD_FUNC_REG4,
 537                                                     &scratch_32);
 538                         scratch_32 |= (1 << 22);
 539                         pci_write_config_dword(chip->pdev,
 540                                                O2_SD_FUNC_REG4, scratch_32);
 541                 }
 542
 543                 /* Set Tuning Windows to 5 */
 544                 pci_write_config_byte(chip->pdev,
 545                                 O2_SD_TUNING_CTRL, 0x55);
 546                 /* Lock WP */
 547                 ret = pci_read_config_byte(chip->pdev,
 548                                            O2_SD_LOCK_WP, &scratch);
 549                 if (ret)
 550                         return ret;
 551                 scratch |= 0x80;
 552                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 553                 break;
 554         }
 555
 556         return 0;
 557 }
 558
 559 #ifdef CONFIG_PM_SLEEP
 560 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
 561 {
 562         sdhci_pci_o2_probe(chip);
 563         return sdhci_pci_resume_host(chip);
 564 }
 565 #endif