drivers/mmc/host/sdhci-xenon.c

   1 /*
   2  * Driver for Marvell Xenon SDHC as a platform device
   3  *
   4  * Copyright (C) 2016 Marvell, All Rights Reserved.
   5  *
   6  * Author:      Hu Ziji <huziji@marvell.com>
   7  * Date:        2016-8-24
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * Inspired by Jisheng Zhang <jszhang@marvell.com>
  14  * Special thanks to Video BG4 project team.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/ktime.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/pm.h>
  22 #include <linux/pm_runtime.h>
  23
  24 #include "sdhci-pltfm.h"
  25 #include "sdhci-xenon.h"
  26
  27 static int xenon_enable_internal_clk(struct sdhci_host *host)
  28 {
  29         u32 reg;
  30         ktime_t timeout;
  31
  32         reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
  33         reg |= SDHCI_CLOCK_INT_EN;
  34         sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
  35         /* Wait max 20 ms */
  36         timeout = ktime_add_ms(ktime_get(), 20);
  37         while (1) {
  38                 bool timedout = ktime_after(ktime_get(), timeout);
  39
  40                 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  41                 if (reg & SDHCI_CLOCK_INT_STABLE)
  42                         break;
  43                 if (timedout) {
  44                         dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n");
  45                         return -ETIMEDOUT;
  46                 }
  47                 usleep_range(900, 1100);
  48         }
  49
  50         return 0;
  51 }
  52
  53 /* Set SDCLK-off-while-idle */
  54 static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
  55                                      unsigned char sdhc_id, bool enable)
  56 {
  57         u32 reg;
  58         u32 mask;
  59
  60         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  61         /* Get the bit shift basing on the SDHC index */
  62         mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
  63         if (enable)
  64                 reg |= mask;
  65         else
  66                 reg &= ~mask;
  67
  68         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  69 }
  70
  71 /* Enable/Disable the Auto Clock Gating function */
  72 static void xenon_set_acg(struct sdhci_host *host, bool enable)
  73 {
  74         u32 reg;
  75
  76         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  77         if (enable)
  78                 reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
  79         else
  80                 reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
  81         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  82 }
  83
  84 /* Enable this SDHC */
  85 static void xenon_enable_sdhc(struct sdhci_host *host,
  86                               unsigned char sdhc_id)
  87 {
  88         u32 reg;
  89
  90         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  91         reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
  92         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  93
  94         host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
  95         /*
  96          * Force to clear BUS_TEST to
  97          * skip bus_test_pre and bus_test_post
  98          */
  99         host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
 100 }
 101
 102 /* Disable this SDHC */
 103 static void xenon_disable_sdhc(struct sdhci_host *host,
 104                                unsigned char sdhc_id)
 105 {
 106         u32 reg;
 107
 108         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
 109         reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
 110         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
 111 }
 112
 113 /* Enable Parallel Transfer Mode */
 114 static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
 115                                             unsigned char sdhc_id)
 116 {
 117         u32 reg;
 118
 119         reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
 120         reg |= BIT(sdhc_id);
 121         sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
 122 }
 123
 124 /* Mask command conflict error */
 125 static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
 126 {
 127         u32  reg;
 128
 129         reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
 130         reg |= XENON_MASK_CMD_CONFLICT_ERR;
 131         sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
 132 }
 133
 134 static void xenon_retune_setup(struct sdhci_host *host)
 135 {
 136         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 137         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 138         u32 reg;
 139
 140         /* Disable the Re-Tuning Request functionality */
 141         reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
 142         reg &= ~XENON_RETUNING_COMPATIBLE;
 143         sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
 144
 145         /* Disable the Re-tuning Interrupt */
 146         reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
 147         reg &= ~SDHCI_INT_RETUNE;
 148         sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
 149         reg = sdhci_readl(host, SDHCI_INT_ENABLE);
 150         reg &= ~SDHCI_INT_RETUNE;
 151         sdhci_writel(host, reg, SDHCI_INT_ENABLE);
 152
 153         /* Force to use Tuning Mode 1 */
 154         host->tuning_mode = SDHCI_TUNING_MODE_1;
 155         /* Set re-tuning period */
 156         host->tuning_count = 1 << (priv->tuning_count - 1);
 157 }
 158
 159 /*
 160  * Operations inside struct sdhci_ops
 161  */
 162 /* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
 163 static void xenon_reset_exit(struct sdhci_host *host,
 164                              unsigned char sdhc_id, u8 mask)
 165 {
 166         /* Only SOFTWARE RESET ALL will clear the register setting */
 167         if (!(mask & SDHCI_RESET_ALL))
 168                 return;
 169
 170         /* Disable tuning request and auto-retuning again */
 171         xenon_retune_setup(host);
 172
 173         /*
 174          * The ACG should be turned off at the early init time, in order
 175          * to solve a possible issues with the 1.8V regulator stabilization.
 176          * The feature is enabled in later stage.
 177          */
 178         xenon_set_acg(host, false);
 179
 180         xenon_set_sdclk_off_idle(host, sdhc_id, false);
 181
 182         xenon_mask_cmd_conflict_err(host);
 183 }
 184
 185 static void xenon_reset(struct sdhci_host *host, u8 mask)
 186 {
 187         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 188         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 189
 190         sdhci_reset(host, mask);
 191         xenon_reset_exit(host, priv->sdhc_id, mask);
 192 }
 193
 194 /*
 195  * Xenon defines different values for HS200 and HS400
 196  * in Host_Control_2
 197  */
 198 static void xenon_set_uhs_signaling(struct sdhci_host *host,
 199                                     unsigned int timing)
 200 {
 201         u16 ctrl_2;
 202
 203         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 204         /* Select Bus Speed Mode for host */
 205         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 206         if (timing == MMC_TIMING_MMC_HS200)
 207                 ctrl_2 |= XENON_CTRL_HS200;
 208         else if (timing == MMC_TIMING_UHS_SDR104)
 209                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 210         else if (timing == MMC_TIMING_UHS_SDR12)
 211                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 212         else if (timing == MMC_TIMING_UHS_SDR25)
 213                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 214         else if (timing == MMC_TIMING_UHS_SDR50)
 215                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 216         else if ((timing == MMC_TIMING_UHS_DDR50) ||
 217                  (timing == MMC_TIMING_MMC_DDR52))
 218                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 219         else if (timing == MMC_TIMING_MMC_HS400)
 220                 ctrl_2 |= XENON_CTRL_HS400;
 221         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 222 }
 223
 224 static void xenon_set_power(struct sdhci_host *host, unsigned char mode,
 225                 unsigned short vdd)
 226 {
 227         struct mmc_host *mmc = host->mmc;
 228         u8 pwr = host->pwr;
 229
 230         sdhci_set_power_noreg(host, mode, vdd);
 231
 232         if (host->pwr == pwr)
 233                 return;
 234
 235         if (host->pwr == 0)
 236                 vdd = 0;
 237
 238         if (!IS_ERR(mmc->supply.vmmc))
 239                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 240 }
 241
 242 static void xenon_voltage_switch(struct sdhci_host *host)
 243 {
 244         /* Wait for 5ms after set 1.8V signal enable bit */
 245         usleep_range(5000, 5500);
 246 }
 247
 248 static const struct sdhci_ops sdhci_xenon_ops = {
 249         .voltage_switch         = xenon_voltage_switch,
 250         .set_clock              = sdhci_set_clock,
 251         .set_power              = xenon_set_power,
 252         .set_bus_width          = sdhci_set_bus_width,
 253         .reset                  = xenon_reset,
 254         .set_uhs_signaling      = xenon_set_uhs_signaling,
 255         .get_max_clock          = sdhci_pltfm_clk_get_max_clock,
 256 };
 257
 258 static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
 259         .ops = &sdhci_xenon_ops,
 260         .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
 261                   SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
 262                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 263 };
 264
 265 /*
 266  * Xenon Specific Operations in mmc_host_ops
 267  */
 268 static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 269 {
 270         struct sdhci_host *host = mmc_priv(mmc);
 271         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 272         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 273         u32 reg;
 274
 275         /*
 276          * HS400/HS200/eMMC HS doesn't have Preset Value register.
 277          * However, sdhci_set_ios will read HS400/HS200 Preset register.
 278          * Disable Preset Value register for HS400/HS200.
 279          * eMMC HS with preset_enabled set will trigger a bug in
 280          * get_preset_value().
 281          */
 282         if ((ios->timing == MMC_TIMING_MMC_HS400) ||
 283             (ios->timing == MMC_TIMING_MMC_HS200) ||
 284             (ios->timing == MMC_TIMING_MMC_HS)) {
 285                 host->preset_enabled = false;
 286                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 287                 host->flags &= ~SDHCI_PV_ENABLED;
 288
 289                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 290                 reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 291                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 292         } else {
 293                 host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 294         }
 295
 296         sdhci_set_ios(mmc, ios);
 297         xenon_phy_adj(host, ios);
 298
 299         if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
 300                 xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
 301 }
 302
 303 static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
 304                                              struct mmc_ios *ios)
 305 {
 306         struct sdhci_host *host = mmc_priv(mmc);
 307
 308         /*
 309          * Before SD/SDIO set signal voltage, SD bus clock should be
 310          * disabled. However, sdhci_set_clock will also disable the Internal
 311          * clock in mmc_set_signal_voltage().
 312          * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
 313          * Thus here manually enable internal clock.
 314          *
 315          * After switch completes, it is unnecessary to disable internal clock,
 316          * since keeping internal clock active obeys SD spec.
 317          */
 318         xenon_enable_internal_clk(host);
 319
 320         xenon_soc_pad_ctrl(host, ios->signal_voltage);
 321
 322         /*
 323          * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable.
 324          * Thus SDHCI_CTRL_VDD_180 bit might not work then.
 325          * Skip the standard voltage switch to avoid any issue.
 326          */
 327         if (PTR_ERR(mmc->supply.vqmmc) == -ENODEV)
 328                 return 0;
 329
 330         return sdhci_start_signal_voltage_switch(mmc, ios);
 331 }
 332
 333 /*
 334  * Update card type.
 335  * priv->init_card_type will be used in PHY timing adjustment.
 336  */
 337 static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
 338 {
 339         struct sdhci_host *host = mmc_priv(mmc);
 340         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 341         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 342
 343         /* Update card type*/
 344         priv->init_card_type = card->type;
 345 }
 346
 347 static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
 348 {
 349         struct sdhci_host *host = mmc_priv(mmc);
 350
 351         if (host->timing == MMC_TIMING_UHS_DDR50 ||
 352                 host->timing == MMC_TIMING_MMC_DDR52)
 353                 return 0;
 354
 355         /*
 356          * Currently force Xenon driver back to support mode 1 only,
 357          * even though Xenon might claim to support mode 2 or mode 3.
 358          * It requires more time to test mode 2/mode 3 on more platforms.
 359          */
 360         if (host->tuning_mode != SDHCI_TUNING_MODE_1)
 361                 xenon_retune_setup(host);
 362
 363         return sdhci_execute_tuning(mmc, opcode);
 364 }
 365
 366 static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
 367 {
 368         struct sdhci_host *host = mmc_priv(mmc);
 369         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 370         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 371         u32 reg;
 372         u8 sdhc_id = priv->sdhc_id;
 373
 374         sdhci_enable_sdio_irq(mmc, enable);
 375
 376         if (enable) {
 377                 /*
 378                  * Set SDIO Card Inserted indication
 379                  * to enable detecting SDIO async irq.
 380                  */
 381                 reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
 382                 reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
 383                 sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
 384         } else {
 385                 /* Clear SDIO Card Inserted indication */
 386                 reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
 387                 reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
 388                 sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
 389         }
 390 }
 391
 392 static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
 393 {
 394         host->mmc_host_ops.set_ios = xenon_set_ios;
 395         host->mmc_host_ops.start_signal_voltage_switch =
 396                         xenon_start_signal_voltage_switch;
 397         host->mmc_host_ops.init_card = xenon_init_card;
 398         host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
 399         host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
 400 }
 401
 402 /*
 403  * Parse Xenon specific DT properties:
 404  * sdhc-id: the index of current SDHC.
 405  *          Refer to XENON_SYS_CFG_INFO register
 406  * tun-count: the interval between re-tuning
 407  */
 408 static int xenon_probe_dt(struct platform_device *pdev)
 409 {
 410         struct device_node *np = pdev->dev.of_node;
 411         struct sdhci_host *host = platform_get_drvdata(pdev);
 412         struct mmc_host *mmc = host->mmc;
 413         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 414         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 415         u32 sdhc_id, nr_sdhc;
 416         u32 tuning_count;
 417
 418         /* Disable HS200 on Armada AP806 */
 419         if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci"))
 420                 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
 421
 422         sdhc_id = 0x0;
 423         if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
 424                 nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
 425                 nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
 426                 if (unlikely(sdhc_id > nr_sdhc)) {
 427                         dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
 428                                 sdhc_id, nr_sdhc);
 429                         return -EINVAL;
 430                 }
 431         }
 432         priv->sdhc_id = sdhc_id;
 433
 434         tuning_count = XENON_DEF_TUNING_COUNT;
 435         if (!of_property_read_u32(np, "marvell,xenon-tun-count",
 436                                   &tuning_count)) {
 437                 if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
 438                         dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
 439                                 XENON_DEF_TUNING_COUNT);
 440                         tuning_count = XENON_DEF_TUNING_COUNT;
 441                 }
 442         }
 443         priv->tuning_count = tuning_count;
 444
 445         return xenon_phy_parse_dt(np, host);
 446 }
 447
 448 static int xenon_sdhc_prepare(struct sdhci_host *host)
 449 {
 450         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 451         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 452         u8 sdhc_id = priv->sdhc_id;
 453
 454         /* Enable SDHC */
 455         xenon_enable_sdhc(host, sdhc_id);
 456
 457         /* Enable ACG */
 458         xenon_set_acg(host, true);
 459
 460         /* Enable Parallel Transfer Mode */
 461         xenon_enable_sdhc_parallel_tran(host, sdhc_id);
 462
 463         /* Disable SDCLK-Off-While-Idle before card init */
 464         xenon_set_sdclk_off_idle(host, sdhc_id, false);
 465
 466         xenon_mask_cmd_conflict_err(host);
 467
 468         return 0;
 469 }
 470
 471 static void xenon_sdhc_unprepare(struct sdhci_host *host)
 472 {
 473         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 474         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 475         u8 sdhc_id = priv->sdhc_id;
 476
 477         /* disable SDHC */
 478         xenon_disable_sdhc(host, sdhc_id);
 479 }
 480
 481 static int xenon_probe(struct platform_device *pdev)
 482 {
 483         struct sdhci_pltfm_host *pltfm_host;
 484         struct sdhci_host *host;
 485         struct xenon_priv *priv;
 486         int err;
 487
 488         host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
 489                                 sizeof(struct xenon_priv));
 490         if (IS_ERR(host))
 491                 return PTR_ERR(host);
 492
 493         pltfm_host = sdhci_priv(host);
 494         priv = sdhci_pltfm_priv(pltfm_host);
 495
 496         /*
 497          * Link Xenon specific mmc_host_ops function,
 498          * to replace standard ones in sdhci_ops.
 499          */
 500         xenon_replace_mmc_host_ops(host);
 501
 502         pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
 503         if (IS_ERR(pltfm_host->clk)) {
 504                 err = PTR_ERR(pltfm_host->clk);
 505                 dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
 506                 goto free_pltfm;
 507         }
 508         err = clk_prepare_enable(pltfm_host->clk);
 509         if (err)
 510                 goto free_pltfm;
 511
 512         priv->axi_clk = devm_clk_get(&pdev->dev, "axi");
 513         if (IS_ERR(priv->axi_clk)) {
 514                 err = PTR_ERR(priv->axi_clk);
 515                 if (err == -EPROBE_DEFER)
 516                         goto err_clk;
 517         } else {
 518                 err = clk_prepare_enable(priv->axi_clk);
 519                 if (err)
 520                         goto err_clk;
 521         }
 522
 523         err = mmc_of_parse(host->mmc);
 524         if (err)
 525                 goto err_clk_axi;
 526
 527         sdhci_get_of_property(pdev);
 528
 529         xenon_set_acg(host, false);
 530
 531         /* Xenon specific dt parse */
 532         err = xenon_probe_dt(pdev);
 533         if (err)
 534                 goto err_clk_axi;
 535
 536         err = xenon_sdhc_prepare(host);
 537         if (err)
 538                 goto err_clk_axi;
 539
 540         pm_runtime_get_noresume(&pdev->dev);
 541         pm_runtime_set_active(&pdev->dev);
 542         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 543         pm_runtime_use_autosuspend(&pdev->dev);
 544         pm_runtime_enable(&pdev->dev);
 545         pm_suspend_ignore_children(&pdev->dev, 1);
 546
 547         err = sdhci_add_host(host);
 548         if (err)
 549                 goto remove_sdhc;
 550
 551         pm_runtime_put_autosuspend(&pdev->dev);
 552
 553         return 0;
 554
 555 remove_sdhc:
 556         pm_runtime_disable(&pdev->dev);
 557         pm_runtime_put_noidle(&pdev->dev);
 558         xenon_sdhc_unprepare(host);
 559 err_clk_axi:
 560         clk_disable_unprepare(priv->axi_clk);
 561 err_clk:
 562         clk_disable_unprepare(pltfm_host->clk);
 563 free_pltfm:
 564         sdhci_pltfm_free(pdev);
 565         return err;
 566 }
 567
 568 static int xenon_remove(struct platform_device *pdev)
 569 {
 570         struct sdhci_host *host = platform_get_drvdata(pdev);
 571         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 572         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 573
 574         pm_runtime_get_sync(&pdev->dev);
 575         pm_runtime_disable(&pdev->dev);
 576         pm_runtime_put_noidle(&pdev->dev);
 577
 578         sdhci_remove_host(host, 0);
 579
 580         xenon_sdhc_unprepare(host);
 581         clk_disable_unprepare(priv->axi_clk);
 582         clk_disable_unprepare(pltfm_host->clk);
 583
 584         sdhci_pltfm_free(pdev);
 585
 586         return 0;
 587 }
 588
 589 #ifdef CONFIG_PM_SLEEP
 590 static int xenon_suspend(struct device *dev)
 591 {
 592         struct sdhci_host *host = dev_get_drvdata(dev);
 593         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 594         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 595         int ret;
 596
 597         ret = pm_runtime_force_suspend(dev);
 598
 599         priv->restore_needed = true;
 600         return ret;
 601 }
 602 #endif
 603
 604 #ifdef CONFIG_PM
 605 static int xenon_runtime_suspend(struct device *dev)
 606 {
 607         struct sdhci_host *host = dev_get_drvdata(dev);
 608         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 609         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 610         int ret;
 611
 612         ret = sdhci_runtime_suspend_host(host);
 613         if (ret)
 614                 return ret;
 615
 616         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 617                 mmc_retune_needed(host->mmc);
 618
 619         clk_disable_unprepare(pltfm_host->clk);
 620         /*
 621          * Need to update the priv->clock here, or when runtime resume
 622          * back, phy don't aware the clock change and won't adjust phy
 623          * which will cause cmd err
 624          */
 625         priv->clock = 0;
 626         return 0;
 627 }
 628
 629 static int xenon_runtime_resume(struct device *dev)
 630 {
 631         struct sdhci_host *host = dev_get_drvdata(dev);
 632         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 633         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 634         int ret;
 635
 636         ret = clk_prepare_enable(pltfm_host->clk);
 637         if (ret) {
 638                 dev_err(dev, "can't enable mainck\n");
 639                 return ret;
 640         }
 641
 642         if (priv->restore_needed) {
 643                 ret = xenon_sdhc_prepare(host);
 644                 if (ret)
 645                         goto out;
 646                 priv->restore_needed = false;
 647         }
 648
 649         ret = sdhci_runtime_resume_host(host);
 650         if (ret)
 651                 goto out;
 652         return 0;
 653 out:
 654         clk_disable_unprepare(pltfm_host->clk);
 655         return ret;
 656 }
 657 #endif /* CONFIG_PM */
 658
 659 static const struct dev_pm_ops sdhci_xenon_dev_pm_ops = {
 660         SET_SYSTEM_SLEEP_PM_OPS(xenon_suspend,
 661                                 pm_runtime_force_resume)
 662         SET_RUNTIME_PM_OPS(xenon_runtime_suspend,
 663                            xenon_runtime_resume,
 664                            NULL)
 665 };
 666
 667 static const struct of_device_id sdhci_xenon_dt_ids[] = {
 668         { .compatible = "marvell,armada-ap806-sdhci",},
 669         { .compatible = "marvell,armada-cp110-sdhci",},
 670         { .compatible = "marvell,armada-3700-sdhci",},
 671         {}
 672 };
 673 MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
 674
 675 static struct platform_driver sdhci_xenon_driver = {
 676         .driver = {
 677                 .name   = "xenon-sdhci",
 678                 .of_match_table = sdhci_xenon_dt_ids,
 679                 .pm = &sdhci_xenon_dev_pm_ops,
 680         },
 681         .probe  = xenon_probe,
 682         .remove = xenon_remove,
 683 };
 684
 685 module_platform_driver(sdhci_xenon_driver);
 686
 687 MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
 688 MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
 689 MODULE_LICENSE("GPL v2");