drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/slot-gpio.h>
  33
  34 #include "sdhci.h"
  35
  36 #define DRIVER_NAME "sdhci"
  37
  38 #define DBG(f, x...) \
  39         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  40
  41 #define MAX_TUNING_LOOP 40
  42
  43 static unsigned int debug_quirks = 0;
  44 static unsigned int debug_quirks2;
  45
  46 static void sdhci_finish_data(struct sdhci_host *);
  47
  48 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  49
  50 static void sdhci_dumpregs(struct sdhci_host *host)
  51 {
  52         pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  53                mmc_hostname(host->mmc));
  54
  55         pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  56                sdhci_readl(host, SDHCI_DMA_ADDRESS),
  57                sdhci_readw(host, SDHCI_HOST_VERSION));
  58         pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  59                sdhci_readw(host, SDHCI_BLOCK_SIZE),
  60                sdhci_readw(host, SDHCI_BLOCK_COUNT));
  61         pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  62                sdhci_readl(host, SDHCI_ARGUMENT),
  63                sdhci_readw(host, SDHCI_TRANSFER_MODE));
  64         pr_err(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  65                sdhci_readl(host, SDHCI_PRESENT_STATE),
  66                sdhci_readb(host, SDHCI_HOST_CONTROL));
  67         pr_err(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  68                sdhci_readb(host, SDHCI_POWER_CONTROL),
  69                sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  70         pr_err(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  71                sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  72                sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  73         pr_err(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  74                sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  75                sdhci_readl(host, SDHCI_INT_STATUS));
  76         pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  77                sdhci_readl(host, SDHCI_INT_ENABLE),
  78                sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  79         pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  80                sdhci_readw(host, SDHCI_ACMD12_ERR),
  81                sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  82         pr_err(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
  83                sdhci_readl(host, SDHCI_CAPABILITIES),
  84                sdhci_readl(host, SDHCI_CAPABILITIES_1));
  85         pr_err(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
  86                sdhci_readw(host, SDHCI_COMMAND),
  87                sdhci_readl(host, SDHCI_MAX_CURRENT));
  88         pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
  89                sdhci_readw(host, SDHCI_HOST_CONTROL2));
  90
  91         if (host->flags & SDHCI_USE_ADMA) {
  92                 if (host->flags & SDHCI_USE_64_BIT_DMA)
  93                         pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
  94                                readl(host->ioaddr + SDHCI_ADMA_ERROR),
  95                                readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
  96                                readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
  97                 else
  98                         pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
  99                                readl(host->ioaddr + SDHCI_ADMA_ERROR),
 100                                readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 101         }
 102
 103         pr_err(DRIVER_NAME ": ===========================================\n");
 104 }
 105
 106 /*****************************************************************************\
 107  *                                                                           *
 108  * Low level functions                                                       *
 109  *                                                                           *
 110 \*****************************************************************************/
 111
 112 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
 113 {
 114         return cmd->data || cmd->flags & MMC_RSP_BUSY;
 115 }
 116
 117 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 118 {
 119         u32 present;
 120
 121         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 122             !mmc_card_is_removable(host->mmc))
 123                 return;
 124
 125         if (enable) {
 126                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 127                                       SDHCI_CARD_PRESENT;
 128
 129                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 130                                        SDHCI_INT_CARD_INSERT;
 131         } else {
 132                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 133         }
 134
 135         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 136         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 137 }
 138
 139 static void sdhci_enable_card_detection(struct sdhci_host *host)
 140 {
 141         sdhci_set_card_detection(host, true);
 142 }
 143
 144 static void sdhci_disable_card_detection(struct sdhci_host *host)
 145 {
 146         sdhci_set_card_detection(host, false);
 147 }
 148
 149 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
 150 {
 151         if (host->bus_on)
 152                 return;
 153         host->bus_on = true;
 154         pm_runtime_get_noresume(host->mmc->parent);
 155 }
 156
 157 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
 158 {
 159         if (!host->bus_on)
 160                 return;
 161         host->bus_on = false;
 162         pm_runtime_put_noidle(host->mmc->parent);
 163 }
 164
 165 void sdhci_reset(struct sdhci_host *host, u8 mask)
 166 {
 167         unsigned long timeout;
 168
 169         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 170
 171         if (mask & SDHCI_RESET_ALL) {
 172                 host->clock = 0;
 173                 /* Reset-all turns off SD Bus Power */
 174                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 175                         sdhci_runtime_pm_bus_off(host);
 176         }
 177
 178         /* Wait max 100 ms */
 179         timeout = 100;
 180
 181         /* hw clears the bit when it's done */
 182         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 183                 if (timeout == 0) {
 184                         pr_err("%s: Reset 0x%x never completed.\n",
 185                                 mmc_hostname(host->mmc), (int)mask);
 186                         sdhci_dumpregs(host);
 187                         return;
 188                 }
 189                 timeout--;
 190                 mdelay(1);
 191         }
 192 }
 193 EXPORT_SYMBOL_GPL(sdhci_reset);
 194
 195 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 196 {
 197         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 198                 struct mmc_host *mmc = host->mmc;
 199
 200                 if (!mmc->ops->get_cd(mmc))
 201                         return;
 202         }
 203
 204         host->ops->reset(host, mask);
 205
 206         if (mask & SDHCI_RESET_ALL) {
 207                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 208                         if (host->ops->enable_dma)
 209                                 host->ops->enable_dma(host);
 210                 }
 211
 212                 /* Resetting the controller clears many */
 213                 host->preset_enabled = false;
 214         }
 215 }
 216
 217 static void sdhci_init(struct sdhci_host *host, int soft)
 218 {
 219         struct mmc_host *mmc = host->mmc;
 220
 221         if (soft)
 222                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 223         else
 224                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 225
 226         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 227                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 228                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 229                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 230                     SDHCI_INT_RESPONSE;
 231
 232         if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
 233             host->tuning_mode == SDHCI_TUNING_MODE_3)
 234                 host->ier |= SDHCI_INT_RETUNE;
 235
 236         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 237         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 238
 239         if (soft) {
 240                 /* force clock reconfiguration */
 241                 host->clock = 0;
 242                 mmc->ops->set_ios(mmc, &mmc->ios);
 243         }
 244 }
 245
 246 static void sdhci_reinit(struct sdhci_host *host)
 247 {
 248         sdhci_init(host, 0);
 249         sdhci_enable_card_detection(host);
 250 }
 251
 252 static void __sdhci_led_activate(struct sdhci_host *host)
 253 {
 254         u8 ctrl;
 255
 256         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 257         ctrl |= SDHCI_CTRL_LED;
 258         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 259 }
 260
 261 static void __sdhci_led_deactivate(struct sdhci_host *host)
 262 {
 263         u8 ctrl;
 264
 265         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 266         ctrl &= ~SDHCI_CTRL_LED;
 267         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 268 }
 269
 270 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
 271 static void sdhci_led_control(struct led_classdev *led,
 272                               enum led_brightness brightness)
 273 {
 274         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 275         unsigned long flags;
 276
 277         spin_lock_irqsave(&host->lock, flags);
 278
 279         if (host->runtime_suspended)
 280                 goto out;
 281
 282         if (brightness == LED_OFF)
 283                 __sdhci_led_deactivate(host);
 284         else
 285                 __sdhci_led_activate(host);
 286 out:
 287         spin_unlock_irqrestore(&host->lock, flags);
 288 }
 289
 290 static int sdhci_led_register(struct sdhci_host *host)
 291 {
 292         struct mmc_host *mmc = host->mmc;
 293
 294         snprintf(host->led_name, sizeof(host->led_name),
 295                  "%s::", mmc_hostname(mmc));
 296
 297         host->led.name = host->led_name;
 298         host->led.brightness = LED_OFF;
 299         host->led.default_trigger = mmc_hostname(mmc);
 300         host->led.brightness_set = sdhci_led_control;
 301
 302         return led_classdev_register(mmc_dev(mmc), &host->led);
 303 }
 304
 305 static void sdhci_led_unregister(struct sdhci_host *host)
 306 {
 307         led_classdev_unregister(&host->led);
 308 }
 309
 310 static inline void sdhci_led_activate(struct sdhci_host *host)
 311 {
 312 }
 313
 314 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 315 {
 316 }
 317
 318 #else
 319
 320 static inline int sdhci_led_register(struct sdhci_host *host)
 321 {
 322         return 0;
 323 }
 324
 325 static inline void sdhci_led_unregister(struct sdhci_host *host)
 326 {
 327 }
 328
 329 static inline void sdhci_led_activate(struct sdhci_host *host)
 330 {
 331         __sdhci_led_activate(host);
 332 }
 333
 334 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 335 {
 336         __sdhci_led_deactivate(host);
 337 }
 338
 339 #endif
 340
 341 /*****************************************************************************\
 342  *                                                                           *
 343  * Core functions                                                            *
 344  *                                                                           *
 345 \*****************************************************************************/
 346
 347 static void sdhci_read_block_pio(struct sdhci_host *host)
 348 {
 349         unsigned long flags;
 350         size_t blksize, len, chunk;
 351         u32 uninitialized_var(scratch);
 352         u8 *buf;
 353
 354         DBG("PIO reading\n");
 355
 356         blksize = host->data->blksz;
 357         chunk = 0;
 358
 359         local_irq_save(flags);
 360
 361         while (blksize) {
 362                 BUG_ON(!sg_miter_next(&host->sg_miter));
 363
 364                 len = min(host->sg_miter.length, blksize);
 365
 366                 blksize -= len;
 367                 host->sg_miter.consumed = len;
 368
 369                 buf = host->sg_miter.addr;
 370
 371                 while (len) {
 372                         if (chunk == 0) {
 373                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 374                                 chunk = 4;
 375                         }
 376
 377                         *buf = scratch & 0xFF;
 378
 379                         buf++;
 380                         scratch >>= 8;
 381                         chunk--;
 382                         len--;
 383                 }
 384         }
 385
 386         sg_miter_stop(&host->sg_miter);
 387
 388         local_irq_restore(flags);
 389 }
 390
 391 static void sdhci_write_block_pio(struct sdhci_host *host)
 392 {
 393         unsigned long flags;
 394         size_t blksize, len, chunk;
 395         u32 scratch;
 396         u8 *buf;
 397
 398         DBG("PIO writing\n");
 399
 400         blksize = host->data->blksz;
 401         chunk = 0;
 402         scratch = 0;
 403
 404         local_irq_save(flags);
 405
 406         while (blksize) {
 407                 BUG_ON(!sg_miter_next(&host->sg_miter));
 408
 409                 len = min(host->sg_miter.length, blksize);
 410
 411                 blksize -= len;
 412                 host->sg_miter.consumed = len;
 413
 414                 buf = host->sg_miter.addr;
 415
 416                 while (len) {
 417                         scratch |= (u32)*buf << (chunk * 8);
 418
 419                         buf++;
 420                         chunk++;
 421                         len--;
 422
 423                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 424                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 425                                 chunk = 0;
 426                                 scratch = 0;
 427                         }
 428                 }
 429         }
 430
 431         sg_miter_stop(&host->sg_miter);
 432
 433         local_irq_restore(flags);
 434 }
 435
 436 static void sdhci_transfer_pio(struct sdhci_host *host)
 437 {
 438         u32 mask;
 439
 440         if (host->blocks == 0)
 441                 return;
 442
 443         if (host->data->flags & MMC_DATA_READ)
 444                 mask = SDHCI_DATA_AVAILABLE;
 445         else
 446                 mask = SDHCI_SPACE_AVAILABLE;
 447
 448         /*
 449          * Some controllers (JMicron JMB38x) mess up the buffer bits
 450          * for transfers < 4 bytes. As long as it is just one block,
 451          * we can ignore the bits.
 452          */
 453         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 454                 (host->data->blocks == 1))
 455                 mask = ~0;
 456
 457         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 458                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 459                         udelay(100);
 460
 461                 if (host->data->flags & MMC_DATA_READ)
 462                         sdhci_read_block_pio(host);
 463                 else
 464                         sdhci_write_block_pio(host);
 465
 466                 host->blocks--;
 467                 if (host->blocks == 0)
 468                         break;
 469         }
 470
 471         DBG("PIO transfer complete.\n");
 472 }
 473
 474 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
 475                                   struct mmc_data *data, int cookie)
 476 {
 477         int sg_count;
 478
 479         /*
 480          * If the data buffers are already mapped, return the previous
 481          * dma_map_sg() result.
 482          */
 483         if (data->host_cookie == COOKIE_PRE_MAPPED)
 484                 return data->sg_count;
 485
 486         sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 487                                 data->flags & MMC_DATA_WRITE ?
 488                                 DMA_TO_DEVICE : DMA_FROM_DEVICE);
 489
 490         if (sg_count == 0)
 491                 return -ENOSPC;
 492
 493         data->sg_count = sg_count;
 494         data->host_cookie = cookie;
 495
 496         return sg_count;
 497 }
 498
 499 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 500 {
 501         local_irq_save(*flags);
 502         return kmap_atomic(sg_page(sg)) + sg->offset;
 503 }
 504
 505 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 506 {
 507         kunmap_atomic(buffer);
 508         local_irq_restore(*flags);
 509 }
 510
 511 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 512                                   dma_addr_t addr, int len, unsigned cmd)
 513 {
 514         struct sdhci_adma2_64_desc *dma_desc = desc;
 515
 516         /* 32-bit and 64-bit descriptors have these members in same position */
 517         dma_desc->cmd = cpu_to_le16(cmd);
 518         dma_desc->len = cpu_to_le16(len);
 519         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 520
 521         if (host->flags & SDHCI_USE_64_BIT_DMA)
 522                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 523 }
 524
 525 static void sdhci_adma_mark_end(void *desc)
 526 {
 527         struct sdhci_adma2_64_desc *dma_desc = desc;
 528
 529         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 530         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 531 }
 532
 533 static void sdhci_adma_table_pre(struct sdhci_host *host,
 534         struct mmc_data *data, int sg_count)
 535 {
 536         struct scatterlist *sg;
 537         unsigned long flags;
 538         dma_addr_t addr, align_addr;
 539         void *desc, *align;
 540         char *buffer;
 541         int len, offset, i;
 542
 543         /*
 544          * The spec does not specify endianness of descriptor table.
 545          * We currently guess that it is LE.
 546          */
 547
 548         host->sg_count = sg_count;
 549
 550         desc = host->adma_table;
 551         align = host->align_buffer;
 552
 553         align_addr = host->align_addr;
 554
 555         for_each_sg(data->sg, sg, host->sg_count, i) {
 556                 addr = sg_dma_address(sg);
 557                 len = sg_dma_len(sg);
 558
 559                 /*
 560                  * The SDHCI specification states that ADMA addresses must
 561                  * be 32-bit aligned. If they aren't, then we use a bounce
 562                  * buffer for the (up to three) bytes that screw up the
 563                  * alignment.
 564                  */
 565                 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
 566                          SDHCI_ADMA2_MASK;
 567                 if (offset) {
 568                         if (data->flags & MMC_DATA_WRITE) {
 569                                 buffer = sdhci_kmap_atomic(sg, &flags);
 570                                 memcpy(align, buffer, offset);
 571                                 sdhci_kunmap_atomic(buffer, &flags);
 572                         }
 573
 574                         /* tran, valid */
 575                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 576                                               ADMA2_TRAN_VALID);
 577
 578                         BUG_ON(offset > 65536);
 579
 580                         align += SDHCI_ADMA2_ALIGN;
 581                         align_addr += SDHCI_ADMA2_ALIGN;
 582
 583                         desc += host->desc_sz;
 584
 585                         addr += offset;
 586                         len -= offset;
 587                 }
 588
 589                 BUG_ON(len > 65536);
 590
 591                 if (len) {
 592                         /* tran, valid */
 593                         sdhci_adma_write_desc(host, desc, addr, len,
 594                                               ADMA2_TRAN_VALID);
 595                         desc += host->desc_sz;
 596                 }
 597
 598                 /*
 599                  * If this triggers then we have a calculation bug
 600                  * somewhere. :/
 601                  */
 602                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 603         }
 604
 605         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 606                 /* Mark the last descriptor as the terminating descriptor */
 607                 if (desc != host->adma_table) {
 608                         desc -= host->desc_sz;
 609                         sdhci_adma_mark_end(desc);
 610                 }
 611         } else {
 612                 /* Add a terminating entry - nop, end, valid */
 613                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 614         }
 615 }
 616
 617 static void sdhci_adma_table_post(struct sdhci_host *host,
 618         struct mmc_data *data)
 619 {
 620         struct scatterlist *sg;
 621         int i, size;
 622         void *align;
 623         char *buffer;
 624         unsigned long flags;
 625
 626         if (data->flags & MMC_DATA_READ) {
 627                 bool has_unaligned = false;
 628
 629                 /* Do a quick scan of the SG list for any unaligned mappings */
 630                 for_each_sg(data->sg, sg, host->sg_count, i)
 631                         if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 632                                 has_unaligned = true;
 633                                 break;
 634                         }
 635
 636                 if (has_unaligned) {
 637                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 638                                             data->sg_len, DMA_FROM_DEVICE);
 639
 640                         align = host->align_buffer;
 641
 642                         for_each_sg(data->sg, sg, host->sg_count, i) {
 643                                 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 644                                         size = SDHCI_ADMA2_ALIGN -
 645                                                (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
 646
 647                                         buffer = sdhci_kmap_atomic(sg, &flags);
 648                                         memcpy(buffer, align, size);
 649                                         sdhci_kunmap_atomic(buffer, &flags);
 650
 651                                         align += SDHCI_ADMA2_ALIGN;
 652                                 }
 653                         }
 654                 }
 655         }
 656 }
 657
 658 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 659 {
 660         u8 count;
 661         struct mmc_data *data = cmd->data;
 662         unsigned target_timeout, current_timeout;
 663
 664         /*
 665          * If the host controller provides us with an incorrect timeout
 666          * value, just skip the check and use 0xE.  The hardware may take
 667          * longer to time out, but that's much better than having a too-short
 668          * timeout value.
 669          */
 670         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 671                 return 0xE;
 672
 673         /* Unspecified timeout, assume max */
 674         if (!data && !cmd->busy_timeout)
 675                 return 0xE;
 676
 677         /* timeout in us */
 678         if (!data)
 679                 target_timeout = cmd->busy_timeout * 1000;
 680         else {
 681                 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
 682                 if (host->clock && data->timeout_clks) {
 683                         unsigned long long val;
 684
 685                         /*
 686                          * data->timeout_clks is in units of clock cycles.
 687                          * host->clock is in Hz.  target_timeout is in us.
 688                          * Hence, us = 1000000 * cycles / Hz.  Round up.
 689                          */
 690                         val = 1000000ULL * data->timeout_clks;
 691                         if (do_div(val, host->clock))
 692                                 target_timeout++;
 693                         target_timeout += val;
 694                 }
 695         }
 696
 697         /*
 698          * Figure out needed cycles.
 699          * We do this in steps in order to fit inside a 32 bit int.
 700          * The first step is the minimum timeout, which will have a
 701          * minimum resolution of 6 bits:
 702          * (1) 2^13*1000 > 2^22,
 703          * (2) host->timeout_clk < 2^16
 704          *     =>
 705          *     (1) / (2) > 2^6
 706          */
 707         count = 0;
 708         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 709         while (current_timeout < target_timeout) {
 710                 count++;
 711                 current_timeout <<= 1;
 712                 if (count >= 0xF)
 713                         break;
 714         }
 715
 716         if (count >= 0xF) {
 717                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 718                     mmc_hostname(host->mmc), count, cmd->opcode);
 719                 count = 0xE;
 720         }
 721
 722         return count;
 723 }
 724
 725 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 726 {
 727         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 728         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 729
 730         if (host->flags & SDHCI_REQ_USE_DMA)
 731                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 732         else
 733                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 734
 735         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 736         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 737 }
 738
 739 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 740 {
 741         u8 count;
 742
 743         if (host->ops->set_timeout) {
 744                 host->ops->set_timeout(host, cmd);
 745         } else {
 746                 count = sdhci_calc_timeout(host, cmd);
 747                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 748         }
 749 }
 750
 751 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 752 {
 753         u8 ctrl;
 754         struct mmc_data *data = cmd->data;
 755
 756         if (sdhci_data_line_cmd(cmd))
 757                 sdhci_set_timeout(host, cmd);
 758
 759         if (!data)
 760                 return;
 761
 762         WARN_ON(host->data);
 763
 764         /* Sanity checks */
 765         BUG_ON(data->blksz * data->blocks > 524288);
 766         BUG_ON(data->blksz > host->mmc->max_blk_size);
 767         BUG_ON(data->blocks > 65535);
 768
 769         host->data = data;
 770         host->data_early = 0;
 771         host->data->bytes_xfered = 0;
 772
 773         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 774                 struct scatterlist *sg;
 775                 unsigned int length_mask, offset_mask;
 776                 int i;
 777
 778                 host->flags |= SDHCI_REQ_USE_DMA;
 779
 780                 /*
 781                  * FIXME: This doesn't account for merging when mapping the
 782                  * scatterlist.
 783                  *
 784                  * The assumption here being that alignment and lengths are
 785                  * the same after DMA mapping to device address space.
 786                  */
 787                 length_mask = 0;
 788                 offset_mask = 0;
 789                 if (host->flags & SDHCI_USE_ADMA) {
 790                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
 791                                 length_mask = 3;
 792                                 /*
 793                                  * As we use up to 3 byte chunks to work
 794                                  * around alignment problems, we need to
 795                                  * check the offset as well.
 796                                  */
 797                                 offset_mask = 3;
 798                         }
 799                 } else {
 800                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 801                                 length_mask = 3;
 802                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 803                                 offset_mask = 3;
 804                 }
 805
 806                 if (unlikely(length_mask | offset_mask)) {
 807                         for_each_sg(data->sg, sg, data->sg_len, i) {
 808                                 if (sg->length & length_mask) {
 809                                         DBG("Reverting to PIO because of transfer size (%d)\n",
 810                                             sg->length);
 811                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 812                                         break;
 813                                 }
 814                                 if (sg->offset & offset_mask) {
 815                                         DBG("Reverting to PIO because of bad alignment\n");
 816                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 817                                         break;
 818                                 }
 819                         }
 820                 }
 821         }
 822
 823         if (host->flags & SDHCI_REQ_USE_DMA) {
 824                 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
 825
 826                 if (sg_cnt <= 0) {
 827                         /*
 828                          * This only happens when someone fed
 829                          * us an invalid request.
 830                          */
 831                         WARN_ON(1);
 832                         host->flags &= ~SDHCI_REQ_USE_DMA;
 833                 } else if (host->flags & SDHCI_USE_ADMA) {
 834                         sdhci_adma_table_pre(host, data, sg_cnt);
 835
 836                         sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
 837                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 838                                 sdhci_writel(host,
 839                                              (u64)host->adma_addr >> 32,
 840                                              SDHCI_ADMA_ADDRESS_HI);
 841                 } else {
 842                         WARN_ON(sg_cnt != 1);
 843                         sdhci_writel(host, sg_dma_address(data->sg),
 844                                 SDHCI_DMA_ADDRESS);
 845                 }
 846         }
 847
 848         /*
 849          * Always adjust the DMA selection as some controllers
 850          * (e.g. JMicron) can't do PIO properly when the selection
 851          * is ADMA.
 852          */
 853         if (host->version >= SDHCI_SPEC_200) {
 854                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 855                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 856                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 857                         (host->flags & SDHCI_USE_ADMA)) {
 858                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 859                                 ctrl |= SDHCI_CTRL_ADMA64;
 860                         else
 861                                 ctrl |= SDHCI_CTRL_ADMA32;
 862                 } else {
 863                         ctrl |= SDHCI_CTRL_SDMA;
 864                 }
 865                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 866         }
 867
 868         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 869                 int flags;
 870
 871                 flags = SG_MITER_ATOMIC;
 872                 if (host->data->flags & MMC_DATA_READ)
 873                         flags |= SG_MITER_TO_SG;
 874                 else
 875                         flags |= SG_MITER_FROM_SG;
 876                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 877                 host->blocks = data->blocks;
 878         }
 879
 880         sdhci_set_transfer_irqs(host);
 881
 882         /* Set the DMA boundary value and block size */
 883         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 884                 data->blksz), SDHCI_BLOCK_SIZE);
 885         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 886 }
 887
 888 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
 889                                     struct mmc_request *mrq)
 890 {
 891         return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
 892                !mrq->cap_cmd_during_tfr;
 893 }
 894
 895 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 896         struct mmc_command *cmd)
 897 {
 898         u16 mode = 0;
 899         struct mmc_data *data = cmd->data;
 900
 901         if (data == NULL) {
 902                 if (host->quirks2 &
 903                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 904                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 905                 } else {
 906                 /* clear Auto CMD settings for no data CMDs */
 907                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 908                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 909                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 910                 }
 911                 return;
 912         }
 913
 914         WARN_ON(!host->data);
 915
 916         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
 917                 mode = SDHCI_TRNS_BLK_CNT_EN;
 918
 919         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 920                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
 921                 /*
 922                  * If we are sending CMD23, CMD12 never gets sent
 923                  * on successful completion (so no Auto-CMD12).
 924                  */
 925                 if (sdhci_auto_cmd12(host, cmd->mrq) &&
 926                     (cmd->opcode != SD_IO_RW_EXTENDED))
 927                         mode |= SDHCI_TRNS_AUTO_CMD12;
 928                 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 929                         mode |= SDHCI_TRNS_AUTO_CMD23;
 930                         sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
 931                 }
 932         }
 933
 934         if (data->flags & MMC_DATA_READ)
 935                 mode |= SDHCI_TRNS_READ;
 936         if (host->flags & SDHCI_REQ_USE_DMA)
 937                 mode |= SDHCI_TRNS_DMA;
 938
 939         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 940 }
 941
 942 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
 943 {
 944         return (!(host->flags & SDHCI_DEVICE_DEAD) &&
 945                 ((mrq->cmd && mrq->cmd->error) ||
 946                  (mrq->sbc && mrq->sbc->error) ||
 947                  (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
 948                  (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
 949 }
 950
 951 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
 952 {
 953         int i;
 954
 955         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
 956                 if (host->mrqs_done[i] == mrq) {
 957                         WARN_ON(1);
 958                         return;
 959                 }
 960         }
 961
 962         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
 963                 if (!host->mrqs_done[i]) {
 964                         host->mrqs_done[i] = mrq;
 965                         break;
 966                 }
 967         }
 968
 969         WARN_ON(i >= SDHCI_MAX_MRQS);
 970
 971         tasklet_schedule(&host->finish_tasklet);
 972 }
 973
 974 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
 975 {
 976         if (host->cmd && host->cmd->mrq == mrq)
 977                 host->cmd = NULL;
 978
 979         if (host->data_cmd && host->data_cmd->mrq == mrq)
 980                 host->data_cmd = NULL;
 981
 982         if (host->data && host->data->mrq == mrq)
 983                 host->data = NULL;
 984
 985         if (sdhci_needs_reset(host, mrq))
 986                 host->pending_reset = true;
 987
 988         __sdhci_finish_mrq(host, mrq);
 989 }
 990
 991 static void sdhci_finish_data(struct sdhci_host *host)
 992 {
 993         struct mmc_command *data_cmd = host->data_cmd;
 994         struct mmc_data *data = host->data;
 995
 996         host->data = NULL;
 997         host->data_cmd = NULL;
 998
 999         /*
1000          * The controller needs a reset of internal state machines upon error
1001          * conditions.
1002          */
1003         if (data->error) {
1004                 if (!host->cmd || host->cmd == data_cmd)
1005                         sdhci_do_reset(host, SDHCI_RESET_CMD);
1006                 sdhci_do_reset(host, SDHCI_RESET_DATA);
1007         }
1008
1009         if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1010             (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1011                 sdhci_adma_table_post(host, data);
1012
1013         /*
1014          * The specification states that the block count register must
1015          * be updated, but it does not specify at what point in the
1016          * data flow. That makes the register entirely useless to read
1017          * back so we have to assume that nothing made it to the card
1018          * in the event of an error.
1019          */
1020         if (data->error)
1021                 data->bytes_xfered = 0;
1022         else
1023                 data->bytes_xfered = data->blksz * data->blocks;
1024
1025         /*
1026          * Need to send CMD12 if -
1027          * a) open-ended multiblock transfer (no CMD23)
1028          * b) error in multiblock transfer
1029          */
1030         if (data->stop &&
1031             (data->error ||
1032              !data->mrq->sbc)) {
1033                 /*
1034                  * 'cap_cmd_during_tfr' request must not use the command line
1035                  * after mmc_command_done() has been called. It is upper layer's
1036                  * responsibility to send the stop command if required.
1037                  */
1038                 if (data->mrq->cap_cmd_during_tfr) {
1039                         sdhci_finish_mrq(host, data->mrq);
1040                 } else {
1041                         /* Avoid triggering warning in sdhci_send_command() */
1042                         host->cmd = NULL;
1043                         sdhci_send_command(host, data->stop);
1044                 }
1045         } else {
1046                 sdhci_finish_mrq(host, data->mrq);
1047         }
1048 }
1049
1050 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1051                             unsigned long timeout)
1052 {
1053         if (sdhci_data_line_cmd(mrq->cmd))
1054                 mod_timer(&host->data_timer, timeout);
1055         else
1056                 mod_timer(&host->timer, timeout);
1057 }
1058
1059 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1060 {
1061         if (sdhci_data_line_cmd(mrq->cmd))
1062                 del_timer(&host->data_timer);
1063         else
1064                 del_timer(&host->timer);
1065 }
1066
1067 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1068 {
1069         int flags;
1070         u32 mask;
1071         unsigned long timeout;
1072
1073         WARN_ON(host->cmd);
1074
1075         /* Initially, a command has no error */
1076         cmd->error = 0;
1077
1078         if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1079             cmd->opcode == MMC_STOP_TRANSMISSION)
1080                 cmd->flags |= MMC_RSP_BUSY;
1081
1082         /* Wait max 10 ms */
1083         timeout = 10;
1084
1085         mask = SDHCI_CMD_INHIBIT;
1086         if (sdhci_data_line_cmd(cmd))
1087                 mask |= SDHCI_DATA_INHIBIT;
1088
1089         /* We shouldn't wait for data inihibit for stop commands, even
1090            though they might use busy signaling */
1091         if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1092                 mask &= ~SDHCI_DATA_INHIBIT;
1093
1094         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1095                 if (timeout == 0) {
1096                         pr_err("%s: Controller never released inhibit bit(s).\n",
1097                                mmc_hostname(host->mmc));
1098                         sdhci_dumpregs(host);
1099                         cmd->error = -EIO;
1100                         sdhci_finish_mrq(host, cmd->mrq);
1101                         return;
1102                 }
1103                 timeout--;
1104                 mdelay(1);
1105         }
1106
1107         timeout = jiffies;
1108         if (!cmd->data && cmd->busy_timeout > 9000)
1109                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1110         else
1111                 timeout += 10 * HZ;
1112         sdhci_mod_timer(host, cmd->mrq, timeout);
1113
1114         host->cmd = cmd;
1115         if (sdhci_data_line_cmd(cmd)) {
1116                 WARN_ON(host->data_cmd);
1117                 host->data_cmd = cmd;
1118         }
1119
1120         sdhci_prepare_data(host, cmd);
1121
1122         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1123
1124         sdhci_set_transfer_mode(host, cmd);
1125
1126         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1127                 pr_err("%s: Unsupported response type!\n",
1128                         mmc_hostname(host->mmc));
1129                 cmd->error = -EINVAL;
1130                 sdhci_finish_mrq(host, cmd->mrq);
1131                 return;
1132         }
1133
1134         if (!(cmd->flags & MMC_RSP_PRESENT))
1135                 flags = SDHCI_CMD_RESP_NONE;
1136         else if (cmd->flags & MMC_RSP_136)
1137                 flags = SDHCI_CMD_RESP_LONG;
1138         else if (cmd->flags & MMC_RSP_BUSY)
1139                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1140         else
1141                 flags = SDHCI_CMD_RESP_SHORT;
1142
1143         if (cmd->flags & MMC_RSP_CRC)
1144                 flags |= SDHCI_CMD_CRC;
1145         if (cmd->flags & MMC_RSP_OPCODE)
1146                 flags |= SDHCI_CMD_INDEX;
1147
1148         /* CMD19 is special in that the Data Present Select should be set */
1149         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1150             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1151                 flags |= SDHCI_CMD_DATA;
1152
1153         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1154 }
1155 EXPORT_SYMBOL_GPL(sdhci_send_command);
1156
1157 static void sdhci_finish_command(struct sdhci_host *host)
1158 {
1159         struct mmc_command *cmd = host->cmd;
1160         int i;
1161
1162         host->cmd = NULL;
1163
1164         if (cmd->flags & MMC_RSP_PRESENT) {
1165                 if (cmd->flags & MMC_RSP_136) {
1166                         /* CRC is stripped so we need to do some shifting. */
1167                         for (i = 0;i < 4;i++) {
1168                                 cmd->resp[i] = sdhci_readl(host,
1169                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1170                                 if (i != 3)
1171                                         cmd->resp[i] |=
1172                                                 sdhci_readb(host,
1173                                                 SDHCI_RESPONSE + (3-i)*4-1);
1174                         }
1175                 } else {
1176                         cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1177                 }
1178         }
1179
1180         if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1181                 mmc_command_done(host->mmc, cmd->mrq);
1182
1183         /*
1184          * The host can send and interrupt when the busy state has
1185          * ended, allowing us to wait without wasting CPU cycles.
1186          * The busy signal uses DAT0 so this is similar to waiting
1187          * for data to complete.
1188          *
1189          * Note: The 1.0 specification is a bit ambiguous about this
1190          *       feature so there might be some problems with older
1191          *       controllers.
1192          */
1193         if (cmd->flags & MMC_RSP_BUSY) {
1194                 if (cmd->data) {
1195                         DBG("Cannot wait for busy signal when also doing a data transfer");
1196                 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1197                            cmd == host->data_cmd) {
1198                         /* Command complete before busy is ended */
1199                         return;
1200                 }
1201         }
1202
1203         /* Finished CMD23, now send actual command. */
1204         if (cmd == cmd->mrq->sbc) {
1205                 sdhci_send_command(host, cmd->mrq->cmd);
1206         } else {
1207
1208                 /* Processed actual command. */
1209                 if (host->data && host->data_early)
1210                         sdhci_finish_data(host);
1211
1212                 if (!cmd->data)
1213                         sdhci_finish_mrq(host, cmd->mrq);
1214         }
1215 }
1216
1217 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1218 {
1219         u16 preset = 0;
1220
1221         switch (host->timing) {
1222         case MMC_TIMING_MMC_HS:
1223         case MMC_TIMING_SD_HS:
1224                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1225                 break;
1226         case MMC_TIMING_UHS_SDR12:
1227                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1228                 break;
1229         case MMC_TIMING_UHS_SDR25:
1230                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1231                 break;
1232         case MMC_TIMING_UHS_SDR50:
1233                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1234                 break;
1235         case MMC_TIMING_UHS_SDR104:
1236         case MMC_TIMING_MMC_HS200:
1237                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1238                 break;
1239         case MMC_TIMING_UHS_DDR50:
1240         case MMC_TIMING_MMC_DDR52:
1241                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1242                 break;
1243         case MMC_TIMING_MMC_HS400:
1244                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1245                 break;
1246         default:
1247                 pr_warn("%s: Invalid UHS-I mode selected\n",
1248                         mmc_hostname(host->mmc));
1249                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1250                 break;
1251         }
1252         return preset;
1253 }
1254
1255 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1256                    unsigned int *actual_clock)
1257 {
1258         int div = 0; /* Initialized for compiler warning */
1259         int real_div = div, clk_mul = 1;
1260         u16 clk = 0;
1261         bool switch_base_clk = false;
1262
1263         if (host->version >= SDHCI_SPEC_300) {
1264                 if (host->preset_enabled) {
1265                         u16 pre_val;
1266
1267                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1268                         pre_val = sdhci_get_preset_value(host);
1269                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1270                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1271                         if (host->clk_mul &&
1272                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1273                                 clk = SDHCI_PROG_CLOCK_MODE;
1274                                 real_div = div + 1;
1275                                 clk_mul = host->clk_mul;
1276                         } else {
1277                                 real_div = max_t(int, 1, div << 1);
1278                         }
1279                         goto clock_set;
1280                 }
1281
1282                 /*
1283                  * Check if the Host Controller supports Programmable Clock
1284                  * Mode.
1285                  */
1286                 if (host->clk_mul) {
1287                         for (div = 1; div <= 1024; div++) {
1288                                 if ((host->max_clk * host->clk_mul / div)
1289                                         <= clock)
1290                                         break;
1291                         }
1292                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1293                                 /*
1294                                  * Set Programmable Clock Mode in the Clock
1295                                  * Control register.
1296                                  */
1297                                 clk = SDHCI_PROG_CLOCK_MODE;
1298                                 real_div = div;
1299                                 clk_mul = host->clk_mul;
1300                                 div--;
1301                         } else {
1302                                 /*
1303                                  * Divisor can be too small to reach clock
1304                                  * speed requirement. Then use the base clock.
1305                                  */
1306                                 switch_base_clk = true;
1307                         }
1308                 }
1309
1310                 if (!host->clk_mul || switch_base_clk) {
1311                         /* Version 3.00 divisors must be a multiple of 2. */
1312                         if (host->max_clk <= clock)
1313                                 div = 1;
1314                         else {
1315                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1316                                      div += 2) {
1317                                         if ((host->max_clk / div) <= clock)
1318                                                 break;
1319                                 }
1320                         }
1321                         real_div = div;
1322                         div >>= 1;
1323                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1324                                 && !div && host->max_clk <= 25000000)
1325                                 div = 1;
1326                 }
1327         } else {
1328                 /* Version 2.00 divisors must be a power of 2. */
1329                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1330                         if ((host->max_clk / div) <= clock)
1331                                 break;
1332                 }
1333                 real_div = div;
1334                 div >>= 1;
1335         }
1336
1337 clock_set:
1338         if (real_div)
1339                 *actual_clock = (host->max_clk * clk_mul) / real_div;
1340         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1341         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1342                 << SDHCI_DIVIDER_HI_SHIFT;
1343
1344         return clk;
1345 }
1346 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1347
1348 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1349 {
1350         u16 clk;
1351         unsigned long timeout;
1352
1353         host->mmc->actual_clock = 0;
1354
1355         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1356
1357         if (clock == 0)
1358                 return;
1359
1360         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1361
1362         clk |= SDHCI_CLOCK_INT_EN;
1363         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1364
1365         /* Wait max 20 ms */
1366         timeout = 20;
1367         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1368                 & SDHCI_CLOCK_INT_STABLE)) {
1369                 if (timeout == 0) {
1370                         pr_err("%s: Internal clock never stabilised.\n",
1371                                mmc_hostname(host->mmc));
1372                         sdhci_dumpregs(host);
1373                         return;
1374                 }
1375                 timeout--;
1376                 spin_unlock_irq(&host->lock);
1377                 usleep_range(900, 1100);
1378                 spin_lock_irq(&host->lock);
1379         }
1380
1381         clk |= SDHCI_CLOCK_CARD_EN;
1382         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1383 }
1384 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1385
1386 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1387                                 unsigned short vdd)
1388 {
1389         struct mmc_host *mmc = host->mmc;
1390
1391         spin_unlock_irq(&host->lock);
1392         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1393         spin_lock_irq(&host->lock);
1394
1395         if (mode != MMC_POWER_OFF)
1396                 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1397         else
1398                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1399 }
1400
1401 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1402                            unsigned short vdd)
1403 {
1404         u8 pwr = 0;
1405
1406         if (mode != MMC_POWER_OFF) {
1407                 switch (1 << vdd) {
1408                 case MMC_VDD_165_195:
1409                 /*
1410                  * Without a regulator, SDHCI does not support 2.0v
1411                  * so we only get here if the driver deliberately
1412                  * added the 2.0v range to ocr_avail. Map it to 1.8v
1413                  * for the purpose of turning on the power.
1414                  */
1415                 case MMC_VDD_20_21:
1416                         pwr = SDHCI_POWER_180;
1417                         break;
1418                 case MMC_VDD_29_30:
1419                 case MMC_VDD_30_31:
1420                         pwr = SDHCI_POWER_300;
1421                         break;
1422                 case MMC_VDD_32_33:
1423                 case MMC_VDD_33_34:
1424                 /*
1425                  * 3.4 ~ 3.6V are valid only for those platforms where it's
1426                  * known that the voltage range is supported by hardware.
1427                  */
1428                 case MMC_VDD_34_35:
1429                 case MMC_VDD_35_36:
1430                         pwr = SDHCI_POWER_330;
1431                         break;
1432                 default:
1433                         WARN(1, "%s: Invalid vdd %#x\n",
1434                              mmc_hostname(host->mmc), vdd);
1435                         break;
1436                 }
1437         }
1438
1439         if (host->pwr == pwr)
1440                 return;
1441
1442         host->pwr = pwr;
1443
1444         if (pwr == 0) {
1445                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1446                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1447                         sdhci_runtime_pm_bus_off(host);
1448         } else {
1449                 /*
1450                  * Spec says that we should clear the power reg before setting
1451                  * a new value. Some controllers don't seem to like this though.
1452                  */
1453                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1454                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1455
1456                 /*
1457                  * At least the Marvell CaFe chip gets confused if we set the
1458                  * voltage and set turn on power at the same time, so set the
1459                  * voltage first.
1460                  */
1461                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1462                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1463
1464                 pwr |= SDHCI_POWER_ON;
1465
1466                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1467
1468                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1469                         sdhci_runtime_pm_bus_on(host);
1470
1471                 /*
1472                  * Some controllers need an extra 10ms delay of 10ms before
1473                  * they can apply clock after applying power
1474                  */
1475                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1476                         mdelay(10);
1477         }
1478 }
1479 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1480
1481 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1482                      unsigned short vdd)
1483 {
1484         if (IS_ERR(host->mmc->supply.vmmc))
1485                 sdhci_set_power_noreg(host, mode, vdd);
1486         else
1487                 sdhci_set_power_reg(host, mode, vdd);
1488 }
1489 EXPORT_SYMBOL_GPL(sdhci_set_power);
1490
1491 /*****************************************************************************\
1492  *                                                                           *
1493  * MMC callbacks                                                             *
1494  *                                                                           *
1495 \*****************************************************************************/
1496
1497 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1498 {
1499         struct sdhci_host *host;
1500         int present;
1501         unsigned long flags;
1502
1503         host = mmc_priv(mmc);
1504
1505         /* Firstly check card presence */
1506         present = mmc->ops->get_cd(mmc);
1507
1508         spin_lock_irqsave(&host->lock, flags);
1509
1510         sdhci_led_activate(host);
1511
1512         /*
1513          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1514          * requests if Auto-CMD12 is enabled.
1515          */
1516         if (sdhci_auto_cmd12(host, mrq)) {
1517                 if (mrq->stop) {
1518                         mrq->data->stop = NULL;
1519                         mrq->stop = NULL;
1520                 }
1521         }
1522
1523         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1524                 mrq->cmd->error = -ENOMEDIUM;
1525                 sdhci_finish_mrq(host, mrq);
1526         } else {
1527                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1528                         sdhci_send_command(host, mrq->sbc);
1529                 else
1530                         sdhci_send_command(host, mrq->cmd);
1531         }
1532
1533         mmiowb();
1534         spin_unlock_irqrestore(&host->lock, flags);
1535 }
1536
1537 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1538 {
1539         u8 ctrl;
1540
1541         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1542         if (width == MMC_BUS_WIDTH_8) {
1543                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1544                 if (host->version >= SDHCI_SPEC_300)
1545                         ctrl |= SDHCI_CTRL_8BITBUS;
1546         } else {
1547                 if (host->version >= SDHCI_SPEC_300)
1548                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1549                 if (width == MMC_BUS_WIDTH_4)
1550                         ctrl |= SDHCI_CTRL_4BITBUS;
1551                 else
1552                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1553         }
1554         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1555 }
1556 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1557
1558 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1559 {
1560         u16 ctrl_2;
1561
1562         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1563         /* Select Bus Speed Mode for host */
1564         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1565         if ((timing == MMC_TIMING_MMC_HS200) ||
1566             (timing == MMC_TIMING_UHS_SDR104))
1567                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1568         else if (timing == MMC_TIMING_UHS_SDR12)
1569                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1570         else if (timing == MMC_TIMING_UHS_SDR25)
1571                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1572         else if (timing == MMC_TIMING_UHS_SDR50)
1573                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1574         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1575                  (timing == MMC_TIMING_MMC_DDR52))
1576                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1577         else if (timing == MMC_TIMING_MMC_HS400)
1578                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1579         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1580 }
1581 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1582
1583 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1584 {
1585         struct sdhci_host *host = mmc_priv(mmc);
1586         unsigned long flags;
1587         u8 ctrl;
1588
1589         spin_lock_irqsave(&host->lock, flags);
1590
1591         if (host->flags & SDHCI_DEVICE_DEAD) {
1592                 spin_unlock_irqrestore(&host->lock, flags);
1593                 if (!IS_ERR(mmc->supply.vmmc) &&
1594                     ios->power_mode == MMC_POWER_OFF)
1595                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1596                 return;
1597         }
1598
1599         /*
1600          * Reset the chip on each power off.
1601          * Should clear out any weird states.
1602          */
1603         if (ios->power_mode == MMC_POWER_OFF) {
1604                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1605                 sdhci_reinit(host);
1606         }
1607
1608         if (host->version >= SDHCI_SPEC_300 &&
1609                 (ios->power_mode == MMC_POWER_UP) &&
1610                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1611                 sdhci_enable_preset_value(host, false);
1612
1613         if (!ios->clock || ios->clock != host->clock) {
1614                 host->ops->set_clock(host, ios->clock);
1615                 host->clock = ios->clock;
1616
1617                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1618                     host->clock) {
1619                         host->timeout_clk = host->mmc->actual_clock ?
1620                                                 host->mmc->actual_clock / 1000 :
1621                                                 host->clock / 1000;
1622                         host->mmc->max_busy_timeout =
1623                                 host->ops->get_max_timeout_count ?
1624                                 host->ops->get_max_timeout_count(host) :
1625                                 1 << 27;
1626                         host->mmc->max_busy_timeout /= host->timeout_clk;
1627                 }
1628         }
1629
1630         if (host->ops->set_power)
1631                 host->ops->set_power(host, ios->power_mode, ios->vdd);
1632         else
1633                 sdhci_set_power(host, ios->power_mode, ios->vdd);
1634
1635         if (host->ops->platform_send_init_74_clocks)
1636                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1637
1638         host->ops->set_bus_width(host, ios->bus_width);
1639
1640         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1641
1642         if ((ios->timing == MMC_TIMING_SD_HS ||
1643              ios->timing == MMC_TIMING_MMC_HS)
1644             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1645                 ctrl |= SDHCI_CTRL_HISPD;
1646         else
1647                 ctrl &= ~SDHCI_CTRL_HISPD;
1648
1649         if (host->version >= SDHCI_SPEC_300) {
1650                 u16 clk, ctrl_2;
1651
1652                 /* In case of UHS-I modes, set High Speed Enable */
1653                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1654                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1655                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1656                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1657                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1658                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1659                     (ios->timing == MMC_TIMING_UHS_SDR25))
1660                         ctrl |= SDHCI_CTRL_HISPD;
1661
1662                 if (!host->preset_enabled) {
1663                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1664                         /*
1665                          * We only need to set Driver Strength if the
1666                          * preset value enable is not set.
1667                          */
1668                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1669                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1670                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1671                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1672                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1673                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1674                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1675                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1676                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1677                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1678                         else {
1679                                 pr_warn("%s: invalid driver type, default to driver type B\n",
1680                                         mmc_hostname(mmc));
1681                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1682                         }
1683
1684                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1685                 } else {
1686                         /*
1687                          * According to SDHC Spec v3.00, if the Preset Value
1688                          * Enable in the Host Control 2 register is set, we
1689                          * need to reset SD Clock Enable before changing High
1690                          * Speed Enable to avoid generating clock gliches.
1691                          */
1692
1693                         /* Reset SD Clock Enable */
1694                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1695                         clk &= ~SDHCI_CLOCK_CARD_EN;
1696                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1697
1698                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1699
1700                         /* Re-enable SD Clock */
1701                         host->ops->set_clock(host, host->clock);
1702                 }
1703
1704                 /* Reset SD Clock Enable */
1705                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1706                 clk &= ~SDHCI_CLOCK_CARD_EN;
1707                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1708
1709                 host->ops->set_uhs_signaling(host, ios->timing);
1710                 host->timing = ios->timing;
1711
1712                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1713                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1714                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1715                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1716                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1717                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
1718                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
1719                         u16 preset;
1720
1721                         sdhci_enable_preset_value(host, true);
1722                         preset = sdhci_get_preset_value(host);
1723                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1724                                 >> SDHCI_PRESET_DRV_SHIFT;
1725                 }
1726
1727                 /* Re-enable SD Clock */
1728                 host->ops->set_clock(host, host->clock);
1729         } else
1730                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1731
1732         /*
1733          * Some (ENE) controllers go apeshit on some ios operation,
1734          * signalling timeout and CRC errors even on CMD0. Resetting
1735          * it on each ios seems to solve the problem.
1736          */
1737         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1738                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1739
1740         mmiowb();
1741         spin_unlock_irqrestore(&host->lock, flags);
1742 }
1743
1744 static int sdhci_get_cd(struct mmc_host *mmc)
1745 {
1746         struct sdhci_host *host = mmc_priv(mmc);
1747         int gpio_cd = mmc_gpio_get_cd(mmc);
1748
1749         if (host->flags & SDHCI_DEVICE_DEAD)
1750                 return 0;
1751
1752         /* If nonremovable, assume that the card is always present. */
1753         if (!mmc_card_is_removable(host->mmc))
1754                 return 1;
1755
1756         /*
1757          * Try slot gpio detect, if defined it take precedence
1758          * over build in controller functionality
1759          */
1760         if (gpio_cd >= 0)
1761                 return !!gpio_cd;
1762
1763         /* If polling, assume that the card is always present. */
1764         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1765                 return 1;
1766
1767         /* Host native card detect */
1768         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1769 }
1770
1771 static int sdhci_check_ro(struct sdhci_host *host)
1772 {
1773         unsigned long flags;
1774         int is_readonly;
1775
1776         spin_lock_irqsave(&host->lock, flags);
1777
1778         if (host->flags & SDHCI_DEVICE_DEAD)
1779                 is_readonly = 0;
1780         else if (host->ops->get_ro)
1781                 is_readonly = host->ops->get_ro(host);
1782         else
1783                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1784                                 & SDHCI_WRITE_PROTECT);
1785
1786         spin_unlock_irqrestore(&host->lock, flags);
1787
1788         /* This quirk needs to be replaced by a callback-function later */
1789         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1790                 !is_readonly : is_readonly;
1791 }
1792
1793 #define SAMPLE_COUNT    5
1794
1795 static int sdhci_get_ro(struct mmc_host *mmc)
1796 {
1797         struct sdhci_host *host = mmc_priv(mmc);
1798         int i, ro_count;
1799
1800         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1801                 return sdhci_check_ro(host);
1802
1803         ro_count = 0;
1804         for (i = 0; i < SAMPLE_COUNT; i++) {
1805                 if (sdhci_check_ro(host)) {
1806                         if (++ro_count > SAMPLE_COUNT / 2)
1807                                 return 1;
1808                 }
1809                 msleep(30);
1810         }
1811         return 0;
1812 }
1813
1814 static void sdhci_hw_reset(struct mmc_host *mmc)
1815 {
1816         struct sdhci_host *host = mmc_priv(mmc);
1817
1818         if (host->ops && host->ops->hw_reset)
1819                 host->ops->hw_reset(host);
1820 }
1821
1822 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1823 {
1824         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1825                 if (enable)
1826                         host->ier |= SDHCI_INT_CARD_INT;
1827                 else
1828                         host->ier &= ~SDHCI_INT_CARD_INT;
1829
1830                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1831                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1832                 mmiowb();
1833         }
1834 }
1835
1836 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1837 {
1838         struct sdhci_host *host = mmc_priv(mmc);
1839         unsigned long flags;
1840
1841         if (enable)
1842                 pm_runtime_get_noresume(host->mmc->parent);
1843
1844         spin_lock_irqsave(&host->lock, flags);
1845         if (enable)
1846                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1847         else
1848                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1849
1850         sdhci_enable_sdio_irq_nolock(host, enable);
1851         spin_unlock_irqrestore(&host->lock, flags);
1852
1853         if (!enable)
1854                 pm_runtime_put_noidle(host->mmc->parent);
1855 }
1856
1857 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1858                                              struct mmc_ios *ios)
1859 {
1860         struct sdhci_host *host = mmc_priv(mmc);
1861         u16 ctrl;
1862         int ret;
1863
1864         /*
1865          * Signal Voltage Switching is only applicable for Host Controllers
1866          * v3.00 and above.
1867          */
1868         if (host->version < SDHCI_SPEC_300)
1869                 return 0;
1870
1871         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1872
1873         switch (ios->signal_voltage) {
1874         case MMC_SIGNAL_VOLTAGE_330:
1875                 if (!(host->flags & SDHCI_SIGNALING_330))
1876                         return -EINVAL;
1877                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1878                 ctrl &= ~SDHCI_CTRL_VDD_180;
1879                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1880
1881                 if (!IS_ERR(mmc->supply.vqmmc)) {
1882                         ret = mmc_regulator_set_vqmmc(mmc, ios);
1883                         if (ret) {
1884                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1885                                         mmc_hostname(mmc));
1886                                 return -EIO;
1887                         }
1888                 }
1889                 /* Wait for 5ms */
1890                 usleep_range(5000, 5500);
1891
1892                 /* 3.3V regulator output should be stable within 5 ms */
1893                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1894                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1895                         return 0;
1896
1897                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1898                         mmc_hostname(mmc));
1899
1900                 return -EAGAIN;
1901         case MMC_SIGNAL_VOLTAGE_180:
1902                 if (!(host->flags & SDHCI_SIGNALING_180))
1903                         return -EINVAL;
1904                 if (!IS_ERR(mmc->supply.vqmmc)) {
1905                         ret = mmc_regulator_set_vqmmc(mmc, ios);
1906                         if (ret) {
1907                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1908                                         mmc_hostname(mmc));
1909                                 return -EIO;
1910                         }
1911                 }
1912
1913                 /*
1914                  * Enable 1.8V Signal Enable in the Host Control2
1915                  * register
1916                  */
1917                 ctrl |= SDHCI_CTRL_VDD_180;
1918                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1919
1920                 /* Some controller need to do more when switching */
1921                 if (host->ops->voltage_switch)
1922                         host->ops->voltage_switch(host);
1923
1924                 /* 1.8V regulator output should be stable within 5 ms */
1925                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1926                 if (ctrl & SDHCI_CTRL_VDD_180)
1927                         return 0;
1928
1929                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1930                         mmc_hostname(mmc));
1931
1932                 return -EAGAIN;
1933         case MMC_SIGNAL_VOLTAGE_120:
1934                 if (!(host->flags & SDHCI_SIGNALING_120))
1935                         return -EINVAL;
1936                 if (!IS_ERR(mmc->supply.vqmmc)) {
1937                         ret = mmc_regulator_set_vqmmc(mmc, ios);
1938                         if (ret) {
1939                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1940                                         mmc_hostname(mmc));
1941                                 return -EIO;
1942                         }
1943                 }
1944                 return 0;
1945         default:
1946                 /* No signal voltage switch required */
1947                 return 0;
1948         }
1949 }
1950
1951 static int sdhci_card_busy(struct mmc_host *mmc)
1952 {
1953         struct sdhci_host *host = mmc_priv(mmc);
1954         u32 present_state;
1955
1956         /* Check whether DAT[0] is 0 */
1957         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1958
1959         return !(present_state & SDHCI_DATA_0_LVL_MASK);
1960 }
1961
1962 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1963 {
1964         struct sdhci_host *host = mmc_priv(mmc);
1965         unsigned long flags;
1966
1967         spin_lock_irqsave(&host->lock, flags);
1968         host->flags |= SDHCI_HS400_TUNING;
1969         spin_unlock_irqrestore(&host->lock, flags);
1970
1971         return 0;
1972 }
1973
1974 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1975 {
1976         struct sdhci_host *host = mmc_priv(mmc);
1977         u16 ctrl;
1978         int tuning_loop_counter = MAX_TUNING_LOOP;
1979         int err = 0;
1980         unsigned long flags;
1981         unsigned int tuning_count = 0;
1982         bool hs400_tuning;
1983
1984         spin_lock_irqsave(&host->lock, flags);
1985
1986         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1987         host->flags &= ~SDHCI_HS400_TUNING;
1988
1989         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1990                 tuning_count = host->tuning_count;
1991
1992         /*
1993          * The Host Controller needs tuning in case of SDR104 and DDR50
1994          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1995          * the Capabilities register.
1996          * If the Host Controller supports the HS200 mode then the
1997          * tuning function has to be executed.
1998          */
1999         switch (host->timing) {
2000         /* HS400 tuning is done in HS200 mode */
2001         case MMC_TIMING_MMC_HS400:
2002                 err = -EINVAL;
2003                 goto out_unlock;
2004
2005         case MMC_TIMING_MMC_HS200:
2006                 /*
2007                  * Periodic re-tuning for HS400 is not expected to be needed, so
2008                  * disable it here.
2009                  */
2010                 if (hs400_tuning)
2011                         tuning_count = 0;
2012                 break;
2013
2014         case MMC_TIMING_UHS_SDR104:
2015         case MMC_TIMING_UHS_DDR50:
2016                 break;
2017
2018         case MMC_TIMING_UHS_SDR50:
2019                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2020                         break;
2021                 /* FALLTHROUGH */
2022
2023         default:
2024                 goto out_unlock;
2025         }
2026
2027         if (host->ops->platform_execute_tuning) {
2028                 spin_unlock_irqrestore(&host->lock, flags);
2029                 err = host->ops->platform_execute_tuning(host, opcode);
2030                 return err;
2031         }
2032
2033         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2034         ctrl |= SDHCI_CTRL_EXEC_TUNING;
2035         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2036                 ctrl |= SDHCI_CTRL_TUNED_CLK;
2037         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2038
2039         /*
2040          * As per the Host Controller spec v3.00, tuning command
2041          * generates Buffer Read Ready interrupt, so enable that.
2042          *
2043          * Note: The spec clearly says that when tuning sequence
2044          * is being performed, the controller does not generate
2045          * interrupts other than Buffer Read Ready interrupt. But
2046          * to make sure we don't hit a controller bug, we _only_
2047          * enable Buffer Read Ready interrupt here.
2048          */
2049         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2050         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2051
2052         /*
2053          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
2054          * of loops reaches 40 times.
2055          */
2056         do {
2057                 struct mmc_command cmd = {0};
2058                 struct mmc_request mrq = {NULL};
2059
2060                 cmd.opcode = opcode;
2061                 cmd.arg = 0;
2062                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2063                 cmd.retries = 0;
2064                 cmd.data = NULL;
2065                 cmd.mrq = &mrq;
2066                 cmd.error = 0;
2067
2068                 if (tuning_loop_counter-- == 0)
2069                         break;
2070
2071                 mrq.cmd = &cmd;
2072
2073                 /*
2074                  * In response to CMD19, the card sends 64 bytes of tuning
2075                  * block to the Host Controller. So we set the block size
2076                  * to 64 here.
2077                  */
2078                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2079                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2080                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2081                                              SDHCI_BLOCK_SIZE);
2082                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2083                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2084                                              SDHCI_BLOCK_SIZE);
2085                 } else {
2086                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2087                                      SDHCI_BLOCK_SIZE);
2088                 }
2089
2090                 /*
2091                  * The tuning block is sent by the card to the host controller.
2092                  * So we set the TRNS_READ bit in the Transfer Mode register.
2093                  * This also takes care of setting DMA Enable and Multi Block
2094                  * Select in the same register to 0.
2095                  */
2096                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2097
2098                 sdhci_send_command(host, &cmd);
2099
2100                 host->cmd = NULL;
2101                 sdhci_del_timer(host, &mrq);
2102
2103                 spin_unlock_irqrestore(&host->lock, flags);
2104                 /* Wait for Buffer Read Ready interrupt */
2105                 wait_event_timeout(host->buf_ready_int,
2106                                         (host->tuning_done == 1),
2107                                         msecs_to_jiffies(50));
2108                 spin_lock_irqsave(&host->lock, flags);
2109
2110                 if (!host->tuning_done) {
2111                         pr_debug(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
2112                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2113                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2114                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2115                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2116
2117                         sdhci_do_reset(host, SDHCI_RESET_CMD);
2118                         sdhci_do_reset(host, SDHCI_RESET_DATA);
2119
2120                         err = -EIO;
2121
2122                         if (cmd.opcode != MMC_SEND_TUNING_BLOCK_HS200)
2123                                 goto out;
2124
2125                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2126                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2127
2128                         spin_unlock_irqrestore(&host->lock, flags);
2129
2130                         memset(&cmd, 0, sizeof(cmd));
2131                         cmd.opcode = MMC_STOP_TRANSMISSION;
2132                         cmd.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
2133                         cmd.busy_timeout = 50;
2134                         mmc_wait_for_cmd(mmc, &cmd, 0);
2135
2136                         spin_lock_irqsave(&host->lock, flags);
2137
2138                         goto out;
2139                 }
2140
2141                 host->tuning_done = 0;
2142
2143                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2144
2145                 /* eMMC spec does not require a delay between tuning cycles */
2146                 if (opcode == MMC_SEND_TUNING_BLOCK)
2147                         mdelay(1);
2148         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2149
2150         /*
2151          * The Host Driver has exhausted the maximum number of loops allowed,
2152          * so use fixed sampling frequency.
2153          */
2154         if (tuning_loop_counter < 0) {
2155                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2156                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2157         }
2158         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2159                 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
2160                 err = -EIO;
2161         }
2162
2163 out:
2164         if (tuning_count) {
2165                 /*
2166                  * In case tuning fails, host controllers which support
2167                  * re-tuning can try tuning again at a later time, when the
2168                  * re-tuning timer expires.  So for these controllers, we
2169                  * return 0. Since there might be other controllers who do not
2170                  * have this capability, we return error for them.
2171                  */
2172                 err = 0;
2173         }
2174
2175         host->mmc->retune_period = err ? 0 : tuning_count;
2176
2177         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2178         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2179 out_unlock:
2180         spin_unlock_irqrestore(&host->lock, flags);
2181         return err;
2182 }
2183
2184 static int sdhci_select_drive_strength(struct mmc_card *card,
2185                                        unsigned int max_dtr, int host_drv,
2186                                        int card_drv, int *drv_type)
2187 {
2188         struct sdhci_host *host = mmc_priv(card->host);
2189
2190         if (!host->ops->select_drive_strength)
2191                 return 0;
2192
2193         return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2194                                                 card_drv, drv_type);
2195 }
2196
2197 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2198 {
2199         /* Host Controller v3.00 defines preset value registers */
2200         if (host->version < SDHCI_SPEC_300)
2201                 return;
2202
2203         /*
2204          * We only enable or disable Preset Value if they are not already
2205          * enabled or disabled respectively. Otherwise, we bail out.
2206          */
2207         if (host->preset_enabled != enable) {
2208                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2209
2210                 if (enable)
2211                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2212                 else
2213                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2214
2215                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2216
2217                 if (enable)
2218                         host->flags |= SDHCI_PV_ENABLED;
2219                 else
2220                         host->flags &= ~SDHCI_PV_ENABLED;
2221
2222                 host->preset_enabled = enable;
2223         }
2224 }
2225
2226 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2227                                 int err)
2228 {
2229         struct sdhci_host *host = mmc_priv(mmc);
2230         struct mmc_data *data = mrq->data;
2231
2232         if (data->host_cookie != COOKIE_UNMAPPED)
2233                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2234                              data->flags & MMC_DATA_WRITE ?
2235                                DMA_TO_DEVICE : DMA_FROM_DEVICE);
2236
2237         data->host_cookie = COOKIE_UNMAPPED;
2238 }
2239
2240 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2241                                bool is_first_req)
2242 {
2243         struct sdhci_host *host = mmc_priv(mmc);
2244
2245         mrq->data->host_cookie = COOKIE_UNMAPPED;
2246
2247         if (host->flags & SDHCI_REQ_USE_DMA)
2248                 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2249 }
2250
2251 static inline bool sdhci_has_requests(struct sdhci_host *host)
2252 {
2253         return host->cmd || host->data_cmd;
2254 }
2255
2256 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2257 {
2258         if (host->data_cmd) {
2259                 host->data_cmd->error = err;
2260                 sdhci_finish_mrq(host, host->data_cmd->mrq);
2261         }
2262
2263         if (host->cmd) {
2264                 host->cmd->error = err;
2265                 sdhci_finish_mrq(host, host->cmd->mrq);
2266         }
2267 }
2268
2269 static void sdhci_card_event(struct mmc_host *mmc)
2270 {
2271         struct sdhci_host *host = mmc_priv(mmc);
2272         unsigned long flags;
2273         int present;
2274
2275         /* First check if client has provided their own card event */
2276         if (host->ops->card_event)
2277                 host->ops->card_event(host);
2278
2279         present = mmc->ops->get_cd(mmc);
2280
2281         spin_lock_irqsave(&host->lock, flags);
2282
2283         /* Check sdhci_has_requests() first in case we are runtime suspended */
2284         if (sdhci_has_requests(host) && !present) {
2285                 pr_err("%s: Card removed during transfer!\n",
2286                         mmc_hostname(host->mmc));
2287                 pr_err("%s: Resetting controller.\n",
2288                         mmc_hostname(host->mmc));
2289
2290                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2291                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2292
2293                 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2294         }
2295
2296         spin_unlock_irqrestore(&host->lock, flags);
2297 }
2298
2299 static const struct mmc_host_ops sdhci_ops = {
2300         .request        = sdhci_request,
2301         .post_req       = sdhci_post_req,
2302         .pre_req        = sdhci_pre_req,
2303         .set_ios        = sdhci_set_ios,
2304         .get_cd         = sdhci_get_cd,
2305         .get_ro         = sdhci_get_ro,
2306         .hw_reset       = sdhci_hw_reset,
2307         .enable_sdio_irq = sdhci_enable_sdio_irq,
2308         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2309         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2310         .execute_tuning                 = sdhci_execute_tuning,
2311         .select_drive_strength          = sdhci_select_drive_strength,
2312         .card_event                     = sdhci_card_event,
2313         .card_busy      = sdhci_card_busy,
2314 };
2315
2316 /*****************************************************************************\
2317  *                                                                           *
2318  * Tasklets                                                                  *
2319  *                                                                           *
2320 \*****************************************************************************/
2321
2322 static bool sdhci_request_done(struct sdhci_host *host)
2323 {
2324         unsigned long flags;
2325         struct mmc_request *mrq;
2326         int i;
2327
2328         spin_lock_irqsave(&host->lock, flags);
2329
2330         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2331                 mrq = host->mrqs_done[i];
2332                 if (mrq)
2333                         break;
2334         }
2335
2336         if (!mrq) {
2337                 spin_unlock_irqrestore(&host->lock, flags);
2338                 return true;
2339         }
2340
2341         sdhci_del_timer(host, mrq);
2342
2343         /*
2344          * Always unmap the data buffers if they were mapped by
2345          * sdhci_prepare_data() whenever we finish with a request.
2346          * This avoids leaking DMA mappings on error.
2347          */
2348         if (host->flags & SDHCI_REQ_USE_DMA) {
2349                 struct mmc_data *data = mrq->data;
2350
2351                 if (data && data->host_cookie == COOKIE_MAPPED) {
2352                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2353                                      (data->flags & MMC_DATA_READ) ?
2354                                      DMA_FROM_DEVICE : DMA_TO_DEVICE);
2355                         data->host_cookie = COOKIE_UNMAPPED;
2356                 }
2357         }
2358
2359         /*
2360          * The controller needs a reset of internal state machines
2361          * upon error conditions.
2362          */
2363         if (sdhci_needs_reset(host, mrq)) {
2364                 /*
2365                  * Do not finish until command and data lines are available for
2366                  * reset. Note there can only be one other mrq, so it cannot
2367                  * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2368                  * would both be null.
2369                  */
2370                 if (host->cmd || host->data_cmd) {
2371                         spin_unlock_irqrestore(&host->lock, flags);
2372                         return true;
2373                 }
2374
2375                 /* Some controllers need this kick or reset won't work here */
2376                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2377                         /* This is to force an update */
2378                         host->ops->set_clock(host, host->clock);
2379
2380                 /* Spec says we should do both at the same time, but Ricoh
2381                    controllers do not like that. */
2382                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2383                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2384
2385                 host->pending_reset = false;
2386         }
2387
2388         if (!sdhci_has_requests(host))
2389                 sdhci_led_deactivate(host);
2390
2391         host->mrqs_done[i] = NULL;
2392
2393         mmiowb();
2394         spin_unlock_irqrestore(&host->lock, flags);
2395
2396         mmc_request_done(host->mmc, mrq);
2397
2398         return false;
2399 }
2400
2401 static void sdhci_tasklet_finish(unsigned long param)
2402 {
2403         struct sdhci_host *host = (struct sdhci_host *)param;
2404
2405         while (!sdhci_request_done(host))
2406                 ;
2407 }
2408
2409 static void sdhci_timeout_timer(unsigned long data)
2410 {
2411         struct sdhci_host *host;
2412         unsigned long flags;
2413
2414         host = (struct sdhci_host*)data;
2415
2416         spin_lock_irqsave(&host->lock, flags);
2417
2418         if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2419                 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2420                        mmc_hostname(host->mmc));
2421                 sdhci_dumpregs(host);
2422
2423                 host->cmd->error = -ETIMEDOUT;
2424                 sdhci_finish_mrq(host, host->cmd->mrq);
2425         }
2426
2427         mmiowb();
2428         spin_unlock_irqrestore(&host->lock, flags);
2429 }
2430
2431 static void sdhci_timeout_data_timer(unsigned long data)
2432 {
2433         struct sdhci_host *host;
2434         unsigned long flags;
2435
2436         host = (struct sdhci_host *)data;
2437
2438         spin_lock_irqsave(&host->lock, flags);
2439
2440         if (host->data || host->data_cmd ||
2441             (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2442                 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2443                        mmc_hostname(host->mmc));
2444                 sdhci_dumpregs(host);
2445
2446                 if (host->data) {
2447                         host->data->error = -ETIMEDOUT;
2448                         sdhci_finish_data(host);
2449                 } else if (host->data_cmd) {
2450                         host->data_cmd->error = -ETIMEDOUT;
2451                         sdhci_finish_mrq(host, host->data_cmd->mrq);
2452                 } else {
2453                         host->cmd->error = -ETIMEDOUT;
2454                         sdhci_finish_mrq(host, host->cmd->mrq);
2455                 }
2456         }
2457
2458         mmiowb();
2459         spin_unlock_irqrestore(&host->lock, flags);
2460 }
2461
2462 /*****************************************************************************\
2463  *                                                                           *
2464  * Interrupt handling                                                        *
2465  *                                                                           *
2466 \*****************************************************************************/
2467
2468 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
2469 {
2470         if (!host->cmd) {
2471                 /*
2472                  * SDHCI recovers from errors by resetting the cmd and data
2473                  * circuits.  Until that is done, there very well might be more
2474                  * interrupts, so ignore them in that case.
2475                  */
2476                 if (host->pending_reset)
2477                         return;
2478                 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2479                        mmc_hostname(host->mmc), (unsigned)intmask);
2480                 sdhci_dumpregs(host);
2481                 return;
2482         }
2483
2484         if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2485                        SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2486                 if (intmask & SDHCI_INT_TIMEOUT)
2487                         host->cmd->error = -ETIMEDOUT;
2488                 else
2489                         host->cmd->error = -EILSEQ;
2490
2491                 /* Treat data command CRC error the same as data CRC error */
2492                 if (host->cmd->data &&
2493                     (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2494                      SDHCI_INT_CRC) {
2495                         host->cmd = NULL;
2496                         *intmask_p |= SDHCI_INT_DATA_CRC;
2497                         return;
2498                 }
2499
2500                 sdhci_finish_mrq(host, host->cmd->mrq);
2501                 return;
2502         }
2503
2504         if (intmask & SDHCI_INT_RESPONSE)
2505                 sdhci_finish_command(host);
2506 }
2507
2508 #ifdef CONFIG_MMC_DEBUG
2509 static void sdhci_adma_show_error(struct sdhci_host *host)
2510 {
2511         const char *name = mmc_hostname(host->mmc);
2512         void *desc = host->adma_table;
2513
2514         sdhci_dumpregs(host);
2515
2516         while (true) {
2517                 struct sdhci_adma2_64_desc *dma_desc = desc;
2518
2519                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2520                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2521                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2522                             le32_to_cpu(dma_desc->addr_lo),
2523                             le16_to_cpu(dma_desc->len),
2524                             le16_to_cpu(dma_desc->cmd));
2525                 else
2526                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2527                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2528                             le16_to_cpu(dma_desc->len),
2529                             le16_to_cpu(dma_desc->cmd));
2530
2531                 desc += host->desc_sz;
2532
2533                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2534                         break;
2535         }
2536 }
2537 #else
2538 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2539 #endif
2540
2541 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2542 {
2543         u32 command;
2544
2545         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2546         if (intmask & SDHCI_INT_DATA_AVAIL) {
2547                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2548                 if (command == MMC_SEND_TUNING_BLOCK ||
2549                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2550                         host->tuning_done = 1;
2551                         wake_up(&host->buf_ready_int);
2552                         return;
2553                 }
2554         }
2555
2556         if (!host->data) {
2557                 struct mmc_command *data_cmd = host->data_cmd;
2558
2559                 /*
2560                  * The "data complete" interrupt is also used to
2561                  * indicate that a busy state has ended. See comment
2562                  * above in sdhci_cmd_irq().
2563                  */
2564                 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2565                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2566                                 host->data_cmd = NULL;
2567                                 data_cmd->error = -ETIMEDOUT;
2568                                 sdhci_finish_mrq(host, data_cmd->mrq);
2569                                 return;
2570                         }
2571                         if (intmask & SDHCI_INT_DATA_END) {
2572                                 host->data_cmd = NULL;
2573                                 /*
2574                                  * Some cards handle busy-end interrupt
2575                                  * before the command completed, so make
2576                                  * sure we do things in the proper order.
2577                                  */
2578                                 if (host->cmd == data_cmd)
2579                                         return;
2580
2581                                 sdhci_finish_mrq(host, data_cmd->mrq);
2582                                 return;
2583                         }
2584                 }
2585
2586                 /*
2587                  * SDHCI recovers from errors by resetting the cmd and data
2588                  * circuits. Until that is done, there very well might be more
2589                  * interrupts, so ignore them in that case.
2590                  */
2591                 if (host->pending_reset)
2592                         return;
2593
2594                 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2595                        mmc_hostname(host->mmc), (unsigned)intmask);
2596                 sdhci_dumpregs(host);
2597
2598                 return;
2599         }
2600
2601         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2602                 host->data->error = -ETIMEDOUT;
2603         else if (intmask & SDHCI_INT_DATA_END_BIT)
2604                 host->data->error = -EILSEQ;
2605         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2606                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2607                         != MMC_BUS_TEST_R)
2608                 host->data->error = -EILSEQ;
2609         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2610                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2611                 sdhci_adma_show_error(host);
2612                 host->data->error = -EIO;
2613                 if (host->ops->adma_workaround)
2614                         host->ops->adma_workaround(host, intmask);
2615         }
2616
2617         if (host->data->error)
2618                 sdhci_finish_data(host);
2619         else {
2620                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2621                         sdhci_transfer_pio(host);
2622
2623                 /*
2624                  * We currently don't do anything fancy with DMA
2625                  * boundaries, but as we can't disable the feature
2626                  * we need to at least restart the transfer.
2627                  *
2628                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2629                  * should return a valid address to continue from, but as
2630                  * some controllers are faulty, don't trust them.
2631                  */
2632                 if (intmask & SDHCI_INT_DMA_END) {
2633                         u32 dmastart, dmanow;
2634                         dmastart = sg_dma_address(host->data->sg);
2635                         dmanow = dmastart + host->data->bytes_xfered;
2636                         /*
2637                          * Force update to the next DMA block boundary.
2638                          */
2639                         dmanow = (dmanow &
2640                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2641                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2642                         host->data->bytes_xfered = dmanow - dmastart;
2643                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2644                                 " next 0x%08x\n",
2645                                 mmc_hostname(host->mmc), dmastart,
2646                                 host->data->bytes_xfered, dmanow);
2647                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2648                 }
2649
2650                 if (intmask & SDHCI_INT_DATA_END) {
2651                         if (host->cmd == host->data_cmd) {
2652                                 /*
2653                                  * Data managed to finish before the
2654                                  * command completed. Make sure we do
2655                                  * things in the proper order.
2656                                  */
2657                                 host->data_early = 1;
2658                         } else {
2659                                 sdhci_finish_data(host);
2660                         }
2661                 }
2662         }
2663 }
2664
2665 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2666 {
2667         irqreturn_t result = IRQ_NONE;
2668         struct sdhci_host *host = dev_id;
2669         u32 intmask, mask, unexpected = 0;
2670         int max_loops = 16;
2671
2672         spin_lock(&host->lock);
2673
2674         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2675                 spin_unlock(&host->lock);
2676                 return IRQ_NONE;
2677         }
2678
2679         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2680         if (!intmask || intmask == 0xffffffff) {
2681                 result = IRQ_NONE;
2682                 goto out;
2683         }
2684
2685         do {
2686                 /* Clear selected interrupts. */
2687                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2688                                   SDHCI_INT_BUS_POWER);
2689                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2690
2691                 DBG("*** %s got interrupt: 0x%08x\n",
2692                         mmc_hostname(host->mmc), intmask);
2693
2694                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2695                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2696                                       SDHCI_CARD_PRESENT;
2697
2698                         /*
2699                          * There is a observation on i.mx esdhc.  INSERT
2700                          * bit will be immediately set again when it gets
2701                          * cleared, if a card is inserted.  We have to mask
2702                          * the irq to prevent interrupt storm which will
2703                          * freeze the system.  And the REMOVE gets the
2704                          * same situation.
2705                          *
2706                          * More testing are needed here to ensure it works
2707                          * for other platforms though.
2708                          */
2709                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2710                                        SDHCI_INT_CARD_REMOVE);
2711                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2712                                                SDHCI_INT_CARD_INSERT;
2713                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2714                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2715
2716                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2717                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2718
2719                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2720                                                        SDHCI_INT_CARD_REMOVE);
2721                         result = IRQ_WAKE_THREAD;
2722                 }
2723
2724                 if (intmask & SDHCI_INT_CMD_MASK)
2725                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
2726
2727                 if (intmask & SDHCI_INT_DATA_MASK)
2728                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2729
2730                 if (intmask & SDHCI_INT_BUS_POWER)
2731                         pr_err("%s: Card is consuming too much power!\n",
2732                                 mmc_hostname(host->mmc));
2733
2734                 if (intmask & SDHCI_INT_RETUNE)
2735                         mmc_retune_needed(host->mmc);
2736
2737                 if ((intmask & SDHCI_INT_CARD_INT) &&
2738                     (host->ier & SDHCI_INT_CARD_INT)) {
2739                         sdhci_enable_sdio_irq_nolock(host, false);
2740                         host->thread_isr |= SDHCI_INT_CARD_INT;
2741                         result = IRQ_WAKE_THREAD;
2742                 }
2743
2744                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2745                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2746                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2747                              SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2748
2749                 if (intmask) {
2750                         unexpected |= intmask;
2751                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2752                 }
2753
2754                 if (result == IRQ_NONE)
2755                         result = IRQ_HANDLED;
2756
2757                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2758         } while (intmask && --max_loops);
2759 out:
2760         spin_unlock(&host->lock);
2761
2762         if (unexpected) {
2763                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2764                            mmc_hostname(host->mmc), unexpected);
2765                 sdhci_dumpregs(host);
2766         }
2767
2768         return result;
2769 }
2770
2771 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2772 {
2773         struct sdhci_host *host = dev_id;
2774         unsigned long flags;
2775         u32 isr;
2776
2777         spin_lock_irqsave(&host->lock, flags);
2778         isr = host->thread_isr;
2779         host->thread_isr = 0;
2780         spin_unlock_irqrestore(&host->lock, flags);
2781
2782         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2783                 struct mmc_host *mmc = host->mmc;
2784
2785                 mmc->ops->card_event(mmc);
2786                 mmc_detect_change(mmc, msecs_to_jiffies(200));
2787         }
2788
2789         if (isr & SDHCI_INT_CARD_INT) {
2790                 sdio_run_irqs(host->mmc);
2791
2792                 spin_lock_irqsave(&host->lock, flags);
2793                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2794                         sdhci_enable_sdio_irq_nolock(host, true);
2795                 spin_unlock_irqrestore(&host->lock, flags);
2796         }
2797
2798         return isr ? IRQ_HANDLED : IRQ_NONE;
2799 }
2800
2801 /*****************************************************************************\
2802  *                                                                           *
2803  * Suspend/resume                                                            *
2804  *                                                                           *
2805 \*****************************************************************************/
2806
2807 #ifdef CONFIG_PM
2808 /*
2809  * To enable wakeup events, the corresponding events have to be enabled in
2810  * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2811  * Table' in the SD Host Controller Standard Specification.
2812  * It is useless to restore SDHCI_INT_ENABLE state in
2813  * sdhci_disable_irq_wakeups() since it will be set by
2814  * sdhci_enable_card_detection() or sdhci_init().
2815  */
2816 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2817 {
2818         u8 val;
2819         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2820                         | SDHCI_WAKE_ON_INT;
2821         u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2822                       SDHCI_INT_CARD_INT;
2823
2824         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2825         val |= mask ;
2826         /* Avoid fake wake up */
2827         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
2828                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2829                 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2830         }
2831         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2832         sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2833 }
2834 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2835
2836 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2837 {
2838         u8 val;
2839         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2840                         | SDHCI_WAKE_ON_INT;
2841
2842         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2843         val &= ~mask;
2844         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2845 }
2846
2847 int sdhci_suspend_host(struct sdhci_host *host)
2848 {
2849         sdhci_disable_card_detection(host);
2850
2851         mmc_retune_timer_stop(host->mmc);
2852         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2853                 mmc_retune_needed(host->mmc);
2854
2855         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2856                 host->ier = 0;
2857                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2858                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2859                 free_irq(host->irq, host);
2860         } else {
2861                 sdhci_enable_irq_wakeups(host);
2862                 enable_irq_wake(host->irq);
2863         }
2864         return 0;
2865 }
2866
2867 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2868
2869 int sdhci_resume_host(struct sdhci_host *host)
2870 {
2871         struct mmc_host *mmc = host->mmc;
2872         int ret = 0;
2873
2874         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2875                 if (host->ops->enable_dma)
2876                         host->ops->enable_dma(host);
2877         }
2878
2879         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2880             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2881                 /* Card keeps power but host controller does not */
2882                 sdhci_init(host, 0);
2883                 host->pwr = 0;
2884                 host->clock = 0;
2885                 mmc->ops->set_ios(mmc, &mmc->ios);
2886         } else {
2887                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2888                 mmiowb();
2889         }
2890
2891         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2892                 ret = request_threaded_irq(host->irq, sdhci_irq,
2893                                            sdhci_thread_irq, IRQF_SHARED,
2894                                            mmc_hostname(host->mmc), host);
2895                 if (ret)
2896                         return ret;
2897         } else {
2898                 sdhci_disable_irq_wakeups(host);
2899                 disable_irq_wake(host->irq);
2900         }
2901
2902         sdhci_enable_card_detection(host);
2903
2904         return ret;
2905 }
2906
2907 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2908
2909 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2910 {
2911         unsigned long flags;
2912
2913         mmc_retune_timer_stop(host->mmc);
2914         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2915                 mmc_retune_needed(host->mmc);
2916
2917         spin_lock_irqsave(&host->lock, flags);
2918         host->ier &= SDHCI_INT_CARD_INT;
2919         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2920         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2921         spin_unlock_irqrestore(&host->lock, flags);
2922
2923         synchronize_hardirq(host->irq);
2924
2925         spin_lock_irqsave(&host->lock, flags);
2926         host->runtime_suspended = true;
2927         spin_unlock_irqrestore(&host->lock, flags);
2928
2929         return 0;
2930 }
2931 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2932
2933 int sdhci_runtime_resume_host(struct sdhci_host *host)
2934 {
2935         struct mmc_host *mmc = host->mmc;
2936         unsigned long flags;
2937         int host_flags = host->flags;
2938
2939         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2940                 if (host->ops->enable_dma)
2941                         host->ops->enable_dma(host);
2942         }
2943
2944         sdhci_init(host, 0);
2945
2946         /* Force clock and power re-program */
2947         host->pwr = 0;
2948         host->clock = 0;
2949         mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2950         mmc->ops->set_ios(mmc, &mmc->ios);
2951
2952         if ((host_flags & SDHCI_PV_ENABLED) &&
2953                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2954                 spin_lock_irqsave(&host->lock, flags);
2955                 sdhci_enable_preset_value(host, true);
2956                 spin_unlock_irqrestore(&host->lock, flags);
2957         }
2958
2959         if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
2960             mmc->ops->hs400_enhanced_strobe)
2961                 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
2962
2963         spin_lock_irqsave(&host->lock, flags);
2964
2965         host->runtime_suspended = false;
2966
2967         /* Enable SDIO IRQ */
2968         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2969                 sdhci_enable_sdio_irq_nolock(host, true);
2970
2971         /* Enable Card Detection */
2972         sdhci_enable_card_detection(host);
2973
2974         spin_unlock_irqrestore(&host->lock, flags);
2975
2976         return 0;
2977 }
2978 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2979
2980 #endif /* CONFIG_PM */
2981
2982 /*****************************************************************************\
2983  *                                                                           *
2984  * Device allocation/registration                                            *
2985  *                                                                           *
2986 \*****************************************************************************/
2987
2988 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2989         size_t priv_size)
2990 {
2991         struct mmc_host *mmc;
2992         struct sdhci_host *host;
2993
2994         WARN_ON(dev == NULL);
2995
2996         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2997         if (!mmc)
2998                 return ERR_PTR(-ENOMEM);
2999
3000         host = mmc_priv(mmc);
3001         host->mmc = mmc;
3002         host->mmc_host_ops = sdhci_ops;
3003         mmc->ops = &host->mmc_host_ops;
3004
3005         host->flags = SDHCI_SIGNALING_330;
3006
3007         return host;
3008 }
3009
3010 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3011
3012 static int sdhci_set_dma_mask(struct sdhci_host *host)
3013 {
3014         struct mmc_host *mmc = host->mmc;
3015         struct device *dev = mmc_dev(mmc);
3016         int ret = -EINVAL;
3017
3018         if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3019                 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3020
3021         /* Try 64-bit mask if hardware is capable  of it */
3022         if (host->flags & SDHCI_USE_64_BIT_DMA) {
3023                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3024                 if (ret) {
3025                         pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3026                                 mmc_hostname(mmc));
3027                         host->flags &= ~SDHCI_USE_64_BIT_DMA;
3028                 }
3029         }
3030
3031         /* 32-bit mask as default & fallback */
3032         if (ret) {
3033                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3034                 if (ret)
3035                         pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3036                                 mmc_hostname(mmc));
3037         }
3038
3039         return ret;
3040 }
3041
3042 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3043 {
3044         u16 v;
3045
3046         if (host->read_caps)
3047                 return;
3048
3049         host->read_caps = true;
3050
3051         if (debug_quirks)
3052                 host->quirks = debug_quirks;
3053
3054         if (debug_quirks2)
3055                 host->quirks2 = debug_quirks2;
3056
3057         sdhci_do_reset(host, SDHCI_RESET_ALL);
3058
3059         v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3060         host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3061
3062         if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3063                 return;
3064
3065         host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
3066
3067         if (host->version < SDHCI_SPEC_300)
3068                 return;
3069
3070         host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
3071 }
3072 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3073
3074 int sdhci_setup_host(struct sdhci_host *host)
3075 {
3076         struct mmc_host *mmc;
3077         u32 max_current_caps;
3078         unsigned int ocr_avail;
3079         unsigned int override_timeout_clk;
3080         u32 max_clk;
3081         int ret;
3082
3083         WARN_ON(host == NULL);
3084         if (host == NULL)
3085                 return -EINVAL;
3086
3087         mmc = host->mmc;
3088
3089         /*
3090          * If there are external regulators, get them. Note this must be done
3091          * early before resetting the host and reading the capabilities so that
3092          * the host can take the appropriate action if regulators are not
3093          * available.
3094          */
3095         ret = mmc_regulator_get_supply(mmc);
3096         if (ret == -EPROBE_DEFER)
3097                 return ret;
3098
3099         sdhci_read_caps(host);
3100
3101         override_timeout_clk = host->timeout_clk;
3102
3103         if (host->version > SDHCI_SPEC_300) {
3104                 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3105                        mmc_hostname(mmc), host->version);
3106         }
3107
3108         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3109                 host->flags |= SDHCI_USE_SDMA;
3110         else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3111                 DBG("Controller doesn't have SDMA capability\n");
3112         else
3113                 host->flags |= SDHCI_USE_SDMA;
3114
3115         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3116                 (host->flags & SDHCI_USE_SDMA)) {
3117                 DBG("Disabling DMA as it is marked broken\n");
3118                 host->flags &= ~SDHCI_USE_SDMA;
3119         }
3120
3121         if ((host->version >= SDHCI_SPEC_200) &&
3122                 (host->caps & SDHCI_CAN_DO_ADMA2))
3123                 host->flags |= SDHCI_USE_ADMA;
3124
3125         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3126                 (host->flags & SDHCI_USE_ADMA)) {
3127                 DBG("Disabling ADMA as it is marked broken\n");
3128                 host->flags &= ~SDHCI_USE_ADMA;
3129         }
3130
3131         /*
3132          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3133          * and *must* do 64-bit DMA.  A driver has the opportunity to change
3134          * that during the first call to ->enable_dma().  Similarly
3135          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3136          * implement.
3137          */
3138         if (host->caps & SDHCI_CAN_64BIT)
3139                 host->flags |= SDHCI_USE_64_BIT_DMA;
3140
3141         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3142                 ret = sdhci_set_dma_mask(host);
3143
3144                 if (!ret && host->ops->enable_dma)
3145                         ret = host->ops->enable_dma(host);
3146
3147                 if (ret) {
3148                         pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3149                                 mmc_hostname(mmc));
3150                         host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3151
3152                         ret = 0;
3153                 }
3154         }
3155
3156         /* SDMA does not support 64-bit DMA */
3157         if (host->flags & SDHCI_USE_64_BIT_DMA)
3158                 host->flags &= ~SDHCI_USE_SDMA;
3159
3160         if (host->flags & SDHCI_USE_ADMA) {
3161                 dma_addr_t dma;
3162                 void *buf;
3163
3164                 /*
3165                  * The DMA descriptor table size is calculated as the maximum
3166                  * number of segments times 2, to allow for an alignment
3167                  * descriptor for each segment, plus 1 for a nop end descriptor,
3168                  * all multipled by the descriptor size.
3169                  */
3170                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3171                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3172                                               SDHCI_ADMA2_64_DESC_SZ;
3173                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3174                 } else {
3175                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3176                                               SDHCI_ADMA2_32_DESC_SZ;
3177                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3178                 }
3179
3180                 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3181                 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3182                                          host->adma_table_sz, &dma, GFP_KERNEL);
3183                 if (!buf) {
3184                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3185                                 mmc_hostname(mmc));
3186                         host->flags &= ~SDHCI_USE_ADMA;
3187                 } else if ((dma + host->align_buffer_sz) &
3188                            (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3189                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3190                                 mmc_hostname(mmc));
3191                         host->flags &= ~SDHCI_USE_ADMA;
3192                         dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3193                                           host->adma_table_sz, buf, dma);
3194                 } else {
3195                         host->align_buffer = buf;
3196                         host->align_addr = dma;
3197
3198                         host->adma_table = buf + host->align_buffer_sz;
3199                         host->adma_addr = dma + host->align_buffer_sz;
3200                 }
3201         }
3202
3203         /*
3204          * If we use DMA, then it's up to the caller to set the DMA
3205          * mask, but PIO does not need the hw shim so we set a new
3206          * mask here in that case.
3207          */
3208         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3209                 host->dma_mask = DMA_BIT_MASK(64);
3210                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3211         }
3212
3213         if (host->version >= SDHCI_SPEC_300)
3214                 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3215                         >> SDHCI_CLOCK_BASE_SHIFT;
3216         else
3217                 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3218                         >> SDHCI_CLOCK_BASE_SHIFT;
3219
3220         host->max_clk *= 1000000;
3221         if (host->max_clk == 0 || host->quirks &
3222                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3223                 if (!host->ops->get_max_clock) {
3224                         pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3225                                mmc_hostname(mmc));
3226                         ret = -ENODEV;
3227                         goto undma;
3228                 }
3229                 host->max_clk = host->ops->get_max_clock(host);
3230         }
3231
3232         /*
3233          * In case of Host Controller v3.00, find out whether clock
3234          * multiplier is supported.
3235          */
3236         host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3237                         SDHCI_CLOCK_MUL_SHIFT;
3238
3239         /*
3240          * In case the value in Clock Multiplier is 0, then programmable
3241          * clock mode is not supported, otherwise the actual clock
3242          * multiplier is one more than the value of Clock Multiplier
3243          * in the Capabilities Register.
3244          */
3245         if (host->clk_mul)
3246                 host->clk_mul += 1;
3247
3248         /*
3249          * Set host parameters.
3250          */
3251         max_clk = host->max_clk;
3252
3253         if (host->ops->get_min_clock)
3254                 mmc->f_min = host->ops->get_min_clock(host);
3255         else if (host->version >= SDHCI_SPEC_300) {
3256                 if (host->clk_mul)
3257                         max_clk = host->max_clk * host->clk_mul;
3258                 /*
3259                  * Divided Clock Mode minimum clock rate is always less than
3260                  * Programmable Clock Mode minimum clock rate.
3261                  */
3262                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3263         } else
3264                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3265
3266         if (!mmc->f_max || mmc->f_max > max_clk)
3267                 mmc->f_max = max_clk;
3268
3269         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3270                 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3271                                         SDHCI_TIMEOUT_CLK_SHIFT;
3272                 if (host->timeout_clk == 0) {
3273                         if (host->ops->get_timeout_clock) {
3274                                 host->timeout_clk =
3275                                         host->ops->get_timeout_clock(host);
3276                         } else {
3277                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3278                                         mmc_hostname(mmc));
3279                                 ret = -ENODEV;
3280                                 goto undma;
3281                         }
3282                 }
3283
3284                 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3285                         host->timeout_clk *= 1000;
3286
3287                 if (override_timeout_clk)
3288                         host->timeout_clk = override_timeout_clk;
3289
3290                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3291                         host->ops->get_max_timeout_count(host) : 1 << 27;
3292                 mmc->max_busy_timeout /= host->timeout_clk;
3293         }
3294
3295         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3296         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3297
3298         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3299                 host->flags |= SDHCI_AUTO_CMD12;
3300
3301         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3302         if ((host->version >= SDHCI_SPEC_300) &&
3303             ((host->flags & SDHCI_USE_ADMA) ||
3304              !(host->flags & SDHCI_USE_SDMA)) &&
3305              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3306                 host->flags |= SDHCI_AUTO_CMD23;
3307                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3308         } else {
3309                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3310         }
3311
3312         /*
3313          * A controller may support 8-bit width, but the board itself
3314          * might not have the pins brought out.  Boards that support
3315          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3316          * their platform code before calling sdhci_add_host(), and we
3317          * won't assume 8-bit width for hosts without that CAP.
3318          */
3319         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3320                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3321
3322         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3323                 mmc->caps &= ~MMC_CAP_CMD23;
3324
3325         if (host->caps & SDHCI_CAN_DO_HISPD)
3326                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3327
3328         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3329             mmc_card_is_removable(mmc) &&
3330             mmc_gpio_get_cd(host->mmc) < 0)
3331                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3332
3333         if (!IS_ERR(mmc->supply.vqmmc)) {
3334                 ret = regulator_enable(mmc->supply.vqmmc);
3335
3336                 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
3337                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3338                                                     1950000))
3339                         host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3340                                          SDHCI_SUPPORT_SDR50 |
3341                                          SDHCI_SUPPORT_DDR50);
3342
3343                 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
3344                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
3345                                                     3600000))
3346                         host->flags &= ~SDHCI_SIGNALING_330;
3347
3348                 if (ret) {
3349                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3350                                 mmc_hostname(mmc), ret);
3351                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3352                 }
3353         }
3354
3355         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3356                 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3357                                  SDHCI_SUPPORT_DDR50);
3358         }
3359
3360         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3361         if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3362                            SDHCI_SUPPORT_DDR50))
3363                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3364
3365         /* SDR104 supports also implies SDR50 support */
3366         if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3367                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3368                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3369                  * field can be promoted to support HS200.
3370                  */
3371                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3372                         mmc->caps2 |= MMC_CAP2_HS200;
3373         } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3374                 mmc->caps |= MMC_CAP_UHS_SDR50;
3375         }
3376
3377         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3378             (host->caps1 & SDHCI_SUPPORT_HS400))
3379                 mmc->caps2 |= MMC_CAP2_HS400;
3380
3381         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3382             (IS_ERR(mmc->supply.vqmmc) ||
3383              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3384                                              1300000)))
3385                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3386
3387         if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3388             !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3389                 mmc->caps |= MMC_CAP_UHS_DDR50;
3390
3391         /* Does the host need tuning for SDR50? */
3392         if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3393                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3394
3395         /* Driver Type(s) (A, C, D) supported by the host */
3396         if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3397                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3398         if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3399                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3400         if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3401                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3402
3403         /* Initial value for re-tuning timer count */
3404         host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3405                              SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3406
3407         /*
3408          * In case Re-tuning Timer is not disabled, the actual value of
3409          * re-tuning timer will be 2 ^ (n - 1).
3410          */
3411         if (host->tuning_count)
3412                 host->tuning_count = 1 << (host->tuning_count - 1);
3413
3414         /* Re-tuning mode supported by the Host Controller */
3415         host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3416                              SDHCI_RETUNING_MODE_SHIFT;
3417
3418         ocr_avail = 0;
3419
3420         /*
3421          * According to SD Host Controller spec v3.00, if the Host System
3422          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3423          * the value is meaningful only if Voltage Support in the Capabilities
3424          * register is set. The actual current value is 4 times the register
3425          * value.
3426          */
3427         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3428         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3429                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3430                 if (curr > 0) {
3431
3432                         /* convert to SDHCI_MAX_CURRENT format */
3433                         curr = curr/1000;  /* convert to mA */
3434                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3435
3436                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3437                         max_current_caps =
3438                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3439                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3440                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3441                 }
3442         }
3443
3444         if (host->caps & SDHCI_CAN_VDD_330) {
3445                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3446
3447                 mmc->max_current_330 = ((max_current_caps &
3448                                    SDHCI_MAX_CURRENT_330_MASK) >>
3449                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3450                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3451         }
3452         if (host->caps & SDHCI_CAN_VDD_300) {
3453                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3454
3455                 mmc->max_current_300 = ((max_current_caps &
3456                                    SDHCI_MAX_CURRENT_300_MASK) >>
3457                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3458                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3459         }
3460         if (host->caps & SDHCI_CAN_VDD_180) {
3461                 ocr_avail |= MMC_VDD_165_195;
3462
3463                 mmc->max_current_180 = ((max_current_caps &
3464                                    SDHCI_MAX_CURRENT_180_MASK) >>
3465                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3466                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3467         }
3468
3469         /* If OCR set by host, use it instead. */
3470         if (host->ocr_mask)
3471                 ocr_avail = host->ocr_mask;
3472
3473         /* If OCR set by external regulators, give it highest prio. */
3474         if (mmc->ocr_avail)
3475                 ocr_avail = mmc->ocr_avail;
3476
3477         mmc->ocr_avail = ocr_avail;
3478         mmc->ocr_avail_sdio = ocr_avail;
3479         if (host->ocr_avail_sdio)
3480                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3481         mmc->ocr_avail_sd = ocr_avail;
3482         if (host->ocr_avail_sd)
3483                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3484         else /* normal SD controllers don't support 1.8V */
3485                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3486         mmc->ocr_avail_mmc = ocr_avail;
3487         if (host->ocr_avail_mmc)
3488                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3489
3490         if (mmc->ocr_avail == 0) {
3491                 pr_err("%s: Hardware doesn't report any support voltages.\n",
3492                        mmc_hostname(mmc));
3493                 ret = -ENODEV;
3494                 goto unreg;
3495         }
3496
3497         if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3498                           MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3499                           MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3500             (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3501                 host->flags |= SDHCI_SIGNALING_180;
3502
3503         if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3504                 host->flags |= SDHCI_SIGNALING_120;
3505
3506         spin_lock_init(&host->lock);
3507
3508         /*
3509          * Maximum number of segments. Depends on if the hardware
3510          * can do scatter/gather or not.
3511          */
3512         if (host->flags & SDHCI_USE_ADMA)
3513                 mmc->max_segs = SDHCI_MAX_SEGS;
3514         else if (host->flags & SDHCI_USE_SDMA)
3515                 mmc->max_segs = 1;
3516         else /* PIO */
3517                 mmc->max_segs = SDHCI_MAX_SEGS;
3518
3519         /*
3520          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3521          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3522          * is less anyway.
3523          */
3524         mmc->max_req_size = 524288;
3525
3526         /*
3527          * Maximum segment size. Could be one segment with the maximum number
3528          * of bytes. When doing hardware scatter/gather, each entry cannot
3529          * be larger than 64 KiB though.
3530          */
3531         if (host->flags & SDHCI_USE_ADMA) {
3532                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3533                         mmc->max_seg_size = 65535;
3534                 else
3535                         mmc->max_seg_size = 65536;
3536         } else {
3537                 mmc->max_seg_size = mmc->max_req_size;
3538         }
3539
3540         /*
3541          * Maximum block size. This varies from controller to controller and
3542          * is specified in the capabilities register.
3543          */
3544         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3545                 mmc->max_blk_size = 2;
3546         } else {
3547                 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3548                                 SDHCI_MAX_BLOCK_SHIFT;
3549                 if (mmc->max_blk_size >= 3) {
3550                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3551                                 mmc_hostname(mmc));
3552                         mmc->max_blk_size = 0;
3553                 }
3554         }
3555
3556         mmc->max_blk_size = 512 << mmc->max_blk_size;
3557
3558         /*
3559          * Maximum block count.
3560          */
3561         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3562
3563         return 0;
3564
3565 unreg:
3566         if (!IS_ERR(mmc->supply.vqmmc))
3567                 regulator_disable(mmc->supply.vqmmc);
3568 undma:
3569         if (host->align_buffer)
3570                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3571                                   host->adma_table_sz, host->align_buffer,
3572                                   host->align_addr);
3573         host->adma_table = NULL;
3574         host->align_buffer = NULL;
3575
3576         return ret;
3577 }
3578 EXPORT_SYMBOL_GPL(sdhci_setup_host);
3579
3580 int __sdhci_add_host(struct sdhci_host *host)
3581 {
3582         struct mmc_host *mmc = host->mmc;
3583         int ret;
3584
3585         /*
3586          * Init tasklets.
3587          */
3588         tasklet_init(&host->finish_tasklet,
3589                 sdhci_tasklet_finish, (unsigned long)host);
3590
3591         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3592         setup_timer(&host->data_timer, sdhci_timeout_data_timer,
3593                     (unsigned long)host);
3594
3595         init_waitqueue_head(&host->buf_ready_int);
3596
3597         sdhci_init(host, 0);
3598
3599         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3600                                    IRQF_SHARED, mmc_hostname(mmc), host);
3601         if (ret) {
3602                 pr_err("%s: Failed to request IRQ %d: %d\n",
3603                        mmc_hostname(mmc), host->irq, ret);
3604                 goto untasklet;
3605         }
3606
3607 #ifdef CONFIG_MMC_DEBUG
3608         sdhci_dumpregs(host);
3609 #endif
3610
3611         ret = sdhci_led_register(host);
3612         if (ret) {
3613                 pr_err("%s: Failed to register LED device: %d\n",
3614                        mmc_hostname(mmc), ret);
3615                 goto unirq;
3616         }
3617
3618         mmiowb();
3619
3620         ret = mmc_add_host(mmc);
3621         if (ret)
3622                 goto unled;
3623
3624         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3625                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3626                 (host->flags & SDHCI_USE_ADMA) ?
3627                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3628                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3629
3630         sdhci_enable_card_detection(host);
3631
3632         return 0;
3633
3634 unled:
3635         sdhci_led_unregister(host);
3636 unirq:
3637         sdhci_do_reset(host, SDHCI_RESET_ALL);
3638         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3639         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3640         free_irq(host->irq, host);
3641 untasklet:
3642         tasklet_kill(&host->finish_tasklet);
3643
3644         if (!IS_ERR(mmc->supply.vqmmc))
3645                 regulator_disable(mmc->supply.vqmmc);
3646
3647         if (host->align_buffer)
3648                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3649                                   host->adma_table_sz, host->align_buffer,
3650                                   host->align_addr);
3651         host->adma_table = NULL;
3652         host->align_buffer = NULL;
3653
3654         return ret;
3655 }
3656 EXPORT_SYMBOL_GPL(__sdhci_add_host);
3657
3658 int sdhci_add_host(struct sdhci_host *host)
3659 {
3660         int ret;
3661
3662         ret = sdhci_setup_host(host);
3663         if (ret)
3664                 return ret;
3665
3666         return __sdhci_add_host(host);
3667 }
3668 EXPORT_SYMBOL_GPL(sdhci_add_host);
3669
3670 void sdhci_remove_host(struct sdhci_host *host, int dead)
3671 {
3672         struct mmc_host *mmc = host->mmc;
3673         unsigned long flags;
3674
3675         if (dead) {
3676                 spin_lock_irqsave(&host->lock, flags);
3677
3678                 host->flags |= SDHCI_DEVICE_DEAD;
3679
3680                 if (sdhci_has_requests(host)) {
3681                         pr_err("%s: Controller removed during "
3682                                 " transfer!\n", mmc_hostname(mmc));
3683                         sdhci_error_out_mrqs(host, -ENOMEDIUM);
3684                 }
3685
3686                 spin_unlock_irqrestore(&host->lock, flags);
3687         }
3688
3689         sdhci_disable_card_detection(host);
3690
3691         mmc_remove_host(mmc);
3692
3693         sdhci_led_unregister(host);
3694
3695         if (!dead)
3696                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3697
3698         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3699         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3700         free_irq(host->irq, host);
3701
3702         del_timer_sync(&host->timer);
3703         del_timer_sync(&host->data_timer);
3704
3705         tasklet_kill(&host->finish_tasklet);
3706
3707         if (!IS_ERR(mmc->supply.vqmmc))
3708                 regulator_disable(mmc->supply.vqmmc);
3709
3710         if (host->align_buffer)
3711                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3712                                   host->adma_table_sz, host->align_buffer,
3713                                   host->align_addr);
3714
3715         host->adma_table = NULL;
3716         host->align_buffer = NULL;
3717 }
3718
3719 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3720
3721 void sdhci_free_host(struct sdhci_host *host)
3722 {
3723         mmc_free_host(host->mmc);
3724 }
3725
3726 EXPORT_SYMBOL_GPL(sdhci_free_host);
3727
3728 /*****************************************************************************\
3729  *                                                                           *
3730  * Driver init/exit                                                          *
3731  *                                                                           *
3732 \*****************************************************************************/
3733
3734 static int __init sdhci_drv_init(void)
3735 {
3736         pr_info(DRIVER_NAME
3737                 ": Secure Digital Host Controller Interface driver\n");
3738         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3739
3740         return 0;
3741 }
3742
3743 static void __exit sdhci_drv_exit(void)
3744 {
3745 }
3746
3747 module_init(sdhci_drv_init);
3748 module_exit(sdhci_drv_exit);
3749
3750 module_param(debug_quirks, uint, 0444);
3751 module_param(debug_quirks2, uint, 0444);
3752
3753 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3754 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3755 MODULE_LICENSE("GPL");
3756
3757 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3758 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");