drivers/mtd/nand/atmel/nand-controller.c

   1 /*
   2  * Copyright 2017 ATMEL
   3  * Copyright 2017 Free Electrons
   4  *
   5  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   6  *
   7  * Derived from the atmel_nand.c driver which contained the following
   8  * copyrights:
   9  *
  10  *   Copyright 2003 Rick Bronson
  11  *
  12  *   Derived from drivers/mtd/nand/autcpu12.c
  13  *      Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
  14  *
  15  *   Derived from drivers/mtd/spia.c
  16  *      Copyright 2000 Steven J. Hill (sjhill@cotw.com)
  17  *
  18  *
  19  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  20  *      Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
  21  *
  22  *   Derived from Das U-Boot source code
  23  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  24  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  25  *
  26  *   Add Programmable Multibit ECC support for various AT91 SoC
  27  *      Copyright 2012 ATMEL, Hong Xu
  28  *
  29  *   Add Nand Flash Controller support for SAMA5 SoC
  30  *      Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
  31  *
  32  * This program is free software; you can redistribute it and/or modify
  33  * it under the terms of the GNU General Public License version 2 as
  34  * published by the Free Software Foundation.
  35  *
  36  * A few words about the naming convention in this file. This convention
  37  * applies to structure and function names.
  38  *
  39  * Prefixes:
  40  *
  41  * - atmel_nand_: all generic structures/functions
  42  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
  43  *                    (at91sam9 and avr32 SoCs)
  44  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
  45  *                     (sama5 SoCs and later)
  46  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
  47  *               that is available in the HSMC block
  48  * - <soc>_nand_: all SoC specific structures/functions
  49  */
  50
  51 #include <linux/clk.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/dmaengine.h>
  54 #include <linux/genalloc.h>
  55 #include <linux/gpio.h>
  56 #include <linux/gpio/consumer.h>
  57 #include <linux/interrupt.h>
  58 #include <linux/mfd/syscon.h>
  59 #include <linux/mfd/syscon/atmel-matrix.h>
  60 #include <linux/mfd/syscon/atmel-smc.h>
  61 #include <linux/module.h>
  62 #include <linux/mtd/rawnand.h>
  63 #include <linux/of_address.h>
  64 #include <linux/of_irq.h>
  65 #include <linux/of_platform.h>
  66 #include <linux/iopoll.h>
  67 #include <linux/platform_device.h>
  68 #include <linux/regmap.h>
  69
  70 #include "pmecc.h"
  71
  72 #define ATMEL_HSMC_NFC_CFG                      0x0
  73 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
  74 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
  75 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
  76 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
  77 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
  78 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
  79 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
  80 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
  81 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
  82 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
  83
  84 #define ATMEL_HSMC_NFC_CTRL                     0x4
  85 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
  86 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
  87
  88 #define ATMEL_HSMC_NFC_SR                       0x8
  89 #define ATMEL_HSMC_NFC_IER                      0xc
  90 #define ATMEL_HSMC_NFC_IDR                      0x10
  91 #define ATMEL_HSMC_NFC_IMR                      0x14
  92 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
  93 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
  94 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
  95 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
  96 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
  97 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
  98 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
  99 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
 100 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
 101 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
 102 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
 103 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
 104 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
 105                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
 106                                                  ATMEL_HSMC_NFC_SR_AWB | \
 107                                                  ATMEL_HSMC_NFC_SR_NFCASE)
 108 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
 109
 110 #define ATMEL_HSMC_NFC_ADDR                     0x18
 111 #define ATMEL_HSMC_NFC_BANK                     0x1c
 112
 113 #define ATMEL_NFC_MAX_RB_ID                     7
 114
 115 #define ATMEL_NFC_SRAM_SIZE                     0x2400
 116
 117 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
 118 #define ATMEL_NFC_VCMD2                         BIT(18)
 119 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
 120 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
 121 #define ATMEL_NFC_DATAEN                        BIT(25)
 122 #define ATMEL_NFC_NFCWR                         BIT(26)
 123
 124 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
 125
 126 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
 127 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
 128
 129 #define DEFAULT_TIMEOUT_MS                      1000
 130 #define MIN_DMA_LEN                             128
 131
 132 static bool atmel_nand_avoid_dma __read_mostly;
 133
 134 MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
 135 module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);
 136
 137 enum atmel_nand_rb_type {
 138         ATMEL_NAND_NO_RB,
 139         ATMEL_NAND_NATIVE_RB,
 140         ATMEL_NAND_GPIO_RB,
 141 };
 142
 143 struct atmel_nand_rb {
 144         enum atmel_nand_rb_type type;
 145         union {
 146                 struct gpio_desc *gpio;
 147                 int id;
 148         };
 149 };
 150
 151 struct atmel_nand_cs {
 152         int id;
 153         struct atmel_nand_rb rb;
 154         struct gpio_desc *csgpio;
 155         struct {
 156                 void __iomem *virt;
 157                 dma_addr_t dma;
 158         } io;
 159
 160         struct atmel_smc_cs_conf smcconf;
 161 };
 162
 163 struct atmel_nand {
 164         struct list_head node;
 165         struct device *dev;
 166         struct nand_chip base;
 167         struct atmel_nand_cs *activecs;
 168         struct atmel_pmecc_user *pmecc;
 169         struct gpio_desc *cdgpio;
 170         int numcs;
 171         struct atmel_nand_cs cs[];
 172 };
 173
 174 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
 175 {
 176         return container_of(chip, struct atmel_nand, base);
 177 }
 178
 179 enum atmel_nfc_data_xfer {
 180         ATMEL_NFC_NO_DATA,
 181         ATMEL_NFC_READ_DATA,
 182         ATMEL_NFC_WRITE_DATA,
 183 };
 184
 185 struct atmel_nfc_op {
 186         u8 cs;
 187         u8 ncmds;
 188         u8 cmds[2];
 189         u8 naddrs;
 190         u8 addrs[5];
 191         enum atmel_nfc_data_xfer data;
 192         u32 wait;
 193         u32 errors;
 194 };
 195
 196 struct atmel_nand_controller;
 197 struct atmel_nand_controller_caps;
 198
 199 struct atmel_nand_controller_ops {
 200         int (*probe)(struct platform_device *pdev,
 201                      const struct atmel_nand_controller_caps *caps);
 202         int (*remove)(struct atmel_nand_controller *nc);
 203         void (*nand_init)(struct atmel_nand_controller *nc,
 204                           struct atmel_nand *nand);
 205         int (*ecc_init)(struct atmel_nand *nand);
 206         int (*setup_data_interface)(struct atmel_nand *nand, int csline,
 207                                     const struct nand_data_interface *conf);
 208 };
 209
 210 struct atmel_nand_controller_caps {
 211         bool has_dma;
 212         bool legacy_of_bindings;
 213         u32 ale_offs;
 214         u32 cle_offs;
 215         const struct atmel_nand_controller_ops *ops;
 216 };
 217
 218 struct atmel_nand_controller {
 219         struct nand_hw_control base;
 220         const struct atmel_nand_controller_caps *caps;
 221         struct device *dev;
 222         struct regmap *smc;
 223         struct dma_chan *dmac;
 224         struct atmel_pmecc *pmecc;
 225         struct list_head chips;
 226         struct clk *mck;
 227 };
 228
 229 static inline struct atmel_nand_controller *
 230 to_nand_controller(struct nand_hw_control *ctl)
 231 {
 232         return container_of(ctl, struct atmel_nand_controller, base);
 233 }
 234
 235 struct atmel_smc_nand_controller {
 236         struct atmel_nand_controller base;
 237         struct regmap *matrix;
 238         unsigned int ebi_csa_offs;
 239 };
 240
 241 static inline struct atmel_smc_nand_controller *
 242 to_smc_nand_controller(struct nand_hw_control *ctl)
 243 {
 244         return container_of(to_nand_controller(ctl),
 245                             struct atmel_smc_nand_controller, base);
 246 }
 247
 248 struct atmel_hsmc_nand_controller {
 249         struct atmel_nand_controller base;
 250         struct {
 251                 struct gen_pool *pool;
 252                 void __iomem *virt;
 253                 dma_addr_t dma;
 254         } sram;
 255         const struct atmel_hsmc_reg_layout *hsmc_layout;
 256         struct regmap *io;
 257         struct atmel_nfc_op op;
 258         struct completion complete;
 259         int irq;
 260
 261         /* Only used when instantiating from legacy DT bindings. */
 262         struct clk *clk;
 263 };
 264
 265 static inline struct atmel_hsmc_nand_controller *
 266 to_hsmc_nand_controller(struct nand_hw_control *ctl)
 267 {
 268         return container_of(to_nand_controller(ctl),
 269                             struct atmel_hsmc_nand_controller, base);
 270 }
 271
 272 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
 273 {
 274         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
 275         op->wait ^= status & op->wait;
 276
 277         return !op->wait || op->errors;
 278 }
 279
 280 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
 281 {
 282         struct atmel_hsmc_nand_controller *nc = data;
 283         u32 sr, rcvd;
 284         bool done;
 285
 286         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
 287
 288         rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 289         done = atmel_nfc_op_done(&nc->op, sr);
 290
 291         if (rcvd)
 292                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
 293
 294         if (done)
 295                 complete(&nc->complete);
 296
 297         return rcvd ? IRQ_HANDLED : IRQ_NONE;
 298 }
 299
 300 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
 301                           unsigned int timeout_ms)
 302 {
 303         int ret;
 304
 305         if (!timeout_ms)
 306                 timeout_ms = DEFAULT_TIMEOUT_MS;
 307
 308         if (poll) {
 309                 u32 status;
 310
 311                 ret = regmap_read_poll_timeout(nc->base.smc,
 312                                                ATMEL_HSMC_NFC_SR, status,
 313                                                atmel_nfc_op_done(&nc->op,
 314                                                                  status),
 315                                                0, timeout_ms * 1000);
 316         } else {
 317                 init_completion(&nc->complete);
 318                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
 319                              nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 320                 ret = wait_for_completion_timeout(&nc->complete,
 321                                                 msecs_to_jiffies(timeout_ms));
 322                 if (!ret)
 323                         ret = -ETIMEDOUT;
 324                 else
 325                         ret = 0;
 326
 327                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
 328         }
 329
 330         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
 331                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
 332                 ret = -ETIMEDOUT;
 333         }
 334
 335         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
 336                 dev_err(nc->base.dev, "Access to an undefined area\n");
 337                 ret = -EIO;
 338         }
 339
 340         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
 341                 dev_err(nc->base.dev, "Access while busy\n");
 342                 ret = -EIO;
 343         }
 344
 345         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
 346                 dev_err(nc->base.dev, "Wrong access size\n");
 347                 ret = -EIO;
 348         }
 349
 350         return ret;
 351 }
 352
 353 static void atmel_nand_dma_transfer_finished(void *data)
 354 {
 355         struct completion *finished = data;
 356
 357         complete(finished);
 358 }
 359
 360 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
 361                                    void *buf, dma_addr_t dev_dma, size_t len,
 362                                    enum dma_data_direction dir)
 363 {
 364         DECLARE_COMPLETION_ONSTACK(finished);
 365         dma_addr_t src_dma, dst_dma, buf_dma;
 366         struct dma_async_tx_descriptor *tx;
 367         dma_cookie_t cookie;
 368
 369         buf_dma = dma_map_single(nc->dev, buf, len, dir);
 370         if (dma_mapping_error(nc->dev, dev_dma)) {
 371                 dev_err(nc->dev,
 372                         "Failed to prepare a buffer for DMA access\n");
 373                 goto err;
 374         }
 375
 376         if (dir == DMA_FROM_DEVICE) {
 377                 src_dma = dev_dma;
 378                 dst_dma = buf_dma;
 379         } else {
 380                 src_dma = buf_dma;
 381                 dst_dma = dev_dma;
 382         }
 383
 384         tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
 385                                        DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
 386         if (!tx) {
 387                 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
 388                 goto err_unmap;
 389         }
 390
 391         tx->callback = atmel_nand_dma_transfer_finished;
 392         tx->callback_param = &finished;
 393
 394         cookie = dmaengine_submit(tx);
 395         if (dma_submit_error(cookie)) {
 396                 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
 397                 goto err_unmap;
 398         }
 399
 400         dma_async_issue_pending(nc->dmac);
 401         wait_for_completion(&finished);
 402
 403         return 0;
 404
 405 err_unmap:
 406         dma_unmap_single(nc->dev, buf_dma, len, dir);
 407
 408 err:
 409         dev_dbg(nc->dev, "Fall back to CPU I/O\n");
 410
 411         return -EIO;
 412 }
 413
 414 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
 415 {
 416         struct nand_chip *chip = mtd_to_nand(mtd);
 417         struct atmel_nand *nand = to_atmel_nand(chip);
 418
 419         return ioread8(nand->activecs->io.virt);
 420 }
 421
 422 static u16 atmel_nand_read_word(struct mtd_info *mtd)
 423 {
 424         struct nand_chip *chip = mtd_to_nand(mtd);
 425         struct atmel_nand *nand = to_atmel_nand(chip);
 426
 427         return ioread16(nand->activecs->io.virt);
 428 }
 429
 430 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
 431 {
 432         struct nand_chip *chip = mtd_to_nand(mtd);
 433         struct atmel_nand *nand = to_atmel_nand(chip);
 434
 435         if (chip->options & NAND_BUSWIDTH_16)
 436                 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
 437         else
 438                 iowrite8(byte, nand->activecs->io.virt);
 439 }
 440
 441 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 442 {
 443         struct nand_chip *chip = mtd_to_nand(mtd);
 444         struct atmel_nand *nand = to_atmel_nand(chip);
 445         struct atmel_nand_controller *nc;
 446
 447         nc = to_nand_controller(chip->controller);
 448
 449         /*
 450          * If the controller supports DMA, the buffer address is DMA-able and
 451          * len is long enough to make DMA transfers profitable, let's trigger
 452          * a DMA transfer. If it fails, fallback to PIO mode.
 453          */
 454         if (nc->dmac && virt_addr_valid(buf) &&
 455             len >= MIN_DMA_LEN &&
 456             !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
 457                                      DMA_FROM_DEVICE))
 458                 return;
 459
 460         if (chip->options & NAND_BUSWIDTH_16)
 461                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
 462         else
 463                 ioread8_rep(nand->activecs->io.virt, buf, len);
 464 }
 465
 466 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 467 {
 468         struct nand_chip *chip = mtd_to_nand(mtd);
 469         struct atmel_nand *nand = to_atmel_nand(chip);
 470         struct atmel_nand_controller *nc;
 471
 472         nc = to_nand_controller(chip->controller);
 473
 474         /*
 475          * If the controller supports DMA, the buffer address is DMA-able and
 476          * len is long enough to make DMA transfers profitable, let's trigger
 477          * a DMA transfer. If it fails, fallback to PIO mode.
 478          */
 479         if (nc->dmac && virt_addr_valid(buf) &&
 480             len >= MIN_DMA_LEN &&
 481             !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
 482                                      len, DMA_TO_DEVICE))
 483                 return;
 484
 485         if (chip->options & NAND_BUSWIDTH_16)
 486                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
 487         else
 488                 iowrite8_rep(nand->activecs->io.virt, buf, len);
 489 }
 490
 491 static int atmel_nand_dev_ready(struct mtd_info *mtd)
 492 {
 493         struct nand_chip *chip = mtd_to_nand(mtd);
 494         struct atmel_nand *nand = to_atmel_nand(chip);
 495
 496         return gpiod_get_value(nand->activecs->rb.gpio);
 497 }
 498
 499 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
 500 {
 501         struct nand_chip *chip = mtd_to_nand(mtd);
 502         struct atmel_nand *nand = to_atmel_nand(chip);
 503
 504         if (cs < 0 || cs >= nand->numcs) {
 505                 nand->activecs = NULL;
 506                 chip->dev_ready = NULL;
 507                 return;
 508         }
 509
 510         nand->activecs = &nand->cs[cs];
 511
 512         if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
 513                 chip->dev_ready = atmel_nand_dev_ready;
 514 }
 515
 516 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
 517 {
 518         struct nand_chip *chip = mtd_to_nand(mtd);
 519         struct atmel_nand *nand = to_atmel_nand(chip);
 520         struct atmel_hsmc_nand_controller *nc;
 521         u32 status;
 522
 523         nc = to_hsmc_nand_controller(chip->controller);
 524
 525         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
 526
 527         return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
 528 }
 529
 530 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
 531 {
 532         struct nand_chip *chip = mtd_to_nand(mtd);
 533         struct atmel_nand *nand = to_atmel_nand(chip);
 534         struct atmel_hsmc_nand_controller *nc;
 535
 536         nc = to_hsmc_nand_controller(chip->controller);
 537
 538         atmel_nand_select_chip(mtd, cs);
 539
 540         if (!nand->activecs) {
 541                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 542                              ATMEL_HSMC_NFC_CTRL_DIS);
 543                 return;
 544         }
 545
 546         if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
 547                 chip->dev_ready = atmel_hsmc_nand_dev_ready;
 548
 549         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
 550                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
 551                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
 552                            ATMEL_HSMC_NFC_CFG_RSPARE |
 553                            ATMEL_HSMC_NFC_CFG_WSPARE,
 554                            ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
 555                            ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
 556                            ATMEL_HSMC_NFC_CFG_RSPARE);
 557         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 558                      ATMEL_HSMC_NFC_CTRL_EN);
 559 }
 560
 561 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
 562 {
 563         u8 *addrs = nc->op.addrs;
 564         unsigned int op = 0;
 565         u32 addr, val;
 566         int i, ret;
 567
 568         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
 569
 570         for (i = 0; i < nc->op.ncmds; i++)
 571                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
 572
 573         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 574                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
 575
 576         op |= ATMEL_NFC_CSID(nc->op.cs) |
 577               ATMEL_NFC_ACYCLE(nc->op.naddrs);
 578
 579         if (nc->op.ncmds > 1)
 580                 op |= ATMEL_NFC_VCMD2;
 581
 582         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
 583                (addrs[3] << 24);
 584
 585         if (nc->op.data != ATMEL_NFC_NO_DATA) {
 586                 op |= ATMEL_NFC_DATAEN;
 587                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
 588
 589                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
 590                         op |= ATMEL_NFC_NFCWR;
 591         }
 592
 593         /* Clear all flags. */
 594         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
 595
 596         /* Send the command. */
 597         regmap_write(nc->io, op, addr);
 598
 599         ret = atmel_nfc_wait(nc, poll, 0);
 600         if (ret)
 601                 dev_err(nc->base.dev,
 602                         "Failed to send NAND command (err = %d)!",
 603                         ret);
 604
 605         /* Reset the op state. */
 606         memset(&nc->op, 0, sizeof(nc->op));
 607
 608         return ret;
 609 }
 610
 611 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
 612                                      unsigned int ctrl)
 613 {
 614         struct nand_chip *chip = mtd_to_nand(mtd);
 615         struct atmel_nand *nand = to_atmel_nand(chip);
 616         struct atmel_hsmc_nand_controller *nc;
 617
 618         nc = to_hsmc_nand_controller(chip->controller);
 619
 620         if (ctrl & NAND_ALE) {
 621                 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 622                         return;
 623
 624                 nc->op.addrs[nc->op.naddrs++] = dat;
 625         } else if (ctrl & NAND_CLE) {
 626                 if (nc->op.ncmds > 1)
 627                         return;
 628
 629                 nc->op.cmds[nc->op.ncmds++] = dat;
 630         }
 631
 632         if (dat == NAND_CMD_NONE) {
 633                 nc->op.cs = nand->activecs->id;
 634                 atmel_nfc_exec_op(nc, true);
 635         }
 636 }
 637
 638 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 639                                 unsigned int ctrl)
 640 {
 641         struct nand_chip *chip = mtd_to_nand(mtd);
 642         struct atmel_nand *nand = to_atmel_nand(chip);
 643         struct atmel_nand_controller *nc;
 644
 645         nc = to_nand_controller(chip->controller);
 646
 647         if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
 648                 if (ctrl & NAND_NCE)
 649                         gpiod_set_value(nand->activecs->csgpio, 0);
 650                 else
 651                         gpiod_set_value(nand->activecs->csgpio, 1);
 652         }
 653
 654         if (ctrl & NAND_ALE)
 655                 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
 656         else if (ctrl & NAND_CLE)
 657                 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
 658 }
 659
 660 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
 661                                    bool oob_required)
 662 {
 663         struct mtd_info *mtd = nand_to_mtd(chip);
 664         struct atmel_hsmc_nand_controller *nc;
 665         int ret = -EIO;
 666
 667         nc = to_hsmc_nand_controller(chip->controller);
 668
 669         if (nc->base.dmac)
 670                 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
 671                                               nc->sram.dma, mtd->writesize,
 672                                               DMA_TO_DEVICE);
 673
 674         /* Falling back to CPU copy. */
 675         if (ret)
 676                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
 677
 678         if (oob_required)
 679                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
 680                             mtd->oobsize);
 681 }
 682
 683 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
 684                                      bool oob_required)
 685 {
 686         struct mtd_info *mtd = nand_to_mtd(chip);
 687         struct atmel_hsmc_nand_controller *nc;
 688         int ret = -EIO;
 689
 690         nc = to_hsmc_nand_controller(chip->controller);
 691
 692         if (nc->base.dmac)
 693                 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
 694                                               mtd->writesize, DMA_FROM_DEVICE);
 695
 696         /* Falling back to CPU copy. */
 697         if (ret)
 698                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
 699
 700         if (oob_required)
 701                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
 702                               mtd->oobsize);
 703 }
 704
 705 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
 706 {
 707         struct mtd_info *mtd = nand_to_mtd(chip);
 708         struct atmel_hsmc_nand_controller *nc;
 709
 710         nc = to_hsmc_nand_controller(chip->controller);
 711
 712         if (column >= 0) {
 713                 nc->op.addrs[nc->op.naddrs++] = column;
 714
 715                 /*
 716                  * 2 address cycles for the column offset on large page NANDs.
 717                  */
 718                 if (mtd->writesize > 512)
 719                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
 720         }
 721
 722         if (page >= 0) {
 723                 nc->op.addrs[nc->op.naddrs++] = page;
 724                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
 725
 726                 if ((mtd->writesize > 512 && chip->chipsize > SZ_128M) ||
 727                     (mtd->writesize <= 512 && chip->chipsize > SZ_32M))
 728                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
 729         }
 730 }
 731
 732 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
 733 {
 734         struct atmel_nand *nand = to_atmel_nand(chip);
 735         struct atmel_nand_controller *nc;
 736         int ret;
 737
 738         nc = to_nand_controller(chip->controller);
 739
 740         if (raw)
 741                 return 0;
 742
 743         ret = atmel_pmecc_enable(nand->pmecc, op);
 744         if (ret)
 745                 dev_err(nc->dev,
 746                         "Failed to enable ECC engine (err = %d)\n", ret);
 747
 748         return ret;
 749 }
 750
 751 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
 752 {
 753         struct atmel_nand *nand = to_atmel_nand(chip);
 754
 755         if (!raw)
 756                 atmel_pmecc_disable(nand->pmecc);
 757 }
 758
 759 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
 760 {
 761         struct atmel_nand *nand = to_atmel_nand(chip);
 762         struct mtd_info *mtd = nand_to_mtd(chip);
 763         struct atmel_nand_controller *nc;
 764         struct mtd_oob_region oobregion;
 765         void *eccbuf;
 766         int ret, i;
 767
 768         nc = to_nand_controller(chip->controller);
 769
 770         if (raw)
 771                 return 0;
 772
 773         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 774         if (ret) {
 775                 dev_err(nc->dev,
 776                         "Failed to transfer NAND page data (err = %d)\n",
 777                         ret);
 778                 return ret;
 779         }
 780
 781         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 782         eccbuf = chip->oob_poi + oobregion.offset;
 783
 784         for (i = 0; i < chip->ecc.steps; i++) {
 785                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
 786                                                    eccbuf);
 787                 eccbuf += chip->ecc.bytes;
 788         }
 789
 790         return 0;
 791 }
 792
 793 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
 794                                          bool raw)
 795 {
 796         struct atmel_nand *nand = to_atmel_nand(chip);
 797         struct mtd_info *mtd = nand_to_mtd(chip);
 798         struct atmel_nand_controller *nc;
 799         struct mtd_oob_region oobregion;
 800         int ret, i, max_bitflips = 0;
 801         void *databuf, *eccbuf;
 802
 803         nc = to_nand_controller(chip->controller);
 804
 805         if (raw)
 806                 return 0;
 807
 808         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 809         if (ret) {
 810                 dev_err(nc->dev,
 811                         "Failed to read NAND page data (err = %d)\n",
 812                         ret);
 813                 return ret;
 814         }
 815
 816         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 817         eccbuf = chip->oob_poi + oobregion.offset;
 818         databuf = buf;
 819
 820         for (i = 0; i < chip->ecc.steps; i++) {
 821                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
 822                                                  eccbuf);
 823                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
 824                         ret = nand_check_erased_ecc_chunk(databuf,
 825                                                           chip->ecc.size,
 826                                                           eccbuf,
 827                                                           chip->ecc.bytes,
 828                                                           NULL, 0,
 829                                                           chip->ecc.strength);
 830
 831                 if (ret >= 0)
 832                         max_bitflips = max(ret, max_bitflips);
 833                 else
 834                         mtd->ecc_stats.failed++;
 835
 836                 databuf += chip->ecc.size;
 837                 eccbuf += chip->ecc.bytes;
 838         }
 839
 840         return max_bitflips;
 841 }
 842
 843 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
 844                                      bool oob_required, int page, bool raw)
 845 {
 846         struct mtd_info *mtd = nand_to_mtd(chip);
 847         struct atmel_nand *nand = to_atmel_nand(chip);
 848         int ret;
 849
 850         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 851         if (ret)
 852                 return ret;
 853
 854         atmel_nand_write_buf(mtd, buf, mtd->writesize);
 855
 856         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 857         if (ret) {
 858                 atmel_pmecc_disable(nand->pmecc);
 859                 return ret;
 860         }
 861
 862         atmel_nand_pmecc_disable(chip, raw);
 863
 864         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 865
 866         return 0;
 867 }
 868
 869 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 870                                        struct nand_chip *chip, const u8 *buf,
 871                                        int oob_required, int page)
 872 {
 873         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
 874 }
 875
 876 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
 877                                            struct nand_chip *chip,
 878                                            const u8 *buf, int oob_required,
 879                                            int page)
 880 {
 881         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
 882 }
 883
 884 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 885                                     bool oob_required, int page, bool raw)
 886 {
 887         struct mtd_info *mtd = nand_to_mtd(chip);
 888         int ret;
 889
 890         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 891         if (ret)
 892                 return ret;
 893
 894         atmel_nand_read_buf(mtd, buf, mtd->writesize);
 895         atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 896
 897         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 898
 899         atmel_nand_pmecc_disable(chip, raw);
 900
 901         return ret;
 902 }
 903
 904 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 905                                       struct nand_chip *chip, u8 *buf,
 906                                       int oob_required, int page)
 907 {
 908         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
 909 }
 910
 911 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
 912                                           struct nand_chip *chip, u8 *buf,
 913                                           int oob_required, int page)
 914 {
 915         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
 916 }
 917
 918 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
 919                                           const u8 *buf, bool oob_required,
 920                                           int page, bool raw)
 921 {
 922         struct mtd_info *mtd = nand_to_mtd(chip);
 923         struct atmel_nand *nand = to_atmel_nand(chip);
 924         struct atmel_hsmc_nand_controller *nc;
 925         int ret, status;
 926
 927         nc = to_hsmc_nand_controller(chip->controller);
 928
 929         atmel_nfc_copy_to_sram(chip, buf, false);
 930
 931         nc->op.cmds[0] = NAND_CMD_SEQIN;
 932         nc->op.ncmds = 1;
 933         atmel_nfc_set_op_addr(chip, page, 0x0);
 934         nc->op.cs = nand->activecs->id;
 935         nc->op.data = ATMEL_NFC_WRITE_DATA;
 936
 937         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 938         if (ret)
 939                 return ret;
 940
 941         ret = atmel_nfc_exec_op(nc, false);
 942         if (ret) {
 943                 atmel_nand_pmecc_disable(chip, raw);
 944                 dev_err(nc->base.dev,
 945                         "Failed to transfer NAND page data (err = %d)\n",
 946                         ret);
 947                 return ret;
 948         }
 949
 950         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 951
 952         atmel_nand_pmecc_disable(chip, raw);
 953
 954         if (ret)
 955                 return ret;
 956
 957         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 958
 959         nc->op.cmds[0] = NAND_CMD_PAGEPROG;
 960         nc->op.ncmds = 1;
 961         nc->op.cs = nand->activecs->id;
 962         ret = atmel_nfc_exec_op(nc, false);
 963         if (ret)
 964                 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
 965                         ret);
 966
 967         status = chip->waitfunc(mtd, chip);
 968         if (status & NAND_STATUS_FAIL)
 969                 return -EIO;
 970
 971         return ret;
 972 }
 973
 974 static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
 975                                             struct nand_chip *chip,
 976                                             const u8 *buf, int oob_required,
 977                                             int page)
 978 {
 979         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 980                                               false);
 981 }
 982
 983 static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
 984                                                 struct nand_chip *chip,
 985                                                 const u8 *buf,
 986                                                 int oob_required, int page)
 987 {
 988         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 989                                               true);
 990 }
 991
 992 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 993                                          bool oob_required, int page,
 994                                          bool raw)
 995 {
 996         struct mtd_info *mtd = nand_to_mtd(chip);
 997         struct atmel_nand *nand = to_atmel_nand(chip);
 998         struct atmel_hsmc_nand_controller *nc;
 999         int ret;
1000
1001         nc = to_hsmc_nand_controller(chip->controller);
1002
1003         /*
1004          * Optimized read page accessors only work when the NAND R/B pin is
1005          * connected to a native SoC R/B pin. If that's not the case, fallback
1006          * to the non-optimized one.
1007          */
1008         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
1009                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1010
1011                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1012                                                 raw);
1013         }
1014
1015         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1016
1017         if (mtd->writesize > 512)
1018                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1019
1020         atmel_nfc_set_op_addr(chip, page, 0x0);
1021         nc->op.cs = nand->activecs->id;
1022         nc->op.data = ATMEL_NFC_READ_DATA;
1023
1024         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1025         if (ret)
1026                 return ret;
1027
1028         ret = atmel_nfc_exec_op(nc, false);
1029         if (ret) {
1030                 atmel_nand_pmecc_disable(chip, raw);
1031                 dev_err(nc->base.dev,
1032                         "Failed to load NAND page data (err = %d)\n",
1033                         ret);
1034                 return ret;
1035         }
1036
1037         atmel_nfc_copy_from_sram(chip, buf, true);
1038
1039         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1040
1041         atmel_nand_pmecc_disable(chip, raw);
1042
1043         return ret;
1044 }
1045
1046 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
1047                                            struct nand_chip *chip, u8 *buf,
1048                                            int oob_required, int page)
1049 {
1050         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1051                                              false);
1052 }
1053
1054 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
1055                                                struct nand_chip *chip,
1056                                                u8 *buf, int oob_required,
1057                                                int page)
1058 {
1059         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1060                                              true);
1061 }
1062
1063 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1064 {
1065         struct mtd_info *mtd = nand_to_mtd(chip);
1066         struct atmel_nand *nand = to_atmel_nand(chip);
1067         struct atmel_nand_controller *nc;
1068         struct atmel_pmecc_user_req req;
1069
1070         nc = to_nand_controller(chip->controller);
1071
1072         if (!nc->pmecc) {
1073                 dev_err(nc->dev, "HW ECC not supported\n");
1074                 return -ENOTSUPP;
1075         }
1076
1077         if (nc->caps->legacy_of_bindings) {
1078                 u32 val;
1079
1080                 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1081                                           &val))
1082                         chip->ecc.strength = val;
1083
1084                 if (!of_property_read_u32(nc->dev->of_node,
1085                                           "atmel,pmecc-sector-size",
1086                                           &val))
1087                         chip->ecc.size = val;
1088         }
1089
1090         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1091                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1092         else if (chip->ecc.strength)
1093                 req.ecc.strength = chip->ecc.strength;
1094         else if (chip->ecc_strength_ds)
1095                 req.ecc.strength = chip->ecc_strength_ds;
1096         else
1097                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1098
1099         if (chip->ecc.size)
1100                 req.ecc.sectorsize = chip->ecc.size;
1101         else if (chip->ecc_step_ds)
1102                 req.ecc.sectorsize = chip->ecc_step_ds;
1103         else
1104                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1105
1106         req.pagesize = mtd->writesize;
1107         req.oobsize = mtd->oobsize;
1108
1109         if (mtd->writesize <= 512) {
1110                 req.ecc.bytes = 4;
1111                 req.ecc.ooboffset = 0;
1112         } else {
1113                 req.ecc.bytes = mtd->oobsize - 2;
1114                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1115         }
1116
1117         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1118         if (IS_ERR(nand->pmecc))
1119                 return PTR_ERR(nand->pmecc);
1120
1121         chip->ecc.algo = NAND_ECC_BCH;
1122         chip->ecc.size = req.ecc.sectorsize;
1123         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1124         chip->ecc.strength = req.ecc.strength;
1125
1126         chip->options |= NAND_NO_SUBPAGE_WRITE;
1127
1128         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1129
1130         return 0;
1131 }
1132
1133 static int atmel_nand_ecc_init(struct atmel_nand *nand)
1134 {
1135         struct nand_chip *chip = &nand->base;
1136         struct atmel_nand_controller *nc;
1137         int ret;
1138
1139         nc = to_nand_controller(chip->controller);
1140
1141         switch (chip->ecc.mode) {
1142         case NAND_ECC_NONE:
1143         case NAND_ECC_SOFT:
1144                 /*
1145                  * Nothing to do, the core will initialize everything for us.
1146                  */
1147                 break;
1148
1149         case NAND_ECC_HW:
1150                 ret = atmel_nand_pmecc_init(chip);
1151                 if (ret)
1152                         return ret;
1153
1154                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1155                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1156                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1157                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1158                 break;
1159
1160         default:
1161                 /* Other modes are not supported. */
1162                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1163                         chip->ecc.mode);
1164                 return -ENOTSUPP;
1165         }
1166
1167         return 0;
1168 }
1169
1170 static int atmel_hsmc_nand_ecc_init(struct atmel_nand *nand)
1171 {
1172         struct nand_chip *chip = &nand->base;
1173         int ret;
1174
1175         ret = atmel_nand_ecc_init(nand);
1176         if (ret)
1177                 return ret;
1178
1179         if (chip->ecc.mode != NAND_ECC_HW)
1180                 return 0;
1181
1182         /* Adjust the ECC operations for the HSMC IP. */
1183         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1184         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1185         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1186         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1187         chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1188
1189         return 0;
1190 }
1191
1192 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1193                                         const struct nand_data_interface *conf,
1194                                         struct atmel_smc_cs_conf *smcconf)
1195 {
1196         u32 ncycles, totalcycles, timeps, mckperiodps;
1197         struct atmel_nand_controller *nc;
1198         int ret;
1199
1200         nc = to_nand_controller(nand->base.controller);
1201
1202         /* DDR interface not supported. */
1203         if (conf->type != NAND_SDR_IFACE)
1204                 return -ENOTSUPP;
1205
1206         /*
1207          * tRC < 30ns implies EDO mode. This controller does not support this
1208          * mode.
1209          */
1210         if (conf->timings.sdr.tRC_min < 30000)
1211                 return -ENOTSUPP;
1212
1213         atmel_smc_cs_conf_init(smcconf);
1214
1215         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1216         mckperiodps *= 1000;
1217
1218         /*
1219          * Set write pulse timing. This one is easy to extract:
1220          *
1221          * NWE_PULSE = tWP
1222          */
1223         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1224         totalcycles = ncycles;
1225         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1226                                           ncycles);
1227         if (ret)
1228                 return ret;
1229
1230         /*
1231          * The write setup timing depends on the operation done on the NAND.
1232          * All operations goes through the same data bus, but the operation
1233          * type depends on the address we are writing to (ALE/CLE address
1234          * lines).
1235          * Since we have no way to differentiate the different operations at
1236          * the SMC level, we must consider the worst case (the biggest setup
1237          * time among all operation types):
1238          *
1239          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1240          */
1241         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1242                       conf->timings.sdr.tALS_min);
1243         timeps = max(timeps, conf->timings.sdr.tDS_min);
1244         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1245         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1246         totalcycles += ncycles;
1247         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1248                                           ncycles);
1249         if (ret)
1250                 return ret;
1251
1252         /*
1253          * As for the write setup timing, the write hold timing depends on the
1254          * operation done on the NAND:
1255          *
1256          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1257          */
1258         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1259                       conf->timings.sdr.tALH_min);
1260         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1261                       conf->timings.sdr.tWH_min);
1262         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1263         totalcycles += ncycles;
1264
1265         /*
1266          * The write cycle timing is directly matching tWC, but is also
1267          * dependent on the other timings on the setup and hold timings we
1268          * calculated earlier, which gives:
1269          *
1270          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1271          */
1272         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1273         ncycles = max(totalcycles, ncycles);
1274         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1275                                           ncycles);
1276         if (ret)
1277                 return ret;
1278
1279         /*
1280          * We don't want the CS line to be toggled between each byte/word
1281          * transfer to the NAND. The only way to guarantee that is to have the
1282          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1283          *
1284          * NCS_WR_PULSE = NWE_CYCLE
1285          */
1286         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1287                                           ncycles);
1288         if (ret)
1289                 return ret;
1290
1291         /*
1292          * As for the write setup timing, the read hold timing depends on the
1293          * operation done on the NAND:
1294          *
1295          * NRD_HOLD = max(tREH, tRHOH)
1296          */
1297         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1298         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1299         totalcycles = ncycles;
1300
1301         /*
1302          * TDF = tRHZ - NRD_HOLD
1303          */
1304         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1305         ncycles -= totalcycles;
1306
1307         /*
1308          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1309          * we might end up with a config that does not fit in the TDF field.
1310          * Just take the max value in this case and hope that the NAND is more
1311          * tolerant than advertised.
1312          */
1313         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1314                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1315         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1316                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1317
1318         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1319                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1320
1321         /*
1322          * Read pulse timing directly matches tRP:
1323          *
1324          * NRD_PULSE = tRP
1325          */
1326         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1327         totalcycles += ncycles;
1328         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1329                                           ncycles);
1330         if (ret)
1331                 return ret;
1332
1333         /*
1334          * The write cycle timing is directly matching tWC, but is also
1335          * dependent on the setup and hold timings we calculated earlier,
1336          * which gives:
1337          *
1338          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1339          *
1340          * NRD_SETUP is always 0.
1341          */
1342         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1343         ncycles = max(totalcycles, ncycles);
1344         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1345                                           ncycles);
1346         if (ret)
1347                 return ret;
1348
1349         /*
1350          * We don't want the CS line to be toggled between each byte/word
1351          * transfer from the NAND. The only way to guarantee that is to have
1352          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1353          *
1354          * NCS_RD_PULSE = NRD_CYCLE
1355          */
1356         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1357                                           ncycles);
1358         if (ret)
1359                 return ret;
1360
1361         /* Txxx timings are directly matching tXXX ones. */
1362         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1363         ret = atmel_smc_cs_conf_set_timing(smcconf,
1364                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1365                                            ncycles);
1366         if (ret)
1367                 return ret;
1368
1369         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1370         ret = atmel_smc_cs_conf_set_timing(smcconf,
1371                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1372                                            ncycles);
1373         /*
1374          * Version 4 of the ONFI spec mandates that tADL be at least 400
1375          * nanoseconds, but, depending on the master clock rate, 400 ns may not
1376          * fit in the tADL field of the SMC reg. We need to relax the check and
1377          * accept the -ERANGE return code.
1378          *
1379          * Note that previous versions of the ONFI spec had a lower tADL_min
1380          * (100 or 200 ns). It's not clear why this timing constraint got
1381          * increased but it seems most NANDs are fine with values lower than
1382          * 400ns, so we should be safe.
1383          */
1384         if (ret && ret != -ERANGE)
1385                 return ret;
1386
1387         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1388         ret = atmel_smc_cs_conf_set_timing(smcconf,
1389                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1390                                            ncycles);
1391         if (ret)
1392                 return ret;
1393
1394         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1395         ret = atmel_smc_cs_conf_set_timing(smcconf,
1396                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1397                                            ncycles);
1398         if (ret)
1399                 return ret;
1400
1401         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1402         ret = atmel_smc_cs_conf_set_timing(smcconf,
1403                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1404                                            ncycles);
1405         if (ret)
1406                 return ret;
1407
1408         /* Attach the CS line to the NFC logic. */
1409         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1410
1411         /* Set the appropriate data bus width. */
1412         if (nand->base.options & NAND_BUSWIDTH_16)
1413                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1414
1415         /* Operate in NRD/NWE READ/WRITEMODE. */
1416         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1417                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1418
1419         return 0;
1420 }
1421
1422 static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1423                                         int csline,
1424                                         const struct nand_data_interface *conf)
1425 {
1426         struct atmel_nand_controller *nc;
1427         struct atmel_smc_cs_conf smcconf;
1428         struct atmel_nand_cs *cs;
1429         int ret;
1430
1431         nc = to_nand_controller(nand->base.controller);
1432
1433         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1434         if (ret)
1435                 return ret;
1436
1437         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1438                 return 0;
1439
1440         cs = &nand->cs[csline];
1441         cs->smcconf = smcconf;
1442         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1443
1444         return 0;
1445 }
1446
1447 static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1448                                         int csline,
1449                                         const struct nand_data_interface *conf)
1450 {
1451         struct atmel_hsmc_nand_controller *nc;
1452         struct atmel_smc_cs_conf smcconf;
1453         struct atmel_nand_cs *cs;
1454         int ret;
1455
1456         nc = to_hsmc_nand_controller(nand->base.controller);
1457
1458         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1459         if (ret)
1460                 return ret;
1461
1462         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1463                 return 0;
1464
1465         cs = &nand->cs[csline];
1466         cs->smcconf = smcconf;
1467
1468         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1469                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1470
1471         atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1472                                  &cs->smcconf);
1473
1474         return 0;
1475 }
1476
1477 static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1478                                         const struct nand_data_interface *conf)
1479 {
1480         struct nand_chip *chip = mtd_to_nand(mtd);
1481         struct atmel_nand *nand = to_atmel_nand(chip);
1482         struct atmel_nand_controller *nc;
1483
1484         nc = to_nand_controller(nand->base.controller);
1485
1486         if (csline >= nand->numcs ||
1487             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1488                 return -EINVAL;
1489
1490         return nc->caps->ops->setup_data_interface(nand, csline, conf);
1491 }
1492
1493 static void atmel_nand_init(struct atmel_nand_controller *nc,
1494                             struct atmel_nand *nand)
1495 {
1496         struct nand_chip *chip = &nand->base;
1497         struct mtd_info *mtd = nand_to_mtd(chip);
1498
1499         mtd->dev.parent = nc->dev;
1500         nand->base.controller = &nc->base;
1501
1502         chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1503         chip->read_byte = atmel_nand_read_byte;
1504         chip->read_word = atmel_nand_read_word;
1505         chip->write_byte = atmel_nand_write_byte;
1506         chip->read_buf = atmel_nand_read_buf;
1507         chip->write_buf = atmel_nand_write_buf;
1508         chip->select_chip = atmel_nand_select_chip;
1509
1510         if (nc->mck && nc->caps->ops->setup_data_interface)
1511                 chip->setup_data_interface = atmel_nand_setup_data_interface;
1512
1513         /* Some NANDs require a longer delay than the default one (20us). */
1514         chip->chip_delay = 40;
1515
1516         /*
1517          * Use a bounce buffer when the buffer passed by the MTD user is not
1518          * suitable for DMA.
1519          */
1520         if (nc->dmac)
1521                 chip->options |= NAND_USE_BOUNCE_BUFFER;
1522
1523         /* Default to HW ECC if pmecc is available. */
1524         if (nc->pmecc)
1525                 chip->ecc.mode = NAND_ECC_HW;
1526 }
1527
1528 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1529                                 struct atmel_nand *nand)
1530 {
1531         struct nand_chip *chip = &nand->base;
1532         struct atmel_smc_nand_controller *smc_nc;
1533         int i;
1534
1535         atmel_nand_init(nc, nand);
1536
1537         smc_nc = to_smc_nand_controller(chip->controller);
1538         if (!smc_nc->matrix)
1539                 return;
1540
1541         /* Attach the CS to the NAND Flash logic. */
1542         for (i = 0; i < nand->numcs; i++)
1543                 regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1544                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1545 }
1546
1547 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1548                                  struct atmel_nand *nand)
1549 {
1550         struct nand_chip *chip = &nand->base;
1551
1552         atmel_nand_init(nc, nand);
1553
1554         /* Overload some methods for the HSMC controller. */
1555         chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1556         chip->select_chip = atmel_hsmc_nand_select_chip;
1557 }
1558
1559 static int atmel_nand_detect(struct atmel_nand *nand)
1560 {
1561         struct nand_chip *chip = &nand->base;
1562         struct mtd_info *mtd = nand_to_mtd(chip);
1563         struct atmel_nand_controller *nc;
1564         int ret;
1565
1566         nc = to_nand_controller(chip->controller);
1567
1568         ret = nand_scan_ident(mtd, nand->numcs, NULL);
1569         if (ret)
1570                 dev_err(nc->dev, "nand_scan_ident() failed: %d\n", ret);
1571
1572         return ret;
1573 }
1574
1575 static int atmel_nand_unregister(struct atmel_nand *nand)
1576 {
1577         struct nand_chip *chip = &nand->base;
1578         struct mtd_info *mtd = nand_to_mtd(chip);
1579         int ret;
1580
1581         ret = mtd_device_unregister(mtd);
1582         if (ret)
1583                 return ret;
1584
1585         nand_cleanup(chip);
1586         list_del(&nand->node);
1587
1588         return 0;
1589 }
1590
1591 static int atmel_nand_register(struct atmel_nand *nand)
1592 {
1593         struct nand_chip *chip = &nand->base;
1594         struct mtd_info *mtd = nand_to_mtd(chip);
1595         struct atmel_nand_controller *nc;
1596         int ret;
1597
1598         nc = to_nand_controller(chip->controller);
1599
1600         if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1601                 /*
1602                  * We keep the MTD name unchanged to avoid breaking platforms
1603                  * where the MTD cmdline parser is used and the bootloader
1604                  * has not been updated to use the new naming scheme.
1605                  */
1606                 mtd->name = "atmel_nand";
1607         } else if (!mtd->name) {
1608                 /*
1609                  * If the new bindings are used and the bootloader has not been
1610                  * updated to pass a new mtdparts parameter on the cmdline, you
1611                  * should define the following property in your nand node:
1612                  *
1613                  *      label = "atmel_nand";
1614                  *
1615                  * This way, mtd->name will be set by the core when
1616                  * nand_set_flash_node() is called.
1617                  */
1618                 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1619                                            "%s:nand.%d", dev_name(nc->dev),
1620                                            nand->cs[0].id);
1621                 if (!mtd->name) {
1622                         dev_err(nc->dev, "Failed to allocate mtd->name\n");
1623                         return -ENOMEM;
1624                 }
1625         }
1626
1627         ret = nand_scan_tail(mtd);
1628         if (ret) {
1629                 dev_err(nc->dev, "nand_scan_tail() failed: %d\n", ret);
1630                 return ret;
1631         }
1632
1633         ret = mtd_device_register(mtd, NULL, 0);
1634         if (ret) {
1635                 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1636                 nand_cleanup(chip);
1637                 return ret;
1638         }
1639
1640         list_add_tail(&nand->node, &nc->chips);
1641
1642         return 0;
1643 }
1644
1645 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1646                                             struct device_node *np,
1647                                             int reg_cells)
1648 {
1649         struct atmel_nand *nand;
1650         struct gpio_desc *gpio;
1651         int numcs, ret, i;
1652
1653         numcs = of_property_count_elems_of_size(np, "reg",
1654                                                 reg_cells * sizeof(u32));
1655         if (numcs < 1) {
1656                 dev_err(nc->dev, "Missing or invalid reg property\n");
1657                 return ERR_PTR(-EINVAL);
1658         }
1659
1660         nand = devm_kzalloc(nc->dev,
1661                             sizeof(*nand) + (numcs * sizeof(*nand->cs)),
1662                             GFP_KERNEL);
1663         if (!nand) {
1664                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1665                 return ERR_PTR(-ENOMEM);
1666         }
1667
1668         nand->numcs = numcs;
1669
1670         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1671                                                       &np->fwnode, GPIOD_IN,
1672                                                       "nand-det");
1673         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1674                 dev_err(nc->dev,
1675                         "Failed to get detect gpio (err = %ld)\n",
1676                         PTR_ERR(gpio));
1677                 return ERR_CAST(gpio);
1678         }
1679
1680         if (!IS_ERR(gpio))
1681                 nand->cdgpio = gpio;
1682
1683         for (i = 0; i < numcs; i++) {
1684                 struct resource res;
1685                 u32 val;
1686
1687                 ret = of_address_to_resource(np, 0, &res);
1688                 if (ret) {
1689                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1690                                 ret);
1691                         return ERR_PTR(ret);
1692                 }
1693
1694                 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1695                                                  &val);
1696                 if (ret) {
1697                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1698                                 ret);
1699                         return ERR_PTR(ret);
1700                 }
1701
1702                 nand->cs[i].id = val;
1703
1704                 nand->cs[i].io.dma = res.start;
1705                 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1706                 if (IS_ERR(nand->cs[i].io.virt))
1707                         return ERR_CAST(nand->cs[i].io.virt);
1708
1709                 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1710                         if (val > ATMEL_NFC_MAX_RB_ID)
1711                                 return ERR_PTR(-EINVAL);
1712
1713                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1714                         nand->cs[i].rb.id = val;
1715                 } else {
1716                         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1717                                                         "rb", i, &np->fwnode,
1718                                                         GPIOD_IN, "nand-rb");
1719                         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1720                                 dev_err(nc->dev,
1721                                         "Failed to get R/B gpio (err = %ld)\n",
1722                                         PTR_ERR(gpio));
1723                                 return ERR_CAST(gpio);
1724                         }
1725
1726                         if (!IS_ERR(gpio)) {
1727                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1728                                 nand->cs[i].rb.gpio = gpio;
1729                         }
1730                 }
1731
1732                 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1733                                                               i, &np->fwnode,
1734                                                               GPIOD_OUT_HIGH,
1735                                                               "nand-cs");
1736                 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1737                         dev_err(nc->dev,
1738                                 "Failed to get CS gpio (err = %ld)\n",
1739                                 PTR_ERR(gpio));
1740                         return ERR_CAST(gpio);
1741                 }
1742
1743                 if (!IS_ERR(gpio))
1744                         nand->cs[i].csgpio = gpio;
1745         }
1746
1747         nand_set_flash_node(&nand->base, np);
1748
1749         return nand;
1750 }
1751
1752 static int
1753 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1754                                struct atmel_nand *nand)
1755 {
1756         int ret;
1757
1758         /* No card inserted, skip this NAND. */
1759         if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1760                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1761                 return 0;
1762         }
1763
1764         nc->caps->ops->nand_init(nc, nand);
1765
1766         ret = atmel_nand_detect(nand);
1767         if (ret)
1768                 return ret;
1769
1770         ret = nc->caps->ops->ecc_init(nand);
1771         if (ret)
1772                 return ret;
1773
1774         return atmel_nand_register(nand);
1775 }
1776
1777 static int
1778 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1779 {
1780         struct atmel_nand *nand, *tmp;
1781         int ret;
1782
1783         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1784                 ret = atmel_nand_unregister(nand);
1785                 if (ret)
1786                         return ret;
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int
1793 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1794 {
1795         struct device *dev = nc->dev;
1796         struct platform_device *pdev = to_platform_device(dev);
1797         struct atmel_nand *nand;
1798         struct gpio_desc *gpio;
1799         struct resource *res;
1800
1801         /*
1802          * Legacy bindings only allow connecting a single NAND with a unique CS
1803          * line to the controller.
1804          */
1805         nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1806                             GFP_KERNEL);
1807         if (!nand)
1808                 return -ENOMEM;
1809
1810         nand->numcs = 1;
1811
1812         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1813         nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1814         if (IS_ERR(nand->cs[0].io.virt))
1815                 return PTR_ERR(nand->cs[0].io.virt);
1816
1817         nand->cs[0].io.dma = res->start;
1818
1819         /*
1820          * The old driver was hardcoding the CS id to 3 for all sama5
1821          * controllers. Since this id is only meaningful for the sama5
1822          * controller we can safely assign this id to 3 no matter the
1823          * controller.
1824          * If one wants to connect a NAND to a different CS line, he will
1825          * have to use the new bindings.
1826          */
1827         nand->cs[0].id = 3;
1828
1829         /* R/B GPIO. */
1830         gpio = devm_gpiod_get_index_optional(dev, NULL, 0,  GPIOD_IN);
1831         if (IS_ERR(gpio)) {
1832                 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1833                         PTR_ERR(gpio));
1834                 return PTR_ERR(gpio);
1835         }
1836
1837         if (gpio) {
1838                 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1839                 nand->cs[0].rb.gpio = gpio;
1840         }
1841
1842         /* CS GPIO. */
1843         gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1844         if (IS_ERR(gpio)) {
1845                 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1846                         PTR_ERR(gpio));
1847                 return PTR_ERR(gpio);
1848         }
1849
1850         nand->cs[0].csgpio = gpio;
1851
1852         /* Card detect GPIO. */
1853         gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1854         if (IS_ERR(gpio)) {
1855                 dev_err(dev,
1856                         "Failed to get detect gpio (err = %ld)\n",
1857                         PTR_ERR(gpio));
1858                 return PTR_ERR(gpio);
1859         }
1860
1861         nand->cdgpio = gpio;
1862
1863         nand_set_flash_node(&nand->base, nc->dev->of_node);
1864
1865         return atmel_nand_controller_add_nand(nc, nand);
1866 }
1867
1868 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1869 {
1870         struct device_node *np, *nand_np;
1871         struct device *dev = nc->dev;
1872         int ret, reg_cells;
1873         u32 val;
1874
1875         /* We do not retrieve the SMC syscon when parsing old DTs. */
1876         if (nc->caps->legacy_of_bindings)
1877                 return atmel_nand_controller_legacy_add_nands(nc);
1878
1879         np = dev->of_node;
1880
1881         ret = of_property_read_u32(np, "#address-cells", &val);
1882         if (ret) {
1883                 dev_err(dev, "missing #address-cells property\n");
1884                 return ret;
1885         }
1886
1887         reg_cells = val;
1888
1889         ret = of_property_read_u32(np, "#size-cells", &val);
1890         if (ret) {
1891                 dev_err(dev, "missing #size-cells property\n");
1892                 return ret;
1893         }
1894
1895         reg_cells += val;
1896
1897         for_each_child_of_node(np, nand_np) {
1898                 struct atmel_nand *nand;
1899
1900                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1901                 if (IS_ERR(nand)) {
1902                         ret = PTR_ERR(nand);
1903                         goto err;
1904                 }
1905
1906                 ret = atmel_nand_controller_add_nand(nc, nand);
1907                 if (ret)
1908                         goto err;
1909         }
1910
1911         return 0;
1912
1913 err:
1914         atmel_nand_controller_remove_nands(nc);
1915
1916         return ret;
1917 }
1918
1919 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1920 {
1921         if (nc->dmac)
1922                 dma_release_channel(nc->dmac);
1923
1924         clk_put(nc->mck);
1925 }
1926
1927 static const struct of_device_id atmel_matrix_of_ids[] = {
1928         {
1929                 .compatible = "atmel,at91sam9260-matrix",
1930                 .data = (void *)AT91SAM9260_MATRIX_EBICSA,
1931         },
1932         {
1933                 .compatible = "atmel,at91sam9261-matrix",
1934                 .data = (void *)AT91SAM9261_MATRIX_EBICSA,
1935         },
1936         {
1937                 .compatible = "atmel,at91sam9263-matrix",
1938                 .data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1939         },
1940         {
1941                 .compatible = "atmel,at91sam9rl-matrix",
1942                 .data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1943         },
1944         {
1945                 .compatible = "atmel,at91sam9g45-matrix",
1946                 .data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1947         },
1948         {
1949                 .compatible = "atmel,at91sam9n12-matrix",
1950                 .data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1951         },
1952         {
1953                 .compatible = "atmel,at91sam9x5-matrix",
1954                 .data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1955         },
1956         { /* sentinel */ },
1957 };
1958
1959 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1960                                 struct platform_device *pdev,
1961                                 const struct atmel_nand_controller_caps *caps)
1962 {
1963         struct device *dev = &pdev->dev;
1964         struct device_node *np = dev->of_node;
1965         int ret;
1966
1967         nand_hw_control_init(&nc->base);
1968         INIT_LIST_HEAD(&nc->chips);
1969         nc->dev = dev;
1970         nc->caps = caps;
1971
1972         platform_set_drvdata(pdev, nc);
1973
1974         nc->pmecc = devm_atmel_pmecc_get(dev);
1975         if (IS_ERR(nc->pmecc)) {
1976                 ret = PTR_ERR(nc->pmecc);
1977                 if (ret != -EPROBE_DEFER)
1978                         dev_err(dev, "Could not get PMECC object (err = %d)\n",
1979                                 ret);
1980                 return ret;
1981         }
1982
1983         if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
1984                 dma_cap_mask_t mask;
1985
1986                 dma_cap_zero(mask);
1987                 dma_cap_set(DMA_MEMCPY, mask);
1988
1989                 nc->dmac = dma_request_channel(mask, NULL, NULL);
1990                 if (!nc->dmac)
1991                         dev_err(nc->dev, "Failed to request DMA channel\n");
1992         }
1993
1994         /* We do not retrieve the SMC syscon when parsing old DTs. */
1995         if (nc->caps->legacy_of_bindings)
1996                 return 0;
1997
1998         nc->mck = of_clk_get(dev->parent->of_node, 0);
1999         if (IS_ERR(nc->mck)) {
2000                 dev_err(dev, "Failed to retrieve MCK clk\n");
2001                 return PTR_ERR(nc->mck);
2002         }
2003
2004         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2005         if (!np) {
2006                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2007                 return -EINVAL;
2008         }
2009
2010         nc->smc = syscon_node_to_regmap(np);
2011         of_node_put(np);
2012         if (IS_ERR(nc->smc)) {
2013                 ret = PTR_ERR(nc->smc);
2014                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2015                 return ret;
2016         }
2017
2018         return 0;
2019 }
2020
2021 static int
2022 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2023 {
2024         struct device *dev = nc->base.dev;
2025         const struct of_device_id *match;
2026         struct device_node *np;
2027         int ret;
2028
2029         /* We do not retrieve the matrix syscon when parsing old DTs. */
2030         if (nc->base.caps->legacy_of_bindings)
2031                 return 0;
2032
2033         np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
2034         if (!np)
2035                 return 0;
2036
2037         match = of_match_node(atmel_matrix_of_ids, np);
2038         if (!match) {
2039                 of_node_put(np);
2040                 return 0;
2041         }
2042
2043         nc->matrix = syscon_node_to_regmap(np);
2044         of_node_put(np);
2045         if (IS_ERR(nc->matrix)) {
2046                 ret = PTR_ERR(nc->matrix);
2047                 dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
2048                 return ret;
2049         }
2050
2051         nc->ebi_csa_offs = (unsigned int)match->data;
2052
2053         /*
2054          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2055          * add 4 to ->ebi_csa_offs.
2056          */
2057         if (of_device_is_compatible(dev->parent->of_node,
2058                                     "atmel,at91sam9263-ebi1"))
2059                 nc->ebi_csa_offs += 4;
2060
2061         return 0;
2062 }
2063
2064 static int
2065 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2066 {
2067         struct regmap_config regmap_conf = {
2068                 .reg_bits = 32,
2069                 .val_bits = 32,
2070                 .reg_stride = 4,
2071         };
2072
2073         struct device *dev = nc->base.dev;
2074         struct device_node *nand_np, *nfc_np;
2075         void __iomem *iomem;
2076         struct resource res;
2077         int ret;
2078
2079         nand_np = dev->of_node;
2080         nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
2081         if (!nfc_np) {
2082                 dev_err(dev, "Could not find device node for sama5d3-nfc\n");
2083                 return -ENODEV;
2084         }
2085
2086         nc->clk = of_clk_get(nfc_np, 0);
2087         if (IS_ERR(nc->clk)) {
2088                 ret = PTR_ERR(nc->clk);
2089                 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2090                         ret);
2091                 goto out;
2092         }
2093
2094         ret = clk_prepare_enable(nc->clk);
2095         if (ret) {
2096                 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2097                         ret);
2098                 goto out;
2099         }
2100
2101         nc->irq = of_irq_get(nand_np, 0);
2102         if (nc->irq <= 0) {
2103                 ret = nc->irq ?: -ENXIO;
2104                 if (ret != -EPROBE_DEFER)
2105                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2106                                 ret);
2107                 goto out;
2108         }
2109
2110         ret = of_address_to_resource(nfc_np, 0, &res);
2111         if (ret) {
2112                 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2113                         ret);
2114                 goto out;
2115         }
2116
2117         iomem = devm_ioremap_resource(dev, &res);
2118         if (IS_ERR(iomem)) {
2119                 ret = PTR_ERR(iomem);
2120                 goto out;
2121         }
2122
2123         regmap_conf.name = "nfc-io";
2124         regmap_conf.max_register = resource_size(&res) - 4;
2125         nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2126         if (IS_ERR(nc->io)) {
2127                 ret = PTR_ERR(nc->io);
2128                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2129                         ret);
2130                 goto out;
2131         }
2132
2133         ret = of_address_to_resource(nfc_np, 1, &res);
2134         if (ret) {
2135                 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2136                         ret);
2137                 goto out;
2138         }
2139
2140         iomem = devm_ioremap_resource(dev, &res);
2141         if (IS_ERR(iomem)) {
2142                 ret = PTR_ERR(iomem);
2143                 goto out;
2144         }
2145
2146         regmap_conf.name = "smc";
2147         regmap_conf.max_register = resource_size(&res) - 4;
2148         nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2149         if (IS_ERR(nc->base.smc)) {
2150                 ret = PTR_ERR(nc->base.smc);
2151                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2152                         ret);
2153                 goto out;
2154         }
2155
2156         ret = of_address_to_resource(nfc_np, 2, &res);
2157         if (ret) {
2158                 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2159                         ret);
2160                 goto out;
2161         }
2162
2163         nc->sram.virt = devm_ioremap_resource(dev, &res);
2164         if (IS_ERR(nc->sram.virt)) {
2165                 ret = PTR_ERR(nc->sram.virt);
2166                 goto out;
2167         }
2168
2169         nc->sram.dma = res.start;
2170
2171 out:
2172         of_node_put(nfc_np);
2173
2174         return ret;
2175 }
2176
2177 static int
2178 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2179 {
2180         struct device *dev = nc->base.dev;
2181         struct device_node *np;
2182         int ret;
2183
2184         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2185         if (!np) {
2186                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2187                 return -EINVAL;
2188         }
2189
2190         nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2191
2192         nc->irq = of_irq_get(np, 0);
2193         of_node_put(np);
2194         if (nc->irq <= 0) {
2195                 ret = nc->irq ?: -ENXIO;
2196                 if (ret != -EPROBE_DEFER)
2197                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2198                                 ret);
2199                 return ret;
2200         }
2201
2202         np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2203         if (!np) {
2204                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2205                 return -EINVAL;
2206         }
2207
2208         nc->io = syscon_node_to_regmap(np);
2209         of_node_put(np);
2210         if (IS_ERR(nc->io)) {
2211                 ret = PTR_ERR(nc->io);
2212                 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2213                 return ret;
2214         }
2215
2216         nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2217                                          "atmel,nfc-sram", 0);
2218         if (!nc->sram.pool) {
2219                 dev_err(nc->base.dev, "Missing SRAM\n");
2220                 return -ENOMEM;
2221         }
2222
2223         nc->sram.virt = gen_pool_dma_alloc(nc->sram.pool,
2224                                             ATMEL_NFC_SRAM_SIZE,
2225                                             &nc->sram.dma);
2226         if (!nc->sram.virt) {
2227                 dev_err(nc->base.dev,
2228                         "Could not allocate memory from the NFC SRAM pool\n");
2229                 return -ENOMEM;
2230         }
2231
2232         return 0;
2233 }
2234
2235 static int
2236 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2237 {
2238         struct atmel_hsmc_nand_controller *hsmc_nc;
2239         int ret;
2240
2241         ret = atmel_nand_controller_remove_nands(nc);
2242         if (ret)
2243                 return ret;
2244
2245         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2246         if (hsmc_nc->sram.pool)
2247                 gen_pool_free(hsmc_nc->sram.pool,
2248                               (unsigned long)hsmc_nc->sram.virt,
2249                               ATMEL_NFC_SRAM_SIZE);
2250
2251         if (hsmc_nc->clk) {
2252                 clk_disable_unprepare(hsmc_nc->clk);
2253                 clk_put(hsmc_nc->clk);
2254         }
2255
2256         atmel_nand_controller_cleanup(nc);
2257
2258         return 0;
2259 }
2260
2261 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2262                                 const struct atmel_nand_controller_caps *caps)
2263 {
2264         struct device *dev = &pdev->dev;
2265         struct atmel_hsmc_nand_controller *nc;
2266         int ret;
2267
2268         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2269         if (!nc)
2270                 return -ENOMEM;
2271
2272         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2273         if (ret)
2274                 return ret;
2275
2276         if (caps->legacy_of_bindings)
2277                 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2278         else
2279                 ret = atmel_hsmc_nand_controller_init(nc);
2280
2281         if (ret)
2282                 return ret;
2283
2284         /* Make sure all irqs are masked before registering our IRQ handler. */
2285         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2286         ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2287                                IRQF_SHARED, "nfc", nc);
2288         if (ret) {
2289                 dev_err(dev,
2290                         "Could not get register NFC interrupt handler (err = %d)\n",
2291                         ret);
2292                 goto err;
2293         }
2294
2295         /* Initial NFC configuration. */
2296         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2297                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2298
2299         ret = atmel_nand_controller_add_nands(&nc->base);
2300         if (ret)
2301                 goto err;
2302
2303         return 0;
2304
2305 err:
2306         atmel_hsmc_nand_controller_remove(&nc->base);
2307
2308         return ret;
2309 }
2310
2311 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2312         .probe = atmel_hsmc_nand_controller_probe,
2313         .remove = atmel_hsmc_nand_controller_remove,
2314         .ecc_init = atmel_hsmc_nand_ecc_init,
2315         .nand_init = atmel_hsmc_nand_init,
2316         .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2317 };
2318
2319 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2320         .has_dma = true,
2321         .ale_offs = BIT(21),
2322         .cle_offs = BIT(22),
2323         .ops = &atmel_hsmc_nc_ops,
2324 };
2325
2326 /* Only used to parse old bindings. */
2327 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2328         .has_dma = true,
2329         .ale_offs = BIT(21),
2330         .cle_offs = BIT(22),
2331         .ops = &atmel_hsmc_nc_ops,
2332         .legacy_of_bindings = true,
2333 };
2334
2335 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2336                                 const struct atmel_nand_controller_caps *caps)
2337 {
2338         struct device *dev = &pdev->dev;
2339         struct atmel_smc_nand_controller *nc;
2340         int ret;
2341
2342         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2343         if (!nc)
2344                 return -ENOMEM;
2345
2346         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2347         if (ret)
2348                 return ret;
2349
2350         ret = atmel_smc_nand_controller_init(nc);
2351         if (ret)
2352                 return ret;
2353
2354         return atmel_nand_controller_add_nands(&nc->base);
2355 }
2356
2357 static int
2358 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2359 {
2360         int ret;
2361
2362         ret = atmel_nand_controller_remove_nands(nc);
2363         if (ret)
2364                 return ret;
2365
2366         atmel_nand_controller_cleanup(nc);
2367
2368         return 0;
2369 }
2370
2371 /*
2372  * The SMC reg layout of at91rm9200 is completely different which prevents us
2373  * from re-using atmel_smc_nand_setup_data_interface() for the
2374  * ->setup_data_interface() hook.
2375  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2376  * ->setup_data_interface() unassigned.
2377  */
2378 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2379         .probe = atmel_smc_nand_controller_probe,
2380         .remove = atmel_smc_nand_controller_remove,
2381         .ecc_init = atmel_nand_ecc_init,
2382         .nand_init = atmel_smc_nand_init,
2383 };
2384
2385 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2386         .ale_offs = BIT(21),
2387         .cle_offs = BIT(22),
2388         .ops = &at91rm9200_nc_ops,
2389 };
2390
2391 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2392         .probe = atmel_smc_nand_controller_probe,
2393         .remove = atmel_smc_nand_controller_remove,
2394         .ecc_init = atmel_nand_ecc_init,
2395         .nand_init = atmel_smc_nand_init,
2396         .setup_data_interface = atmel_smc_nand_setup_data_interface,
2397 };
2398
2399 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2400         .ale_offs = BIT(21),
2401         .cle_offs = BIT(22),
2402         .ops = &atmel_smc_nc_ops,
2403 };
2404
2405 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2406         .ale_offs = BIT(22),
2407         .cle_offs = BIT(21),
2408         .ops = &atmel_smc_nc_ops,
2409 };
2410
2411 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2412         .has_dma = true,
2413         .ale_offs = BIT(21),
2414         .cle_offs = BIT(22),
2415         .ops = &atmel_smc_nc_ops,
2416 };
2417
2418 /* Only used to parse old bindings. */
2419 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2420         .ale_offs = BIT(21),
2421         .cle_offs = BIT(22),
2422         .ops = &atmel_smc_nc_ops,
2423         .legacy_of_bindings = true,
2424 };
2425
2426 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2427         .ale_offs = BIT(22),
2428         .cle_offs = BIT(21),
2429         .ops = &atmel_smc_nc_ops,
2430         .legacy_of_bindings = true,
2431 };
2432
2433 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2434         .has_dma = true,
2435         .ale_offs = BIT(21),
2436         .cle_offs = BIT(22),
2437         .ops = &atmel_smc_nc_ops,
2438         .legacy_of_bindings = true,
2439 };
2440
2441 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2442         {
2443                 .compatible = "atmel,at91rm9200-nand-controller",
2444                 .data = &atmel_rm9200_nc_caps,
2445         },
2446         {
2447                 .compatible = "atmel,at91sam9260-nand-controller",
2448                 .data = &atmel_sam9260_nc_caps,
2449         },
2450         {
2451                 .compatible = "atmel,at91sam9261-nand-controller",
2452                 .data = &atmel_sam9261_nc_caps,
2453         },
2454         {
2455                 .compatible = "atmel,at91sam9g45-nand-controller",
2456                 .data = &atmel_sam9g45_nc_caps,
2457         },
2458         {
2459                 .compatible = "atmel,sama5d3-nand-controller",
2460                 .data = &atmel_sama5_nc_caps,
2461         },
2462         /* Support for old/deprecated bindings: */
2463         {
2464                 .compatible = "atmel,at91rm9200-nand",
2465                 .data = &atmel_rm9200_nand_caps,
2466         },
2467         {
2468                 .compatible = "atmel,sama5d4-nand",
2469                 .data = &atmel_rm9200_nand_caps,
2470         },
2471         {
2472                 .compatible = "atmel,sama5d2-nand",
2473                 .data = &atmel_rm9200_nand_caps,
2474         },
2475         { /* sentinel */ },
2476 };
2477 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2478
2479 static int atmel_nand_controller_probe(struct platform_device *pdev)
2480 {
2481         const struct atmel_nand_controller_caps *caps;
2482
2483         if (pdev->id_entry)
2484                 caps = (void *)pdev->id_entry->driver_data;
2485         else
2486                 caps = of_device_get_match_data(&pdev->dev);
2487
2488         if (!caps) {
2489                 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2490                 return -EINVAL;
2491         }
2492
2493         if (caps->legacy_of_bindings) {
2494                 struct device_node *nfc_node;
2495                 u32 ale_offs = 21;
2496
2497                 /*
2498                  * If we are parsing legacy DT props and the DT contains a
2499                  * valid NFC node, forward the request to the sama5 logic.
2500                  */
2501                 nfc_node = of_get_compatible_child(pdev->dev.of_node,
2502                                                    "atmel,sama5d3-nfc");
2503                 if (nfc_node) {
2504                         caps = &atmel_sama5_nand_caps;
2505                         of_node_put(nfc_node);
2506                 }
2507
2508                 /*
2509                  * Even if the compatible says we are dealing with an
2510                  * at91rm9200 controller, the atmel,nand-has-dma specify that
2511                  * this controller supports DMA, which means we are in fact
2512                  * dealing with an at91sam9g45+ controller.
2513                  */
2514                 if (!caps->has_dma &&
2515                     of_property_read_bool(pdev->dev.of_node,
2516                                           "atmel,nand-has-dma"))
2517                         caps = &atmel_sam9g45_nand_caps;
2518
2519                 /*
2520                  * All SoCs except the at91sam9261 are assigning ALE to A21 and
2521                  * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2522                  * actually dealing with an at91sam9261 controller.
2523                  */
2524                 of_property_read_u32(pdev->dev.of_node,
2525                                      "atmel,nand-addr-offset", &ale_offs);
2526                 if (ale_offs != 21)
2527                         caps = &atmel_sam9261_nand_caps;
2528         }
2529
2530         return caps->ops->probe(pdev, caps);
2531 }
2532
2533 static int atmel_nand_controller_remove(struct platform_device *pdev)
2534 {
2535         struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2536
2537         return nc->caps->ops->remove(nc);
2538 }
2539
2540 static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2541 {
2542         struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2543         struct atmel_nand *nand;
2544
2545         list_for_each_entry(nand, &nc->chips, node) {
2546                 int i;
2547
2548                 for (i = 0; i < nand->numcs; i++)
2549                         nand_reset(&nand->base, i);
2550         }
2551
2552         return 0;
2553 }
2554
2555 static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2556                          atmel_nand_controller_resume);
2557
2558 static struct platform_driver atmel_nand_controller_driver = {
2559         .driver = {
2560                 .name = "atmel-nand-controller",
2561                 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2562                 .pm = &atmel_nand_controller_pm_ops,
2563         },
2564         .probe = atmel_nand_controller_probe,
2565         .remove = atmel_nand_controller_remove,
2566 };
2567 module_platform_driver(atmel_nand_controller_driver);
2568
2569 MODULE_LICENSE("GPL");
2570 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2571 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2572 MODULE_ALIAS("platform:atmel-nand-controller");