drivers/mtd/nand/atmel_nand.c

   1 /*
   2  *  Copyright © 2003 Rick Bronson
   3  *
   4  *  Derived from drivers/mtd/nand/autcpu12.c
   5  *       Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
   6  *
   7  *  Derived from drivers/mtd/spia.c
   8  *       Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
   9  *
  10  *
  11  *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  12  *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
  13  *
  14  *     Derived from Das U-Boot source code
  15  *              (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  16  *     © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  17  *
  18  *  Add Programmable Multibit ECC support for various AT91 SoC
  19  *     © Copyright 2012 ATMEL, Hong Xu
  20  *
  21  *  Add Nand Flash Controller support for SAMA5 SoC
  22  *     © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
  23  *
  24  * This program is free software; you can redistribute it and/or modify
  25  * it under the terms of the GNU General Public License version 2 as
  26  * published by the Free Software Foundation.
  27  *
  28  */
  29
  30 #include <linux/clk.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/slab.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/of.h>
  37 #include <linux/of_device.h>
  38 #include <linux/of_gpio.h>
  39 #include <linux/mtd/mtd.h>
  40 #include <linux/mtd/nand.h>
  41 #include <linux/mtd/partitions.h>
  42
  43 #include <linux/delay.h>
  44 #include <linux/dmaengine.h>
  45 #include <linux/gpio.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/io.h>
  48 #include <linux/platform_data/atmel.h>
  49
  50 static int use_dma = 1;
  51 module_param(use_dma, int, 0);
  52
  53 static int on_flash_bbt = 0;
  54 module_param(on_flash_bbt, int, 0);
  55
  56 /* Register access macros */
  57 #define ecc_readl(add, reg)                             \
  58         __raw_readl(add + ATMEL_ECC_##reg)
  59 #define ecc_writel(add, reg, value)                     \
  60         __raw_writel((value), add + ATMEL_ECC_##reg)
  61
  62 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  63 #include "atmel_nand_nfc.h"     /* Nand Flash Controller definition */
  64
  65 struct atmel_nand_caps {
  66         bool pmecc_correct_erase_page;
  67         uint8_t pmecc_max_correction;
  68 };
  69
  70 /*
  71  * oob layout for large page size
  72  * bad block info is on bytes 0 and 1
  73  * the bytes have to be consecutives to avoid
  74  * several NAND_CMD_RNDOUT during read
  75  *
  76  * oob layout for small page size
  77  * bad block info is on bytes 4 and 5
  78  * the bytes have to be consecutives to avoid
  79  * several NAND_CMD_RNDOUT during read
  80  */
  81 static int atmel_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
  82                                   struct mtd_oob_region *oobregion)
  83 {
  84         if (section)
  85                 return -ERANGE;
  86
  87         oobregion->length = 4;
  88         oobregion->offset = 0;
  89
  90         return 0;
  91 }
  92
  93 static int atmel_ooblayout_free_sp(struct mtd_info *mtd, int section,
  94                                    struct mtd_oob_region *oobregion)
  95 {
  96         if (section)
  97                 return -ERANGE;
  98
  99         oobregion->offset = 6;
 100         oobregion->length = mtd->oobsize - oobregion->offset;
 101
 102         return 0;
 103 }
 104
 105 static const struct mtd_ooblayout_ops atmel_ooblayout_sp_ops = {
 106         .ecc = atmel_ooblayout_ecc_sp,
 107         .free = atmel_ooblayout_free_sp,
 108 };
 109
 110 struct atmel_nfc {
 111         void __iomem            *base_cmd_regs;
 112         void __iomem            *hsmc_regs;
 113         void                    *sram_bank0;
 114         dma_addr_t              sram_bank0_phys;
 115         bool                    use_nfc_sram;
 116         bool                    write_by_sram;
 117
 118         struct clk              *clk;
 119
 120         bool                    is_initialized;
 121         struct completion       comp_ready;
 122         struct completion       comp_cmd_done;
 123         struct completion       comp_xfer_done;
 124
 125         /* Point to the sram bank which include readed data via NFC */
 126         void                    *data_in_sram;
 127         bool                    will_write_sram;
 128 };
 129 static struct atmel_nfc nand_nfc;
 130
 131 struct atmel_nand_host {
 132         struct nand_chip        nand_chip;
 133         void __iomem            *io_base;
 134         dma_addr_t              io_phys;
 135         struct atmel_nand_data  board;
 136         struct device           *dev;
 137         void __iomem            *ecc;
 138
 139         struct completion       comp;
 140         struct dma_chan         *dma_chan;
 141
 142         struct atmel_nfc        *nfc;
 143
 144         const struct atmel_nand_caps    *caps;
 145         bool                    has_pmecc;
 146         u8                      pmecc_corr_cap;
 147         u16                     pmecc_sector_size;
 148         bool                    has_no_lookup_table;
 149         u32                     pmecc_lookup_table_offset;
 150         u32                     pmecc_lookup_table_offset_512;
 151         u32                     pmecc_lookup_table_offset_1024;
 152
 153         int                     pmecc_degree;   /* Degree of remainders */
 154         int                     pmecc_cw_len;   /* Length of codeword */
 155
 156         void __iomem            *pmerrloc_base;
 157         void __iomem            *pmerrloc_el_base;
 158         void __iomem            *pmecc_rom_base;
 159
 160         /* lookup table for alpha_to and index_of */
 161         void __iomem            *pmecc_alpha_to;
 162         void __iomem            *pmecc_index_of;
 163
 164         /* data for pmecc computation */
 165         int16_t                 *pmecc_partial_syn;
 166         int16_t                 *pmecc_si;
 167         int16_t                 *pmecc_smu;     /* Sigma table */
 168         int16_t                 *pmecc_lmu;     /* polynomal order */
 169         int                     *pmecc_mu;
 170         int                     *pmecc_dmu;
 171         int                     *pmecc_delta;
 172 };
 173
 174 /*
 175  * Enable NAND.
 176  */
 177 static void atmel_nand_enable(struct atmel_nand_host *host)
 178 {
 179         if (gpio_is_valid(host->board.enable_pin))
 180                 gpio_set_value(host->board.enable_pin, 0);
 181 }
 182
 183 /*
 184  * Disable NAND.
 185  */
 186 static void atmel_nand_disable(struct atmel_nand_host *host)
 187 {
 188         if (gpio_is_valid(host->board.enable_pin))
 189                 gpio_set_value(host->board.enable_pin, 1);
 190 }
 191
 192 /*
 193  * Hardware specific access to control-lines
 194  */
 195 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 196 {
 197         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 198         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 199
 200         if (ctrl & NAND_CTRL_CHANGE) {
 201                 if (ctrl & NAND_NCE)
 202                         atmel_nand_enable(host);
 203                 else
 204                         atmel_nand_disable(host);
 205         }
 206         if (cmd == NAND_CMD_NONE)
 207                 return;
 208
 209         if (ctrl & NAND_CLE)
 210                 writeb(cmd, host->io_base + (1 << host->board.cle));
 211         else
 212                 writeb(cmd, host->io_base + (1 << host->board.ale));
 213 }
 214
 215 /*
 216  * Read the Device Ready pin.
 217  */
 218 static int atmel_nand_device_ready(struct mtd_info *mtd)
 219 {
 220         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 221         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 222
 223         return gpio_get_value(host->board.rdy_pin) ^
 224                 !!host->board.rdy_pin_active_low;
 225 }
 226
 227 /* Set up for hardware ready pin and enable pin. */
 228 static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
 229 {
 230         struct nand_chip *chip = mtd_to_nand(mtd);
 231         struct atmel_nand_host *host = nand_get_controller_data(chip);
 232         int res = 0;
 233
 234         if (gpio_is_valid(host->board.rdy_pin)) {
 235                 res = devm_gpio_request(host->dev,
 236                                 host->board.rdy_pin, "nand_rdy");
 237                 if (res < 0) {
 238                         dev_err(host->dev,
 239                                 "can't request rdy gpio %d\n",
 240                                 host->board.rdy_pin);
 241                         return res;
 242                 }
 243
 244                 res = gpio_direction_input(host->board.rdy_pin);
 245                 if (res < 0) {
 246                         dev_err(host->dev,
 247                                 "can't request input direction rdy gpio %d\n",
 248                                 host->board.rdy_pin);
 249                         return res;
 250                 }
 251
 252                 chip->dev_ready = atmel_nand_device_ready;
 253         }
 254
 255         if (gpio_is_valid(host->board.enable_pin)) {
 256                 res = devm_gpio_request(host->dev,
 257                                 host->board.enable_pin, "nand_enable");
 258                 if (res < 0) {
 259                         dev_err(host->dev,
 260                                 "can't request enable gpio %d\n",
 261                                 host->board.enable_pin);
 262                         return res;
 263                 }
 264
 265                 res = gpio_direction_output(host->board.enable_pin, 1);
 266                 if (res < 0) {
 267                         dev_err(host->dev,
 268                                 "can't request output direction enable gpio %d\n",
 269                                 host->board.enable_pin);
 270                         return res;
 271                 }
 272         }
 273
 274         return res;
 275 }
 276
 277 /*
 278  * Minimal-overhead PIO for data access.
 279  */
 280 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
 281 {
 282         struct nand_chip        *nand_chip = mtd_to_nand(mtd);
 283         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 284
 285         if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
 286                 memcpy(buf, host->nfc->data_in_sram, len);
 287                 host->nfc->data_in_sram += len;
 288         } else {
 289                 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
 290         }
 291 }
 292
 293 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
 294 {
 295         struct nand_chip        *nand_chip = mtd_to_nand(mtd);
 296         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 297
 298         if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
 299                 memcpy(buf, host->nfc->data_in_sram, len);
 300                 host->nfc->data_in_sram += len;
 301         } else {
 302                 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
 303         }
 304 }
 305
 306 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
 307 {
 308         struct nand_chip        *nand_chip = mtd_to_nand(mtd);
 309
 310         __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
 311 }
 312
 313 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
 314 {
 315         struct nand_chip        *nand_chip = mtd_to_nand(mtd);
 316
 317         __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
 318 }
 319
 320 static void dma_complete_func(void *completion)
 321 {
 322         complete(completion);
 323 }
 324
 325 static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
 326 {
 327         /* NFC only has two banks. Must be 0 or 1 */
 328         if (bank > 1)
 329                 return -EINVAL;
 330
 331         if (bank) {
 332                 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
 333
 334                 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
 335                 if (mtd->writesize > 2048)
 336                         return -EINVAL;
 337                 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
 338         } else {
 339                 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
 340         }
 341
 342         return 0;
 343 }
 344
 345 static uint nfc_get_sram_off(struct atmel_nand_host *host)
 346 {
 347         if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
 348                 return NFC_SRAM_BANK1_OFFSET;
 349         else
 350                 return 0;
 351 }
 352
 353 static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
 354 {
 355         if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
 356                 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
 357         else
 358                 return host->nfc->sram_bank0_phys;
 359 }
 360
 361 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
 362                                int is_read)
 363 {
 364         struct dma_device *dma_dev;
 365         enum dma_ctrl_flags flags;
 366         dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
 367         struct dma_async_tx_descriptor *tx = NULL;
 368         dma_cookie_t cookie;
 369         struct nand_chip *chip = mtd_to_nand(mtd);
 370         struct atmel_nand_host *host = nand_get_controller_data(chip);
 371         void *p = buf;
 372         int err = -EIO;
 373         enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 374         struct atmel_nfc *nfc = host->nfc;
 375
 376         if (buf >= high_memory)
 377                 goto err_buf;
 378
 379         dma_dev = host->dma_chan->device;
 380
 381         flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 382
 383         phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
 384         if (dma_mapping_error(dma_dev->dev, phys_addr)) {
 385                 dev_err(host->dev, "Failed to dma_map_single\n");
 386                 goto err_buf;
 387         }
 388
 389         if (is_read) {
 390                 if (nfc && nfc->data_in_sram)
 391                         dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
 392                                 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
 393                 else
 394                         dma_src_addr = host->io_phys;
 395
 396                 dma_dst_addr = phys_addr;
 397         } else {
 398                 dma_src_addr = phys_addr;
 399
 400                 if (nfc && nfc->write_by_sram)
 401                         dma_dst_addr = nfc_sram_phys(host);
 402                 else
 403                         dma_dst_addr = host->io_phys;
 404         }
 405
 406         tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
 407                                              dma_src_addr, len, flags);
 408         if (!tx) {
 409                 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
 410                 goto err_dma;
 411         }
 412
 413         init_completion(&host->comp);
 414         tx->callback = dma_complete_func;
 415         tx->callback_param = &host->comp;
 416
 417         cookie = tx->tx_submit(tx);
 418         if (dma_submit_error(cookie)) {
 419                 dev_err(host->dev, "Failed to do DMA tx_submit\n");
 420                 goto err_dma;
 421         }
 422
 423         dma_async_issue_pending(host->dma_chan);
 424         wait_for_completion(&host->comp);
 425
 426         if (is_read && nfc && nfc->data_in_sram)
 427                 /* After read data from SRAM, need to increase the position */
 428                 nfc->data_in_sram += len;
 429
 430         err = 0;
 431
 432 err_dma:
 433         dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
 434 err_buf:
 435         if (err != 0)
 436                 dev_dbg(host->dev, "Fall back to CPU I/O\n");
 437         return err;
 438 }
 439
 440 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 441 {
 442         struct nand_chip *chip = mtd_to_nand(mtd);
 443
 444         if (use_dma && len > mtd->oobsize)
 445                 /* only use DMA for bigger than oob size: better performances */
 446                 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
 447                         return;
 448
 449         if (chip->options & NAND_BUSWIDTH_16)
 450                 atmel_read_buf16(mtd, buf, len);
 451         else
 452                 atmel_read_buf8(mtd, buf, len);
 453 }
 454
 455 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 456 {
 457         struct nand_chip *chip = mtd_to_nand(mtd);
 458
 459         if (use_dma && len > mtd->oobsize)
 460                 /* only use DMA for bigger than oob size: better performances */
 461                 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
 462                         return;
 463
 464         if (chip->options & NAND_BUSWIDTH_16)
 465                 atmel_write_buf16(mtd, buf, len);
 466         else
 467                 atmel_write_buf8(mtd, buf, len);
 468 }
 469
 470 /*
 471  * Return number of ecc bytes per sector according to sector size and
 472  * correction capability
 473  *
 474  * Following table shows what at91 PMECC supported:
 475  * Correction Capability        Sector_512_bytes        Sector_1024_bytes
 476  * =====================        ================        =================
 477  *                2-bits                 4-bytes                  4-bytes
 478  *                4-bits                 7-bytes                  7-bytes
 479  *                8-bits                13-bytes                 14-bytes
 480  *               12-bits                20-bytes                 21-bytes
 481  *               24-bits                39-bytes                 42-bytes
 482  *               32-bits                52-bytes                 56-bytes
 483  */
 484 static int pmecc_get_ecc_bytes(int cap, int sector_size)
 485 {
 486         int m = 12 + sector_size / 512;
 487         return (m * cap + 7) / 8;
 488 }
 489
 490 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
 491 {
 492         int table_size;
 493
 494         table_size = host->pmecc_sector_size == 512 ?
 495                 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
 496
 497         return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
 498                         table_size * sizeof(int16_t);
 499 }
 500
 501 static int pmecc_data_alloc(struct atmel_nand_host *host)
 502 {
 503         const int cap = host->pmecc_corr_cap;
 504         int size;
 505
 506         size = (2 * cap + 1) * sizeof(int16_t);
 507         host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
 508         host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
 509         host->pmecc_lmu = devm_kzalloc(host->dev,
 510                         (cap + 1) * sizeof(int16_t), GFP_KERNEL);
 511         host->pmecc_smu = devm_kzalloc(host->dev,
 512                         (cap + 2) * size, GFP_KERNEL);
 513
 514         size = (cap + 1) * sizeof(int);
 515         host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
 516         host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
 517         host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
 518
 519         if (!host->pmecc_partial_syn ||
 520                 !host->pmecc_si ||
 521                 !host->pmecc_lmu ||
 522                 !host->pmecc_smu ||
 523                 !host->pmecc_mu ||
 524                 !host->pmecc_dmu ||
 525                 !host->pmecc_delta)
 526                 return -ENOMEM;
 527
 528         return 0;
 529 }
 530
 531 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 532 {
 533         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 534         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 535         int i;
 536         uint32_t value;
 537
 538         /* Fill odd syndromes */
 539         for (i = 0; i < host->pmecc_corr_cap; i++) {
 540                 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
 541                 if (i & 1)
 542                         value >>= 16;
 543                 value &= 0xffff;
 544                 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
 545         }
 546 }
 547
 548 static void pmecc_substitute(struct mtd_info *mtd)
 549 {
 550         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 551         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 552         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 553         int16_t __iomem *index_of = host->pmecc_index_of;
 554         int16_t *partial_syn = host->pmecc_partial_syn;
 555         const int cap = host->pmecc_corr_cap;
 556         int16_t *si;
 557         int i, j;
 558
 559         /* si[] is a table that holds the current syndrome value,
 560          * an element of that table belongs to the field
 561          */
 562         si = host->pmecc_si;
 563
 564         memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
 565
 566         /* Computation 2t syndromes based on S(x) */
 567         /* Odd syndromes */
 568         for (i = 1; i < 2 * cap; i += 2) {
 569                 for (j = 0; j < host->pmecc_degree; j++) {
 570                         if (partial_syn[i] & ((unsigned short)0x1 << j))
 571                                 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
 572                 }
 573         }
 574         /* Even syndrome = (Odd syndrome) ** 2 */
 575         for (i = 2, j = 1; j <= cap; i = ++j << 1) {
 576                 if (si[j] == 0) {
 577                         si[i] = 0;
 578                 } else {
 579                         int16_t tmp;
 580
 581                         tmp = readw_relaxed(index_of + si[j]);
 582                         tmp = (tmp * 2) % host->pmecc_cw_len;
 583                         si[i] = readw_relaxed(alpha_to + tmp);
 584                 }
 585         }
 586
 587         return;
 588 }
 589
 590 static void pmecc_get_sigma(struct mtd_info *mtd)
 591 {
 592         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 593         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 594
 595         int16_t *lmu = host->pmecc_lmu;
 596         int16_t *si = host->pmecc_si;
 597         int *mu = host->pmecc_mu;
 598         int *dmu = host->pmecc_dmu;     /* Discrepancy */
 599         int *delta = host->pmecc_delta; /* Delta order */
 600         int cw_len = host->pmecc_cw_len;
 601         const int16_t cap = host->pmecc_corr_cap;
 602         const int num = 2 * cap + 1;
 603         int16_t __iomem *index_of = host->pmecc_index_of;
 604         int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 605         int i, j, k;
 606         uint32_t dmu_0_count, tmp;
 607         int16_t *smu = host->pmecc_smu;
 608
 609         /* index of largest delta */
 610         int ro;
 611         int largest;
 612         int diff;
 613
 614         dmu_0_count = 0;
 615
 616         /* First Row */
 617
 618         /* Mu */
 619         mu[0] = -1;
 620
 621         memset(smu, 0, sizeof(int16_t) * num);
 622         smu[0] = 1;
 623
 624         /* discrepancy set to 1 */
 625         dmu[0] = 1;
 626         /* polynom order set to 0 */
 627         lmu[0] = 0;
 628         delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
 629
 630         /* Second Row */
 631
 632         /* Mu */
 633         mu[1] = 0;
 634         /* Sigma(x) set to 1 */
 635         memset(&smu[num], 0, sizeof(int16_t) * num);
 636         smu[num] = 1;
 637
 638         /* discrepancy set to S1 */
 639         dmu[1] = si[1];
 640
 641         /* polynom order set to 0 */
 642         lmu[1] = 0;
 643
 644         delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
 645
 646         /* Init the Sigma(x) last row */
 647         memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
 648
 649         for (i = 1; i <= cap; i++) {
 650                 mu[i + 1] = i << 1;
 651                 /* Begin Computing Sigma (Mu+1) and L(mu) */
 652                 /* check if discrepancy is set to 0 */
 653                 if (dmu[i] == 0) {
 654                         dmu_0_count++;
 655
 656                         tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
 657                         if ((cap - (lmu[i] >> 1) - 1) & 0x1)
 658                                 tmp += 2;
 659                         else
 660                                 tmp += 1;
 661
 662                         if (dmu_0_count == tmp) {
 663                                 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
 664                                         smu[(cap + 1) * num + j] =
 665                                                         smu[i * num + j];
 666
 667                                 lmu[cap + 1] = lmu[i];
 668                                 return;
 669                         }
 670
 671                         /* copy polynom */
 672                         for (j = 0; j <= lmu[i] >> 1; j++)
 673                                 smu[(i + 1) * num + j] = smu[i * num + j];
 674
 675                         /* copy previous polynom order to the next */
 676                         lmu[i + 1] = lmu[i];
 677                 } else {
 678                         ro = 0;
 679                         largest = -1;
 680                         /* find largest delta with dmu != 0 */
 681                         for (j = 0; j < i; j++) {
 682                                 if ((dmu[j]) && (delta[j] > largest)) {
 683                                         largest = delta[j];
 684                                         ro = j;
 685                                 }
 686                         }
 687
 688                         /* compute difference */
 689                         diff = (mu[i] - mu[ro]);
 690
 691                         /* Compute degree of the new smu polynomial */
 692                         if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
 693                                 lmu[i + 1] = lmu[i];
 694                         else
 695                                 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
 696
 697                         /* Init smu[i+1] with 0 */
 698                         for (k = 0; k < num; k++)
 699                                 smu[(i + 1) * num + k] = 0;
 700
 701                         /* Compute smu[i+1] */
 702                         for (k = 0; k <= lmu[ro] >> 1; k++) {
 703                                 int16_t a, b, c;
 704
 705                                 if (!(smu[ro * num + k] && dmu[i]))
 706                                         continue;
 707                                 a = readw_relaxed(index_of + dmu[i]);
 708                                 b = readw_relaxed(index_of + dmu[ro]);
 709                                 c = readw_relaxed(index_of + smu[ro * num + k]);
 710                                 tmp = a + (cw_len - b) + c;
 711                                 a = readw_relaxed(alpha_to + tmp % cw_len);
 712                                 smu[(i + 1) * num + (k + diff)] = a;
 713                         }
 714
 715                         for (k = 0; k <= lmu[i] >> 1; k++)
 716                                 smu[(i + 1) * num + k] ^= smu[i * num + k];
 717                 }
 718
 719                 /* End Computing Sigma (Mu+1) and L(mu) */
 720                 /* In either case compute delta */
 721                 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
 722
 723                 /* Do not compute discrepancy for the last iteration */
 724                 if (i >= cap)
 725                         continue;
 726
 727                 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
 728                         tmp = 2 * (i - 1);
 729                         if (k == 0) {
 730                                 dmu[i + 1] = si[tmp + 3];
 731                         } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
 732                                 int16_t a, b, c;
 733                                 a = readw_relaxed(index_of +
 734                                                 smu[(i + 1) * num + k]);
 735                                 b = si[2 * (i - 1) + 3 - k];
 736                                 c = readw_relaxed(index_of + b);
 737                                 tmp = a + c;
 738                                 tmp %= cw_len;
 739                                 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
 740                                         dmu[i + 1];
 741                         }
 742                 }
 743         }
 744
 745         return;
 746 }
 747
 748 static int pmecc_err_location(struct mtd_info *mtd)
 749 {
 750         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 751         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 752         unsigned long end_time;
 753         const int cap = host->pmecc_corr_cap;
 754         const int num = 2 * cap + 1;
 755         int sector_size = host->pmecc_sector_size;
 756         int err_nbr = 0;        /* number of error */
 757         int roots_nbr;          /* number of roots */
 758         int i;
 759         uint32_t val;
 760         int16_t *smu = host->pmecc_smu;
 761
 762         pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
 763
 764         for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
 765                 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
 766                                       smu[(cap + 1) * num + i]);
 767                 err_nbr++;
 768         }
 769
 770         val = (err_nbr - 1) << 16;
 771         if (sector_size == 1024)
 772                 val |= 1;
 773
 774         pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
 775         pmerrloc_writel(host->pmerrloc_base, ELEN,
 776                         sector_size * 8 + host->pmecc_degree * cap);
 777
 778         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
 779         while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
 780                  & PMERRLOC_CALC_DONE)) {
 781                 if (unlikely(time_after(jiffies, end_time))) {
 782                         dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
 783                         return -1;
 784                 }
 785                 cpu_relax();
 786         }
 787
 788         roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
 789                 & PMERRLOC_ERR_NUM_MASK) >> 8;
 790         /* Number of roots == degree of smu hence <= cap */
 791         if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
 792                 return err_nbr - 1;
 793
 794         /* Number of roots does not match the degree of smu
 795          * unable to correct error */
 796         return -1;
 797 }
 798
 799 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 800                 int sector_num, int extra_bytes, int err_nbr)
 801 {
 802         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 803         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 804         int i = 0;
 805         int byte_pos, bit_pos, sector_size, pos;
 806         uint32_t tmp;
 807         uint8_t err_byte;
 808
 809         sector_size = host->pmecc_sector_size;
 810
 811         while (err_nbr) {
 812                 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_el_base, i) - 1;
 813                 byte_pos = tmp / 8;
 814                 bit_pos  = tmp % 8;
 815
 816                 if (byte_pos >= (sector_size + extra_bytes))
 817                         BUG();  /* should never happen */
 818
 819                 if (byte_pos < sector_size) {
 820                         err_byte = *(buf + byte_pos);
 821                         *(buf + byte_pos) ^= (1 << bit_pos);
 822
 823                         pos = sector_num * host->pmecc_sector_size + byte_pos;
 824                         dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 825                                 pos, bit_pos, err_byte, *(buf + byte_pos));
 826                 } else {
 827                         struct mtd_oob_region oobregion;
 828
 829                         /* Bit flip in OOB area */
 830                         tmp = sector_num * nand_chip->ecc.bytes
 831                                         + (byte_pos - sector_size);
 832                         err_byte = ecc[tmp];
 833                         ecc[tmp] ^= (1 << bit_pos);
 834
 835                         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 836                         pos = tmp + oobregion.offset;
 837                         dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
 838                                 pos, bit_pos, err_byte, ecc[tmp]);
 839                 }
 840
 841                 i++;
 842                 err_nbr--;
 843         }
 844
 845         return;
 846 }
 847
 848 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 849         u8 *ecc)
 850 {
 851         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 852         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 853         int i, err_nbr;
 854         uint8_t *buf_pos;
 855         int max_bitflips = 0;
 856
 857         for (i = 0; i < nand_chip->ecc.steps; i++) {
 858                 err_nbr = 0;
 859                 if (pmecc_stat & 0x1) {
 860                         buf_pos = buf + i * host->pmecc_sector_size;
 861
 862                         pmecc_gen_syndrome(mtd, i);
 863                         pmecc_substitute(mtd);
 864                         pmecc_get_sigma(mtd);
 865
 866                         err_nbr = pmecc_err_location(mtd);
 867                         if (err_nbr >= 0) {
 868                                 pmecc_correct_data(mtd, buf_pos, ecc, i,
 869                                                    nand_chip->ecc.bytes,
 870                                                    err_nbr);
 871                         } else if (!host->caps->pmecc_correct_erase_page) {
 872                                 u8 *ecc_pos = ecc + (i * nand_chip->ecc.bytes);
 873
 874                                 /* Try to detect erased pages */
 875                                 err_nbr = nand_check_erased_ecc_chunk(buf_pos,
 876                                                         host->pmecc_sector_size,
 877                                                         ecc_pos,
 878                                                         nand_chip->ecc.bytes,
 879                                                         NULL, 0,
 880                                                         nand_chip->ecc.strength);
 881                         }
 882
 883                         if (err_nbr < 0) {
 884                                 dev_err(host->dev, "PMECC: Too many errors\n");
 885                                 mtd->ecc_stats.failed++;
 886                                 return -EIO;
 887                         }
 888
 889                         mtd->ecc_stats.corrected += err_nbr;
 890                         max_bitflips = max_t(int, max_bitflips, err_nbr);
 891                 }
 892                 pmecc_stat >>= 1;
 893         }
 894
 895         return max_bitflips;
 896 }
 897
 898 static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
 899 {
 900         u32 val;
 901
 902         if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
 903                 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
 904                 return;
 905         }
 906
 907         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
 908         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
 909         val = pmecc_readl_relaxed(host->ecc, CFG);
 910
 911         if (ecc_op == NAND_ECC_READ)
 912                 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
 913                         | PMECC_CFG_AUTO_ENABLE);
 914         else
 915                 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
 916                         & ~PMECC_CFG_AUTO_ENABLE);
 917
 918         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
 919         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
 920 }
 921
 922 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 923         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 924 {
 925         struct atmel_nand_host *host = nand_get_controller_data(chip);
 926         int eccsize = chip->ecc.size * chip->ecc.steps;
 927         uint8_t *oob = chip->oob_poi;
 928         uint32_t stat;
 929         unsigned long end_time;
 930         int bitflips = 0;
 931
 932         if (!host->nfc || !host->nfc->use_nfc_sram)
 933                 pmecc_enable(host, NAND_ECC_READ);
 934
 935         chip->read_buf(mtd, buf, eccsize);
 936         chip->read_buf(mtd, oob, mtd->oobsize);
 937
 938         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
 939         while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
 940                 if (unlikely(time_after(jiffies, end_time))) {
 941                         dev_err(host->dev, "PMECC: Timeout to get error status.\n");
 942                         return -EIO;
 943                 }
 944                 cpu_relax();
 945         }
 946
 947         stat = pmecc_readl_relaxed(host->ecc, ISR);
 948         if (stat != 0) {
 949                 struct mtd_oob_region oobregion;
 950
 951                 mtd_ooblayout_ecc(mtd, 0, &oobregion);
 952                 bitflips = pmecc_correction(mtd, stat, buf,
 953                                             &oob[oobregion.offset]);
 954                 if (bitflips < 0)
 955                         /* uncorrectable errors */
 956                         return 0;
 957         }
 958
 959         return bitflips;
 960 }
 961
 962 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 963                 struct nand_chip *chip, const uint8_t *buf, int oob_required,
 964                 int page)
 965 {
 966         struct atmel_nand_host *host = nand_get_controller_data(chip);
 967         struct mtd_oob_region oobregion = { };
 968         int i, j, section = 0;
 969         unsigned long end_time;
 970
 971         if (!host->nfc || !host->nfc->write_by_sram) {
 972                 pmecc_enable(host, NAND_ECC_WRITE);
 973                 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
 974         }
 975
 976         end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
 977         while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
 978                 if (unlikely(time_after(jiffies, end_time))) {
 979                         dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
 980                         return -EIO;
 981                 }
 982                 cpu_relax();
 983         }
 984
 985         for (i = 0; i < chip->ecc.steps; i++) {
 986                 for (j = 0; j < chip->ecc.bytes; j++) {
 987                         if (!oobregion.length)
 988                                 mtd_ooblayout_ecc(mtd, section, &oobregion);
 989
 990                         chip->oob_poi[oobregion.offset] =
 991                                 pmecc_readb_ecc_relaxed(host->ecc, i, j);
 992                         oobregion.length--;
 993                         oobregion.offset++;
 994                         section++;
 995                 }
 996         }
 997         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 998
 999         return 0;
1000 }
1001
1002 static void atmel_pmecc_core_init(struct mtd_info *mtd)
1003 {
1004         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1005         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1006         int eccbytes = mtd_ooblayout_count_eccbytes(mtd);
1007         uint32_t val = 0;
1008         struct mtd_oob_region oobregion;
1009
1010         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1011         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1012
1013         switch (host->pmecc_corr_cap) {
1014         case 2:
1015                 val = PMECC_CFG_BCH_ERR2;
1016                 break;
1017         case 4:
1018                 val = PMECC_CFG_BCH_ERR4;
1019                 break;
1020         case 8:
1021                 val = PMECC_CFG_BCH_ERR8;
1022                 break;
1023         case 12:
1024                 val = PMECC_CFG_BCH_ERR12;
1025                 break;
1026         case 24:
1027                 val = PMECC_CFG_BCH_ERR24;
1028                 break;
1029         case 32:
1030                 val = PMECC_CFG_BCH_ERR32;
1031                 break;
1032         }
1033
1034         if (host->pmecc_sector_size == 512)
1035                 val |= PMECC_CFG_SECTOR512;
1036         else if (host->pmecc_sector_size == 1024)
1037                 val |= PMECC_CFG_SECTOR1024;
1038
1039         switch (nand_chip->ecc.steps) {
1040         case 1:
1041                 val |= PMECC_CFG_PAGE_1SECTOR;
1042                 break;
1043         case 2:
1044                 val |= PMECC_CFG_PAGE_2SECTORS;
1045                 break;
1046         case 4:
1047                 val |= PMECC_CFG_PAGE_4SECTORS;
1048                 break;
1049         case 8:
1050                 val |= PMECC_CFG_PAGE_8SECTORS;
1051                 break;
1052         }
1053
1054         val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1055                 | PMECC_CFG_AUTO_DISABLE);
1056         pmecc_writel(host->ecc, CFG, val);
1057
1058         pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1059         mtd_ooblayout_ecc(mtd, 0, &oobregion);
1060         pmecc_writel(host->ecc, SADDR, oobregion.offset);
1061         pmecc_writel(host->ecc, EADDR,
1062                      oobregion.offset + eccbytes - 1);
1063         /* See datasheet about PMECC Clock Control Register */
1064         pmecc_writel(host->ecc, CLK, 2);
1065         pmecc_writel(host->ecc, IDR, 0xff);
1066         pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1067 }
1068
1069 /*
1070  * Get minimum ecc requirements from NAND.
1071  * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1072  * will set them according to minimum ecc requirement. Otherwise, use the
1073  * value in DTS file.
1074  * return 0 if success. otherwise return error code.
1075  */
1076 static int pmecc_choose_ecc(struct atmel_nand_host *host,
1077                 int *cap, int *sector_size)
1078 {
1079         /* Get minimum ECC requirements */
1080         if (host->nand_chip.ecc_strength_ds) {
1081                 *cap = host->nand_chip.ecc_strength_ds;
1082                 *sector_size = host->nand_chip.ecc_step_ds;
1083                 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
1084                                 *cap, *sector_size);
1085         } else {
1086                 *cap = 2;
1087                 *sector_size = 512;
1088                 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1089         }
1090
1091         /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1092         if (host->pmecc_corr_cap == 0) {
1093                 if (*cap > host->caps->pmecc_max_correction)
1094                         return -EINVAL;
1095
1096                 /* use the most fitable ecc bits (the near bigger one ) */
1097                 if (*cap <= 2)
1098                         host->pmecc_corr_cap = 2;
1099                 else if (*cap <= 4)
1100                         host->pmecc_corr_cap = 4;
1101                 else if (*cap <= 8)
1102                         host->pmecc_corr_cap = 8;
1103                 else if (*cap <= 12)
1104                         host->pmecc_corr_cap = 12;
1105                 else if (*cap <= 24)
1106                         host->pmecc_corr_cap = 24;
1107                 else if (*cap <= 32)
1108                         host->pmecc_corr_cap = 32;
1109                 else
1110                         return -EINVAL;
1111         }
1112         if (host->pmecc_sector_size == 0) {
1113                 /* use the most fitable sector size (the near smaller one ) */
1114                 if (*sector_size >= 1024)
1115                         host->pmecc_sector_size = 1024;
1116                 else if (*sector_size >= 512)
1117                         host->pmecc_sector_size = 512;
1118                 else
1119                         return -EINVAL;
1120         }
1121         return 0;
1122 }
1123
1124 static inline int deg(unsigned int poly)
1125 {
1126         /* polynomial degree is the most-significant bit index */
1127         return fls(poly) - 1;
1128 }
1129
1130 static int build_gf_tables(int mm, unsigned int poly,
1131                 int16_t *index_of, int16_t *alpha_to)
1132 {
1133         unsigned int i, x = 1;
1134         const unsigned int k = 1 << deg(poly);
1135         unsigned int nn = (1 << mm) - 1;
1136
1137         /* primitive polynomial must be of degree m */
1138         if (k != (1u << mm))
1139                 return -EINVAL;
1140
1141         for (i = 0; i < nn; i++) {
1142                 alpha_to[i] = x;
1143                 index_of[x] = i;
1144                 if (i && (x == 1))
1145                         /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
1146                         return -EINVAL;
1147                 x <<= 1;
1148                 if (x & k)
1149                         x ^= poly;
1150         }
1151         alpha_to[nn] = 1;
1152         index_of[0] = 0;
1153
1154         return 0;
1155 }
1156
1157 static uint16_t *create_lookup_table(struct device *dev, int sector_size)
1158 {
1159         int degree = (sector_size == 512) ?
1160                         PMECC_GF_DIMENSION_13 :
1161                         PMECC_GF_DIMENSION_14;
1162         unsigned int poly = (sector_size == 512) ?
1163                         PMECC_GF_13_PRIMITIVE_POLY :
1164                         PMECC_GF_14_PRIMITIVE_POLY;
1165         int table_size = (sector_size == 512) ?
1166                         PMECC_LOOKUP_TABLE_SIZE_512 :
1167                         PMECC_LOOKUP_TABLE_SIZE_1024;
1168
1169         int16_t *addr = devm_kzalloc(dev, 2 * table_size * sizeof(uint16_t),
1170                         GFP_KERNEL);
1171         if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
1172                 return NULL;
1173
1174         return addr;
1175 }
1176
1177 static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1178                                          struct atmel_nand_host *host)
1179 {
1180         struct nand_chip *nand_chip = &host->nand_chip;
1181         struct mtd_info *mtd = nand_to_mtd(nand_chip);
1182         struct resource *regs, *regs_pmerr, *regs_rom;
1183         uint16_t *galois_table;
1184         int cap, sector_size, err_no;
1185
1186         err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1187         if (err_no) {
1188                 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1189                 return err_no;
1190         }
1191
1192         if (cap > host->pmecc_corr_cap ||
1193                         sector_size != host->pmecc_sector_size)
1194                 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1195
1196         cap = host->pmecc_corr_cap;
1197         sector_size = host->pmecc_sector_size;
1198         host->pmecc_lookup_table_offset = (sector_size == 512) ?
1199                         host->pmecc_lookup_table_offset_512 :
1200                         host->pmecc_lookup_table_offset_1024;
1201
1202         dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1203                  cap, sector_size);
1204
1205         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1206         if (!regs) {
1207                 dev_warn(host->dev,
1208                         "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1209                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1210                 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1211                 return 0;
1212         }
1213
1214         host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1215         if (IS_ERR(host->ecc)) {
1216                 err_no = PTR_ERR(host->ecc);
1217                 goto err;
1218         }
1219
1220         regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1221         host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1222         if (IS_ERR(host->pmerrloc_base)) {
1223                 err_no = PTR_ERR(host->pmerrloc_base);
1224                 goto err;
1225         }
1226         host->pmerrloc_el_base = host->pmerrloc_base + ATMEL_PMERRLOC_SIGMAx +
1227                 (host->caps->pmecc_max_correction + 1) * 4;
1228
1229         if (!host->has_no_lookup_table) {
1230                 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1231                 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev,
1232                                                                 regs_rom);
1233                 if (IS_ERR(host->pmecc_rom_base)) {
1234                         dev_err(host->dev, "Can not get I/O resource for ROM, will build a lookup table in runtime!\n");
1235                         host->has_no_lookup_table = true;
1236                 }
1237         }
1238
1239         if (host->has_no_lookup_table) {
1240                 /* Build the look-up table in runtime */
1241                 galois_table = create_lookup_table(host->dev, sector_size);
1242                 if (!galois_table) {
1243                         dev_err(host->dev, "Failed to build a lookup table in runtime!\n");
1244                         err_no = -EINVAL;
1245                         goto err;
1246                 }
1247
1248                 host->pmecc_rom_base = (void __iomem *)galois_table;
1249                 host->pmecc_lookup_table_offset = 0;
1250         }
1251
1252         nand_chip->ecc.size = sector_size;
1253
1254         /* set ECC page size and oob layout */
1255         switch (mtd->writesize) {
1256         case 512:
1257         case 1024:
1258         case 2048:
1259         case 4096:
1260         case 8192:
1261                 if (sector_size > mtd->writesize) {
1262                         dev_err(host->dev, "pmecc sector size is bigger than the page size!\n");
1263                         err_no = -EINVAL;
1264                         goto err;
1265                 }
1266
1267                 host->pmecc_degree = (sector_size == 512) ?
1268                         PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1269                 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1270                 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1271                 host->pmecc_index_of = host->pmecc_rom_base +
1272                         host->pmecc_lookup_table_offset;
1273
1274                 nand_chip->ecc.strength = cap;
1275                 nand_chip->ecc.bytes = pmecc_get_ecc_bytes(cap, sector_size);
1276                 nand_chip->ecc.steps = mtd->writesize / sector_size;
1277                 nand_chip->ecc.total = nand_chip->ecc.bytes *
1278                         nand_chip->ecc.steps;
1279                 if (nand_chip->ecc.total >
1280                                 mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
1281                         dev_err(host->dev, "No room for ECC bytes\n");
1282                         err_no = -EINVAL;
1283                         goto err;
1284                 }
1285
1286                 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1287                 break;
1288         default:
1289                 dev_warn(host->dev,
1290                         "Unsupported page size for PMECC, use Software ECC\n");
1291                 /* page size not handled by HW ECC */
1292                 /* switching back to soft ECC */
1293                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1294                 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1295                 return 0;
1296         }
1297
1298         /* Allocate data for PMECC computation */
1299         err_no = pmecc_data_alloc(host);
1300         if (err_no) {
1301                 dev_err(host->dev,
1302                                 "Cannot allocate memory for PMECC computation!\n");
1303                 goto err;
1304         }
1305
1306         nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1307         nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1308         nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1309
1310         atmel_pmecc_core_init(mtd);
1311
1312         return 0;
1313
1314 err:
1315         return err_no;
1316 }
1317
1318 /*
1319  * Calculate HW ECC
1320  *
1321  * function called after a write
1322  *
1323  * mtd:        MTD block structure
1324  * dat:        raw data (unused)
1325  * ecc_code:   buffer for ECC
1326  */
1327 static int atmel_nand_calculate(struct mtd_info *mtd,
1328                 const u_char *dat, unsigned char *ecc_code)
1329 {
1330         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1331         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1332         unsigned int ecc_value;
1333
1334         /* get the first 2 ECC bytes */
1335         ecc_value = ecc_readl(host->ecc, PR);
1336
1337         ecc_code[0] = ecc_value & 0xFF;
1338         ecc_code[1] = (ecc_value >> 8) & 0xFF;
1339
1340         /* get the last 2 ECC bytes */
1341         ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1342
1343         ecc_code[2] = ecc_value & 0xFF;
1344         ecc_code[3] = (ecc_value >> 8) & 0xFF;
1345
1346         return 0;
1347 }
1348
1349 /*
1350  * HW ECC read page function
1351  *
1352  * mtd:        mtd info structure
1353  * chip:       nand chip info structure
1354  * buf:        buffer to store read data
1355  * oob_required:    caller expects OOB data read to chip->oob_poi
1356  */
1357 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1358                                 uint8_t *buf, int oob_required, int page)
1359 {
1360         int eccsize = chip->ecc.size;
1361         int eccbytes = chip->ecc.bytes;
1362         uint8_t *p = buf;
1363         uint8_t *oob = chip->oob_poi;
1364         uint8_t *ecc_pos;
1365         int stat;
1366         unsigned int max_bitflips = 0;
1367         struct mtd_oob_region oobregion = {};
1368
1369         /*
1370          * Errata: ALE is incorrectly wired up to the ECC controller
1371          * on the AP7000, so it will include the address cycles in the
1372          * ECC calculation.
1373          *
1374          * Workaround: Reset the parity registers before reading the
1375          * actual data.
1376          */
1377         struct atmel_nand_host *host = nand_get_controller_data(chip);
1378         if (host->board.need_reset_workaround)
1379                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1380
1381         /* read the page */
1382         chip->read_buf(mtd, p, eccsize);
1383
1384         /* move to ECC position if needed */
1385         mtd_ooblayout_ecc(mtd, 0, &oobregion);
1386         if (oobregion.offset != 0) {
1387                 /*
1388                  * This only works on large pages because the ECC controller
1389                  * waits for NAND_CMD_RNDOUTSTART after the NAND_CMD_RNDOUT.
1390                  * Anyway, for small pages, the first ECC byte is at offset
1391                  * 0 in the OOB area.
1392                  */
1393                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1394                               mtd->writesize + oobregion.offset, -1);
1395         }
1396
1397         /* the ECC controller needs to read the ECC just after the data */
1398         ecc_pos = oob + oobregion.offset;
1399         chip->read_buf(mtd, ecc_pos, eccbytes);
1400
1401         /* check if there's an error */
1402         stat = chip->ecc.correct(mtd, p, oob, NULL);
1403
1404         if (stat < 0) {
1405                 mtd->ecc_stats.failed++;
1406         } else {
1407                 mtd->ecc_stats.corrected += stat;
1408                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1409         }
1410
1411         /* get back to oob start (end of page) */
1412         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1413
1414         /* read the oob */
1415         chip->read_buf(mtd, oob, mtd->oobsize);
1416
1417         return max_bitflips;
1418 }
1419
1420 /*
1421  * HW ECC Correction
1422  *
1423  * function called after a read
1424  *
1425  * mtd:        MTD block structure
1426  * dat:        raw data read from the chip
1427  * read_ecc:   ECC from the chip (unused)
1428  * isnull:     unused
1429  *
1430  * Detect and correct a 1 bit error for a page
1431  */
1432 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1433                 u_char *read_ecc, u_char *isnull)
1434 {
1435         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1436         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1437         unsigned int ecc_status;
1438         unsigned int ecc_word, ecc_bit;
1439
1440         /* get the status from the Status Register */
1441         ecc_status = ecc_readl(host->ecc, SR);
1442
1443         /* if there's no error */
1444         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1445                 return 0;
1446
1447         /* get error bit offset (4 bits) */
1448         ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1449         /* get word address (12 bits) */
1450         ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1451         ecc_word >>= 4;
1452
1453         /* if there are multiple errors */
1454         if (ecc_status & ATMEL_ECC_MULERR) {
1455                 /* check if it is a freshly erased block
1456                  * (filled with 0xff) */
1457                 if ((ecc_bit == ATMEL_ECC_BITADDR)
1458                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1459                         /* the block has just been erased, return OK */
1460                         return 0;
1461                 }
1462                 /* it doesn't seems to be a freshly
1463                  * erased block.
1464                  * We can't correct so many errors */
1465                 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1466                                 " Unable to correct.\n");
1467                 return -EBADMSG;
1468         }
1469
1470         /* if there's a single bit error : we can correct it */
1471         if (ecc_status & ATMEL_ECC_ECCERR) {
1472                 /* there's nothing much to do here.
1473                  * the bit error is on the ECC itself.
1474                  */
1475                 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1476                                 " Nothing to correct\n");
1477                 return 0;
1478         }
1479
1480         dev_dbg(host->dev, "atmel_nand : one bit error on data."
1481                         " (word offset in the page :"
1482                         " 0x%x bit offset : 0x%x)\n",
1483                         ecc_word, ecc_bit);
1484         /* correct the error */
1485         if (nand_chip->options & NAND_BUSWIDTH_16) {
1486                 /* 16 bits words */
1487                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1488         } else {
1489                 /* 8 bits words */
1490                 dat[ecc_word] ^= (1 << ecc_bit);
1491         }
1492         dev_dbg(host->dev, "atmel_nand : error corrected\n");
1493         return 1;
1494 }
1495
1496 /*
1497  * Enable HW ECC : unused on most chips
1498  */
1499 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1500 {
1501         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1502         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1503
1504         if (host->board.need_reset_workaround)
1505                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1506 }
1507
1508 static int atmel_of_init_ecc(struct atmel_nand_host *host,
1509                              struct device_node *np)
1510 {
1511         u32 offset[2];
1512         u32 val;
1513
1514         host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1515
1516         /* Not using PMECC */
1517         if (!(host->nand_chip.ecc.mode == NAND_ECC_HW) || !host->has_pmecc)
1518                 return 0;
1519
1520         /* use PMECC, get correction capability, sector size and lookup
1521          * table offset.
1522          * If correction bits and sector size are not specified, then find
1523          * them from NAND ONFI parameters.
1524          */
1525         if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1526                 if (val > host->caps->pmecc_max_correction) {
1527                         dev_err(host->dev,
1528                                 "Required ECC strength too high: %u max %u\n",
1529                                 val, host->caps->pmecc_max_correction);
1530                         return -EINVAL;
1531                 }
1532                 if ((val != 2)  && (val != 4)  && (val != 8) &&
1533                     (val != 12) && (val != 24) && (val != 32)) {
1534                         dev_err(host->dev,
1535                                 "Required ECC strength not supported: %u\n",
1536                                 val);
1537                         return -EINVAL;
1538                 }
1539                 host->pmecc_corr_cap = (u8)val;
1540         }
1541
1542         if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1543                 if ((val != 512) && (val != 1024)) {
1544                         dev_err(host->dev,
1545                                 "Required ECC sector size not supported: %u\n",
1546                                 val);
1547                         return -EINVAL;
1548                 }
1549                 host->pmecc_sector_size = (u16)val;
1550         }
1551
1552         if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1553                         offset, 2) != 0) {
1554                 dev_err(host->dev, "Cannot get PMECC lookup table offset, will build a lookup table in runtime.\n");
1555                 host->has_no_lookup_table = true;
1556                 /* Will build a lookup table and initialize the offset later */
1557                 return 0;
1558         }
1559
1560         if (!offset[0] && !offset[1]) {
1561                 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1562                 return -EINVAL;
1563         }
1564
1565         host->pmecc_lookup_table_offset_512 = offset[0];
1566         host->pmecc_lookup_table_offset_1024 = offset[1];
1567
1568         return 0;
1569 }
1570
1571 static int atmel_of_init_port(struct atmel_nand_host *host,
1572                               struct device_node *np)
1573 {
1574         u32 val;
1575         struct atmel_nand_data *board = &host->board;
1576         enum of_gpio_flags flags = 0;
1577
1578         host->caps = (struct atmel_nand_caps *)
1579                 of_device_get_match_data(host->dev);
1580
1581         if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1582                 if (val >= 32) {
1583                         dev_err(host->dev, "invalid addr-offset %u\n", val);
1584                         return -EINVAL;
1585                 }
1586                 board->ale = val;
1587         }
1588
1589         if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1590                 if (val >= 32) {
1591                         dev_err(host->dev, "invalid cmd-offset %u\n", val);
1592                         return -EINVAL;
1593                 }
1594                 board->cle = val;
1595         }
1596
1597         board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1598
1599         board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1600         board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1601
1602         board->enable_pin = of_get_gpio(np, 1);
1603         board->det_pin = of_get_gpio(np, 2);
1604
1605         /* load the nfc driver if there is */
1606         of_platform_populate(np, NULL, NULL, host->dev);
1607
1608         /*
1609          * Initialize ECC mode to NAND_ECC_SOFT so that we have a correct value
1610          * even if the nand-ecc-mode property is not defined.
1611          */
1612         host->nand_chip.ecc.mode = NAND_ECC_SOFT;
1613         host->nand_chip.ecc.algo = NAND_ECC_HAMMING;
1614
1615         return 0;
1616 }
1617
1618 static int atmel_hw_nand_init_params(struct platform_device *pdev,
1619                                          struct atmel_nand_host *host)
1620 {
1621         struct nand_chip *nand_chip = &host->nand_chip;
1622         struct mtd_info *mtd = nand_to_mtd(nand_chip);
1623         struct resource         *regs;
1624
1625         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1626         if (!regs) {
1627                 dev_err(host->dev,
1628                         "Can't get I/O resource regs, use software ECC\n");
1629                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1630                 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1631                 return 0;
1632         }
1633
1634         host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1635         if (IS_ERR(host->ecc))
1636                 return PTR_ERR(host->ecc);
1637
1638         /* ECC is calculated for the whole page (1 step) */
1639         nand_chip->ecc.size = mtd->writesize;
1640
1641         /* set ECC page size and oob layout */
1642         switch (mtd->writesize) {
1643         case 512:
1644                 mtd_set_ooblayout(mtd, &atmel_ooblayout_sp_ops);
1645                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1646                 break;
1647         case 1024:
1648                 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1649                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1650                 break;
1651         case 2048:
1652                 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1653                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1654                 break;
1655         case 4096:
1656                 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1657                 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1658                 break;
1659         default:
1660                 /* page size not handled by HW ECC */
1661                 /* switching back to soft ECC */
1662                 nand_chip->ecc.mode = NAND_ECC_SOFT;
1663                 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1664                 return 0;
1665         }
1666
1667         /* set up for HW ECC */
1668         nand_chip->ecc.calculate = atmel_nand_calculate;
1669         nand_chip->ecc.correct = atmel_nand_correct;
1670         nand_chip->ecc.hwctl = atmel_nand_hwctl;
1671         nand_chip->ecc.read_page = atmel_nand_read_page;
1672         nand_chip->ecc.bytes = 4;
1673         nand_chip->ecc.strength = 1;
1674
1675         return 0;
1676 }
1677
1678 static inline u32 nfc_read_status(struct atmel_nand_host *host)
1679 {
1680         u32 err_flags = NFC_SR_DTOE | NFC_SR_UNDEF | NFC_SR_AWB | NFC_SR_ASE;
1681         u32 nfc_status = nfc_readl(host->nfc->hsmc_regs, SR);
1682
1683         if (unlikely(nfc_status & err_flags)) {
1684                 if (nfc_status & NFC_SR_DTOE)
1685                         dev_err(host->dev, "NFC: Waiting Nand R/B Timeout Error\n");
1686                 else if (nfc_status & NFC_SR_UNDEF)
1687                         dev_err(host->dev, "NFC: Access Undefined Area Error\n");
1688                 else if (nfc_status & NFC_SR_AWB)
1689                         dev_err(host->dev, "NFC: Access memory While NFC is busy\n");
1690                 else if (nfc_status & NFC_SR_ASE)
1691                         dev_err(host->dev, "NFC: Access memory Size Error\n");
1692         }
1693
1694         return nfc_status;
1695 }
1696
1697 /* SMC interrupt service routine */
1698 static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1699 {
1700         struct atmel_nand_host *host = dev_id;
1701         u32 status, mask, pending;
1702         irqreturn_t ret = IRQ_NONE;
1703
1704         status = nfc_read_status(host);
1705         mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1706         pending = status & mask;
1707
1708         if (pending & NFC_SR_XFR_DONE) {
1709                 complete(&host->nfc->comp_xfer_done);
1710                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1711                 ret = IRQ_HANDLED;
1712         }
1713         if (pending & NFC_SR_RB_EDGE) {
1714                 complete(&host->nfc->comp_ready);
1715                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1716                 ret = IRQ_HANDLED;
1717         }
1718         if (pending & NFC_SR_CMD_DONE) {
1719                 complete(&host->nfc->comp_cmd_done);
1720                 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1721                 ret = IRQ_HANDLED;
1722         }
1723
1724         return ret;
1725 }
1726
1727 /* NFC(Nand Flash Controller) related functions */
1728 static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
1729 {
1730         if (flag & NFC_SR_XFR_DONE)
1731                 init_completion(&host->nfc->comp_xfer_done);
1732
1733         if (flag & NFC_SR_RB_EDGE)
1734                 init_completion(&host->nfc->comp_ready);
1735
1736         if (flag & NFC_SR_CMD_DONE)
1737                 init_completion(&host->nfc->comp_cmd_done);
1738
1739         /* Enable interrupt that need to wait for */
1740         nfc_writel(host->nfc->hsmc_regs, IER, flag);
1741 }
1742
1743 static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1744 {
1745         int i, index = 0;
1746         struct completion *comp[3];     /* Support 3 interrupt completion */
1747
1748         if (flag & NFC_SR_XFR_DONE)
1749                 comp[index++] = &host->nfc->comp_xfer_done;
1750
1751         if (flag & NFC_SR_RB_EDGE)
1752                 comp[index++] = &host->nfc->comp_ready;
1753
1754         if (flag & NFC_SR_CMD_DONE)
1755                 comp[index++] = &host->nfc->comp_cmd_done;
1756
1757         if (index == 0) {
1758                 dev_err(host->dev, "Unknown interrupt flag: 0x%08x\n", flag);
1759                 return -EINVAL;
1760         }
1761
1762         for (i = 0; i < index; i++) {
1763                 if (wait_for_completion_timeout(comp[i],
1764                                 msecs_to_jiffies(NFC_TIME_OUT_MS)))
1765                         continue;       /* wait for next completion */
1766                 else
1767                         goto err_timeout;
1768         }
1769
1770         return 0;
1771
1772 err_timeout:
1773         dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1774         /* Disable the interrupt as it is not handled by interrupt handler */
1775         nfc_writel(host->nfc->hsmc_regs, IDR, flag);
1776         return -ETIMEDOUT;
1777 }
1778
1779 static int nfc_send_command(struct atmel_nand_host *host,
1780         unsigned int cmd, unsigned int addr, unsigned char cycle0)
1781 {
1782         unsigned long timeout;
1783         u32 flag = NFC_SR_CMD_DONE;
1784         flag |= cmd & NFCADDR_CMD_DATAEN ? NFC_SR_XFR_DONE : 0;
1785
1786         dev_dbg(host->dev,
1787                 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1788                 cmd, addr, cycle0);
1789
1790         timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1791         while (nfc_readl(host->nfc->hsmc_regs, SR) & NFC_SR_BUSY) {
1792                 if (time_after(jiffies, timeout)) {
1793                         dev_err(host->dev,
1794                                 "Time out to wait for NFC ready!\n");
1795                         return -ETIMEDOUT;
1796                 }
1797         }
1798
1799         nfc_prepare_interrupt(host, flag);
1800         nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1801         nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1802         return nfc_wait_interrupt(host, flag);
1803 }
1804
1805 static int nfc_device_ready(struct mtd_info *mtd)
1806 {
1807         u32 status, mask;
1808         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1809         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1810
1811         status = nfc_read_status(host);
1812         mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1813
1814         /* The mask should be 0. If not we may lost interrupts */
1815         if (unlikely(mask & status))
1816                 dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
1817                                 mask & status);
1818
1819         return status & NFC_SR_RB_EDGE;
1820 }
1821
1822 static void nfc_select_chip(struct mtd_info *mtd, int chip)
1823 {
1824         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1825         struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1826
1827         if (chip == -1)
1828                 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1829         else
1830                 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1831 }
1832
1833 static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
1834                 int page_addr, unsigned int *addr1234, unsigned int *cycle0)
1835 {
1836         struct nand_chip *chip = mtd_to_nand(mtd);
1837
1838         int acycle = 0;
1839         unsigned char addr_bytes[8];
1840         int index = 0, bit_shift;
1841
1842         BUG_ON(addr1234 == NULL || cycle0 == NULL);
1843
1844         *cycle0 = 0;
1845         *addr1234 = 0;
1846
1847         if (column != -1) {
1848                 if (chip->options & NAND_BUSWIDTH_16 &&
1849                                 !nand_opcode_8bits(command))
1850                         column >>= 1;
1851                 addr_bytes[acycle++] = column & 0xff;
1852                 if (mtd->writesize > 512)
1853                         addr_bytes[acycle++] = (column >> 8) & 0xff;
1854         }
1855
1856         if (page_addr != -1) {
1857                 addr_bytes[acycle++] = page_addr & 0xff;
1858                 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1859                 if (chip->chipsize > (128 << 20))
1860                         addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1861         }
1862
1863         if (acycle > 4)
1864                 *cycle0 = addr_bytes[index++];
1865
1866         for (bit_shift = 0; index < acycle; bit_shift += 8)
1867                 *addr1234 += addr_bytes[index++] << bit_shift;
1868
1869         /* return acycle in cmd register */
1870         return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1871 }
1872
1873 static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1874                                 int column, int page_addr)
1875 {
1876         struct nand_chip *chip = mtd_to_nand(mtd);
1877         struct atmel_nand_host *host = nand_get_controller_data(chip);
1878         unsigned long timeout;
1879         unsigned int nfc_addr_cmd = 0;
1880
1881         unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1882
1883         /* Set default settings: no cmd2, no addr cycle. read from nand */
1884         unsigned int cmd2 = 0;
1885         unsigned int vcmd2 = 0;
1886         int acycle = NFCADDR_CMD_ACYCLE_NONE;
1887         int csid = NFCADDR_CMD_CSID_3;
1888         int dataen = NFCADDR_CMD_DATADIS;
1889         int nfcwr = NFCADDR_CMD_NFCRD;
1890         unsigned int addr1234 = 0;
1891         unsigned int cycle0 = 0;
1892         bool do_addr = true;
1893         host->nfc->data_in_sram = NULL;
1894
1895         dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1896              __func__, command, column, page_addr);
1897
1898         switch (command) {
1899         case NAND_CMD_RESET:
1900                 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1901                 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1902                 udelay(chip->chip_delay);
1903
1904                 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1905                 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1906                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1907                         if (time_after(jiffies, timeout)) {
1908                                 dev_err(host->dev,
1909                                         "Time out to wait status ready!\n");
1910                                 break;
1911                         }
1912                 }
1913                 return;
1914         case NAND_CMD_STATUS:
1915                 do_addr = false;
1916                 break;
1917         case NAND_CMD_PARAM:
1918         case NAND_CMD_READID:
1919                 do_addr = false;
1920                 acycle = NFCADDR_CMD_ACYCLE_1;
1921                 if (column != -1)
1922                         addr1234 = column;
1923                 break;
1924         case NAND_CMD_RNDOUT:
1925                 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1926                 vcmd2 = NFCADDR_CMD_VCMD2;
1927                 break;
1928         case NAND_CMD_READ0:
1929         case NAND_CMD_READOOB:
1930                 if (command == NAND_CMD_READOOB) {
1931                         column += mtd->writesize;
1932                         command = NAND_CMD_READ0; /* only READ0 is valid */
1933                         cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1934                 }
1935                 if (host->nfc->use_nfc_sram) {
1936                         /* Enable Data transfer to sram */
1937                         dataen = NFCADDR_CMD_DATAEN;
1938
1939                         /* Need enable PMECC now, since NFC will transfer
1940                          * data in bus after sending nfc read command.
1941                          */
1942                         if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1943                                 pmecc_enable(host, NAND_ECC_READ);
1944                 }
1945
1946                 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1947                 vcmd2 = NFCADDR_CMD_VCMD2;
1948                 break;
1949         /* For prgramming command, the cmd need set to write enable */
1950         case NAND_CMD_PAGEPROG:
1951         case NAND_CMD_SEQIN:
1952         case NAND_CMD_RNDIN:
1953                 nfcwr = NFCADDR_CMD_NFCWR;
1954                 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1955                         dataen = NFCADDR_CMD_DATAEN;
1956                 break;
1957         default:
1958                 break;
1959         }
1960
1961         if (do_addr)
1962                 acycle = nfc_make_addr(mtd, command, column, page_addr,
1963                                 &addr1234, &cycle0);
1964
1965         nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1966         nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1967
1968         /*
1969          * Program and erase have their own busy handlers status, sequential
1970          * in, and deplete1 need no delay.
1971          */
1972         switch (command) {
1973         case NAND_CMD_CACHEDPROG:
1974         case NAND_CMD_PAGEPROG:
1975         case NAND_CMD_ERASE1:
1976         case NAND_CMD_ERASE2:
1977         case NAND_CMD_RNDIN:
1978         case NAND_CMD_STATUS:
1979         case NAND_CMD_RNDOUT:
1980         case NAND_CMD_SEQIN:
1981         case NAND_CMD_READID:
1982                 return;
1983
1984         case NAND_CMD_READ0:
1985                 if (dataen == NFCADDR_CMD_DATAEN) {
1986                         host->nfc->data_in_sram = host->nfc->sram_bank0 +
1987                                 nfc_get_sram_off(host);
1988                         return;
1989                 }
1990                 /* fall through */
1991         default:
1992                 nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
1993                 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1994         }
1995 }
1996
1997 static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1998                         uint32_t offset, int data_len, const uint8_t *buf,
1999                         int oob_required, int page, int cached, int raw)
2000 {
2001         int cfg, len;
2002         int status = 0;
2003         struct atmel_nand_host *host = nand_get_controller_data(chip);
2004         void *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
2005
2006         /* Subpage write is not supported */
2007         if (offset || (data_len < mtd->writesize))
2008                 return -EINVAL;
2009
2010         len = mtd->writesize;
2011         /* Copy page data to sram that will write to nand via NFC */
2012         if (use_dma) {
2013                 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
2014                         /* Fall back to use cpu copy */
2015                         memcpy(sram, buf, len);
2016         } else {
2017                 memcpy(sram, buf, len);
2018         }
2019
2020         cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
2021         if (unlikely(raw) && oob_required) {
2022                 memcpy(sram + len, chip->oob_poi, mtd->oobsize);
2023                 len += mtd->oobsize;
2024                 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
2025         } else {
2026                 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
2027         }
2028
2029         if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
2030                 /*
2031                  * When use NFC sram, need set up PMECC before send
2032                  * NAND_CMD_SEQIN command. Since when the nand command
2033                  * is sent, nfc will do transfer from sram and nand.
2034                  */
2035                 pmecc_enable(host, NAND_ECC_WRITE);
2036
2037         host->nfc->will_write_sram = true;
2038         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2039         host->nfc->will_write_sram = false;
2040
2041         if (likely(!raw))
2042                 /* Need to write ecc into oob */
2043                 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2044                                               page);
2045
2046         if (status < 0)
2047                 return status;
2048
2049         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2050         status = chip->waitfunc(mtd, chip);
2051
2052         if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2053                 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
2054
2055         if (status & NAND_STATUS_FAIL)
2056                 return -EIO;
2057
2058         return 0;
2059 }
2060
2061 static int nfc_sram_init(struct mtd_info *mtd)
2062 {
2063         struct nand_chip *chip = mtd_to_nand(mtd);
2064         struct atmel_nand_host *host = nand_get_controller_data(chip);
2065         int res = 0;
2066
2067         /* Initialize the NFC CFG register */
2068         unsigned int cfg_nfc = 0;
2069
2070         /* set page size and oob layout */
2071         switch (mtd->writesize) {
2072         case 512:
2073                 cfg_nfc = NFC_CFG_PAGESIZE_512;
2074                 break;
2075         case 1024:
2076                 cfg_nfc = NFC_CFG_PAGESIZE_1024;
2077                 break;
2078         case 2048:
2079                 cfg_nfc = NFC_CFG_PAGESIZE_2048;
2080                 break;
2081         case 4096:
2082                 cfg_nfc = NFC_CFG_PAGESIZE_4096;
2083                 break;
2084         case 8192:
2085                 cfg_nfc = NFC_CFG_PAGESIZE_8192;
2086                 break;
2087         default:
2088                 dev_err(host->dev, "Unsupported page size for NFC.\n");
2089                 res = -ENXIO;
2090                 return res;
2091         }
2092
2093         /* oob bytes size = (NFCSPARESIZE + 1) * 4
2094          * Max support spare size is 512 bytes. */
2095         cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
2096                 & NFC_CFG_NFC_SPARESIZE);
2097         /* default set a max timeout */
2098         cfg_nfc |= NFC_CFG_RSPARE |
2099                         NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
2100
2101         nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
2102
2103         host->nfc->will_write_sram = false;
2104         nfc_set_sram_bank(host, 0);
2105
2106         /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
2107         if (host->nfc->write_by_sram) {
2108                 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
2109                                 chip->ecc.mode == NAND_ECC_NONE)
2110                         chip->write_page = nfc_sram_write_page;
2111                 else
2112                         host->nfc->write_by_sram = false;
2113         }
2114
2115         dev_info(host->dev, "Using NFC Sram read %s\n",
2116                         host->nfc->write_by_sram ? "and write" : "");
2117         return 0;
2118 }
2119
2120 static struct platform_driver atmel_nand_nfc_driver;
2121 /*
2122  * Probe for the NAND device.
2123  */
2124 static int atmel_nand_probe(struct platform_device *pdev)
2125 {
2126         struct atmel_nand_host *host;
2127         struct mtd_info *mtd;
2128         struct nand_chip *nand_chip;
2129         struct resource *mem;
2130         int res, irq;
2131
2132         /* Allocate memory for the device structure (and zero it) */
2133         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2134         if (!host)
2135                 return -ENOMEM;
2136
2137         res = platform_driver_register(&atmel_nand_nfc_driver);
2138         if (res)
2139                 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
2140
2141         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2142         host->io_base = devm_ioremap_resource(&pdev->dev, mem);
2143         if (IS_ERR(host->io_base)) {
2144                 res = PTR_ERR(host->io_base);
2145                 goto err_nand_ioremap;
2146         }
2147         host->io_phys = (dma_addr_t)mem->start;
2148
2149         nand_chip = &host->nand_chip;
2150         mtd = nand_to_mtd(nand_chip);
2151         host->dev = &pdev->dev;
2152         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2153                 nand_set_flash_node(nand_chip, pdev->dev.of_node);
2154                 /* Only when CONFIG_OF is enabled of_node can be parsed */
2155                 res = atmel_of_init_port(host, pdev->dev.of_node);
2156                 if (res)
2157                         goto err_nand_ioremap;
2158         } else {
2159                 memcpy(&host->board, dev_get_platdata(&pdev->dev),
2160                        sizeof(struct atmel_nand_data));
2161                 nand_chip->ecc.mode = host->board.ecc_mode;
2162
2163                 /*
2164                  * When using software ECC every supported avr32 board means
2165                  * Hamming algorithm. If that ever changes we'll need to add
2166                  * ecc_algo field to the struct atmel_nand_data.
2167                  */
2168                 if (nand_chip->ecc.mode == NAND_ECC_SOFT)
2169                         nand_chip->ecc.algo = NAND_ECC_HAMMING;
2170
2171                 /* 16-bit bus width */
2172                 if (host->board.bus_width_16)
2173                         nand_chip->options |= NAND_BUSWIDTH_16;
2174         }
2175
2176          /* link the private data structures */
2177         nand_set_controller_data(nand_chip, host);
2178         mtd->dev.parent = &pdev->dev;
2179
2180         /* Set address of NAND IO lines */
2181         nand_chip->IO_ADDR_R = host->io_base;
2182         nand_chip->IO_ADDR_W = host->io_base;
2183
2184         if (nand_nfc.is_initialized) {
2185                 /* NFC driver is probed and initialized */
2186                 host->nfc = &nand_nfc;
2187
2188                 nand_chip->select_chip = nfc_select_chip;
2189                 nand_chip->dev_ready = nfc_device_ready;
2190                 nand_chip->cmdfunc = nfc_nand_command;
2191
2192                 /* Initialize the interrupt for NFC */
2193                 irq = platform_get_irq(pdev, 0);
2194                 if (irq < 0) {
2195                         dev_err(host->dev, "Cannot get HSMC irq!\n");
2196                         res = irq;
2197                         goto err_nand_ioremap;
2198                 }
2199
2200                 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2201                                 0, "hsmc", host);
2202                 if (res) {
2203                         dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2204                                 irq);
2205                         goto err_nand_ioremap;
2206                 }
2207         } else {
2208                 res = atmel_nand_set_enable_ready_pins(mtd);
2209                 if (res)
2210                         goto err_nand_ioremap;
2211
2212                 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2213         }
2214
2215         nand_chip->chip_delay = 40;             /* 40us command delay time */
2216
2217
2218         nand_chip->read_buf = atmel_read_buf;
2219         nand_chip->write_buf = atmel_write_buf;
2220
2221         platform_set_drvdata(pdev, host);
2222         atmel_nand_enable(host);
2223
2224         if (gpio_is_valid(host->board.det_pin)) {
2225                 res = devm_gpio_request(&pdev->dev,
2226                                 host->board.det_pin, "nand_det");
2227                 if (res < 0) {
2228                         dev_err(&pdev->dev,
2229                                 "can't request det gpio %d\n",
2230                                 host->board.det_pin);
2231                         goto err_no_card;
2232                 }
2233
2234                 res = gpio_direction_input(host->board.det_pin);
2235                 if (res < 0) {
2236                         dev_err(&pdev->dev,
2237                                 "can't request input direction det gpio %d\n",
2238                                 host->board.det_pin);
2239                         goto err_no_card;
2240                 }
2241
2242                 if (gpio_get_value(host->board.det_pin)) {
2243                         dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
2244                         res = -ENXIO;
2245                         goto err_no_card;
2246                 }
2247         }
2248
2249         if (!host->board.has_dma)
2250                 use_dma = 0;
2251
2252         if (use_dma) {
2253                 dma_cap_mask_t mask;
2254
2255                 dma_cap_zero(mask);
2256                 dma_cap_set(DMA_MEMCPY, mask);
2257                 host->dma_chan = dma_request_channel(mask, NULL, NULL);
2258                 if (!host->dma_chan) {
2259                         dev_err(host->dev, "Failed to request DMA channel\n");
2260                         use_dma = 0;
2261                 }
2262         }
2263         if (use_dma)
2264                 dev_info(host->dev, "Using %s for DMA transfers.\n",
2265                                         dma_chan_name(host->dma_chan));
2266         else
2267                 dev_info(host->dev, "No DMA support for NAND access.\n");
2268
2269         /* first scan to find the device and get the page size */
2270         if (nand_scan_ident(mtd, 1, NULL)) {
2271                 res = -ENXIO;
2272                 goto err_scan_ident;
2273         }
2274
2275         if (host->board.on_flash_bbt || on_flash_bbt)
2276                 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2277
2278         if (nand_chip->bbt_options & NAND_BBT_USE_FLASH)
2279                 dev_info(&pdev->dev, "Use On Flash BBT\n");
2280
2281         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2282                 res = atmel_of_init_ecc(host, pdev->dev.of_node);
2283                 if (res)
2284                         goto err_hw_ecc;
2285         }
2286
2287         if (nand_chip->ecc.mode == NAND_ECC_HW) {
2288                 if (host->has_pmecc)
2289                         res = atmel_pmecc_nand_init_params(pdev, host);
2290                 else
2291                         res = atmel_hw_nand_init_params(pdev, host);
2292
2293                 if (res != 0)
2294                         goto err_hw_ecc;
2295         }
2296
2297         /* initialize the nfc configuration register */
2298         if (host->nfc && host->nfc->use_nfc_sram) {
2299                 res = nfc_sram_init(mtd);
2300                 if (res) {
2301                         host->nfc->use_nfc_sram = false;
2302                         dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2303                 }
2304         }
2305
2306         /* second phase scan */
2307         if (nand_scan_tail(mtd)) {
2308                 res = -ENXIO;
2309                 goto err_scan_tail;
2310         }
2311
2312         mtd->name = "atmel_nand";
2313         res = mtd_device_register(mtd, host->board.parts,
2314                                   host->board.num_parts);
2315         if (!res)
2316                 return res;
2317
2318 err_scan_tail:
2319         if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2320                 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2321 err_hw_ecc:
2322 err_scan_ident:
2323 err_no_card:
2324         atmel_nand_disable(host);
2325         if (host->dma_chan)
2326                 dma_release_channel(host->dma_chan);
2327 err_nand_ioremap:
2328         return res;
2329 }
2330
2331 /*
2332  * Remove a NAND device.
2333  */
2334 static int atmel_nand_remove(struct platform_device *pdev)
2335 {
2336         struct atmel_nand_host *host = platform_get_drvdata(pdev);
2337
2338         nand_release(&host->nand_chip);
2339
2340         atmel_nand_disable(host);
2341
2342         if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2343                 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2344                 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2345                                 PMERRLOC_DISABLE);
2346         }
2347
2348         if (host->dma_chan)
2349                 dma_release_channel(host->dma_chan);
2350
2351         platform_driver_unregister(&atmel_nand_nfc_driver);
2352
2353         return 0;
2354 }
2355
2356 /*
2357  * AT91RM9200 does not have PMECC or PMECC Errloc peripherals for
2358  * BCH ECC. Combined with the "atmel,has-pmecc", it is used to describe
2359  * devices from the SAM9 family that have those.
2360  */
2361 static const struct atmel_nand_caps at91rm9200_caps = {
2362         .pmecc_correct_erase_page = false,
2363         .pmecc_max_correction = 24,
2364 };
2365
2366 static const struct atmel_nand_caps sama5d4_caps = {
2367         .pmecc_correct_erase_page = true,
2368         .pmecc_max_correction = 24,
2369 };
2370
2371 /*
2372  * The PMECC Errloc controller starting in SAMA5D2 is not compatible,
2373  * as the increased correction strength requires more registers.
2374  */
2375 static const struct atmel_nand_caps sama5d2_caps = {
2376         .pmecc_correct_erase_page = true,
2377         .pmecc_max_correction = 32,
2378 };
2379
2380 static const struct of_device_id atmel_nand_dt_ids[] = {
2381         { .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
2382         { .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
2383         { .compatible = "atmel,sama5d2-nand", .data = &sama5d2_caps },
2384         { /* sentinel */ }
2385 };
2386
2387 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2388
2389 static int atmel_nand_nfc_probe(struct platform_device *pdev)
2390 {
2391         struct atmel_nfc *nfc = &nand_nfc;
2392         struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2393         int ret;
2394
2395         nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2396         nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2397         if (IS_ERR(nfc->base_cmd_regs))
2398                 return PTR_ERR(nfc->base_cmd_regs);
2399
2400         nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2401         nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2402         if (IS_ERR(nfc->hsmc_regs))
2403                 return PTR_ERR(nfc->hsmc_regs);
2404
2405         nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2406         if (nfc_sram) {
2407                 nfc->sram_bank0 = (void * __force)
2408                                 devm_ioremap_resource(&pdev->dev, nfc_sram);
2409                 if (IS_ERR(nfc->sram_bank0)) {
2410                         dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2411                                         PTR_ERR(nfc->sram_bank0));
2412                 } else {
2413                         nfc->use_nfc_sram = true;
2414                         nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2415
2416                         if (pdev->dev.of_node)
2417                                 nfc->write_by_sram = of_property_read_bool(
2418                                                 pdev->dev.of_node,
2419                                                 "atmel,write-by-sram");
2420                 }
2421         }
2422
2423         nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
2424         nfc_readl(nfc->hsmc_regs, SR);  /* clear the NFC_SR */
2425
2426         nfc->clk = devm_clk_get(&pdev->dev, NULL);
2427         if (!IS_ERR(nfc->clk)) {
2428                 ret = clk_prepare_enable(nfc->clk);
2429                 if (ret)
2430                         return ret;
2431         } else {
2432                 dev_warn(&pdev->dev, "NFC clock missing, update your Device Tree");
2433         }
2434
2435         nfc->is_initialized = true;
2436         dev_info(&pdev->dev, "NFC is probed.\n");
2437
2438         return 0;
2439 }
2440
2441 static int atmel_nand_nfc_remove(struct platform_device *pdev)
2442 {
2443         struct atmel_nfc *nfc = &nand_nfc;
2444
2445         if (!IS_ERR(nfc->clk))
2446                 clk_disable_unprepare(nfc->clk);
2447
2448         return 0;
2449 }
2450
2451 static const struct of_device_id atmel_nand_nfc_match[] = {
2452         { .compatible = "atmel,sama5d3-nfc" },
2453         { /* sentinel */ }
2454 };
2455 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
2456
2457 static struct platform_driver atmel_nand_nfc_driver = {
2458         .driver = {
2459                 .name = "atmel_nand_nfc",
2460                 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2461         },
2462         .probe = atmel_nand_nfc_probe,
2463         .remove = atmel_nand_nfc_remove,
2464 };
2465
2466 static struct platform_driver atmel_nand_driver = {
2467         .probe          = atmel_nand_probe,
2468         .remove         = atmel_nand_remove,
2469         .driver         = {
2470                 .name   = "atmel_nand",
2471                 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
2472         },
2473 };
2474
2475 module_platform_driver(atmel_nand_driver);
2476
2477 MODULE_LICENSE("GPL");
2478 MODULE_AUTHOR("Rick Bronson");
2479 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2480 MODULE_ALIAS("platform:atmel_nand");