2 * Copyright © 2010-2015 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/version.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/err.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/spinlock.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/ioport.h>
27 #include <linux/bug.h>
28 #include <linux/kernel.h>
29 #include <linux/bitops.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/rawnand.h>
33 #include <linux/mtd/partitions.h>
35 #include <linux/of_platform.h>
36 #include <linux/slab.h>
37 #include <linux/list.h>
38 #include <linux/log2.h>
43 * This flag controls if WP stays on between erase/write commands to mitigate
44 * flash corruption due to power glitches. Values:
45 * 0: NAND_WP is not used or not available
46 * 1: NAND_WP is set by default, cleared for erase/write operations
47 * 2: NAND_WP is always cleared
50 module_param(wp_on, int, 0444);
52 /***********************************************************************
54 ***********************************************************************/
56 #define DRV_NAME "brcmnand"
59 #define CMD_PAGE_READ 0x01
60 #define CMD_SPARE_AREA_READ 0x02
61 #define CMD_STATUS_READ 0x03
62 #define CMD_PROGRAM_PAGE 0x04
63 #define CMD_PROGRAM_SPARE_AREA 0x05
64 #define CMD_COPY_BACK 0x06
65 #define CMD_DEVICE_ID_READ 0x07
66 #define CMD_BLOCK_ERASE 0x08
67 #define CMD_FLASH_RESET 0x09
68 #define CMD_BLOCKS_LOCK 0x0a
69 #define CMD_BLOCKS_LOCK_DOWN 0x0b
70 #define CMD_BLOCKS_UNLOCK 0x0c
71 #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
72 #define CMD_PARAMETER_READ 0x0e
73 #define CMD_PARAMETER_CHANGE_COL 0x0f
74 #define CMD_LOW_LEVEL_OP 0x10
76 struct brcm_nand_dma_desc {
91 /* Bitfields for brcm_nand_dma_desc::status_valid */
92 #define FLASH_DMA_ECC_ERROR (1 << 8)
93 #define FLASH_DMA_CORR_ERROR (1 << 9)
95 /* 512B flash cache in the NAND controller HW */
98 #define FC_WORDS (FC_BYTES >> 2)
100 #define BRCMNAND_MIN_PAGESIZE 512
101 #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
102 #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
104 #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY)
105 #define NAND_POLL_STATUS_TIMEOUT_MS 100
107 /* Controller feature flags */
109 BRCMNAND_HAS_1K_SECTORS = BIT(0),
110 BRCMNAND_HAS_PREFETCH = BIT(1),
111 BRCMNAND_HAS_CACHE_MODE = BIT(2),
112 BRCMNAND_HAS_WP = BIT(3),
115 struct brcmnand_controller {
117 struct nand_controller controller;
118 void __iomem *nand_base;
119 void __iomem *nand_fc; /* flash cache */
120 void __iomem *flash_dma_base;
122 unsigned int dma_irq;
125 /* Some SoCs provide custom interrupt status register(s) */
126 struct brcmnand_soc *soc;
128 /* Some SoCs have a gateable clock for the controller */
133 struct completion done;
134 struct completion dma_done;
136 /* List of NAND hosts (one for each chip-select) */
137 struct list_head host_list;
139 struct brcm_nand_dma_desc *dma_desc;
142 /* in-memory cache of the FLASH_CACHE, used only for some commands */
143 u8 flash_cache[FC_BYTES];
145 /* Controller revision details */
146 const u16 *reg_offsets;
147 unsigned int reg_spacing; /* between CS1, CS2, ... regs */
148 const u8 *cs_offsets; /* within each chip-select */
149 const u8 *cs0_offsets; /* within CS0, if different */
150 unsigned int max_block_size;
151 const unsigned int *block_sizes;
152 unsigned int max_page_size;
153 const unsigned int *page_sizes;
154 unsigned int max_oob;
157 /* for low-power standby/resume only */
158 u32 nand_cs_nand_select;
159 u32 nand_cs_nand_xor;
160 u32 corr_stat_threshold;
164 struct brcmnand_cfg {
166 unsigned int block_size;
167 unsigned int page_size;
168 unsigned int spare_area_size;
169 unsigned int device_width;
170 unsigned int col_adr_bytes;
171 unsigned int blk_adr_bytes;
172 unsigned int ful_adr_bytes;
173 unsigned int sector_size_1k;
174 unsigned int ecc_level;
175 /* use for low-power standby/resume only */
183 struct brcmnand_host {
184 struct list_head node;
186 struct nand_chip chip;
187 struct platform_device *pdev;
190 unsigned int last_cmd;
191 unsigned int last_byte;
193 struct brcmnand_cfg hwcfg;
194 struct brcmnand_controller *ctrl;
198 BRCMNAND_CMD_START = 0,
199 BRCMNAND_CMD_EXT_ADDRESS,
200 BRCMNAND_CMD_ADDRESS,
201 BRCMNAND_INTFC_STATUS,
206 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
207 BRCMNAND_CORR_THRESHOLD,
208 BRCMNAND_CORR_THRESHOLD_EXT,
209 BRCMNAND_UNCORR_COUNT,
211 BRCMNAND_CORR_EXT_ADDR,
213 BRCMNAND_UNCORR_EXT_ADDR,
214 BRCMNAND_UNCORR_ADDR,
219 BRCMNAND_OOB_READ_BASE,
220 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
221 BRCMNAND_OOB_WRITE_BASE,
222 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
227 static const u16 brcmnand_regs_v40[] = {
228 [BRCMNAND_CMD_START] = 0x04,
229 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
230 [BRCMNAND_CMD_ADDRESS] = 0x0c,
231 [BRCMNAND_INTFC_STATUS] = 0x6c,
232 [BRCMNAND_CS_SELECT] = 0x14,
233 [BRCMNAND_CS_XOR] = 0x18,
234 [BRCMNAND_LL_OP] = 0x178,
235 [BRCMNAND_CS0_BASE] = 0x40,
236 [BRCMNAND_CS1_BASE] = 0xd0,
237 [BRCMNAND_CORR_THRESHOLD] = 0x84,
238 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
239 [BRCMNAND_UNCORR_COUNT] = 0,
240 [BRCMNAND_CORR_COUNT] = 0,
241 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
242 [BRCMNAND_CORR_ADDR] = 0x74,
243 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
244 [BRCMNAND_UNCORR_ADDR] = 0x7c,
245 [BRCMNAND_SEMAPHORE] = 0x58,
246 [BRCMNAND_ID] = 0x60,
247 [BRCMNAND_ID_EXT] = 0x64,
248 [BRCMNAND_LL_RDATA] = 0x17c,
249 [BRCMNAND_OOB_READ_BASE] = 0x20,
250 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
251 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
252 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
253 [BRCMNAND_FC_BASE] = 0x200,
257 static const u16 brcmnand_regs_v50[] = {
258 [BRCMNAND_CMD_START] = 0x04,
259 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
260 [BRCMNAND_CMD_ADDRESS] = 0x0c,
261 [BRCMNAND_INTFC_STATUS] = 0x6c,
262 [BRCMNAND_CS_SELECT] = 0x14,
263 [BRCMNAND_CS_XOR] = 0x18,
264 [BRCMNAND_LL_OP] = 0x178,
265 [BRCMNAND_CS0_BASE] = 0x40,
266 [BRCMNAND_CS1_BASE] = 0xd0,
267 [BRCMNAND_CORR_THRESHOLD] = 0x84,
268 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
269 [BRCMNAND_UNCORR_COUNT] = 0,
270 [BRCMNAND_CORR_COUNT] = 0,
271 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
272 [BRCMNAND_CORR_ADDR] = 0x74,
273 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
274 [BRCMNAND_UNCORR_ADDR] = 0x7c,
275 [BRCMNAND_SEMAPHORE] = 0x58,
276 [BRCMNAND_ID] = 0x60,
277 [BRCMNAND_ID_EXT] = 0x64,
278 [BRCMNAND_LL_RDATA] = 0x17c,
279 [BRCMNAND_OOB_READ_BASE] = 0x20,
280 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
281 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
282 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
283 [BRCMNAND_FC_BASE] = 0x200,
286 /* BRCMNAND v6.0 - v7.1 */
287 static const u16 brcmnand_regs_v60[] = {
288 [BRCMNAND_CMD_START] = 0x04,
289 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
290 [BRCMNAND_CMD_ADDRESS] = 0x0c,
291 [BRCMNAND_INTFC_STATUS] = 0x14,
292 [BRCMNAND_CS_SELECT] = 0x18,
293 [BRCMNAND_CS_XOR] = 0x1c,
294 [BRCMNAND_LL_OP] = 0x20,
295 [BRCMNAND_CS0_BASE] = 0x50,
296 [BRCMNAND_CS1_BASE] = 0,
297 [BRCMNAND_CORR_THRESHOLD] = 0xc0,
298 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
299 [BRCMNAND_UNCORR_COUNT] = 0xfc,
300 [BRCMNAND_CORR_COUNT] = 0x100,
301 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
302 [BRCMNAND_CORR_ADDR] = 0x110,
303 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
304 [BRCMNAND_UNCORR_ADDR] = 0x118,
305 [BRCMNAND_SEMAPHORE] = 0x150,
306 [BRCMNAND_ID] = 0x194,
307 [BRCMNAND_ID_EXT] = 0x198,
308 [BRCMNAND_LL_RDATA] = 0x19c,
309 [BRCMNAND_OOB_READ_BASE] = 0x200,
310 [BRCMNAND_OOB_READ_10_BASE] = 0,
311 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
312 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
313 [BRCMNAND_FC_BASE] = 0x400,
317 static const u16 brcmnand_regs_v71[] = {
318 [BRCMNAND_CMD_START] = 0x04,
319 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
320 [BRCMNAND_CMD_ADDRESS] = 0x0c,
321 [BRCMNAND_INTFC_STATUS] = 0x14,
322 [BRCMNAND_CS_SELECT] = 0x18,
323 [BRCMNAND_CS_XOR] = 0x1c,
324 [BRCMNAND_LL_OP] = 0x20,
325 [BRCMNAND_CS0_BASE] = 0x50,
326 [BRCMNAND_CS1_BASE] = 0,
327 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
328 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
329 [BRCMNAND_UNCORR_COUNT] = 0xfc,
330 [BRCMNAND_CORR_COUNT] = 0x100,
331 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
332 [BRCMNAND_CORR_ADDR] = 0x110,
333 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
334 [BRCMNAND_UNCORR_ADDR] = 0x118,
335 [BRCMNAND_SEMAPHORE] = 0x150,
336 [BRCMNAND_ID] = 0x194,
337 [BRCMNAND_ID_EXT] = 0x198,
338 [BRCMNAND_LL_RDATA] = 0x19c,
339 [BRCMNAND_OOB_READ_BASE] = 0x200,
340 [BRCMNAND_OOB_READ_10_BASE] = 0,
341 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
342 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
343 [BRCMNAND_FC_BASE] = 0x400,
347 static const u16 brcmnand_regs_v72[] = {
348 [BRCMNAND_CMD_START] = 0x04,
349 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
350 [BRCMNAND_CMD_ADDRESS] = 0x0c,
351 [BRCMNAND_INTFC_STATUS] = 0x14,
352 [BRCMNAND_CS_SELECT] = 0x18,
353 [BRCMNAND_CS_XOR] = 0x1c,
354 [BRCMNAND_LL_OP] = 0x20,
355 [BRCMNAND_CS0_BASE] = 0x50,
356 [BRCMNAND_CS1_BASE] = 0,
357 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
358 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
359 [BRCMNAND_UNCORR_COUNT] = 0xfc,
360 [BRCMNAND_CORR_COUNT] = 0x100,
361 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
362 [BRCMNAND_CORR_ADDR] = 0x110,
363 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
364 [BRCMNAND_UNCORR_ADDR] = 0x118,
365 [BRCMNAND_SEMAPHORE] = 0x150,
366 [BRCMNAND_ID] = 0x194,
367 [BRCMNAND_ID_EXT] = 0x198,
368 [BRCMNAND_LL_RDATA] = 0x19c,
369 [BRCMNAND_OOB_READ_BASE] = 0x200,
370 [BRCMNAND_OOB_READ_10_BASE] = 0,
371 [BRCMNAND_OOB_WRITE_BASE] = 0x400,
372 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
373 [BRCMNAND_FC_BASE] = 0x600,
376 enum brcmnand_cs_reg {
377 BRCMNAND_CS_CFG_EXT = 0,
379 BRCMNAND_CS_ACC_CONTROL,
384 /* Per chip-select offsets for v7.1 */
385 static const u8 brcmnand_cs_offsets_v71[] = {
386 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
387 [BRCMNAND_CS_CFG_EXT] = 0x04,
388 [BRCMNAND_CS_CFG] = 0x08,
389 [BRCMNAND_CS_TIMING1] = 0x0c,
390 [BRCMNAND_CS_TIMING2] = 0x10,
393 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
394 static const u8 brcmnand_cs_offsets[] = {
395 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
396 [BRCMNAND_CS_CFG_EXT] = 0x04,
397 [BRCMNAND_CS_CFG] = 0x04,
398 [BRCMNAND_CS_TIMING1] = 0x08,
399 [BRCMNAND_CS_TIMING2] = 0x0c,
402 /* Per chip-select offset for <= v5.0 on CS0 only */
403 static const u8 brcmnand_cs_offsets_cs0[] = {
404 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
405 [BRCMNAND_CS_CFG_EXT] = 0x08,
406 [BRCMNAND_CS_CFG] = 0x08,
407 [BRCMNAND_CS_TIMING1] = 0x10,
408 [BRCMNAND_CS_TIMING2] = 0x14,
412 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
413 * one config register, but once the bitfields overflowed, newer controllers
414 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
417 CFG_BLK_ADR_BYTES_SHIFT = 8,
418 CFG_COL_ADR_BYTES_SHIFT = 12,
419 CFG_FUL_ADR_BYTES_SHIFT = 16,
420 CFG_BUS_WIDTH_SHIFT = 23,
421 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
422 CFG_DEVICE_SIZE_SHIFT = 24,
424 /* Only for pre-v7.1 (with no CFG_EXT register) */
425 CFG_PAGE_SIZE_SHIFT = 20,
426 CFG_BLK_SIZE_SHIFT = 28,
428 /* Only for v7.1+ (with CFG_EXT register) */
429 CFG_EXT_PAGE_SIZE_SHIFT = 0,
430 CFG_EXT_BLK_SIZE_SHIFT = 4,
433 /* BRCMNAND_INTFC_STATUS */
435 INTFC_FLASH_STATUS = GENMASK(7, 0),
437 INTFC_ERASED = BIT(27),
438 INTFC_OOB_VALID = BIT(28),
439 INTFC_CACHE_VALID = BIT(29),
440 INTFC_FLASH_READY = BIT(30),
441 INTFC_CTLR_READY = BIT(31),
444 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
446 return brcmnand_readl(ctrl->nand_base + offs);
449 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
452 brcmnand_writel(val, ctrl->nand_base + offs);
455 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
457 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
458 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
459 static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
461 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
463 /* Only support v4.0+? */
464 if (ctrl->nand_version < 0x0400) {
465 dev_err(ctrl->dev, "version %#x not supported\n",
470 /* Register offsets */
471 if (ctrl->nand_version >= 0x0702)
472 ctrl->reg_offsets = brcmnand_regs_v72;
473 else if (ctrl->nand_version >= 0x0701)
474 ctrl->reg_offsets = brcmnand_regs_v71;
475 else if (ctrl->nand_version >= 0x0600)
476 ctrl->reg_offsets = brcmnand_regs_v60;
477 else if (ctrl->nand_version >= 0x0500)
478 ctrl->reg_offsets = brcmnand_regs_v50;
479 else if (ctrl->nand_version >= 0x0400)
480 ctrl->reg_offsets = brcmnand_regs_v40;
482 /* Chip-select stride */
483 if (ctrl->nand_version >= 0x0701)
484 ctrl->reg_spacing = 0x14;
486 ctrl->reg_spacing = 0x10;
488 /* Per chip-select registers */
489 if (ctrl->nand_version >= 0x0701) {
490 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
492 ctrl->cs_offsets = brcmnand_cs_offsets;
494 /* v3.3-5.0 have a different CS0 offset layout */
495 if (ctrl->nand_version >= 0x0303 &&
496 ctrl->nand_version <= 0x0500)
497 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
500 /* Page / block sizes */
501 if (ctrl->nand_version >= 0x0701) {
502 /* >= v7.1 use nice power-of-2 values! */
503 ctrl->max_page_size = 16 * 1024;
504 ctrl->max_block_size = 2 * 1024 * 1024;
506 ctrl->page_sizes = page_sizes;
507 if (ctrl->nand_version >= 0x0600)
508 ctrl->block_sizes = block_sizes_v6;
510 ctrl->block_sizes = block_sizes_v4;
512 if (ctrl->nand_version < 0x0400) {
513 ctrl->max_page_size = 4096;
514 ctrl->max_block_size = 512 * 1024;
518 /* Maximum spare area sector size (per 512B) */
519 if (ctrl->nand_version >= 0x0702)
521 else if (ctrl->nand_version >= 0x0600)
523 else if (ctrl->nand_version >= 0x0500)
528 /* v6.0 and newer (except v6.1) have prefetch support */
529 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
530 ctrl->features |= BRCMNAND_HAS_PREFETCH;
533 * v6.x has cache mode, but it's implemented differently. Ignore it for
536 if (ctrl->nand_version >= 0x0700)
537 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
539 if (ctrl->nand_version >= 0x0500)
540 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
542 if (ctrl->nand_version >= 0x0700)
543 ctrl->features |= BRCMNAND_HAS_WP;
544 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
545 ctrl->features |= BRCMNAND_HAS_WP;
550 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
551 enum brcmnand_reg reg)
553 u16 offs = ctrl->reg_offsets[reg];
556 return nand_readreg(ctrl, offs);
561 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
562 enum brcmnand_reg reg, u32 val)
564 u16 offs = ctrl->reg_offsets[reg];
567 nand_writereg(ctrl, offs, val);
570 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
571 enum brcmnand_reg reg, u32 mask, unsigned
574 u32 tmp = brcmnand_read_reg(ctrl, reg);
578 brcmnand_write_reg(ctrl, reg, tmp);
581 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
583 return __raw_readl(ctrl->nand_fc + word * 4);
586 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
589 __raw_writel(val, ctrl->nand_fc + word * 4);
592 static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl)
595 /* Clear error addresses */
596 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
597 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
598 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
599 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
602 static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl)
606 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR);
607 err_addr |= ((u64)(brcmnand_read_reg(ctrl,
608 BRCMNAND_UNCORR_EXT_ADDR)
614 static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl)
618 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR);
619 err_addr |= ((u64)(brcmnand_read_reg(ctrl,
620 BRCMNAND_CORR_EXT_ADDR)
626 static void brcmnand_set_cmd_addr(struct mtd_info *mtd, u64 addr)
628 struct nand_chip *chip = mtd_to_nand(mtd);
629 struct brcmnand_host *host = nand_get_controller_data(chip);
630 struct brcmnand_controller *ctrl = host->ctrl;
632 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
633 (host->cs << 16) | ((addr >> 32) & 0xffff));
634 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
635 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
636 lower_32_bits(addr));
637 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
640 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
641 enum brcmnand_cs_reg reg)
643 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
644 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
647 if (cs == 0 && ctrl->cs0_offsets)
648 cs_offs = ctrl->cs0_offsets[reg];
650 cs_offs = ctrl->cs_offsets[reg];
653 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
655 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
658 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
660 if (ctrl->nand_version < 0x0600)
662 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
665 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
667 struct brcmnand_controller *ctrl = host->ctrl;
668 unsigned int shift = 0, bits;
669 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
672 if (ctrl->nand_version >= 0x0702)
674 else if (ctrl->nand_version >= 0x0600)
676 else if (ctrl->nand_version >= 0x0500)
681 if (ctrl->nand_version >= 0x0702) {
683 reg = BRCMNAND_CORR_THRESHOLD_EXT;
684 shift = (cs % 4) * bits;
685 } else if (ctrl->nand_version >= 0x0600) {
687 reg = BRCMNAND_CORR_THRESHOLD_EXT;
688 shift = (cs % 5) * bits;
690 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
693 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
695 if (ctrl->nand_version < 0x0602)
700 /***********************************************************************
701 * NAND ACC CONTROL bitfield
703 * Some bits have remained constant throughout hardware revision, while
704 * others have shifted around.
705 ***********************************************************************/
707 /* Constant for all versions (where supported) */
709 /* See BRCMNAND_HAS_CACHE_MODE */
710 ACC_CONTROL_CACHE_MODE = BIT(22),
712 /* See BRCMNAND_HAS_PREFETCH */
713 ACC_CONTROL_PREFETCH = BIT(23),
715 ACC_CONTROL_PAGE_HIT = BIT(24),
716 ACC_CONTROL_WR_PREEMPT = BIT(25),
717 ACC_CONTROL_PARTIAL_PAGE = BIT(26),
718 ACC_CONTROL_RD_ERASED = BIT(27),
719 ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
720 ACC_CONTROL_WR_ECC = BIT(30),
721 ACC_CONTROL_RD_ECC = BIT(31),
724 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
726 if (ctrl->nand_version >= 0x0702)
727 return GENMASK(7, 0);
728 else if (ctrl->nand_version >= 0x0600)
729 return GENMASK(6, 0);
731 return GENMASK(5, 0);
734 #define NAND_ACC_CONTROL_ECC_SHIFT 16
735 #define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13
737 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
739 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
741 mask <<= NAND_ACC_CONTROL_ECC_SHIFT;
743 /* v7.2 includes additional ECC levels */
744 if (ctrl->nand_version >= 0x0702)
745 mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT;
750 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
752 struct brcmnand_controller *ctrl = host->ctrl;
753 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
754 u32 acc_control = nand_readreg(ctrl, offs);
755 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
758 acc_control |= ecc_flags; /* enable RD/WR ECC */
759 acc_control |= host->hwcfg.ecc_level
760 << NAND_ACC_CONTROL_ECC_SHIFT;
762 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
763 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
766 nand_writereg(ctrl, offs, acc_control);
769 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
771 if (ctrl->nand_version >= 0x0702)
773 else if (ctrl->nand_version >= 0x0600)
775 else if (ctrl->nand_version >= 0x0500)
781 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
783 struct brcmnand_controller *ctrl = host->ctrl;
784 int shift = brcmnand_sector_1k_shift(ctrl);
785 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
786 BRCMNAND_CS_ACC_CONTROL);
791 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
794 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
796 struct brcmnand_controller *ctrl = host->ctrl;
797 int shift = brcmnand_sector_1k_shift(ctrl);
798 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
799 BRCMNAND_CS_ACC_CONTROL);
805 tmp = nand_readreg(ctrl, acc_control_offs);
806 tmp &= ~(1 << shift);
807 tmp |= (!!val) << shift;
808 nand_writereg(ctrl, acc_control_offs, tmp);
811 /***********************************************************************
813 ***********************************************************************/
816 CS_SELECT_NAND_WP = BIT(29),
817 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
820 static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,
821 u32 mask, u32 expected_val,
822 unsigned long timeout_ms)
828 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;
830 limit = jiffies + msecs_to_jiffies(timeout_ms);
832 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
833 if ((val & mask) == expected_val)
837 } while (time_after(limit, jiffies));
839 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n",
840 expected_val, val & mask);
845 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
847 u32 val = en ? CS_SELECT_NAND_WP : 0;
849 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
852 /***********************************************************************
854 ***********************************************************************/
857 FLASH_DMA_REVISION = 0x00,
858 FLASH_DMA_FIRST_DESC = 0x04,
859 FLASH_DMA_FIRST_DESC_EXT = 0x08,
860 FLASH_DMA_CTRL = 0x0c,
861 FLASH_DMA_MODE = 0x10,
862 FLASH_DMA_STATUS = 0x14,
863 FLASH_DMA_INTERRUPT_DESC = 0x18,
864 FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
865 FLASH_DMA_ERROR_STATUS = 0x20,
866 FLASH_DMA_CURRENT_DESC = 0x24,
867 FLASH_DMA_CURRENT_DESC_EXT = 0x28,
870 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
872 return ctrl->flash_dma_base;
875 static inline bool flash_dma_buf_ok(const void *buf)
877 return buf && !is_vmalloc_addr(buf) &&
878 likely(IS_ALIGNED((uintptr_t)buf, 4));
881 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
884 brcmnand_writel(val, ctrl->flash_dma_base + offs);
887 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
889 return brcmnand_readl(ctrl->flash_dma_base + offs);
892 /* Low-level operation types: command, address, write, or read */
893 enum brcmnand_llop_type {
900 /***********************************************************************
901 * Internal support functions
902 ***********************************************************************/
904 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
905 struct brcmnand_cfg *cfg)
907 if (ctrl->nand_version <= 0x0701)
908 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
909 cfg->ecc_level == 15;
911 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&
912 cfg->ecc_level == 15) ||
913 (cfg->spare_area_size == 28 && cfg->ecc_level == 16));
917 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
918 * the layout/configuration.
919 * Returns -ERRCODE on failure.
921 static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section,
922 struct mtd_oob_region *oobregion)
924 struct nand_chip *chip = mtd_to_nand(mtd);
925 struct brcmnand_host *host = nand_get_controller_data(chip);
926 struct brcmnand_cfg *cfg = &host->hwcfg;
927 int sas = cfg->spare_area_size << cfg->sector_size_1k;
928 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
930 if (section >= sectors)
933 oobregion->offset = (section * sas) + 6;
934 oobregion->length = 3;
939 static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section,
940 struct mtd_oob_region *oobregion)
942 struct nand_chip *chip = mtd_to_nand(mtd);
943 struct brcmnand_host *host = nand_get_controller_data(chip);
944 struct brcmnand_cfg *cfg = &host->hwcfg;
945 int sas = cfg->spare_area_size << cfg->sector_size_1k;
946 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
948 if (section >= sectors * 2)
951 oobregion->offset = (section / 2) * sas;
954 oobregion->offset += 9;
955 oobregion->length = 7;
957 oobregion->length = 6;
959 /* First sector of each page may have BBI */
962 * Small-page NAND use byte 6 for BBI while large-page
963 * NAND use bytes 0 and 1.
965 if (cfg->page_size > 512) {
966 oobregion->offset += 2;
967 oobregion->length -= 2;
977 static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = {
978 .ecc = brcmnand_hamming_ooblayout_ecc,
979 .free = brcmnand_hamming_ooblayout_free,
982 static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section,
983 struct mtd_oob_region *oobregion)
985 struct nand_chip *chip = mtd_to_nand(mtd);
986 struct brcmnand_host *host = nand_get_controller_data(chip);
987 struct brcmnand_cfg *cfg = &host->hwcfg;
988 int sas = cfg->spare_area_size << cfg->sector_size_1k;
989 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
991 if (section >= sectors)
994 oobregion->offset = (section * (sas + 1)) - chip->ecc.bytes;
995 oobregion->length = chip->ecc.bytes;
1000 static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section,
1001 struct mtd_oob_region *oobregion)
1003 struct nand_chip *chip = mtd_to_nand(mtd);
1004 struct brcmnand_host *host = nand_get_controller_data(chip);
1005 struct brcmnand_cfg *cfg = &host->hwcfg;
1006 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1007 int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
1009 if (section >= sectors)
1012 if (sas <= chip->ecc.bytes)
1015 oobregion->offset = section * sas;
1016 oobregion->length = sas - chip->ecc.bytes;
1019 oobregion->offset++;
1020 oobregion->length--;
1026 static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section,
1027 struct mtd_oob_region *oobregion)
1029 struct nand_chip *chip = mtd_to_nand(mtd);
1030 struct brcmnand_host *host = nand_get_controller_data(chip);
1031 struct brcmnand_cfg *cfg = &host->hwcfg;
1032 int sas = cfg->spare_area_size << cfg->sector_size_1k;
1034 if (section > 1 || sas - chip->ecc.bytes < 6 ||
1035 (section && sas - chip->ecc.bytes == 6))
1039 oobregion->offset = 0;
1040 oobregion->length = 5;
1042 oobregion->offset = 6;
1043 oobregion->length = sas - chip->ecc.bytes - 6;
1049 static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = {
1050 .ecc = brcmnand_bch_ooblayout_ecc,
1051 .free = brcmnand_bch_ooblayout_free_lp,
1054 static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = {
1055 .ecc = brcmnand_bch_ooblayout_ecc,
1056 .free = brcmnand_bch_ooblayout_free_sp,
1059 static int brcmstb_choose_ecc_layout(struct brcmnand_host *host)
1061 struct brcmnand_cfg *p = &host->hwcfg;
1062 struct mtd_info *mtd = nand_to_mtd(&host->chip);
1063 struct nand_ecc_ctrl *ecc = &host->chip.ecc;
1064 unsigned int ecc_level = p->ecc_level;
1065 int sas = p->spare_area_size << p->sector_size_1k;
1066 int sectors = p->page_size / (512 << p->sector_size_1k);
1068 if (p->sector_size_1k)
1071 if (is_hamming_ecc(host->ctrl, p)) {
1072 ecc->bytes = 3 * sectors;
1073 mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops);
1078 * CONTROLLER_VERSION:
1079 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
1080 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
1081 * But we will just be conservative.
1083 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);
1084 if (p->page_size == 512)
1085 mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops);
1087 mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops);
1089 if (ecc->bytes >= sas) {
1090 dev_err(&host->pdev->dev,
1091 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
1099 static void brcmnand_wp(struct mtd_info *mtd, int wp)
1101 struct nand_chip *chip = mtd_to_nand(mtd);
1102 struct brcmnand_host *host = nand_get_controller_data(chip);
1103 struct brcmnand_controller *ctrl = host->ctrl;
1105 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
1106 static int old_wp = -1;
1110 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
1115 * make sure ctrl/flash ready before and after
1116 * changing state of #WP pin
1118 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY |
1121 NAND_STATUS_READY, 0);
1125 brcmnand_set_wp(ctrl, wp);
1126 nand_status_op(chip, NULL);
1127 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
1128 ret = bcmnand_ctrl_poll_status(ctrl,
1134 (wp ? 0 : NAND_STATUS_WP), 0);
1137 dev_err_ratelimited(&host->pdev->dev,
1138 "nand #WP expected %s\n",
1143 /* Helper functions for reading and writing OOB registers */
1144 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
1146 u16 offset0, offset10, reg_offs;
1148 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
1149 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
1151 if (offs >= ctrl->max_oob)
1154 if (offs >= 16 && offset10)
1155 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1157 reg_offs = offset0 + (offs & ~0x03);
1159 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
1162 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
1165 u16 offset0, offset10, reg_offs;
1167 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
1168 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
1170 if (offs >= ctrl->max_oob)
1173 if (offs >= 16 && offset10)
1174 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1176 reg_offs = offset0 + (offs & ~0x03);
1178 nand_writereg(ctrl, reg_offs, data);
1182 * read_oob_from_regs - read data from OOB registers
1183 * @ctrl: NAND controller
1184 * @i: sub-page sector index
1185 * @oob: buffer to read to
1186 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1187 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1189 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
1190 int sas, int sector_1k)
1192 int tbytes = sas << sector_1k;
1195 /* Adjust OOB values for 1K sector size */
1196 if (sector_1k && (i & 0x01))
1197 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1198 tbytes = min_t(int, tbytes, ctrl->max_oob);
1200 for (j = 0; j < tbytes; j++)
1201 oob[j] = oob_reg_read(ctrl, j);
1206 * write_oob_to_regs - write data to OOB registers
1207 * @i: sub-page sector index
1208 * @oob: buffer to write from
1209 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1210 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1212 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
1213 const u8 *oob, int sas, int sector_1k)
1215 int tbytes = sas << sector_1k;
1218 /* Adjust OOB values for 1K sector size */
1219 if (sector_1k && (i & 0x01))
1220 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1221 tbytes = min_t(int, tbytes, ctrl->max_oob);
1223 for (j = 0; j < tbytes; j += 4)
1224 oob_reg_write(ctrl, j,
1225 (oob[j + 0] << 24) |
1226 (oob[j + 1] << 16) |
1232 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1234 struct brcmnand_controller *ctrl = data;
1236 /* Discard all NAND_CTLRDY interrupts during DMA */
1237 if (ctrl->dma_pending)
1240 complete(&ctrl->done);
1244 /* Handle SoC-specific interrupt hardware */
1245 static irqreturn_t brcmnand_irq(int irq, void *data)
1247 struct brcmnand_controller *ctrl = data;
1249 if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1250 return brcmnand_ctlrdy_irq(irq, data);
1255 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1257 struct brcmnand_controller *ctrl = data;
1259 complete(&ctrl->dma_done);
1264 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1266 struct brcmnand_controller *ctrl = host->ctrl;
1270 cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1272 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr);
1274 BUG_ON(ctrl->cmd_pending != 0);
1275 ctrl->cmd_pending = cmd;
1277 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
1280 mb(); /* flush previous writes */
1281 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1282 cmd << brcmnand_cmd_shift(ctrl));
1285 /***********************************************************************
1286 * NAND MTD API: read/program/erase
1287 ***********************************************************************/
1289 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1292 /* intentionally left blank */
1295 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1297 struct nand_chip *chip = mtd_to_nand(mtd);
1298 struct brcmnand_host *host = nand_get_controller_data(chip);
1299 struct brcmnand_controller *ctrl = host->ctrl;
1300 unsigned long timeo = msecs_to_jiffies(100);
1302 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1303 if (ctrl->cmd_pending &&
1304 wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1305 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1306 >> brcmnand_cmd_shift(ctrl);
1308 dev_err_ratelimited(ctrl->dev,
1309 "timeout waiting for command %#02x\n", cmd);
1310 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1311 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1313 ctrl->cmd_pending = 0;
1314 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1323 LLOP_RETURN_IDLE = BIT(31),
1325 LLOP_DATA_MASK = GENMASK(15, 0),
1328 static int brcmnand_low_level_op(struct brcmnand_host *host,
1329 enum brcmnand_llop_type type, u32 data,
1332 struct mtd_info *mtd = nand_to_mtd(&host->chip);
1333 struct nand_chip *chip = &host->chip;
1334 struct brcmnand_controller *ctrl = host->ctrl;
1337 tmp = data & LLOP_DATA_MASK;
1340 tmp |= LLOP_WE | LLOP_CLE;
1344 tmp |= LLOP_WE | LLOP_ALE;
1357 tmp |= LLOP_RETURN_IDLE;
1359 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1361 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1362 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1364 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1365 return brcmnand_waitfunc(mtd, chip);
1368 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1369 int column, int page_addr)
1371 struct nand_chip *chip = mtd_to_nand(mtd);
1372 struct brcmnand_host *host = nand_get_controller_data(chip);
1373 struct brcmnand_controller *ctrl = host->ctrl;
1374 u64 addr = (u64)page_addr << chip->page_shift;
1377 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1378 command == NAND_CMD_RNDOUT)
1380 /* Avoid propagating a negative, don't-care address */
1381 else if (page_addr < 0)
1384 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1385 (unsigned long long)addr);
1387 host->last_cmd = command;
1388 host->last_byte = 0;
1389 host->last_addr = addr;
1392 case NAND_CMD_RESET:
1393 native_cmd = CMD_FLASH_RESET;
1395 case NAND_CMD_STATUS:
1396 native_cmd = CMD_STATUS_READ;
1398 case NAND_CMD_READID:
1399 native_cmd = CMD_DEVICE_ID_READ;
1401 case NAND_CMD_READOOB:
1402 native_cmd = CMD_SPARE_AREA_READ;
1404 case NAND_CMD_ERASE1:
1405 native_cmd = CMD_BLOCK_ERASE;
1406 brcmnand_wp(mtd, 0);
1408 case NAND_CMD_PARAM:
1409 native_cmd = CMD_PARAMETER_READ;
1411 case NAND_CMD_SET_FEATURES:
1412 case NAND_CMD_GET_FEATURES:
1413 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1414 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1416 case NAND_CMD_RNDOUT:
1417 native_cmd = CMD_PARAMETER_CHANGE_COL;
1418 addr &= ~((u64)(FC_BYTES - 1));
1420 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1421 * NB: hwcfg.sector_size_1k may not be initialized yet
1423 if (brcmnand_get_sector_size_1k(host)) {
1424 host->hwcfg.sector_size_1k =
1425 brcmnand_get_sector_size_1k(host);
1426 brcmnand_set_sector_size_1k(host, 0);
1434 brcmnand_set_cmd_addr(mtd, addr);
1435 brcmnand_send_cmd(host, native_cmd);
1436 brcmnand_waitfunc(mtd, chip);
1438 if (native_cmd == CMD_PARAMETER_READ ||
1439 native_cmd == CMD_PARAMETER_CHANGE_COL) {
1440 /* Copy flash cache word-wise */
1441 u32 *flash_cache = (u32 *)ctrl->flash_cache;
1444 brcmnand_soc_data_bus_prepare(ctrl->soc, true);
1447 * Must cache the FLASH_CACHE now, since changes in
1448 * SECTOR_SIZE_1K may invalidate it
1450 for (i = 0; i < FC_WORDS; i++)
1452 * Flash cache is big endian for parameter pages, at
1455 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));
1457 brcmnand_soc_data_bus_unprepare(ctrl->soc, true);
1459 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1460 if (host->hwcfg.sector_size_1k)
1461 brcmnand_set_sector_size_1k(host,
1462 host->hwcfg.sector_size_1k);
1465 /* Re-enable protection is necessary only after erase */
1466 if (command == NAND_CMD_ERASE1)
1467 brcmnand_wp(mtd, 1);
1470 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1472 struct nand_chip *chip = mtd_to_nand(mtd);
1473 struct brcmnand_host *host = nand_get_controller_data(chip);
1474 struct brcmnand_controller *ctrl = host->ctrl;
1478 switch (host->last_cmd) {
1479 case NAND_CMD_READID:
1480 if (host->last_byte < 4)
1481 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1482 (24 - (host->last_byte << 3));
1483 else if (host->last_byte < 8)
1484 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1485 (56 - (host->last_byte << 3));
1488 case NAND_CMD_READOOB:
1489 ret = oob_reg_read(ctrl, host->last_byte);
1492 case NAND_CMD_STATUS:
1493 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1495 if (wp_on) /* hide WP status */
1496 ret |= NAND_STATUS_WP;
1499 case NAND_CMD_PARAM:
1500 case NAND_CMD_RNDOUT:
1501 addr = host->last_addr + host->last_byte;
1502 offs = addr & (FC_BYTES - 1);
1504 /* At FC_BYTES boundary, switch to next column */
1505 if (host->last_byte > 0 && offs == 0)
1506 nand_change_read_column_op(chip, addr, NULL, 0, false);
1508 ret = ctrl->flash_cache[offs];
1510 case NAND_CMD_GET_FEATURES:
1511 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1514 bool last = host->last_byte ==
1515 ONFI_SUBFEATURE_PARAM_LEN - 1;
1516 brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1517 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1521 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1527 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1531 for (i = 0; i < len; i++, buf++)
1532 *buf = brcmnand_read_byte(mtd);
1535 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1539 struct nand_chip *chip = mtd_to_nand(mtd);
1540 struct brcmnand_host *host = nand_get_controller_data(chip);
1542 switch (host->last_cmd) {
1543 case NAND_CMD_SET_FEATURES:
1544 for (i = 0; i < len; i++)
1545 brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1555 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1556 * following ahead of time:
1557 * - Is this descriptor the beginning or end of a linked list?
1558 * - What is the (DMA) address of the next descriptor in the linked list?
1560 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1561 struct brcm_nand_dma_desc *desc, u64 addr,
1562 dma_addr_t buf, u32 len, u8 dma_cmd,
1563 bool begin, bool end,
1564 dma_addr_t next_desc)
1566 memset(desc, 0, sizeof(*desc));
1567 /* Descriptors are written in native byte order (wordwise) */
1568 desc->next_desc = lower_32_bits(next_desc);
1569 desc->next_desc_ext = upper_32_bits(next_desc);
1570 desc->cmd_irq = (dma_cmd << 24) |
1571 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1572 (!!begin) | ((!!end) << 1); /* head, tail */
1573 #ifdef CONFIG_CPU_BIG_ENDIAN
1574 desc->cmd_irq |= 0x01 << 12;
1576 desc->dram_addr = lower_32_bits(buf);
1577 desc->dram_addr_ext = upper_32_bits(buf);
1578 desc->tfr_len = len;
1579 desc->total_len = len;
1580 desc->flash_addr = lower_32_bits(addr);
1581 desc->flash_addr_ext = upper_32_bits(addr);
1582 desc->cs = host->cs;
1583 desc->status_valid = 0x01;
1588 * Kick the FLASH_DMA engine, with a given DMA descriptor
1590 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1592 struct brcmnand_controller *ctrl = host->ctrl;
1593 unsigned long timeo = msecs_to_jiffies(100);
1595 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1596 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1597 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1598 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1600 /* Start FLASH_DMA engine */
1601 ctrl->dma_pending = true;
1602 mb(); /* flush previous writes */
1603 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1605 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1607 "timeout waiting for DMA; status %#x, error status %#x\n",
1608 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1609 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1611 ctrl->dma_pending = false;
1612 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1615 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1616 u32 len, u8 dma_cmd)
1618 struct brcmnand_controller *ctrl = host->ctrl;
1620 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1622 buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1623 if (dma_mapping_error(ctrl->dev, buf_pa)) {
1624 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1628 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1629 dma_cmd, true, true, 0);
1631 brcmnand_dma_run(host, ctrl->dma_pa);
1633 dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1635 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1637 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1644 * Assumes proper CS is already set
1646 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1647 u64 addr, unsigned int trans, u32 *buf,
1648 u8 *oob, u64 *err_addr)
1650 struct brcmnand_host *host = nand_get_controller_data(chip);
1651 struct brcmnand_controller *ctrl = host->ctrl;
1654 brcmnand_clear_ecc_addr(ctrl);
1656 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1657 brcmnand_set_cmd_addr(mtd, addr);
1658 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1659 brcmnand_send_cmd(host, CMD_PAGE_READ);
1660 brcmnand_waitfunc(mtd, chip);
1663 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1665 for (j = 0; j < FC_WORDS; j++, buf++)
1666 *buf = brcmnand_read_fc(ctrl, j);
1668 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1672 oob += read_oob_from_regs(ctrl, i, oob,
1673 mtd->oobsize / trans,
1674 host->hwcfg.sector_size_1k);
1676 if (ret != -EBADMSG) {
1677 *err_addr = brcmnand_get_uncorrecc_addr(ctrl);
1684 *err_addr = brcmnand_get_correcc_addr(ctrl);
1695 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
1698 * Because the HW ECC signals an ECC error if an erase paged has even a single
1699 * bitflip, we must check each ECC error to see if it is actually an erased
1700 * page with bitflips, not a truly corrupted page.
1702 * On a real error, return a negative error code (-EBADMSG for ECC error), and
1703 * buf will contain raw data.
1704 * Otherwise, buf gets filled with 0xffs and return the maximum number of
1705 * bitflips-per-ECC-sector to the caller.
1708 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
1709 struct nand_chip *chip, void *buf, u64 addr)
1712 void *oob = chip->oob_poi;
1714 int page = addr >> chip->page_shift;
1718 buf = chip->data_buf;
1719 /* Invalidate page cache */
1723 sas = mtd->oobsize / chip->ecc.steps;
1725 /* read without ecc for verification */
1726 ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
1730 for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
1731 ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
1733 chip->ecc.strength);
1737 bitflips = max(bitflips, ret);
1743 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1744 u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1746 struct brcmnand_host *host = nand_get_controller_data(chip);
1747 struct brcmnand_controller *ctrl = host->ctrl;
1752 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1755 brcmnand_clear_ecc_addr(ctrl);
1757 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1758 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1761 if (mtd_is_bitflip_or_eccerr(err))
1768 memset(oob, 0x99, mtd->oobsize);
1770 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1774 if (mtd_is_eccerr(err)) {
1776 * On controller version and 7.0, 7.1 , DMA read after a
1777 * prior PIO read that reported uncorrectable error,
1778 * the DMA engine captures this error following DMA read
1779 * cleared only on subsequent DMA read, so just retry once
1780 * to clear a possible false error reported for current DMA
1783 if ((ctrl->nand_version == 0x0700) ||
1784 (ctrl->nand_version == 0x0701)) {
1792 * Controller version 7.2 has hw encoder to detect erased page
1793 * bitflips, apply sw verification for older controllers only
1795 if (ctrl->nand_version < 0x0702) {
1796 err = brcmstb_nand_verify_erased_page(mtd, chip, buf,
1798 /* erased page bitflips corrected */
1803 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1804 (unsigned long long)err_addr);
1805 mtd->ecc_stats.failed++;
1806 /* NAND layer expects zero on ECC errors */
1810 if (mtd_is_bitflip(err)) {
1811 unsigned int corrected = brcmnand_count_corrected(ctrl);
1813 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1814 (unsigned long long)err_addr);
1815 mtd->ecc_stats.corrected += corrected;
1816 /* Always exceed the software-imposed threshold */
1817 return max(mtd->bitflip_threshold, corrected);
1823 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1824 uint8_t *buf, int oob_required, int page)
1826 struct brcmnand_host *host = nand_get_controller_data(chip);
1827 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1829 nand_read_page_op(chip, page, 0, NULL, 0);
1831 return brcmnand_read(mtd, chip, host->last_addr,
1832 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1835 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1836 uint8_t *buf, int oob_required, int page)
1838 struct brcmnand_host *host = nand_get_controller_data(chip);
1839 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1842 nand_read_page_op(chip, page, 0, NULL, 0);
1844 brcmnand_set_ecc_enabled(host, 0);
1845 ret = brcmnand_read(mtd, chip, host->last_addr,
1846 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1847 brcmnand_set_ecc_enabled(host, 1);
1851 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1854 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1855 mtd->writesize >> FC_SHIFT,
1856 NULL, (u8 *)chip->oob_poi);
1859 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1862 struct brcmnand_host *host = nand_get_controller_data(chip);
1864 brcmnand_set_ecc_enabled(host, 0);
1865 brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1866 mtd->writesize >> FC_SHIFT,
1867 NULL, (u8 *)chip->oob_poi);
1868 brcmnand_set_ecc_enabled(host, 1);
1872 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1873 u64 addr, const u32 *buf, u8 *oob)
1875 struct brcmnand_host *host = nand_get_controller_data(chip);
1876 struct brcmnand_controller *ctrl = host->ctrl;
1877 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1878 int status, ret = 0;
1880 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1882 if (unlikely((unsigned long)buf & 0x03)) {
1883 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1884 buf = (u32 *)((unsigned long)buf & ~0x03);
1887 brcmnand_wp(mtd, 0);
1889 for (i = 0; i < ctrl->max_oob; i += 4)
1890 oob_reg_write(ctrl, i, 0xffffffff);
1892 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1893 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1894 mtd->writesize, CMD_PROGRAM_PAGE))
1899 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1900 /* full address MUST be set before populating FC */
1901 brcmnand_set_cmd_addr(mtd, addr);
1904 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1906 for (j = 0; j < FC_WORDS; j++, buf++)
1907 brcmnand_write_fc(ctrl, j, *buf);
1909 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1911 for (j = 0; j < FC_WORDS; j++)
1912 brcmnand_write_fc(ctrl, j, 0xffffffff);
1916 oob += write_oob_to_regs(ctrl, i, oob,
1917 mtd->oobsize / trans,
1918 host->hwcfg.sector_size_1k);
1921 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1922 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1923 status = brcmnand_waitfunc(mtd, chip);
1925 if (status & NAND_STATUS_FAIL) {
1926 dev_info(ctrl->dev, "program failed at %llx\n",
1927 (unsigned long long)addr);
1933 brcmnand_wp(mtd, 1);
1937 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1938 const uint8_t *buf, int oob_required, int page)
1940 struct brcmnand_host *host = nand_get_controller_data(chip);
1941 void *oob = oob_required ? chip->oob_poi : NULL;
1943 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1944 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1946 return nand_prog_page_end_op(chip);
1949 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1950 struct nand_chip *chip, const uint8_t *buf,
1951 int oob_required, int page)
1953 struct brcmnand_host *host = nand_get_controller_data(chip);
1954 void *oob = oob_required ? chip->oob_poi : NULL;
1956 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1957 brcmnand_set_ecc_enabled(host, 0);
1958 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1959 brcmnand_set_ecc_enabled(host, 1);
1961 return nand_prog_page_end_op(chip);
1964 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1967 return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1968 NULL, chip->oob_poi);
1971 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1974 struct brcmnand_host *host = nand_get_controller_data(chip);
1977 brcmnand_set_ecc_enabled(host, 0);
1978 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1979 (u8 *)chip->oob_poi);
1980 brcmnand_set_ecc_enabled(host, 1);
1985 /***********************************************************************
1986 * Per-CS setup (1 NAND device)
1987 ***********************************************************************/
1989 static int brcmnand_set_cfg(struct brcmnand_host *host,
1990 struct brcmnand_cfg *cfg)
1992 struct brcmnand_controller *ctrl = host->ctrl;
1993 struct nand_chip *chip = &host->chip;
1994 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1995 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1996 BRCMNAND_CS_CFG_EXT);
1997 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1998 BRCMNAND_CS_ACC_CONTROL);
1999 u8 block_size = 0, page_size = 0, device_size = 0;
2002 if (ctrl->block_sizes) {
2005 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
2006 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
2011 dev_warn(ctrl->dev, "invalid block size %u\n",
2016 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
2019 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
2020 cfg->block_size > ctrl->max_block_size)) {
2021 dev_warn(ctrl->dev, "invalid block size %u\n",
2026 if (ctrl->page_sizes) {
2029 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
2030 if (ctrl->page_sizes[i] == cfg->page_size) {
2035 dev_warn(ctrl->dev, "invalid page size %u\n",
2040 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
2043 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
2044 cfg->page_size > ctrl->max_page_size)) {
2045 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
2049 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
2050 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
2051 (unsigned long long)cfg->device_size);
2054 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
2056 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
2057 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
2058 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
2059 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
2060 (device_size << CFG_DEVICE_SIZE_SHIFT);
2061 if (cfg_offs == cfg_ext_offs) {
2062 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
2063 (block_size << CFG_BLK_SIZE_SHIFT);
2064 nand_writereg(ctrl, cfg_offs, tmp);
2066 nand_writereg(ctrl, cfg_offs, tmp);
2067 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
2068 (block_size << CFG_EXT_BLK_SIZE_SHIFT);
2069 nand_writereg(ctrl, cfg_ext_offs, tmp);
2072 tmp = nand_readreg(ctrl, acc_control_offs);
2073 tmp &= ~brcmnand_ecc_level_mask(ctrl);
2074 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
2075 tmp &= ~brcmnand_spare_area_mask(ctrl);
2076 tmp |= cfg->spare_area_size;
2077 nand_writereg(ctrl, acc_control_offs, tmp);
2079 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
2081 /* threshold = ceil(BCH-level * 0.75) */
2082 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
2087 static void brcmnand_print_cfg(struct brcmnand_host *host,
2088 char *buf, struct brcmnand_cfg *cfg)
2091 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
2092 (unsigned long long)cfg->device_size >> 20,
2093 cfg->block_size >> 10,
2094 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
2095 cfg->page_size >= 1024 ? "KiB" : "B",
2096 cfg->spare_area_size, cfg->device_width);
2098 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
2099 if (is_hamming_ecc(host->ctrl, cfg))
2100 sprintf(buf, ", Hamming ECC");
2101 else if (cfg->sector_size_1k)
2102 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
2104 sprintf(buf, ", BCH-%u", cfg->ecc_level);
2108 * Minimum number of bytes to address a page. Calculated as:
2109 * roundup(log2(size / page-size) / 8)
2111 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2112 * OK because many other things will break if 'size' is irregular...
2114 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
2116 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
2119 static int brcmnand_setup_dev(struct brcmnand_host *host)
2121 struct mtd_info *mtd = nand_to_mtd(&host->chip);
2122 struct nand_chip *chip = &host->chip;
2123 struct brcmnand_controller *ctrl = host->ctrl;
2124 struct brcmnand_cfg *cfg = &host->hwcfg;
2126 u32 offs, tmp, oob_sector;
2129 memset(cfg, 0, sizeof(*cfg));
2131 ret = of_property_read_u32(nand_get_flash_node(chip),
2132 "brcm,nand-oob-sector-size",
2135 /* Use detected size */
2136 cfg->spare_area_size = mtd->oobsize /
2137 (mtd->writesize >> FC_SHIFT);
2139 cfg->spare_area_size = oob_sector;
2141 if (cfg->spare_area_size > ctrl->max_oob)
2142 cfg->spare_area_size = ctrl->max_oob;
2144 * Set oobsize to be consistent with controller's spare_area_size, as
2145 * the rest is inaccessible.
2147 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
2149 cfg->device_size = mtd->size;
2150 cfg->block_size = mtd->erasesize;
2151 cfg->page_size = mtd->writesize;
2152 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
2153 cfg->col_adr_bytes = 2;
2154 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
2156 if (chip->ecc.mode != NAND_ECC_HW) {
2157 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
2162 if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
2163 if (chip->ecc.strength == 1 && chip->ecc.size == 512)
2164 /* Default to Hamming for 1-bit ECC, if unspecified */
2165 chip->ecc.algo = NAND_ECC_HAMMING;
2167 /* Otherwise, BCH */
2168 chip->ecc.algo = NAND_ECC_BCH;
2171 if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
2172 chip->ecc.size != 512)) {
2173 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
2174 chip->ecc.strength, chip->ecc.size);
2178 switch (chip->ecc.size) {
2180 if (chip->ecc.algo == NAND_ECC_HAMMING)
2181 cfg->ecc_level = 15;
2183 cfg->ecc_level = chip->ecc.strength;
2184 cfg->sector_size_1k = 0;
2187 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
2188 dev_err(ctrl->dev, "1KB sectors not supported\n");
2191 if (chip->ecc.strength & 0x1) {
2193 "odd ECC not supported with 1KB sectors\n");
2197 cfg->ecc_level = chip->ecc.strength >> 1;
2198 cfg->sector_size_1k = 1;
2201 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
2206 cfg->ful_adr_bytes = cfg->blk_adr_bytes;
2207 if (mtd->writesize > 512)
2208 cfg->ful_adr_bytes += cfg->col_adr_bytes;
2210 cfg->ful_adr_bytes += 1;
2212 ret = brcmnand_set_cfg(host, cfg);
2216 brcmnand_set_ecc_enabled(host, 1);
2218 brcmnand_print_cfg(host, msg, cfg);
2219 dev_info(ctrl->dev, "detected %s\n", msg);
2221 /* Configure ACC_CONTROL */
2222 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
2223 tmp = nand_readreg(ctrl, offs);
2224 tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
2225 tmp &= ~ACC_CONTROL_RD_ERASED;
2227 /* We need to turn on Read from erased paged protected by ECC */
2228 if (ctrl->nand_version >= 0x0702)
2229 tmp |= ACC_CONTROL_RD_ERASED;
2230 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
2231 if (ctrl->features & BRCMNAND_HAS_PREFETCH)
2232 tmp &= ~ACC_CONTROL_PREFETCH;
2234 nand_writereg(ctrl, offs, tmp);
2239 static int brcmnand_attach_chip(struct nand_chip *chip)
2241 struct mtd_info *mtd = nand_to_mtd(chip);
2242 struct brcmnand_host *host = nand_get_controller_data(chip);
2245 chip->options |= NAND_NO_SUBPAGE_WRITE;
2247 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2248 * to/from, and have nand_base pass us a bounce buffer instead, as
2251 chip->options |= NAND_USE_BOUNCE_BUFFER;
2253 if (chip->bbt_options & NAND_BBT_USE_FLASH)
2254 chip->bbt_options |= NAND_BBT_NO_OOB;
2256 if (brcmnand_setup_dev(host))
2259 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2261 /* only use our internal HW threshold */
2262 mtd->bitflip_threshold = 1;
2264 ret = brcmstb_choose_ecc_layout(host);
2266 /* If OOB is written with ECC enabled it will cause ECC errors */
2267 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) {
2268 chip->ecc.write_oob = brcmnand_write_oob_raw;
2269 chip->ecc.read_oob = brcmnand_read_oob_raw;
2275 static const struct nand_controller_ops brcmnand_controller_ops = {
2276 .attach_chip = brcmnand_attach_chip,
2279 static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
2281 struct brcmnand_controller *ctrl = host->ctrl;
2282 struct platform_device *pdev = host->pdev;
2283 struct mtd_info *mtd;
2284 struct nand_chip *chip;
2288 ret = of_property_read_u32(dn, "reg", &host->cs);
2290 dev_err(&pdev->dev, "can't get chip-select\n");
2294 mtd = nand_to_mtd(&host->chip);
2297 nand_set_flash_node(chip, dn);
2298 nand_set_controller_data(chip, host);
2299 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
2304 mtd->owner = THIS_MODULE;
2305 mtd->dev.parent = &pdev->dev;
2307 chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
2308 chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
2310 chip->cmd_ctrl = brcmnand_cmd_ctrl;
2311 chip->cmdfunc = brcmnand_cmdfunc;
2312 chip->waitfunc = brcmnand_waitfunc;
2313 chip->read_byte = brcmnand_read_byte;
2314 chip->read_buf = brcmnand_read_buf;
2315 chip->write_buf = brcmnand_write_buf;
2317 chip->ecc.mode = NAND_ECC_HW;
2318 chip->ecc.read_page = brcmnand_read_page;
2319 chip->ecc.write_page = brcmnand_write_page;
2320 chip->ecc.read_page_raw = brcmnand_read_page_raw;
2321 chip->ecc.write_page_raw = brcmnand_write_page_raw;
2322 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
2323 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
2324 chip->ecc.read_oob = brcmnand_read_oob;
2325 chip->ecc.write_oob = brcmnand_write_oob;
2327 chip->controller = &ctrl->controller;
2330 * The bootloader might have configured 16bit mode but
2331 * NAND READID command only works in 8bit mode. We force
2332 * 8bit mode here to ensure that NAND READID commands works.
2334 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2335 nand_writereg(ctrl, cfg_offs,
2336 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
2338 ret = nand_scan(chip, 1);
2342 ret = mtd_device_register(mtd, NULL, 0);
2349 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2352 struct brcmnand_controller *ctrl = host->ctrl;
2353 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2354 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2355 BRCMNAND_CS_CFG_EXT);
2356 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2357 BRCMNAND_CS_ACC_CONTROL);
2358 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2359 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2362 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2363 if (cfg_offs != cfg_ext_offs)
2364 nand_writereg(ctrl, cfg_ext_offs,
2365 host->hwcfg.config_ext);
2366 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2367 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2368 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2370 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2371 if (cfg_offs != cfg_ext_offs)
2372 host->hwcfg.config_ext =
2373 nand_readreg(ctrl, cfg_ext_offs);
2374 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2375 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2376 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2380 static int brcmnand_suspend(struct device *dev)
2382 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2383 struct brcmnand_host *host;
2385 list_for_each_entry(host, &ctrl->host_list, node)
2386 brcmnand_save_restore_cs_config(host, 0);
2388 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2389 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2390 ctrl->corr_stat_threshold =
2391 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2393 if (has_flash_dma(ctrl))
2394 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2399 static int brcmnand_resume(struct device *dev)
2401 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2402 struct brcmnand_host *host;
2404 if (has_flash_dma(ctrl)) {
2405 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2406 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2409 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2410 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2411 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2412 ctrl->corr_stat_threshold);
2414 /* Clear/re-enable interrupt */
2415 ctrl->soc->ctlrdy_ack(ctrl->soc);
2416 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2419 list_for_each_entry(host, &ctrl->host_list, node) {
2420 struct nand_chip *chip = &host->chip;
2422 brcmnand_save_restore_cs_config(host, 1);
2424 /* Reset the chip, required by some chips after power-up */
2425 nand_reset_op(chip);
2431 const struct dev_pm_ops brcmnand_pm_ops = {
2432 .suspend = brcmnand_suspend,
2433 .resume = brcmnand_resume,
2435 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2437 static const struct of_device_id brcmnand_of_match[] = {
2438 { .compatible = "brcm,brcmnand-v4.0" },
2439 { .compatible = "brcm,brcmnand-v5.0" },
2440 { .compatible = "brcm,brcmnand-v6.0" },
2441 { .compatible = "brcm,brcmnand-v6.1" },
2442 { .compatible = "brcm,brcmnand-v6.2" },
2443 { .compatible = "brcm,brcmnand-v7.0" },
2444 { .compatible = "brcm,brcmnand-v7.1" },
2445 { .compatible = "brcm,brcmnand-v7.2" },
2448 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2450 /***********************************************************************
2451 * Platform driver setup (per controller)
2452 ***********************************************************************/
2454 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2456 struct device *dev = &pdev->dev;
2457 struct device_node *dn = dev->of_node, *child;
2458 struct brcmnand_controller *ctrl;
2459 struct resource *res;
2462 /* We only support device-tree instantiation */
2466 if (!of_match_node(brcmnand_of_match, dn))
2469 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2473 dev_set_drvdata(dev, ctrl);
2476 init_completion(&ctrl->done);
2477 init_completion(&ctrl->dma_done);
2478 nand_controller_init(&ctrl->controller);
2479 ctrl->controller.ops = &brcmnand_controller_ops;
2480 INIT_LIST_HEAD(&ctrl->host_list);
2482 /* NAND register range */
2483 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2484 ctrl->nand_base = devm_ioremap_resource(dev, res);
2485 if (IS_ERR(ctrl->nand_base))
2486 return PTR_ERR(ctrl->nand_base);
2488 /* Enable clock before using NAND registers */
2489 ctrl->clk = devm_clk_get(dev, "nand");
2490 if (!IS_ERR(ctrl->clk)) {
2491 ret = clk_prepare_enable(ctrl->clk);
2495 ret = PTR_ERR(ctrl->clk);
2496 if (ret == -EPROBE_DEFER)
2502 /* Initialize NAND revision */
2503 ret = brcmnand_revision_init(ctrl);
2508 * Most chips have this cache at a fixed offset within 'nand' block.
2509 * Some must specify this region separately.
2511 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2513 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2514 if (IS_ERR(ctrl->nand_fc)) {
2515 ret = PTR_ERR(ctrl->nand_fc);
2519 ctrl->nand_fc = ctrl->nand_base +
2520 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2524 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2526 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2527 if (IS_ERR(ctrl->flash_dma_base)) {
2528 ret = PTR_ERR(ctrl->flash_dma_base);
2532 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2533 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2535 /* Allocate descriptor(s) */
2536 ctrl->dma_desc = dmam_alloc_coherent(dev,
2537 sizeof(*ctrl->dma_desc),
2538 &ctrl->dma_pa, GFP_KERNEL);
2539 if (!ctrl->dma_desc) {
2544 ctrl->dma_irq = platform_get_irq(pdev, 1);
2545 if ((int)ctrl->dma_irq < 0) {
2546 dev_err(dev, "missing FLASH_DMA IRQ\n");
2551 ret = devm_request_irq(dev, ctrl->dma_irq,
2552 brcmnand_dma_irq, 0, DRV_NAME,
2555 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2556 ctrl->dma_irq, ret);
2560 dev_info(dev, "enabling FLASH_DMA\n");
2563 /* Disable automatic device ID config, direct addressing */
2564 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2565 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2566 /* Disable XOR addressing */
2567 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2569 if (ctrl->features & BRCMNAND_HAS_WP) {
2570 /* Permanently disable write protection */
2572 brcmnand_set_wp(ctrl, false);
2578 ctrl->irq = platform_get_irq(pdev, 0);
2579 if ((int)ctrl->irq < 0) {
2580 dev_err(dev, "no IRQ defined\n");
2586 * Some SoCs integrate this controller (e.g., its interrupt bits) in
2592 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2595 /* Enable interrupt */
2596 ctrl->soc->ctlrdy_ack(ctrl->soc);
2597 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2599 /* Use standard interrupt infrastructure */
2600 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2604 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2609 for_each_available_child_of_node(dn, child) {
2610 if (of_device_is_compatible(child, "brcm,nandcs")) {
2611 struct brcmnand_host *host;
2613 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2622 ret = brcmnand_init_cs(host, child);
2624 devm_kfree(dev, host);
2625 continue; /* Try all chip-selects */
2628 list_add_tail(&host->node, &ctrl->host_list);
2632 /* No chip-selects could initialize properly */
2633 if (list_empty(&ctrl->host_list)) {
2641 clk_disable_unprepare(ctrl->clk);
2645 EXPORT_SYMBOL_GPL(brcmnand_probe);
2647 int brcmnand_remove(struct platform_device *pdev)
2649 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2650 struct brcmnand_host *host;
2652 list_for_each_entry(host, &ctrl->host_list, node)
2653 nand_release(&host->chip);
2655 clk_disable_unprepare(ctrl->clk);
2657 dev_set_drvdata(&pdev->dev, NULL);
2661 EXPORT_SYMBOL_GPL(brcmnand_remove);
2663 MODULE_LICENSE("GPL v2");
2664 MODULE_AUTHOR("Kevin Cernekee");
2665 MODULE_AUTHOR("Brian Norris");
2666 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2667 MODULE_ALIAS("platform:brcmnand");