drivers/mtd/spi-nor/cadence-quadspi.c

   1 /*
   2  * Driver for Cadence QSPI Controller
   3  *
   4  * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include <linux/clk.h>
  19 #include <linux/completion.h>
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/err.h>
  24 #include <linux/errno.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/mtd/spi-nor.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/sched.h>
  38 #include <linux/spi/spi.h>
  39 #include <linux/timer.h>
  40
  41 #define CQSPI_NAME                      "cadence-qspi"
  42 #define CQSPI_MAX_CHIPSELECT            16
  43
  44 /* Quirks */
  45 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  46
  47 struct cqspi_st;
  48
  49 struct cqspi_flash_pdata {
  50         struct spi_nor  nor;
  51         struct cqspi_st *cqspi;
  52         u32             clk_rate;
  53         u32             read_delay;
  54         u32             tshsl_ns;
  55         u32             tsd2d_ns;
  56         u32             tchsh_ns;
  57         u32             tslch_ns;
  58         u8              inst_width;
  59         u8              addr_width;
  60         u8              data_width;
  61         u8              cs;
  62         bool            registered;
  63         bool            use_direct_mode;
  64 };
  65
  66 struct cqspi_st {
  67         struct platform_device  *pdev;
  68
  69         struct clk              *clk;
  70         unsigned int            sclk;
  71
  72         void __iomem            *iobase;
  73         void __iomem            *ahb_base;
  74         resource_size_t         ahb_size;
  75         struct completion       transfer_complete;
  76         struct mutex            bus_mutex;
  77
  78         struct dma_chan         *rx_chan;
  79         struct completion       rx_dma_complete;
  80         dma_addr_t              mmap_phys_base;
  81
  82         int                     current_cs;
  83         unsigned long           master_ref_clk_hz;
  84         bool                    is_decoded_cs;
  85         u32                     fifo_depth;
  86         u32                     fifo_width;
  87         bool                    rclk_en;
  88         u32                     trigger_address;
  89         u32                     wr_delay;
  90         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  91 };
  92
  93 /* Operation timeout value */
  94 #define CQSPI_TIMEOUT_MS                        500
  95 #define CQSPI_READ_TIMEOUT_MS                   10
  96
  97 /* Instruction type */
  98 #define CQSPI_INST_TYPE_SINGLE                  0
  99 #define CQSPI_INST_TYPE_DUAL                    1
 100 #define CQSPI_INST_TYPE_QUAD                    2
 101
 102 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
 103 #define CQSPI_DUMMY_BYTES_MAX                   4
 104 #define CQSPI_DUMMY_CLKS_MAX                    31
 105
 106 #define CQSPI_STIG_DATA_LEN_MAX                 8
 107
 108 /* Register map */
 109 #define CQSPI_REG_CONFIG                        0x00
 110 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 111 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL       BIT(7)
 112 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 113 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 114 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 115 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 116 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 117 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 118 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 119
 120 #define CQSPI_REG_RD_INSTR                      0x04
 121 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 122 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 123 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 124 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 125 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 126 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 127 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 128 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 129 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 130 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 131
 132 #define CQSPI_REG_WR_INSTR                      0x08
 133 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 134 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 135 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 136
 137 #define CQSPI_REG_DELAY                         0x0C
 138 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 139 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 140 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 141 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 142 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 143 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 144 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 145 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 146
 147 #define CQSPI_REG_READCAPTURE                   0x10
 148 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 149 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 150 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 151
 152 #define CQSPI_REG_SIZE                          0x14
 153 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 154 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 155 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 156 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 157 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 158 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 159
 160 #define CQSPI_REG_SRAMPARTITION                 0x18
 161 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 162
 163 #define CQSPI_REG_DMA                           0x20
 164 #define CQSPI_REG_DMA_SINGLE_LSB                0
 165 #define CQSPI_REG_DMA_BURST_LSB                 8
 166 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 167 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 168
 169 #define CQSPI_REG_REMAP                         0x24
 170 #define CQSPI_REG_MODE_BIT                      0x28
 171
 172 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 173 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 174 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 175 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 176 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 177
 178 #define CQSPI_REG_IRQSTATUS                     0x40
 179 #define CQSPI_REG_IRQMASK                       0x44
 180
 181 #define CQSPI_REG_INDIRECTRD                    0x60
 182 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 183 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 184 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 185
 186 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 187 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 188 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 189
 190 #define CQSPI_REG_CMDCTRL                       0x90
 191 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 192 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 193 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 194 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 195 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 196 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 197 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 198 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 199 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 200 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 201 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 202 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 203
 204 #define CQSPI_REG_INDIRECTWR                    0x70
 205 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 206 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 207 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 208
 209 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 210 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 211 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 212
 213 #define CQSPI_REG_CMDADDRESS                    0x94
 214 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 215 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 216 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 217 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 218
 219 /* Interrupt status bits */
 220 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 221 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 222 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 223 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 224 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 225 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 226 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 227 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 228
 229 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 230                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 231                                          CQSPI_REG_IRQ_IND_COMP)
 232
 233 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 234                                          CQSPI_REG_IRQ_WATERMARK        | \
 235                                          CQSPI_REG_IRQ_UNDERFLOW)
 236
 237 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 238
 239 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
 240 {
 241         unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 242         u32 val;
 243
 244         while (1) {
 245                 val = readl(reg);
 246                 if (clear)
 247                         val = ~val;
 248                 val &= mask;
 249
 250                 if (val == mask)
 251                         return 0;
 252
 253                 if (time_after(jiffies, end))
 254                         return -ETIMEDOUT;
 255         }
 256 }
 257
 258 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 259 {
 260         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 261
 262         return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
 263 }
 264
 265 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 266 {
 267         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 268
 269         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 270         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 271 }
 272
 273 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 274 {
 275         struct cqspi_st *cqspi = dev;
 276         unsigned int irq_status;
 277
 278         /* Read interrupt status */
 279         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 280
 281         /* Clear interrupt */
 282         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 283
 284         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 285
 286         if (irq_status)
 287                 complete(&cqspi->transfer_complete);
 288
 289         return IRQ_HANDLED;
 290 }
 291
 292 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
 293 {
 294         struct cqspi_flash_pdata *f_pdata = nor->priv;
 295         u32 rdreg = 0;
 296
 297         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 298         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 299         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 300
 301         return rdreg;
 302 }
 303
 304 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 305 {
 306         const unsigned int poll_idle_retry = 3;
 307         unsigned int count = 0;
 308         unsigned long timeout;
 309
 310         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 311         while (1) {
 312                 /*
 313                  * Read few times in succession to ensure the controller
 314                  * is indeed idle, that is, the bit does not transition
 315                  * low again.
 316                  */
 317                 if (cqspi_is_idle(cqspi))
 318                         count++;
 319                 else
 320                         count = 0;
 321
 322                 if (count >= poll_idle_retry)
 323                         return 0;
 324
 325                 if (time_after(jiffies, timeout)) {
 326                         /* Timeout, in busy mode. */
 327                         dev_err(&cqspi->pdev->dev,
 328                                 "QSPI is still busy after %dms timeout.\n",
 329                                 CQSPI_TIMEOUT_MS);
 330                         return -ETIMEDOUT;
 331                 }
 332
 333                 cpu_relax();
 334         }
 335 }
 336
 337 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 338 {
 339         void __iomem *reg_base = cqspi->iobase;
 340         int ret;
 341
 342         /* Write the CMDCTRL without start execution. */
 343         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 344         /* Start execute */
 345         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 346         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 347
 348         /* Polling for completion. */
 349         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 350                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 351         if (ret) {
 352                 dev_err(&cqspi->pdev->dev,
 353                         "Flash command execution timed out.\n");
 354                 return ret;
 355         }
 356
 357         /* Polling QSPI idle status. */
 358         return cqspi_wait_idle(cqspi);
 359 }
 360
 361 static int cqspi_command_read(struct spi_nor *nor,
 362                               const u8 *txbuf, const unsigned n_tx,
 363                               u8 *rxbuf, const unsigned n_rx)
 364 {
 365         struct cqspi_flash_pdata *f_pdata = nor->priv;
 366         struct cqspi_st *cqspi = f_pdata->cqspi;
 367         void __iomem *reg_base = cqspi->iobase;
 368         unsigned int rdreg;
 369         unsigned int reg;
 370         unsigned int read_len;
 371         int status;
 372
 373         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 374                 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
 375                         n_rx, rxbuf);
 376                 return -EINVAL;
 377         }
 378
 379         reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 380
 381         rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
 382         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 383
 384         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 385
 386         /* 0 means 1 byte. */
 387         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 388                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 389         status = cqspi_exec_flash_cmd(cqspi, reg);
 390         if (status)
 391                 return status;
 392
 393         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 394
 395         /* Put the read value into rx_buf */
 396         read_len = (n_rx > 4) ? 4 : n_rx;
 397         memcpy(rxbuf, &reg, read_len);
 398         rxbuf += read_len;
 399
 400         if (n_rx > 4) {
 401                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 402
 403                 read_len = n_rx - read_len;
 404                 memcpy(rxbuf, &reg, read_len);
 405         }
 406
 407         return 0;
 408 }
 409
 410 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
 411                                const u8 *txbuf, const unsigned n_tx)
 412 {
 413         struct cqspi_flash_pdata *f_pdata = nor->priv;
 414         struct cqspi_st *cqspi = f_pdata->cqspi;
 415         void __iomem *reg_base = cqspi->iobase;
 416         unsigned int reg;
 417         unsigned int data;
 418         int ret;
 419
 420         if (n_tx > 4 || (n_tx && !txbuf)) {
 421                 dev_err(nor->dev,
 422                         "Invalid input argument, cmdlen %d txbuf 0x%p\n",
 423                         n_tx, txbuf);
 424                 return -EINVAL;
 425         }
 426
 427         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 428         if (n_tx) {
 429                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 430                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 431                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 432                 data = 0;
 433                 memcpy(&data, txbuf, n_tx);
 434                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 435         }
 436
 437         ret = cqspi_exec_flash_cmd(cqspi, reg);
 438         return ret;
 439 }
 440
 441 static int cqspi_command_write_addr(struct spi_nor *nor,
 442                                     const u8 opcode, const unsigned int addr)
 443 {
 444         struct cqspi_flash_pdata *f_pdata = nor->priv;
 445         struct cqspi_st *cqspi = f_pdata->cqspi;
 446         void __iomem *reg_base = cqspi->iobase;
 447         unsigned int reg;
 448
 449         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 450         reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 451         reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 452                 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 453
 454         writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
 455
 456         return cqspi_exec_flash_cmd(cqspi, reg);
 457 }
 458
 459 static int cqspi_read_setup(struct spi_nor *nor)
 460 {
 461         struct cqspi_flash_pdata *f_pdata = nor->priv;
 462         struct cqspi_st *cqspi = f_pdata->cqspi;
 463         void __iomem *reg_base = cqspi->iobase;
 464         unsigned int dummy_clk = 0;
 465         unsigned int reg;
 466
 467         reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 468         reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
 469
 470         /* Setup dummy clock cycles */
 471         dummy_clk = nor->read_dummy;
 472         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 473                 return -EOPNOTSUPP;
 474
 475         if (dummy_clk / 8) {
 476                 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 477                 /* Set mode bits high to ensure chip doesn't enter XIP */
 478                 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
 479
 480                 /* Need to subtract the mode byte (8 clocks). */
 481                 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
 482                         dummy_clk -= 8;
 483
 484                 if (dummy_clk)
 485                         reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 486                                << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 487         }
 488
 489         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 490
 491         /* Set address width */
 492         reg = readl(reg_base + CQSPI_REG_SIZE);
 493         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 494         reg |= (nor->addr_width - 1);
 495         writel(reg, reg_base + CQSPI_REG_SIZE);
 496         return 0;
 497 }
 498
 499 static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
 500                                        loff_t from_addr, const size_t n_rx)
 501 {
 502         struct cqspi_flash_pdata *f_pdata = nor->priv;
 503         struct cqspi_st *cqspi = f_pdata->cqspi;
 504         void __iomem *reg_base = cqspi->iobase;
 505         void __iomem *ahb_base = cqspi->ahb_base;
 506         unsigned int remaining = n_rx;
 507         unsigned int mod_bytes = n_rx % 4;
 508         unsigned int bytes_to_read = 0;
 509         u8 *rxbuf_end = rxbuf + n_rx;
 510         int ret = 0;
 511
 512         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 513         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 514
 515         /* Clear all interrupts. */
 516         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 517
 518         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 519
 520         reinit_completion(&cqspi->transfer_complete);
 521         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 522                reg_base + CQSPI_REG_INDIRECTRD);
 523
 524         while (remaining > 0) {
 525                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 526                                 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
 527                         ret = -ETIMEDOUT;
 528
 529                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 530
 531                 if (ret && bytes_to_read == 0) {
 532                         dev_err(nor->dev, "Indirect read timeout, no bytes\n");
 533                         goto failrd;
 534                 }
 535
 536                 while (bytes_to_read != 0) {
 537                         unsigned int word_remain = round_down(remaining, 4);
 538
 539                         bytes_to_read *= cqspi->fifo_width;
 540                         bytes_to_read = bytes_to_read > remaining ?
 541                                         remaining : bytes_to_read;
 542                         bytes_to_read = round_down(bytes_to_read, 4);
 543                         /* Read 4 byte word chunks then single bytes */
 544                         if (bytes_to_read) {
 545                                 ioread32_rep(ahb_base, rxbuf,
 546                                              (bytes_to_read / 4));
 547                         } else if (!word_remain && mod_bytes) {
 548                                 unsigned int temp = ioread32(ahb_base);
 549
 550                                 bytes_to_read = mod_bytes;
 551                                 memcpy(rxbuf, &temp, min((unsigned int)
 552                                                          (rxbuf_end - rxbuf),
 553                                                          bytes_to_read));
 554                         }
 555                         rxbuf += bytes_to_read;
 556                         remaining -= bytes_to_read;
 557                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 558                 }
 559
 560                 if (remaining > 0)
 561                         reinit_completion(&cqspi->transfer_complete);
 562         }
 563
 564         /* Check indirect done status */
 565         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 566                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 567         if (ret) {
 568                 dev_err(nor->dev,
 569                         "Indirect read completion error (%i)\n", ret);
 570                 goto failrd;
 571         }
 572
 573         /* Disable interrupt */
 574         writel(0, reg_base + CQSPI_REG_IRQMASK);
 575
 576         /* Clear indirect completion status */
 577         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 578
 579         return 0;
 580
 581 failrd:
 582         /* Disable interrupt */
 583         writel(0, reg_base + CQSPI_REG_IRQMASK);
 584
 585         /* Cancel the indirect read */
 586         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 587                reg_base + CQSPI_REG_INDIRECTRD);
 588         return ret;
 589 }
 590
 591 static int cqspi_write_setup(struct spi_nor *nor)
 592 {
 593         unsigned int reg;
 594         struct cqspi_flash_pdata *f_pdata = nor->priv;
 595         struct cqspi_st *cqspi = f_pdata->cqspi;
 596         void __iomem *reg_base = cqspi->iobase;
 597
 598         /* Set opcode. */
 599         reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 600         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 601         reg = cqspi_calc_rdreg(nor, nor->program_opcode);
 602         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 603
 604         reg = readl(reg_base + CQSPI_REG_SIZE);
 605         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 606         reg |= (nor->addr_width - 1);
 607         writel(reg, reg_base + CQSPI_REG_SIZE);
 608         return 0;
 609 }
 610
 611 static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
 612                                         const u8 *txbuf, const size_t n_tx)
 613 {
 614         const unsigned int page_size = nor->page_size;
 615         struct cqspi_flash_pdata *f_pdata = nor->priv;
 616         struct cqspi_st *cqspi = f_pdata->cqspi;
 617         void __iomem *reg_base = cqspi->iobase;
 618         unsigned int remaining = n_tx;
 619         unsigned int write_bytes;
 620         int ret;
 621
 622         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 623         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 624
 625         /* Clear all interrupts. */
 626         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 627
 628         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 629
 630         reinit_completion(&cqspi->transfer_complete);
 631         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 632                reg_base + CQSPI_REG_INDIRECTWR);
 633         /*
 634          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
 635          * Controller programming sequence, couple of cycles of
 636          * QSPI_REF_CLK delay is required for the above bit to
 637          * be internally synchronized by the QSPI module. Provide 5
 638          * cycles of delay.
 639          */
 640         if (cqspi->wr_delay)
 641                 ndelay(cqspi->wr_delay);
 642
 643         while (remaining > 0) {
 644                 size_t write_words, mod_bytes;
 645
 646                 write_bytes = remaining > page_size ? page_size : remaining;
 647                 write_words = write_bytes / 4;
 648                 mod_bytes = write_bytes % 4;
 649                 /* Write 4 bytes at a time then single bytes. */
 650                 if (write_words) {
 651                         iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
 652                         txbuf += (write_words * 4);
 653                 }
 654                 if (mod_bytes) {
 655                         unsigned int temp = 0xFFFFFFFF;
 656
 657                         memcpy(&temp, txbuf, mod_bytes);
 658                         iowrite32(temp, cqspi->ahb_base);
 659                         txbuf += mod_bytes;
 660                 }
 661
 662                 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
 663                                         msecs_to_jiffies(CQSPI_TIMEOUT_MS))) {
 664                         dev_err(nor->dev, "Indirect write timeout\n");
 665                         ret = -ETIMEDOUT;
 666                         goto failwr;
 667                 }
 668
 669                 remaining -= write_bytes;
 670
 671                 if (remaining > 0)
 672                         reinit_completion(&cqspi->transfer_complete);
 673         }
 674
 675         /* Check indirect done status */
 676         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
 677                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
 678         if (ret) {
 679                 dev_err(nor->dev,
 680                         "Indirect write completion error (%i)\n", ret);
 681                 goto failwr;
 682         }
 683
 684         /* Disable interrupt. */
 685         writel(0, reg_base + CQSPI_REG_IRQMASK);
 686
 687         /* Clear indirect completion status */
 688         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
 689
 690         cqspi_wait_idle(cqspi);
 691
 692         return 0;
 693
 694 failwr:
 695         /* Disable interrupt. */
 696         writel(0, reg_base + CQSPI_REG_IRQMASK);
 697
 698         /* Cancel the indirect write */
 699         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 700                reg_base + CQSPI_REG_INDIRECTWR);
 701         return ret;
 702 }
 703
 704 static void cqspi_chipselect(struct spi_nor *nor)
 705 {
 706         struct cqspi_flash_pdata *f_pdata = nor->priv;
 707         struct cqspi_st *cqspi = f_pdata->cqspi;
 708         void __iomem *reg_base = cqspi->iobase;
 709         unsigned int chip_select = f_pdata->cs;
 710         unsigned int reg;
 711
 712         reg = readl(reg_base + CQSPI_REG_CONFIG);
 713         if (cqspi->is_decoded_cs) {
 714                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 715         } else {
 716                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 717
 718                 /* Convert CS if without decoder.
 719                  * CS0 to 4b'1110
 720                  * CS1 to 4b'1101
 721                  * CS2 to 4b'1011
 722                  * CS3 to 4b'0111
 723                  */
 724                 chip_select = 0xF & ~(1 << chip_select);
 725         }
 726
 727         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 728                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 729         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 730             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 731         writel(reg, reg_base + CQSPI_REG_CONFIG);
 732 }
 733
 734 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
 735                                            const unsigned int ns_val)
 736 {
 737         unsigned int ticks;
 738
 739         ticks = ref_clk_hz / 1000;      /* kHz */
 740         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
 741
 742         return ticks;
 743 }
 744
 745 static void cqspi_delay(struct spi_nor *nor)
 746 {
 747         struct cqspi_flash_pdata *f_pdata = nor->priv;
 748         struct cqspi_st *cqspi = f_pdata->cqspi;
 749         void __iomem *iobase = cqspi->iobase;
 750         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 751         unsigned int tshsl, tchsh, tslch, tsd2d;
 752         unsigned int reg;
 753         unsigned int tsclk;
 754
 755         /* calculate the number of ref ticks for one sclk tick */
 756         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
 757
 758         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
 759         /* this particular value must be at least one sclk */
 760         if (tshsl < tsclk)
 761                 tshsl = tsclk;
 762
 763         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
 764         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
 765         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
 766
 767         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 768                << CQSPI_REG_DELAY_TSHSL_LSB;
 769         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 770                 << CQSPI_REG_DELAY_TCHSH_LSB;
 771         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 772                 << CQSPI_REG_DELAY_TSLCH_LSB;
 773         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 774                 << CQSPI_REG_DELAY_TSD2D_LSB;
 775         writel(reg, iobase + CQSPI_REG_DELAY);
 776 }
 777
 778 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 779 {
 780         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 781         void __iomem *reg_base = cqspi->iobase;
 782         u32 reg, div;
 783
 784         /* Recalculate the baudrate divisor based on QSPI specification. */
 785         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 786
 787         reg = readl(reg_base + CQSPI_REG_CONFIG);
 788         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 789         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 790         writel(reg, reg_base + CQSPI_REG_CONFIG);
 791 }
 792
 793 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
 794                                    const bool bypass,
 795                                    const unsigned int delay)
 796 {
 797         void __iomem *reg_base = cqspi->iobase;
 798         unsigned int reg;
 799
 800         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
 801
 802         if (bypass)
 803                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 804         else
 805                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 806
 807         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
 808                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
 809
 810         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
 811                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
 812
 813         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
 814 }
 815
 816 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
 817 {
 818         void __iomem *reg_base = cqspi->iobase;
 819         unsigned int reg;
 820
 821         reg = readl(reg_base + CQSPI_REG_CONFIG);
 822
 823         if (enable)
 824                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 825         else
 826                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 827
 828         writel(reg, reg_base + CQSPI_REG_CONFIG);
 829 }
 830
 831 static void cqspi_configure(struct spi_nor *nor)
 832 {
 833         struct cqspi_flash_pdata *f_pdata = nor->priv;
 834         struct cqspi_st *cqspi = f_pdata->cqspi;
 835         const unsigned int sclk = f_pdata->clk_rate;
 836         int switch_cs = (cqspi->current_cs != f_pdata->cs);
 837         int switch_ck = (cqspi->sclk != sclk);
 838
 839         if (switch_cs || switch_ck)
 840                 cqspi_controller_enable(cqspi, 0);
 841
 842         /* Switch chip select. */
 843         if (switch_cs) {
 844                 cqspi->current_cs = f_pdata->cs;
 845                 cqspi_chipselect(nor);
 846         }
 847
 848         /* Setup baudrate divisor and delays */
 849         if (switch_ck) {
 850                 cqspi->sclk = sclk;
 851                 cqspi_config_baudrate_div(cqspi);
 852                 cqspi_delay(nor);
 853                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
 854                                        f_pdata->read_delay);
 855         }
 856
 857         if (switch_cs || switch_ck)
 858                 cqspi_controller_enable(cqspi, 1);
 859 }
 860
 861 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
 862 {
 863         struct cqspi_flash_pdata *f_pdata = nor->priv;
 864
 865         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
 866         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
 867         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 868
 869         if (read) {
 870                 switch (nor->read_proto) {
 871                 case SNOR_PROTO_1_1_1:
 872                         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 873                         break;
 874                 case SNOR_PROTO_1_1_2:
 875                         f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
 876                         break;
 877                 case SNOR_PROTO_1_1_4:
 878                         f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
 879                         break;
 880                 default:
 881                         return -EINVAL;
 882                 }
 883         }
 884
 885         cqspi_configure(nor);
 886
 887         return 0;
 888 }
 889
 890 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
 891                            size_t len, const u_char *buf)
 892 {
 893         struct cqspi_flash_pdata *f_pdata = nor->priv;
 894         struct cqspi_st *cqspi = f_pdata->cqspi;
 895         int ret;
 896
 897         ret = cqspi_set_protocol(nor, 0);
 898         if (ret)
 899                 return ret;
 900
 901         ret = cqspi_write_setup(nor);
 902         if (ret)
 903                 return ret;
 904
 905         if (f_pdata->use_direct_mode) {
 906                 memcpy_toio(cqspi->ahb_base + to, buf, len);
 907                 ret = cqspi_wait_idle(cqspi);
 908         } else {
 909                 ret = cqspi_indirect_write_execute(nor, to, buf, len);
 910         }
 911         if (ret)
 912                 return ret;
 913
 914         return len;
 915 }
 916
 917 static void cqspi_rx_dma_callback(void *param)
 918 {
 919         struct cqspi_st *cqspi = param;
 920
 921         complete(&cqspi->rx_dma_complete);
 922 }
 923
 924 static int cqspi_direct_read_execute(struct spi_nor *nor, u_char *buf,
 925                                      loff_t from, size_t len)
 926 {
 927         struct cqspi_flash_pdata *f_pdata = nor->priv;
 928         struct cqspi_st *cqspi = f_pdata->cqspi;
 929         enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 930         dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
 931         int ret = 0;
 932         struct dma_async_tx_descriptor *tx;
 933         dma_cookie_t cookie;
 934         dma_addr_t dma_dst;
 935
 936         if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
 937                 memcpy_fromio(buf, cqspi->ahb_base + from, len);
 938                 return 0;
 939         }
 940
 941         dma_dst = dma_map_single(nor->dev, buf, len, DMA_FROM_DEVICE);
 942         if (dma_mapping_error(nor->dev, dma_dst)) {
 943                 dev_err(nor->dev, "dma mapping failed\n");
 944                 return -ENOMEM;
 945         }
 946         tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
 947                                        len, flags);
 948         if (!tx) {
 949                 dev_err(nor->dev, "device_prep_dma_memcpy error\n");
 950                 ret = -EIO;
 951                 goto err_unmap;
 952         }
 953
 954         tx->callback = cqspi_rx_dma_callback;
 955         tx->callback_param = cqspi;
 956         cookie = tx->tx_submit(tx);
 957         reinit_completion(&cqspi->rx_dma_complete);
 958
 959         ret = dma_submit_error(cookie);
 960         if (ret) {
 961                 dev_err(nor->dev, "dma_submit_error %d\n", cookie);
 962                 ret = -EIO;
 963                 goto err_unmap;
 964         }
 965
 966         dma_async_issue_pending(cqspi->rx_chan);
 967         if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
 968                                          msecs_to_jiffies(len))) {
 969                 dmaengine_terminate_sync(cqspi->rx_chan);
 970                 dev_err(nor->dev, "DMA wait_for_completion_timeout\n");
 971                 ret = -ETIMEDOUT;
 972                 goto err_unmap;
 973         }
 974
 975 err_unmap:
 976         dma_unmap_single(nor->dev, dma_dst, len, DMA_FROM_DEVICE);
 977
 978         return ret;
 979 }
 980
 981 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
 982                           size_t len, u_char *buf)
 983 {
 984         struct cqspi_flash_pdata *f_pdata = nor->priv;
 985         int ret;
 986
 987         ret = cqspi_set_protocol(nor, 1);
 988         if (ret)
 989                 return ret;
 990
 991         ret = cqspi_read_setup(nor);
 992         if (ret)
 993                 return ret;
 994
 995         if (f_pdata->use_direct_mode)
 996                 ret = cqspi_direct_read_execute(nor, buf, from, len);
 997         else
 998                 ret = cqspi_indirect_read_execute(nor, buf, from, len);
 999         if (ret)
1000                 return ret;
1001
1002         return len;
1003 }
1004
1005 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
1006 {
1007         int ret;
1008
1009         ret = cqspi_set_protocol(nor, 0);
1010         if (ret)
1011                 return ret;
1012
1013         /* Send write enable, then erase commands. */
1014         ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
1015         if (ret)
1016                 return ret;
1017
1018         /* Set up command buffer. */
1019         ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
1020         if (ret)
1021                 return ret;
1022
1023         return 0;
1024 }
1025
1026 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
1027 {
1028         struct cqspi_flash_pdata *f_pdata = nor->priv;
1029         struct cqspi_st *cqspi = f_pdata->cqspi;
1030
1031         mutex_lock(&cqspi->bus_mutex);
1032
1033         return 0;
1034 }
1035
1036 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
1037 {
1038         struct cqspi_flash_pdata *f_pdata = nor->priv;
1039         struct cqspi_st *cqspi = f_pdata->cqspi;
1040
1041         mutex_unlock(&cqspi->bus_mutex);
1042 }
1043
1044 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1045 {
1046         int ret;
1047
1048         ret = cqspi_set_protocol(nor, 0);
1049         if (!ret)
1050                 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
1051
1052         return ret;
1053 }
1054
1055 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
1056 {
1057         int ret;
1058
1059         ret = cqspi_set_protocol(nor, 0);
1060         if (!ret)
1061                 ret = cqspi_command_write(nor, opcode, buf, len);
1062
1063         return ret;
1064 }
1065
1066 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
1067                                     struct cqspi_flash_pdata *f_pdata,
1068                                     struct device_node *np)
1069 {
1070         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
1071                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
1072                 return -ENXIO;
1073         }
1074
1075         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1076                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1077                 return -ENXIO;
1078         }
1079
1080         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1081                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1082                 return -ENXIO;
1083         }
1084
1085         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1086                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1087                 return -ENXIO;
1088         }
1089
1090         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1091                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1092                 return -ENXIO;
1093         }
1094
1095         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1096                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1097                 return -ENXIO;
1098         }
1099
1100         return 0;
1101 }
1102
1103 static int cqspi_of_get_pdata(struct platform_device *pdev)
1104 {
1105         struct device_node *np = pdev->dev.of_node;
1106         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1107
1108         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1109
1110         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1111                 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1112                 return -ENXIO;
1113         }
1114
1115         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1116                 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1117                 return -ENXIO;
1118         }
1119
1120         if (of_property_read_u32(np, "cdns,trigger-address",
1121                                  &cqspi->trigger_address)) {
1122                 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1123                 return -ENXIO;
1124         }
1125
1126         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1127
1128         return 0;
1129 }
1130
1131 static void cqspi_controller_init(struct cqspi_st *cqspi)
1132 {
1133         u32 reg;
1134
1135         cqspi_controller_enable(cqspi, 0);
1136
1137         /* Configure the remap address register, no remap */
1138         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1139
1140         /* Disable all interrupts. */
1141         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1142
1143         /* Configure the SRAM split to 1:1 . */
1144         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1145
1146         /* Load indirect trigger address. */
1147         writel(cqspi->trigger_address,
1148                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1149
1150         /* Program read watermark -- 1/2 of the FIFO. */
1151         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1152                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1153         /* Program write watermark -- 1/8 of the FIFO. */
1154         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1155                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1156
1157         /* Enable Direct Access Controller */
1158         reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1159         reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
1160         writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1161
1162         cqspi_controller_enable(cqspi, 1);
1163 }
1164
1165 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1166 {
1167         dma_cap_mask_t mask;
1168
1169         dma_cap_zero(mask);
1170         dma_cap_set(DMA_MEMCPY, mask);
1171
1172         cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1173         if (IS_ERR(cqspi->rx_chan)) {
1174                 int ret = PTR_ERR(cqspi->rx_chan);
1175
1176                 if (ret != -EPROBE_DEFER)
1177                         dev_err(&cqspi->pdev->dev, "No Rx DMA available\n");
1178                 cqspi->rx_chan = NULL;
1179                 return ret;
1180         }
1181         init_completion(&cqspi->rx_dma_complete);
1182
1183         return 0;
1184 }
1185
1186 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1187 {
1188         const struct spi_nor_hwcaps hwcaps = {
1189                 .mask = SNOR_HWCAPS_READ |
1190                         SNOR_HWCAPS_READ_FAST |
1191                         SNOR_HWCAPS_READ_1_1_2 |
1192                         SNOR_HWCAPS_READ_1_1_4 |
1193                         SNOR_HWCAPS_PP,
1194         };
1195         struct platform_device *pdev = cqspi->pdev;
1196         struct device *dev = &pdev->dev;
1197         struct cqspi_flash_pdata *f_pdata;
1198         struct spi_nor *nor;
1199         struct mtd_info *mtd;
1200         unsigned int cs;
1201         int i, ret;
1202
1203         /* Get flash device data */
1204         for_each_available_child_of_node(dev->of_node, np) {
1205                 ret = of_property_read_u32(np, "reg", &cs);
1206                 if (ret) {
1207                         dev_err(dev, "Couldn't determine chip select.\n");
1208                         goto err;
1209                 }
1210
1211                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1212                         ret = -EINVAL;
1213                         dev_err(dev, "Chip select %d out of range.\n", cs);
1214                         goto err;
1215                 }
1216
1217                 f_pdata = &cqspi->f_pdata[cs];
1218                 f_pdata->cqspi = cqspi;
1219                 f_pdata->cs = cs;
1220
1221                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1222                 if (ret)
1223                         goto err;
1224
1225                 nor = &f_pdata->nor;
1226                 mtd = &nor->mtd;
1227
1228                 mtd->priv = nor;
1229
1230                 nor->dev = dev;
1231                 spi_nor_set_flash_node(nor, np);
1232                 nor->priv = f_pdata;
1233
1234                 nor->read_reg = cqspi_read_reg;
1235                 nor->write_reg = cqspi_write_reg;
1236                 nor->read = cqspi_read;
1237                 nor->write = cqspi_write;
1238                 nor->erase = cqspi_erase;
1239                 nor->prepare = cqspi_prep;
1240                 nor->unprepare = cqspi_unprep;
1241
1242                 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1243                                            dev_name(dev), cs);
1244                 if (!mtd->name) {
1245                         ret = -ENOMEM;
1246                         goto err;
1247                 }
1248
1249                 ret = spi_nor_scan(nor, NULL, &hwcaps);
1250                 if (ret)
1251                         goto err;
1252
1253                 ret = mtd_device_register(mtd, NULL, 0);
1254                 if (ret)
1255                         goto err;
1256
1257                 f_pdata->registered = true;
1258
1259                 if (mtd->size <= cqspi->ahb_size) {
1260                         f_pdata->use_direct_mode = true;
1261                         dev_dbg(nor->dev, "using direct mode for %s\n",
1262                                 mtd->name);
1263
1264                         if (!cqspi->rx_chan) {
1265                                 ret = cqspi_request_mmap_dma(cqspi);
1266                                 if (ret == -EPROBE_DEFER)
1267                                         goto err;
1268                         }
1269                 }
1270         }
1271
1272         return 0;
1273
1274 err:
1275         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1276                 if (cqspi->f_pdata[i].registered)
1277                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1278         return ret;
1279 }
1280
1281 static int cqspi_probe(struct platform_device *pdev)
1282 {
1283         struct device_node *np = pdev->dev.of_node;
1284         struct device *dev = &pdev->dev;
1285         struct cqspi_st *cqspi;
1286         struct resource *res;
1287         struct resource *res_ahb;
1288         unsigned long data;
1289         int ret;
1290         int irq;
1291
1292         cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1293         if (!cqspi)
1294                 return -ENOMEM;
1295
1296         mutex_init(&cqspi->bus_mutex);
1297         cqspi->pdev = pdev;
1298         platform_set_drvdata(pdev, cqspi);
1299
1300         /* Obtain configuration from OF. */
1301         ret = cqspi_of_get_pdata(pdev);
1302         if (ret) {
1303                 dev_err(dev, "Cannot get mandatory OF data.\n");
1304                 return -ENODEV;
1305         }
1306
1307         /* Obtain QSPI clock. */
1308         cqspi->clk = devm_clk_get(dev, NULL);
1309         if (IS_ERR(cqspi->clk)) {
1310                 dev_err(dev, "Cannot claim QSPI clock.\n");
1311                 return PTR_ERR(cqspi->clk);
1312         }
1313
1314         /* Obtain and remap controller address. */
1315         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1316         cqspi->iobase = devm_ioremap_resource(dev, res);
1317         if (IS_ERR(cqspi->iobase)) {
1318                 dev_err(dev, "Cannot remap controller address.\n");
1319                 return PTR_ERR(cqspi->iobase);
1320         }
1321
1322         /* Obtain and remap AHB address. */
1323         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1324         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1325         if (IS_ERR(cqspi->ahb_base)) {
1326                 dev_err(dev, "Cannot remap AHB address.\n");
1327                 return PTR_ERR(cqspi->ahb_base);
1328         }
1329         cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1330         cqspi->ahb_size = resource_size(res_ahb);
1331
1332         init_completion(&cqspi->transfer_complete);
1333
1334         /* Obtain IRQ line. */
1335         irq = platform_get_irq(pdev, 0);
1336         if (irq < 0) {
1337                 dev_err(dev, "Cannot obtain IRQ.\n");
1338                 return -ENXIO;
1339         }
1340
1341         pm_runtime_enable(dev);
1342         ret = pm_runtime_get_sync(dev);
1343         if (ret < 0) {
1344                 pm_runtime_put_noidle(dev);
1345                 return ret;
1346         }
1347
1348         ret = clk_prepare_enable(cqspi->clk);
1349         if (ret) {
1350                 dev_err(dev, "Cannot enable QSPI clock.\n");
1351                 goto probe_clk_failed;
1352         }
1353
1354         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1355         data  = (unsigned long)of_device_get_match_data(dev);
1356         if (data & CQSPI_NEEDS_WR_DELAY)
1357                 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1358                                                    cqspi->master_ref_clk_hz);
1359
1360         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1361                                pdev->name, cqspi);
1362         if (ret) {
1363                 dev_err(dev, "Cannot request IRQ.\n");
1364                 goto probe_irq_failed;
1365         }
1366
1367         cqspi_wait_idle(cqspi);
1368         cqspi_controller_init(cqspi);
1369         cqspi->current_cs = -1;
1370         cqspi->sclk = 0;
1371
1372         ret = cqspi_setup_flash(cqspi, np);
1373         if (ret) {
1374                 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1375                 goto probe_setup_failed;
1376         }
1377
1378         return ret;
1379 probe_setup_failed:
1380         cqspi_controller_enable(cqspi, 0);
1381 probe_irq_failed:
1382         clk_disable_unprepare(cqspi->clk);
1383 probe_clk_failed:
1384         pm_runtime_put_sync(dev);
1385         pm_runtime_disable(dev);
1386         return ret;
1387 }
1388
1389 static int cqspi_remove(struct platform_device *pdev)
1390 {
1391         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1392         int i;
1393
1394         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1395                 if (cqspi->f_pdata[i].registered)
1396                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1397
1398         cqspi_controller_enable(cqspi, 0);
1399
1400         if (cqspi->rx_chan)
1401                 dma_release_channel(cqspi->rx_chan);
1402
1403         clk_disable_unprepare(cqspi->clk);
1404
1405         pm_runtime_put_sync(&pdev->dev);
1406         pm_runtime_disable(&pdev->dev);
1407
1408         return 0;
1409 }
1410
1411 #ifdef CONFIG_PM_SLEEP
1412 static int cqspi_suspend(struct device *dev)
1413 {
1414         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1415         struct spi_master *master = dev_get_drvdata(dev);
1416         int ret;
1417
1418         ret = spi_master_suspend(master);
1419         cqspi_controller_enable(cqspi, 0);
1420
1421         clk_disable_unprepare(cqspi->clk);
1422
1423         return ret;
1424 }
1425
1426 static int cqspi_resume(struct device *dev)
1427 {
1428         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1429         struct spi_master *master = dev_get_drvdata(dev);
1430
1431         clk_prepare_enable(cqspi->clk);
1432         cqspi_wait_idle(cqspi);
1433         cqspi_controller_init(cqspi);
1434
1435         cqspi->current_cs = -1;
1436         cqspi->sclk = 0;
1437
1438         return spi_master_resume(master);
1439 }
1440
1441 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1442         .suspend = cqspi_suspend,
1443         .resume = cqspi_resume,
1444 };
1445
1446 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1447 #else
1448 #define CQSPI_DEV_PM_OPS        NULL
1449 #endif
1450
1451 static const struct of_device_id cqspi_dt_ids[] = {
1452         {
1453                 .compatible = "cdns,qspi-nor",
1454                 .data = (void *)0,
1455         },
1456         {
1457                 .compatible = "ti,k2g-qspi",
1458                 .data = (void *)CQSPI_NEEDS_WR_DELAY,
1459         },
1460         { /* end of table */ }
1461 };
1462
1463 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1464
1465 static struct platform_driver cqspi_platform_driver = {
1466         .probe = cqspi_probe,
1467         .remove = cqspi_remove,
1468         .driver = {
1469                 .name = CQSPI_NAME,
1470                 .pm = CQSPI_DEV_PM_OPS,
1471                 .of_match_table = cqspi_dt_ids,
1472         },
1473 };
1474
1475 module_platform_driver(cqspi_platform_driver);
1476
1477 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1478 MODULE_LICENSE("GPL v2");
1479 MODULE_ALIAS("platform:" CQSPI_NAME);
1480 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1481 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");