drivers/net/can/grcan.c

   1 /*
   2  * Socket CAN driver for Aeroflex Gaisler GRCAN and GRHCAN.
   3  *
   4  * 2012 (c) Aeroflex Gaisler AB
   5  *
   6  * This driver supports GRCAN and GRHCAN CAN controllers available in the GRLIB
   7  * VHDL IP core library.
   8  *
   9  * Full documentation of the GRCAN core can be found here:
  10  * http://www.gaisler.com/products/grlib/grip.pdf
  11  *
  12  * See "Documentation/devicetree/bindings/net/can/grcan.txt" for information on
  13  * open firmware properties.
  14  *
  15  * See "Documentation/ABI/testing/sysfs-class-net-grcan" for information on the
  16  * sysfs interface.
  17  *
  18  * See "Documentation/admin-guide/kernel-parameters.rst" for information on the module
  19  * parameters.
  20  *
  21  * This program is free software; you can redistribute it and/or modify it
  22  * under the terms of the GNU General Public License as published by the
  23  * Free Software Foundation; either version 2 of the License, or (at your
  24  * option) any later version.
  25  *
  26  * Contributors: Andreas Larsson <andreas@gaisler.com>
  27  */
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/delay.h>
  34 #include <linux/io.h>
  35 #include <linux/can/dev.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/of_platform.h>
  38 #include <linux/of_irq.h>
  39
  40 #include <linux/dma-mapping.h>
  41
  42 #define DRV_NAME        "grcan"
  43
  44 #define GRCAN_NAPI_WEIGHT       32
  45
  46 #define GRCAN_RESERVE_SIZE(slot1, slot2) (((slot2) - (slot1)) / 4 - 1)
  47
  48 struct grcan_registers {
  49         u32 conf;       /* 0x00 */
  50         u32 stat;       /* 0x04 */
  51         u32 ctrl;       /* 0x08 */
  52         u32 __reserved1[GRCAN_RESERVE_SIZE(0x08, 0x18)];
  53         u32 smask;      /* 0x18 - CanMASK */
  54         u32 scode;      /* 0x1c - CanCODE */
  55         u32 __reserved2[GRCAN_RESERVE_SIZE(0x1c, 0x100)];
  56         u32 pimsr;      /* 0x100 */
  57         u32 pimr;       /* 0x104 */
  58         u32 pisr;       /* 0x108 */
  59         u32 pir;        /* 0x10C */
  60         u32 imr;        /* 0x110 */
  61         u32 picr;       /* 0x114 */
  62         u32 __reserved3[GRCAN_RESERVE_SIZE(0x114, 0x200)];
  63         u32 txctrl;     /* 0x200 */
  64         u32 txaddr;     /* 0x204 */
  65         u32 txsize;     /* 0x208 */
  66         u32 txwr;       /* 0x20C */
  67         u32 txrd;       /* 0x210 */
  68         u32 txirq;      /* 0x214 */
  69         u32 __reserved4[GRCAN_RESERVE_SIZE(0x214, 0x300)];
  70         u32 rxctrl;     /* 0x300 */
  71         u32 rxaddr;     /* 0x304 */
  72         u32 rxsize;     /* 0x308 */
  73         u32 rxwr;       /* 0x30C */
  74         u32 rxrd;       /* 0x310 */
  75         u32 rxirq;      /* 0x314 */
  76         u32 rxmask;     /* 0x318 */
  77         u32 rxcode;     /* 0x31C */
  78 };
  79
  80 #define GRCAN_CONF_ABORT        0x00000001
  81 #define GRCAN_CONF_ENABLE0      0x00000002
  82 #define GRCAN_CONF_ENABLE1      0x00000004
  83 #define GRCAN_CONF_SELECT       0x00000008
  84 #define GRCAN_CONF_SILENT       0x00000010
  85 #define GRCAN_CONF_SAM          0x00000020 /* Available in some hardware */
  86 #define GRCAN_CONF_BPR          0x00000300 /* Note: not BRP */
  87 #define GRCAN_CONF_RSJ          0x00007000
  88 #define GRCAN_CONF_PS1          0x00f00000
  89 #define GRCAN_CONF_PS2          0x000f0000
  90 #define GRCAN_CONF_SCALER       0xff000000
  91 #define GRCAN_CONF_OPERATION                                            \
  92         (GRCAN_CONF_ABORT | GRCAN_CONF_ENABLE0 | GRCAN_CONF_ENABLE1     \
  93          | GRCAN_CONF_SELECT | GRCAN_CONF_SILENT | GRCAN_CONF_SAM)
  94 #define GRCAN_CONF_TIMING                                               \
  95         (GRCAN_CONF_BPR | GRCAN_CONF_RSJ | GRCAN_CONF_PS1               \
  96          | GRCAN_CONF_PS2 | GRCAN_CONF_SCALER)
  97
  98 #define GRCAN_CONF_RSJ_MIN      1
  99 #define GRCAN_CONF_RSJ_MAX      4
 100 #define GRCAN_CONF_PS1_MIN      1
 101 #define GRCAN_CONF_PS1_MAX      15
 102 #define GRCAN_CONF_PS2_MIN      2
 103 #define GRCAN_CONF_PS2_MAX      8
 104 #define GRCAN_CONF_SCALER_MIN   0
 105 #define GRCAN_CONF_SCALER_MAX   255
 106 #define GRCAN_CONF_SCALER_INC   1
 107
 108 #define GRCAN_CONF_BPR_BIT      8
 109 #define GRCAN_CONF_RSJ_BIT      12
 110 #define GRCAN_CONF_PS1_BIT      20
 111 #define GRCAN_CONF_PS2_BIT      16
 112 #define GRCAN_CONF_SCALER_BIT   24
 113
 114 #define GRCAN_STAT_PASS         0x000001
 115 #define GRCAN_STAT_OFF          0x000002
 116 #define GRCAN_STAT_OR           0x000004
 117 #define GRCAN_STAT_AHBERR       0x000008
 118 #define GRCAN_STAT_ACTIVE       0x000010
 119 #define GRCAN_STAT_RXERRCNT     0x00ff00
 120 #define GRCAN_STAT_TXERRCNT     0xff0000
 121
 122 #define GRCAN_STAT_ERRCTR_RELATED       (GRCAN_STAT_PASS | GRCAN_STAT_OFF)
 123
 124 #define GRCAN_STAT_RXERRCNT_BIT 8
 125 #define GRCAN_STAT_TXERRCNT_BIT 16
 126
 127 #define GRCAN_STAT_ERRCNT_WARNING_LIMIT 96
 128 #define GRCAN_STAT_ERRCNT_PASSIVE_LIMIT 127
 129
 130 #define GRCAN_CTRL_RESET        0x2
 131 #define GRCAN_CTRL_ENABLE       0x1
 132
 133 #define GRCAN_TXCTRL_ENABLE     0x1
 134 #define GRCAN_TXCTRL_ONGOING    0x2
 135 #define GRCAN_TXCTRL_SINGLE     0x4
 136
 137 #define GRCAN_RXCTRL_ENABLE     0x1
 138 #define GRCAN_RXCTRL_ONGOING    0x2
 139
 140 /* Relative offset of IRQ sources to AMBA Plug&Play */
 141 #define GRCAN_IRQIX_IRQ         0
 142 #define GRCAN_IRQIX_TXSYNC      1
 143 #define GRCAN_IRQIX_RXSYNC      2
 144
 145 #define GRCAN_IRQ_PASS          0x00001
 146 #define GRCAN_IRQ_OFF           0x00002
 147 #define GRCAN_IRQ_OR            0x00004
 148 #define GRCAN_IRQ_RXAHBERR      0x00008
 149 #define GRCAN_IRQ_TXAHBERR      0x00010
 150 #define GRCAN_IRQ_RXIRQ         0x00020
 151 #define GRCAN_IRQ_TXIRQ         0x00040
 152 #define GRCAN_IRQ_RXFULL        0x00080
 153 #define GRCAN_IRQ_TXEMPTY       0x00100
 154 #define GRCAN_IRQ_RX            0x00200
 155 #define GRCAN_IRQ_TX            0x00400
 156 #define GRCAN_IRQ_RXSYNC        0x00800
 157 #define GRCAN_IRQ_TXSYNC        0x01000
 158 #define GRCAN_IRQ_RXERRCTR      0x02000
 159 #define GRCAN_IRQ_TXERRCTR      0x04000
 160 #define GRCAN_IRQ_RXMISS        0x08000
 161 #define GRCAN_IRQ_TXLOSS        0x10000
 162
 163 #define GRCAN_IRQ_NONE  0
 164 #define GRCAN_IRQ_ALL                                                   \
 165         (GRCAN_IRQ_PASS | GRCAN_IRQ_OFF | GRCAN_IRQ_OR                  \
 166          | GRCAN_IRQ_RXAHBERR | GRCAN_IRQ_TXAHBERR                      \
 167          | GRCAN_IRQ_RXIRQ | GRCAN_IRQ_TXIRQ                            \
 168          | GRCAN_IRQ_RXFULL | GRCAN_IRQ_TXEMPTY                         \
 169          | GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_RXSYNC               \
 170          | GRCAN_IRQ_TXSYNC | GRCAN_IRQ_RXERRCTR                        \
 171          | GRCAN_IRQ_TXERRCTR | GRCAN_IRQ_RXMISS                        \
 172          | GRCAN_IRQ_TXLOSS)
 173
 174 #define GRCAN_IRQ_ERRCTR_RELATED (GRCAN_IRQ_RXERRCTR | GRCAN_IRQ_TXERRCTR \
 175                                   | GRCAN_IRQ_PASS | GRCAN_IRQ_OFF)
 176 #define GRCAN_IRQ_ERRORS (GRCAN_IRQ_ERRCTR_RELATED | GRCAN_IRQ_OR       \
 177                           | GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR     \
 178                           | GRCAN_IRQ_TXLOSS)
 179 #define GRCAN_IRQ_DEFAULT (GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_ERRORS)
 180
 181 #define GRCAN_MSG_SIZE          16
 182
 183 #define GRCAN_MSG_IDE           0x80000000
 184 #define GRCAN_MSG_RTR           0x40000000
 185 #define GRCAN_MSG_BID           0x1ffc0000
 186 #define GRCAN_MSG_EID           0x1fffffff
 187 #define GRCAN_MSG_IDE_BIT       31
 188 #define GRCAN_MSG_RTR_BIT       30
 189 #define GRCAN_MSG_BID_BIT       18
 190 #define GRCAN_MSG_EID_BIT       0
 191
 192 #define GRCAN_MSG_DLC           0xf0000000
 193 #define GRCAN_MSG_TXERRC        0x00ff0000
 194 #define GRCAN_MSG_RXERRC        0x0000ff00
 195 #define GRCAN_MSG_DLC_BIT       28
 196 #define GRCAN_MSG_TXERRC_BIT    16
 197 #define GRCAN_MSG_RXERRC_BIT    8
 198 #define GRCAN_MSG_AHBERR        0x00000008
 199 #define GRCAN_MSG_OR            0x00000004
 200 #define GRCAN_MSG_OFF           0x00000002
 201 #define GRCAN_MSG_PASS          0x00000001
 202
 203 #define GRCAN_MSG_DATA_SLOT_INDEX(i) (2 + (i) / 4)
 204 #define GRCAN_MSG_DATA_SHIFT(i) ((3 - (i) % 4) * 8)
 205
 206 #define GRCAN_BUFFER_ALIGNMENT          1024
 207 #define GRCAN_DEFAULT_BUFFER_SIZE       1024
 208 #define GRCAN_VALID_TR_SIZE_MASK        0x001fffc0
 209
 210 #define GRCAN_INVALID_BUFFER_SIZE(s)                    \
 211         ((s) == 0 || ((s) & ~GRCAN_VALID_TR_SIZE_MASK))
 212
 213 #if GRCAN_INVALID_BUFFER_SIZE(GRCAN_DEFAULT_BUFFER_SIZE)
 214 #error "Invalid default buffer size"
 215 #endif
 216
 217 struct grcan_dma_buffer {
 218         size_t size;
 219         void *buf;
 220         dma_addr_t handle;
 221 };
 222
 223 struct grcan_dma {
 224         size_t base_size;
 225         void *base_buf;
 226         dma_addr_t base_handle;
 227         struct grcan_dma_buffer tx;
 228         struct grcan_dma_buffer rx;
 229 };
 230
 231 /* GRCAN configuration parameters */
 232 struct grcan_device_config {
 233         unsigned short enable0;
 234         unsigned short enable1;
 235         unsigned short select;
 236         unsigned int txsize;
 237         unsigned int rxsize;
 238 };
 239
 240 #define GRCAN_DEFAULT_DEVICE_CONFIG {                           \
 241                 .enable0        = 0,                            \
 242                 .enable1        = 0,                            \
 243                 .select         = 0,                            \
 244                 .txsize         = GRCAN_DEFAULT_BUFFER_SIZE,    \
 245                 .rxsize         = GRCAN_DEFAULT_BUFFER_SIZE,    \
 246                 }
 247
 248 #define GRCAN_TXBUG_SAFE_GRLIB_VERSION  4100
 249 #define GRLIB_VERSION_MASK              0xffff
 250
 251 /* GRCAN private data structure */
 252 struct grcan_priv {
 253         struct can_priv can;    /* must be the first member */
 254         struct net_device *dev;
 255         struct device *ofdev_dev;
 256         struct napi_struct napi;
 257
 258         struct grcan_registers __iomem *regs;   /* ioremap'ed registers */
 259         struct grcan_device_config config;
 260         struct grcan_dma dma;
 261
 262         struct sk_buff **echo_skb;      /* We allocate this on our own */
 263         u8 *txdlc;                      /* Length of queued frames */
 264
 265         /* The echo skb pointer, pointing into echo_skb and indicating which
 266          * frames can be echoed back. See the "Notes on the tx cyclic buffer
 267          * handling"-comment for grcan_start_xmit for more details.
 268          */
 269         u32 eskbp;
 270
 271         /* Lock for controlling changes to the netif tx queue state, accesses to
 272          * the echo_skb pointer eskbp and for making sure that a running reset
 273          * and/or a close of the interface is done without interference from
 274          * other parts of the code.
 275          *
 276          * The echo_skb pointer, eskbp, should only be accessed under this lock
 277          * as it can be changed in several places and together with decisions on
 278          * whether to wake up the tx queue.
 279          *
 280          * The tx queue must never be woken up if there is a running reset or
 281          * close in progress.
 282          *
 283          * A running reset (see below on need_txbug_workaround) should never be
 284          * done if the interface is closing down and several running resets
 285          * should never be scheduled simultaneously.
 286          */
 287         spinlock_t lock;
 288
 289         /* Whether a workaround is needed due to a bug in older hardware. In
 290          * this case, the driver both tries to prevent the bug from being
 291          * triggered and recovers, if the bug nevertheless happens, by doing a
 292          * running reset. A running reset, resets the device and continues from
 293          * where it were without being noticeable from outside the driver (apart
 294          * from slight delays).
 295          */
 296         bool need_txbug_workaround;
 297
 298         /* To trigger initization of running reset and to trigger running reset
 299          * respectively in the case of a hanged device due to a txbug.
 300          */
 301         struct timer_list hang_timer;
 302         struct timer_list rr_timer;
 303
 304         /* To avoid waking up the netif queue and restarting timers
 305          * when a reset is scheduled or when closing of the device is
 306          * undergoing
 307          */
 308         bool resetting;
 309         bool closing;
 310 };
 311
 312 /* Wait time for a short wait for ongoing to clear */
 313 #define GRCAN_SHORTWAIT_USECS   10
 314
 315 /* Limit on the number of transmitted bits of an eff frame according to the CAN
 316  * specification: 1 bit start of frame, 32 bits arbitration field, 6 bits
 317  * control field, 8 bytes data field, 16 bits crc field, 2 bits ACK field and 7
 318  * bits end of frame
 319  */
 320 #define GRCAN_EFF_FRAME_MAX_BITS        (1+32+6+8*8+16+2+7)
 321
 322 #if defined(__BIG_ENDIAN)
 323 static inline u32 grcan_read_reg(u32 __iomem *reg)
 324 {
 325         return ioread32be(reg);
 326 }
 327
 328 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
 329 {
 330         iowrite32be(val, reg);
 331 }
 332 #else
 333 static inline u32 grcan_read_reg(u32 __iomem *reg)
 334 {
 335         return ioread32(reg);
 336 }
 337
 338 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
 339 {
 340         iowrite32(val, reg);
 341 }
 342 #endif
 343
 344 static inline void grcan_clear_bits(u32 __iomem *reg, u32 mask)
 345 {
 346         grcan_write_reg(reg, grcan_read_reg(reg) & ~mask);
 347 }
 348
 349 static inline void grcan_set_bits(u32 __iomem *reg, u32 mask)
 350 {
 351         grcan_write_reg(reg, grcan_read_reg(reg) | mask);
 352 }
 353
 354 static inline u32 grcan_read_bits(u32 __iomem *reg, u32 mask)
 355 {
 356         return grcan_read_reg(reg) & mask;
 357 }
 358
 359 static inline void grcan_write_bits(u32 __iomem *reg, u32 value, u32 mask)
 360 {
 361         u32 old = grcan_read_reg(reg);
 362
 363         grcan_write_reg(reg, (old & ~mask) | (value & mask));
 364 }
 365
 366 /* a and b should both be in [0,size] and a == b == size should not hold */
 367 static inline u32 grcan_ring_add(u32 a, u32 b, u32 size)
 368 {
 369         u32 sum = a + b;
 370
 371         if (sum < size)
 372                 return sum;
 373         else
 374                 return sum - size;
 375 }
 376
 377 /* a and b should both be in [0,size) */
 378 static inline u32 grcan_ring_sub(u32 a, u32 b, u32 size)
 379 {
 380         return grcan_ring_add(a, size - b, size);
 381 }
 382
 383 /* Available slots for new transmissions */
 384 static inline u32 grcan_txspace(size_t txsize, u32 txwr, u32 eskbp)
 385 {
 386         u32 slots = txsize / GRCAN_MSG_SIZE - 1;
 387         u32 used = grcan_ring_sub(txwr, eskbp, txsize) / GRCAN_MSG_SIZE;
 388
 389         return slots - used;
 390 }
 391
 392 /* Configuration parameters that can be set via module parameters */
 393 static struct grcan_device_config grcan_module_config =
 394         GRCAN_DEFAULT_DEVICE_CONFIG;
 395
 396 static const struct can_bittiming_const grcan_bittiming_const = {
 397         .name           = DRV_NAME,
 398         .tseg1_min      = GRCAN_CONF_PS1_MIN + 1,
 399         .tseg1_max      = GRCAN_CONF_PS1_MAX + 1,
 400         .tseg2_min      = GRCAN_CONF_PS2_MIN,
 401         .tseg2_max      = GRCAN_CONF_PS2_MAX,
 402         .sjw_max        = GRCAN_CONF_RSJ_MAX,
 403         .brp_min        = GRCAN_CONF_SCALER_MIN + 1,
 404         .brp_max        = GRCAN_CONF_SCALER_MAX + 1,
 405         .brp_inc        = GRCAN_CONF_SCALER_INC,
 406 };
 407
 408 static int grcan_set_bittiming(struct net_device *dev)
 409 {
 410         struct grcan_priv *priv = netdev_priv(dev);
 411         struct grcan_registers __iomem *regs = priv->regs;
 412         struct can_bittiming *bt = &priv->can.bittiming;
 413         u32 timing = 0;
 414         int bpr, rsj, ps1, ps2, scaler;
 415
 416         /* Should never happen - function will not be called when
 417          * device is up
 418          */
 419         if (grcan_read_bits(&regs->ctrl, GRCAN_CTRL_ENABLE))
 420                 return -EBUSY;
 421
 422         bpr = 0; /* Note bpr and brp are different concepts */
 423         rsj = bt->sjw;
 424         ps1 = (bt->prop_seg + bt->phase_seg1) - 1; /* tseg1 - 1 */
 425         ps2 = bt->phase_seg2;
 426         scaler = (bt->brp - 1);
 427         netdev_dbg(dev, "Request for BPR=%d, RSJ=%d, PS1=%d, PS2=%d, SCALER=%d",
 428                    bpr, rsj, ps1, ps2, scaler);
 429         if (!(ps1 > ps2)) {
 430                 netdev_err(dev, "PS1 > PS2 must hold: PS1=%d, PS2=%d\n",
 431                            ps1, ps2);
 432                 return -EINVAL;
 433         }
 434         if (!(ps2 >= rsj)) {
 435                 netdev_err(dev, "PS2 >= RSJ must hold: PS2=%d, RSJ=%d\n",
 436                            ps2, rsj);
 437                 return -EINVAL;
 438         }
 439
 440         timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR;
 441         timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ;
 442         timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1;
 443         timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2;
 444         timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER;
 445         netdev_info(dev, "setting timing=0x%x\n", timing);
 446         grcan_write_bits(&regs->conf, timing, GRCAN_CONF_TIMING);
 447
 448         return 0;
 449 }
 450
 451 static int grcan_get_berr_counter(const struct net_device *dev,
 452                                   struct can_berr_counter *bec)
 453 {
 454         struct grcan_priv *priv = netdev_priv(dev);
 455         struct grcan_registers __iomem *regs = priv->regs;
 456         u32 status = grcan_read_reg(&regs->stat);
 457
 458         bec->txerr = (status & GRCAN_STAT_TXERRCNT) >> GRCAN_STAT_TXERRCNT_BIT;
 459         bec->rxerr = (status & GRCAN_STAT_RXERRCNT) >> GRCAN_STAT_RXERRCNT_BIT;
 460         return 0;
 461 }
 462
 463 static int grcan_poll(struct napi_struct *napi, int budget);
 464
 465 /* Reset device, but keep configuration information */
 466 static void grcan_reset(struct net_device *dev)
 467 {
 468         struct grcan_priv *priv = netdev_priv(dev);
 469         struct grcan_registers __iomem *regs = priv->regs;
 470         u32 config = grcan_read_reg(&regs->conf);
 471
 472         grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
 473         grcan_write_reg(&regs->conf, config);
 474
 475         priv->eskbp = grcan_read_reg(&regs->txrd);
 476         priv->can.state = CAN_STATE_STOPPED;
 477
 478         /* Turn off hardware filtering - regs->rxcode set to 0 by reset */
 479         grcan_write_reg(&regs->rxmask, 0);
 480 }
 481
 482 /* stop device without changing any configurations */
 483 static void grcan_stop_hardware(struct net_device *dev)
 484 {
 485         struct grcan_priv *priv = netdev_priv(dev);
 486         struct grcan_registers __iomem *regs = priv->regs;
 487
 488         grcan_write_reg(&regs->imr, GRCAN_IRQ_NONE);
 489         grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 490         grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 491         grcan_clear_bits(&regs->ctrl, GRCAN_CTRL_ENABLE);
 492 }
 493
 494 /* Let priv->eskbp catch up to regs->txrd and echo back the skbs if echo
 495  * is true and free them otherwise.
 496  *
 497  * If budget is >= 0, stop after handling at most budget skbs. Otherwise,
 498  * continue until priv->eskbp catches up to regs->txrd.
 499  *
 500  * priv->lock *must* be held when calling this function
 501  */
 502 static int catch_up_echo_skb(struct net_device *dev, int budget, bool echo)
 503 {
 504         struct grcan_priv *priv = netdev_priv(dev);
 505         struct grcan_registers __iomem *regs = priv->regs;
 506         struct grcan_dma *dma = &priv->dma;
 507         struct net_device_stats *stats = &dev->stats;
 508         int i, work_done;
 509
 510         /* Updates to priv->eskbp and wake-ups of the queue needs to
 511          * be atomic towards the reads of priv->eskbp and shut-downs
 512          * of the queue in grcan_start_xmit.
 513          */
 514         u32 txrd = grcan_read_reg(&regs->txrd);
 515
 516         for (work_done = 0; work_done < budget || budget < 0; work_done++) {
 517                 if (priv->eskbp == txrd)
 518                         break;
 519                 i = priv->eskbp / GRCAN_MSG_SIZE;
 520                 if (echo) {
 521                         /* Normal echo of messages */
 522                         stats->tx_packets++;
 523                         stats->tx_bytes += priv->txdlc[i];
 524                         priv->txdlc[i] = 0;
 525                         can_get_echo_skb(dev, i);
 526                 } else {
 527                         /* For cleanup of untransmitted messages */
 528                         can_free_echo_skb(dev, i);
 529                 }
 530
 531                 priv->eskbp = grcan_ring_add(priv->eskbp, GRCAN_MSG_SIZE,
 532                                              dma->tx.size);
 533                 txrd = grcan_read_reg(&regs->txrd);
 534         }
 535         return work_done;
 536 }
 537
 538 static void grcan_lost_one_shot_frame(struct net_device *dev)
 539 {
 540         struct grcan_priv *priv = netdev_priv(dev);
 541         struct grcan_registers __iomem *regs = priv->regs;
 542         struct grcan_dma *dma = &priv->dma;
 543         u32 txrd;
 544         unsigned long flags;
 545
 546         spin_lock_irqsave(&priv->lock, flags);
 547
 548         catch_up_echo_skb(dev, -1, true);
 549
 550         if (unlikely(grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE))) {
 551                 /* Should never happen */
 552                 netdev_err(dev, "TXCTRL enabled at TXLOSS in one shot mode\n");
 553         } else {
 554                 /* By the time an GRCAN_IRQ_TXLOSS is generated in
 555                  * one-shot mode there is no problem in writing
 556                  * to TXRD even in versions of the hardware in
 557                  * which GRCAN_TXCTRL_ONGOING is not cleared properly
 558                  * in one-shot mode.
 559                  */
 560
 561                 /* Skip message and discard echo-skb */
 562                 txrd = grcan_read_reg(&regs->txrd);
 563                 txrd = grcan_ring_add(txrd, GRCAN_MSG_SIZE, dma->tx.size);
 564                 grcan_write_reg(&regs->txrd, txrd);
 565                 catch_up_echo_skb(dev, -1, false);
 566
 567                 if (!priv->resetting && !priv->closing &&
 568                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) {
 569                         netif_wake_queue(dev);
 570                         grcan_set_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 571                 }
 572         }
 573
 574         spin_unlock_irqrestore(&priv->lock, flags);
 575 }
 576
 577 static void grcan_err(struct net_device *dev, u32 sources, u32 status)
 578 {
 579         struct grcan_priv *priv = netdev_priv(dev);
 580         struct grcan_registers __iomem *regs = priv->regs;
 581         struct grcan_dma *dma = &priv->dma;
 582         struct net_device_stats *stats = &dev->stats;
 583         struct can_frame cf;
 584
 585         /* Zero potential error_frame */
 586         memset(&cf, 0, sizeof(cf));
 587
 588         /* Message lost interrupt. This might be due to arbitration error, but
 589          * is also triggered when there is no one else on the can bus or when
 590          * there is a problem with the hardware interface or the bus itself. As
 591          * arbitration errors can not be singled out, no error frames are
 592          * generated reporting this event as an arbitration error.
 593          */
 594         if (sources & GRCAN_IRQ_TXLOSS) {
 595                 /* Take care of failed one-shot transmit */
 596                 if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
 597                         grcan_lost_one_shot_frame(dev);
 598
 599                 /* Stop printing as soon as error passive or bus off is in
 600                  * effect to limit the amount of txloss debug printouts.
 601                  */
 602                 if (!(status & GRCAN_STAT_ERRCTR_RELATED)) {
 603                         netdev_dbg(dev, "tx message lost\n");
 604                         stats->tx_errors++;
 605                 }
 606         }
 607
 608         /* Conditions dealing with the error counters. There is no interrupt for
 609          * error warning, but there are interrupts for increases of the error
 610          * counters.
 611          */
 612         if ((sources & GRCAN_IRQ_ERRCTR_RELATED) ||
 613             (status & GRCAN_STAT_ERRCTR_RELATED)) {
 614                 enum can_state state = priv->can.state;
 615                 enum can_state oldstate = state;
 616                 u32 txerr = (status & GRCAN_STAT_TXERRCNT)
 617                         >> GRCAN_STAT_TXERRCNT_BIT;
 618                 u32 rxerr = (status & GRCAN_STAT_RXERRCNT)
 619                         >> GRCAN_STAT_RXERRCNT_BIT;
 620
 621                 /* Figure out current state */
 622                 if (status & GRCAN_STAT_OFF) {
 623                         state = CAN_STATE_BUS_OFF;
 624                 } else if (status & GRCAN_STAT_PASS) {
 625                         state = CAN_STATE_ERROR_PASSIVE;
 626                 } else if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT ||
 627                            rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) {
 628                         state = CAN_STATE_ERROR_WARNING;
 629                 } else {
 630                         state = CAN_STATE_ERROR_ACTIVE;
 631                 }
 632
 633                 /* Handle and report state changes */
 634                 if (state != oldstate) {
 635                         switch (state) {
 636                         case CAN_STATE_BUS_OFF:
 637                                 netdev_dbg(dev, "bus-off\n");
 638                                 netif_carrier_off(dev);
 639                                 priv->can.can_stats.bus_off++;
 640
 641                                 /* Prevent the hardware from recovering from bus
 642                                  * off on its own if restart is disabled.
 643                                  */
 644                                 if (!priv->can.restart_ms)
 645                                         grcan_stop_hardware(dev);
 646
 647                                 cf.can_id |= CAN_ERR_BUSOFF;
 648                                 break;
 649
 650                         case CAN_STATE_ERROR_PASSIVE:
 651                                 netdev_dbg(dev, "Error passive condition\n");
 652                                 priv->can.can_stats.error_passive++;
 653
 654                                 cf.can_id |= CAN_ERR_CRTL;
 655                                 if (txerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
 656                                         cf.data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
 657                                 if (rxerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
 658                                         cf.data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
 659                                 break;
 660
 661                         case CAN_STATE_ERROR_WARNING:
 662                                 netdev_dbg(dev, "Error warning condition\n");
 663                                 priv->can.can_stats.error_warning++;
 664
 665                                 cf.can_id |= CAN_ERR_CRTL;
 666                                 if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
 667                                         cf.data[1] |= CAN_ERR_CRTL_TX_WARNING;
 668                                 if (rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
 669                                         cf.data[1] |= CAN_ERR_CRTL_RX_WARNING;
 670                                 break;
 671
 672                         case CAN_STATE_ERROR_ACTIVE:
 673                                 netdev_dbg(dev, "Error active condition\n");
 674                                 cf.can_id |= CAN_ERR_CRTL;
 675                                 break;
 676
 677                         default:
 678                                 /* There are no others at this point */
 679                                 break;
 680                         }
 681                         cf.data[6] = txerr;
 682                         cf.data[7] = rxerr;
 683                         priv->can.state = state;
 684                 }
 685
 686                 /* Report automatic restarts */
 687                 if (priv->can.restart_ms && oldstate == CAN_STATE_BUS_OFF) {
 688                         unsigned long flags;
 689
 690                         cf.can_id |= CAN_ERR_RESTARTED;
 691                         netdev_dbg(dev, "restarted\n");
 692                         priv->can.can_stats.restarts++;
 693                         netif_carrier_on(dev);
 694
 695                         spin_lock_irqsave(&priv->lock, flags);
 696
 697                         if (!priv->resetting && !priv->closing) {
 698                                 u32 txwr = grcan_read_reg(&regs->txwr);
 699
 700                                 if (grcan_txspace(dma->tx.size, txwr,
 701                                                   priv->eskbp))
 702                                         netif_wake_queue(dev);
 703                         }
 704
 705                         spin_unlock_irqrestore(&priv->lock, flags);
 706                 }
 707         }
 708
 709         /* Data overrun interrupt */
 710         if ((sources & GRCAN_IRQ_OR) || (status & GRCAN_STAT_OR)) {
 711                 netdev_dbg(dev, "got data overrun interrupt\n");
 712                 stats->rx_over_errors++;
 713                 stats->rx_errors++;
 714
 715                 cf.can_id |= CAN_ERR_CRTL;
 716                 cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
 717         }
 718
 719         /* AHB bus error interrupts (not CAN bus errors) - shut down the
 720          * device.
 721          */
 722         if (sources & (GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR) ||
 723             (status & GRCAN_STAT_AHBERR)) {
 724                 char *txrx = "";
 725                 unsigned long flags;
 726
 727                 if (sources & GRCAN_IRQ_TXAHBERR) {
 728                         txrx = "on tx ";
 729                         stats->tx_errors++;
 730                 } else if (sources & GRCAN_IRQ_RXAHBERR) {
 731                         txrx = "on rx ";
 732                         stats->rx_errors++;
 733                 }
 734                 netdev_err(dev, "Fatal AHB buss error %s- halting device\n",
 735                            txrx);
 736
 737                 spin_lock_irqsave(&priv->lock, flags);
 738
 739                 /* Prevent anything to be enabled again and halt device */
 740                 priv->closing = true;
 741                 netif_stop_queue(dev);
 742                 grcan_stop_hardware(dev);
 743                 priv->can.state = CAN_STATE_STOPPED;
 744
 745                 spin_unlock_irqrestore(&priv->lock, flags);
 746         }
 747
 748         /* Pass on error frame if something to report,
 749          * i.e. id contains some information
 750          */
 751         if (cf.can_id) {
 752                 struct can_frame *skb_cf;
 753                 struct sk_buff *skb = alloc_can_err_skb(dev, &skb_cf);
 754
 755                 if (skb == NULL) {
 756                         netdev_dbg(dev, "could not allocate error frame\n");
 757                         return;
 758                 }
 759                 skb_cf->can_id |= cf.can_id;
 760                 memcpy(skb_cf->data, cf.data, sizeof(cf.data));
 761
 762                 netif_rx(skb);
 763         }
 764 }
 765
 766 static irqreturn_t grcan_interrupt(int irq, void *dev_id)
 767 {
 768         struct net_device *dev = dev_id;
 769         struct grcan_priv *priv = netdev_priv(dev);
 770         struct grcan_registers __iomem *regs = priv->regs;
 771         u32 sources, status;
 772
 773         /* Find out the source */
 774         sources = grcan_read_reg(&regs->pimsr);
 775         if (!sources)
 776                 return IRQ_NONE;
 777         grcan_write_reg(&regs->picr, sources);
 778         status = grcan_read_reg(&regs->stat);
 779
 780         /* If we got TX progress, the device has not hanged,
 781          * so disable the hang timer
 782          */
 783         if (priv->need_txbug_workaround &&
 784             (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_TXLOSS))) {
 785                 del_timer(&priv->hang_timer);
 786         }
 787
 788         /* Frame(s) received or transmitted */
 789         if (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_RX)) {
 790                 /* Disable tx/rx interrupts and schedule poll(). No need for
 791                  * locking as interference from a running reset at worst leads
 792                  * to an extra interrupt.
 793                  */
 794                 grcan_clear_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
 795                 napi_schedule(&priv->napi);
 796         }
 797
 798         /* (Potential) error conditions to take care of */
 799         if (sources & GRCAN_IRQ_ERRORS)
 800                 grcan_err(dev, sources, status);
 801
 802         return IRQ_HANDLED;
 803 }
 804
 805 /* Reset device and restart operations from where they were.
 806  *
 807  * This assumes that RXCTRL & RXCTRL is properly disabled and that RX
 808  * is not ONGOING (TX might be stuck in ONGOING due to a harwrware bug
 809  * for single shot)
 810  */
 811 static void grcan_running_reset(struct timer_list *t)
 812 {
 813         struct grcan_priv *priv = from_timer(priv, t, rr_timer);
 814         struct net_device *dev = priv->dev;
 815         struct grcan_registers __iomem *regs = priv->regs;
 816         unsigned long flags;
 817
 818         /* This temporarily messes with eskbp, so we need to lock
 819          * priv->lock
 820          */
 821         spin_lock_irqsave(&priv->lock, flags);
 822
 823         priv->resetting = false;
 824         del_timer(&priv->hang_timer);
 825         del_timer(&priv->rr_timer);
 826
 827         if (!priv->closing) {
 828                 /* Save and reset - config register preserved by grcan_reset */
 829                 u32 imr = grcan_read_reg(&regs->imr);
 830
 831                 u32 txaddr = grcan_read_reg(&regs->txaddr);
 832                 u32 txsize = grcan_read_reg(&regs->txsize);
 833                 u32 txwr = grcan_read_reg(&regs->txwr);
 834                 u32 txrd = grcan_read_reg(&regs->txrd);
 835                 u32 eskbp = priv->eskbp;
 836
 837                 u32 rxaddr = grcan_read_reg(&regs->rxaddr);
 838                 u32 rxsize = grcan_read_reg(&regs->rxsize);
 839                 u32 rxwr = grcan_read_reg(&regs->rxwr);
 840                 u32 rxrd = grcan_read_reg(&regs->rxrd);
 841
 842                 grcan_reset(dev);
 843
 844                 /* Restore */
 845                 grcan_write_reg(&regs->txaddr, txaddr);
 846                 grcan_write_reg(&regs->txsize, txsize);
 847                 grcan_write_reg(&regs->txwr, txwr);
 848                 grcan_write_reg(&regs->txrd, txrd);
 849                 priv->eskbp = eskbp;
 850
 851                 grcan_write_reg(&regs->rxaddr, rxaddr);
 852                 grcan_write_reg(&regs->rxsize, rxsize);
 853                 grcan_write_reg(&regs->rxwr, rxwr);
 854                 grcan_write_reg(&regs->rxrd, rxrd);
 855
 856                 /* Turn on device again */
 857                 grcan_write_reg(&regs->imr, imr);
 858                 priv->can.state = CAN_STATE_ERROR_ACTIVE;
 859                 grcan_write_reg(&regs->txctrl, GRCAN_TXCTRL_ENABLE
 860                                 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
 861                                    ? GRCAN_TXCTRL_SINGLE : 0));
 862                 grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 863                 grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
 864
 865                 /* Start queue if there is size and listen-onle mode is not
 866                  * enabled
 867                  */
 868                 if (grcan_txspace(priv->dma.tx.size, txwr, priv->eskbp) &&
 869                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
 870                         netif_wake_queue(dev);
 871         }
 872
 873         spin_unlock_irqrestore(&priv->lock, flags);
 874
 875         netdev_err(dev, "Device reset and restored\n");
 876 }
 877
 878 /* Waiting time in usecs corresponding to the transmission of three maximum
 879  * sized can frames in the given bitrate (in bits/sec). Waiting for this amount
 880  * of time makes sure that the can controller have time to finish sending or
 881  * receiving a frame with a good margin.
 882  *
 883  * usecs/sec * number of frames * bits/frame / bits/sec
 884  */
 885 static inline u32 grcan_ongoing_wait_usecs(__u32 bitrate)
 886 {
 887         return 1000000 * 3 * GRCAN_EFF_FRAME_MAX_BITS / bitrate;
 888 }
 889
 890 /* Set timer so that it will not fire until after a period in which the can
 891  * controller have a good margin to finish transmitting a frame unless it has
 892  * hanged
 893  */
 894 static inline void grcan_reset_timer(struct timer_list *timer, __u32 bitrate)
 895 {
 896         u32 wait_jiffies = usecs_to_jiffies(grcan_ongoing_wait_usecs(bitrate));
 897
 898         mod_timer(timer, jiffies + wait_jiffies);
 899 }
 900
 901 /* Disable channels and schedule a running reset */
 902 static void grcan_initiate_running_reset(struct timer_list *t)
 903 {
 904         struct grcan_priv *priv = from_timer(priv, t, hang_timer);
 905         struct net_device *dev = priv->dev;
 906         struct grcan_registers __iomem *regs = priv->regs;
 907         unsigned long flags;
 908
 909         netdev_err(dev, "Device seems hanged - reset scheduled\n");
 910
 911         spin_lock_irqsave(&priv->lock, flags);
 912
 913         /* The main body of this function must never be executed again
 914          * until after an execution of grcan_running_reset
 915          */
 916         if (!priv->resetting && !priv->closing) {
 917                 priv->resetting = true;
 918                 netif_stop_queue(dev);
 919                 grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 920                 grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 921                 grcan_reset_timer(&priv->rr_timer, priv->can.bittiming.bitrate);
 922         }
 923
 924         spin_unlock_irqrestore(&priv->lock, flags);
 925 }
 926
 927 static void grcan_free_dma_buffers(struct net_device *dev)
 928 {
 929         struct grcan_priv *priv = netdev_priv(dev);
 930         struct grcan_dma *dma = &priv->dma;
 931
 932         dma_free_coherent(priv->ofdev_dev, dma->base_size, dma->base_buf,
 933                           dma->base_handle);
 934         memset(dma, 0, sizeof(*dma));
 935 }
 936
 937 static int grcan_allocate_dma_buffers(struct net_device *dev,
 938                                       size_t tsize, size_t rsize)
 939 {
 940         struct grcan_priv *priv = netdev_priv(dev);
 941         struct grcan_dma *dma = &priv->dma;
 942         struct grcan_dma_buffer *large = rsize > tsize ? &dma->rx : &dma->tx;
 943         struct grcan_dma_buffer *small = rsize > tsize ? &dma->tx : &dma->rx;
 944         size_t shift;
 945
 946         /* Need a whole number of GRCAN_BUFFER_ALIGNMENT for the large,
 947          * i.e. first buffer
 948          */
 949         size_t maxs = max(tsize, rsize);
 950         size_t lsize = ALIGN(maxs, GRCAN_BUFFER_ALIGNMENT);
 951
 952         /* Put the small buffer after that */
 953         size_t ssize = min(tsize, rsize);
 954
 955         /* Extra GRCAN_BUFFER_ALIGNMENT to allow for alignment */
 956         dma->base_size = lsize + ssize + GRCAN_BUFFER_ALIGNMENT;
 957         dma->base_buf = dma_alloc_coherent(priv->ofdev_dev,
 958                                            dma->base_size,
 959                                            &dma->base_handle,
 960                                            GFP_KERNEL);
 961
 962         if (!dma->base_buf)
 963                 return -ENOMEM;
 964
 965         dma->tx.size = tsize;
 966         dma->rx.size = rsize;
 967
 968         large->handle = ALIGN(dma->base_handle, GRCAN_BUFFER_ALIGNMENT);
 969         small->handle = large->handle + lsize;
 970         shift = large->handle - dma->base_handle;
 971
 972         large->buf = dma->base_buf + shift;
 973         small->buf = large->buf + lsize;
 974
 975         return 0;
 976 }
 977
 978 /* priv->lock *must* be held when calling this function */
 979 static int grcan_start(struct net_device *dev)
 980 {
 981         struct grcan_priv *priv = netdev_priv(dev);
 982         struct grcan_registers __iomem *regs = priv->regs;
 983         u32 confop, txctrl;
 984
 985         grcan_reset(dev);
 986
 987         grcan_write_reg(&regs->txaddr, priv->dma.tx.handle);
 988         grcan_write_reg(&regs->txsize, priv->dma.tx.size);
 989         /* regs->txwr, regs->txrd and priv->eskbp already set to 0 by reset */
 990
 991         grcan_write_reg(&regs->rxaddr, priv->dma.rx.handle);
 992         grcan_write_reg(&regs->rxsize, priv->dma.rx.size);
 993         /* regs->rxwr and regs->rxrd already set to 0 by reset */
 994
 995         /* Enable interrupts */
 996         grcan_read_reg(&regs->pir);
 997         grcan_write_reg(&regs->imr, GRCAN_IRQ_DEFAULT);
 998
 999         /* Enable interfaces, channels and device */
1000         confop = GRCAN_CONF_ABORT
1001                 | (priv->config.enable0 ? GRCAN_CONF_ENABLE0 : 0)
1002                 | (priv->config.enable1 ? GRCAN_CONF_ENABLE1 : 0)
1003                 | (priv->config.select ? GRCAN_CONF_SELECT : 0)
1004                 | (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY ?
1005                    GRCAN_CONF_SILENT : 0)
1006                 | (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
1007                    GRCAN_CONF_SAM : 0);
1008         grcan_write_bits(&regs->conf, confop, GRCAN_CONF_OPERATION);
1009         txctrl = GRCAN_TXCTRL_ENABLE
1010                 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
1011                    ? GRCAN_TXCTRL_SINGLE : 0);
1012         grcan_write_reg(&regs->txctrl, txctrl);
1013         grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
1014         grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
1015
1016         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1017
1018         return 0;
1019 }
1020
1021 static int grcan_set_mode(struct net_device *dev, enum can_mode mode)
1022 {
1023         struct grcan_priv *priv = netdev_priv(dev);
1024         unsigned long flags;
1025         int err = 0;
1026
1027         if (mode == CAN_MODE_START) {
1028                 /* This might be called to restart the device to recover from
1029                  * bus off errors
1030                  */
1031                 spin_lock_irqsave(&priv->lock, flags);
1032                 if (priv->closing || priv->resetting) {
1033                         err = -EBUSY;
1034                 } else {
1035                         netdev_info(dev, "Restarting device\n");
1036                         grcan_start(dev);
1037                         if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1038                                 netif_wake_queue(dev);
1039                 }
1040                 spin_unlock_irqrestore(&priv->lock, flags);
1041                 return err;
1042         }
1043         return -EOPNOTSUPP;
1044 }
1045
1046 static int grcan_open(struct net_device *dev)
1047 {
1048         struct grcan_priv *priv = netdev_priv(dev);
1049         struct grcan_dma *dma = &priv->dma;
1050         unsigned long flags;
1051         int err;
1052
1053         /* Allocate memory */
1054         err = grcan_allocate_dma_buffers(dev, priv->config.txsize,
1055                                          priv->config.rxsize);
1056         if (err) {
1057                 netdev_err(dev, "could not allocate DMA buffers\n");
1058                 return err;
1059         }
1060
1061         priv->echo_skb = kcalloc(dma->tx.size, sizeof(*priv->echo_skb),
1062                                  GFP_KERNEL);
1063         if (!priv->echo_skb) {
1064                 err = -ENOMEM;
1065                 goto exit_free_dma_buffers;
1066         }
1067         priv->can.echo_skb_max = dma->tx.size;
1068         priv->can.echo_skb = priv->echo_skb;
1069
1070         priv->txdlc = kcalloc(dma->tx.size, sizeof(*priv->txdlc), GFP_KERNEL);
1071         if (!priv->txdlc) {
1072                 err = -ENOMEM;
1073                 goto exit_free_echo_skb;
1074         }
1075
1076         /* Get can device up */
1077         err = open_candev(dev);
1078         if (err)
1079                 goto exit_free_txdlc;
1080
1081         err = request_irq(dev->irq, grcan_interrupt, IRQF_SHARED,
1082                           dev->name, dev);
1083         if (err)
1084                 goto exit_close_candev;
1085
1086         spin_lock_irqsave(&priv->lock, flags);
1087
1088         napi_enable(&priv->napi);
1089         grcan_start(dev);
1090         if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1091                 netif_start_queue(dev);
1092         priv->resetting = false;
1093         priv->closing = false;
1094
1095         spin_unlock_irqrestore(&priv->lock, flags);
1096
1097         return 0;
1098
1099 exit_close_candev:
1100         close_candev(dev);
1101 exit_free_txdlc:
1102         kfree(priv->txdlc);
1103 exit_free_echo_skb:
1104         kfree(priv->echo_skb);
1105 exit_free_dma_buffers:
1106         grcan_free_dma_buffers(dev);
1107         return err;
1108 }
1109
1110 static int grcan_close(struct net_device *dev)
1111 {
1112         struct grcan_priv *priv = netdev_priv(dev);
1113         unsigned long flags;
1114
1115         napi_disable(&priv->napi);
1116
1117         spin_lock_irqsave(&priv->lock, flags);
1118
1119         priv->closing = true;
1120         if (priv->need_txbug_workaround) {
1121                 spin_unlock_irqrestore(&priv->lock, flags);
1122                 del_timer_sync(&priv->hang_timer);
1123                 del_timer_sync(&priv->rr_timer);
1124                 spin_lock_irqsave(&priv->lock, flags);
1125         }
1126         netif_stop_queue(dev);
1127         grcan_stop_hardware(dev);
1128         priv->can.state = CAN_STATE_STOPPED;
1129
1130         spin_unlock_irqrestore(&priv->lock, flags);
1131
1132         free_irq(dev->irq, dev);
1133         close_candev(dev);
1134
1135         grcan_free_dma_buffers(dev);
1136         priv->can.echo_skb_max = 0;
1137         priv->can.echo_skb = NULL;
1138         kfree(priv->echo_skb);
1139         kfree(priv->txdlc);
1140
1141         return 0;
1142 }
1143
1144 static void grcan_transmit_catch_up(struct net_device *dev)
1145 {
1146         struct grcan_priv *priv = netdev_priv(dev);
1147         unsigned long flags;
1148         int work_done;
1149
1150         spin_lock_irqsave(&priv->lock, flags);
1151
1152         work_done = catch_up_echo_skb(dev, -1, true);
1153         if (work_done) {
1154                 if (!priv->resetting && !priv->closing &&
1155                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1156                         netif_wake_queue(dev);
1157
1158                 /* With napi we don't get TX interrupts for a while,
1159                  * so prevent a running reset while catching up
1160                  */
1161                 if (priv->need_txbug_workaround)
1162                         del_timer(&priv->hang_timer);
1163         }
1164
1165         spin_unlock_irqrestore(&priv->lock, flags);
1166 }
1167
1168 static int grcan_receive(struct net_device *dev, int budget)
1169 {
1170         struct grcan_priv *priv = netdev_priv(dev);
1171         struct grcan_registers __iomem *regs = priv->regs;
1172         struct grcan_dma *dma = &priv->dma;
1173         struct net_device_stats *stats = &dev->stats;
1174         struct can_frame *cf;
1175         struct sk_buff *skb;
1176         u32 wr, rd, startrd;
1177         u32 *slot;
1178         u32 i, rtr, eff, j, shift;
1179         int work_done = 0;
1180
1181         rd = grcan_read_reg(&regs->rxrd);
1182         startrd = rd;
1183         for (work_done = 0; work_done < budget; work_done++) {
1184                 /* Check for packet to receive */
1185                 wr = grcan_read_reg(&regs->rxwr);
1186                 if (rd == wr)
1187                         break;
1188
1189                 /* Take care of packet */
1190                 skb = alloc_can_skb(dev, &cf);
1191                 if (skb == NULL) {
1192                         netdev_err(dev,
1193                                    "dropping frame: skb allocation failed\n");
1194                         stats->rx_dropped++;
1195                         continue;
1196                 }
1197
1198                 slot = dma->rx.buf + rd;
1199                 eff = slot[0] & GRCAN_MSG_IDE;
1200                 rtr = slot[0] & GRCAN_MSG_RTR;
1201                 if (eff) {
1202                         cf->can_id = ((slot[0] & GRCAN_MSG_EID)
1203                                       >> GRCAN_MSG_EID_BIT);
1204                         cf->can_id |= CAN_EFF_FLAG;
1205                 } else {
1206                         cf->can_id = ((slot[0] & GRCAN_MSG_BID)
1207                                       >> GRCAN_MSG_BID_BIT);
1208                 }
1209                 cf->can_dlc = get_can_dlc((slot[1] & GRCAN_MSG_DLC)
1210                                           >> GRCAN_MSG_DLC_BIT);
1211                 if (rtr) {
1212                         cf->can_id |= CAN_RTR_FLAG;
1213                 } else {
1214                         for (i = 0; i < cf->can_dlc; i++) {
1215                                 j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1216                                 shift = GRCAN_MSG_DATA_SHIFT(i);
1217                                 cf->data[i] = (u8)(slot[j] >> shift);
1218                         }
1219                 }
1220
1221                 /* Update statistics and read pointer */
1222                 stats->rx_packets++;
1223                 stats->rx_bytes += cf->can_dlc;
1224                 netif_receive_skb(skb);
1225
1226                 rd = grcan_ring_add(rd, GRCAN_MSG_SIZE, dma->rx.size);
1227         }
1228
1229         /* Make sure everything is read before allowing hardware to
1230          * use the memory
1231          */
1232         mb();
1233
1234         /* Update read pointer - no need to check for ongoing */
1235         if (likely(rd != startrd))
1236                 grcan_write_reg(&regs->rxrd, rd);
1237
1238         return work_done;
1239 }
1240
1241 static int grcan_poll(struct napi_struct *napi, int budget)
1242 {
1243         struct grcan_priv *priv = container_of(napi, struct grcan_priv, napi);
1244         struct net_device *dev = priv->dev;
1245         struct grcan_registers __iomem *regs = priv->regs;
1246         unsigned long flags;
1247         int work_done;
1248
1249         work_done = grcan_receive(dev, budget);
1250
1251         grcan_transmit_catch_up(dev);
1252
1253         if (work_done < budget) {
1254                 napi_complete(napi);
1255
1256                 /* Guarantee no interference with a running reset that otherwise
1257                  * could turn off interrupts.
1258                  */
1259                 spin_lock_irqsave(&priv->lock, flags);
1260
1261                 /* Enable tx and rx interrupts again. No need to check
1262                  * priv->closing as napi_disable in grcan_close is waiting for
1263                  * scheduled napi calls to finish.
1264                  */
1265                 grcan_set_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
1266
1267                 spin_unlock_irqrestore(&priv->lock, flags);
1268         }
1269
1270         return work_done;
1271 }
1272
1273 /* Work tx bug by waiting while for the risky situation to clear. If that fails,
1274  * drop a frame in one-shot mode or indicate a busy device otherwise.
1275  *
1276  * Returns 0 on successful wait. Otherwise it sets *netdev_tx_status to the
1277  * value that should be returned by grcan_start_xmit when aborting the xmit.
1278  */
1279 static int grcan_txbug_workaround(struct net_device *dev, struct sk_buff *skb,
1280                                   u32 txwr, u32 oneshotmode,
1281                                   netdev_tx_t *netdev_tx_status)
1282 {
1283         struct grcan_priv *priv = netdev_priv(dev);
1284         struct grcan_registers __iomem *regs = priv->regs;
1285         struct grcan_dma *dma = &priv->dma;
1286         int i;
1287         unsigned long flags;
1288
1289         /* Wait a while for ongoing to be cleared or read pointer to catch up to
1290          * write pointer. The latter is needed due to a bug in older versions of
1291          * GRCAN in which ONGOING is not cleared properly one-shot mode when a
1292          * transmission fails.
1293          */
1294         for (i = 0; i < GRCAN_SHORTWAIT_USECS; i++) {
1295                 udelay(1);
1296                 if (!grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ONGOING) ||
1297                     grcan_read_reg(&regs->txrd) == txwr) {
1298                         return 0;
1299                 }
1300         }
1301
1302         /* Clean up, in case the situation was not resolved */
1303         spin_lock_irqsave(&priv->lock, flags);
1304         if (!priv->resetting && !priv->closing) {
1305                 /* Queue might have been stopped earlier in grcan_start_xmit */
1306                 if (grcan_txspace(dma->tx.size, txwr, priv->eskbp))
1307                         netif_wake_queue(dev);
1308                 /* Set a timer to resolve a hanged tx controller */
1309                 if (!timer_pending(&priv->hang_timer))
1310                         grcan_reset_timer(&priv->hang_timer,
1311                                           priv->can.bittiming.bitrate);
1312         }
1313         spin_unlock_irqrestore(&priv->lock, flags);
1314
1315         if (oneshotmode) {
1316                 /* In one-shot mode we should never end up here because
1317                  * then the interrupt handler increases txrd on TXLOSS,
1318                  * but it is consistent with one-shot mode to drop the
1319                  * frame in this case.
1320                  */
1321                 kfree_skb(skb);
1322                 *netdev_tx_status = NETDEV_TX_OK;
1323         } else {
1324                 /* In normal mode the socket-can transmission queue get
1325                  * to keep the frame so that it can be retransmitted
1326                  * later
1327                  */
1328                 *netdev_tx_status = NETDEV_TX_BUSY;
1329         }
1330         return -EBUSY;
1331 }
1332
1333 /* Notes on the tx cyclic buffer handling:
1334  *
1335  * regs->txwr   - the next slot for the driver to put data to be sent
1336  * regs->txrd   - the next slot for the device to read data
1337  * priv->eskbp  - the next slot for the driver to call can_put_echo_skb for
1338  *
1339  * grcan_start_xmit can enter more messages as long as regs->txwr does
1340  * not reach priv->eskbp (within 1 message gap)
1341  *
1342  * The device sends messages until regs->txrd reaches regs->txwr
1343  *
1344  * The interrupt calls handler calls can_put_echo_skb until
1345  * priv->eskbp reaches regs->txrd
1346  */
1347 static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
1348                                     struct net_device *dev)
1349 {
1350         struct grcan_priv *priv = netdev_priv(dev);
1351         struct grcan_registers __iomem *regs = priv->regs;
1352         struct grcan_dma *dma = &priv->dma;
1353         struct can_frame *cf = (struct can_frame *)skb->data;
1354         u32 id, txwr, txrd, space, txctrl;
1355         int slotindex;
1356         u32 *slot;
1357         u32 i, rtr, eff, dlc, tmp, err;
1358         int j, shift;
1359         unsigned long flags;
1360         u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;
1361
1362         if (can_dropped_invalid_skb(dev, skb))
1363                 return NETDEV_TX_OK;
1364
1365         /* Trying to transmit in silent mode will generate error interrupts, but
1366          * this should never happen - the queue should not have been started.
1367          */
1368         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1369                 return NETDEV_TX_BUSY;
1370
1371         /* Reads of priv->eskbp and shut-downs of the queue needs to
1372          * be atomic towards the updates to priv->eskbp and wake-ups
1373          * of the queue in the interrupt handler.
1374          */
1375         spin_lock_irqsave(&priv->lock, flags);
1376
1377         txwr = grcan_read_reg(&regs->txwr);
1378         space = grcan_txspace(dma->tx.size, txwr, priv->eskbp);
1379
1380         slotindex = txwr / GRCAN_MSG_SIZE;
1381         slot = dma->tx.buf + txwr;
1382
1383         if (unlikely(space == 1))
1384                 netif_stop_queue(dev);
1385
1386         spin_unlock_irqrestore(&priv->lock, flags);
1387         /* End of critical section*/
1388
1389         /* This should never happen. If circular buffer is full, the
1390          * netif_stop_queue should have been stopped already.
1391          */
1392         if (unlikely(!space)) {
1393                 netdev_err(dev, "No buffer space, but queue is non-stopped.\n");
1394                 return NETDEV_TX_BUSY;
1395         }
1396
1397         /* Convert and write CAN message to DMA buffer */
1398         eff = cf->can_id & CAN_EFF_FLAG;
1399         rtr = cf->can_id & CAN_RTR_FLAG;
1400         id = cf->can_id & (eff ? CAN_EFF_MASK : CAN_SFF_MASK);
1401         dlc = cf->can_dlc;
1402         if (eff)
1403                 tmp = (id << GRCAN_MSG_EID_BIT) & GRCAN_MSG_EID;
1404         else
1405                 tmp = (id << GRCAN_MSG_BID_BIT) & GRCAN_MSG_BID;
1406         slot[0] = (eff ? GRCAN_MSG_IDE : 0) | (rtr ? GRCAN_MSG_RTR : 0) | tmp;
1407
1408         slot[1] = ((dlc << GRCAN_MSG_DLC_BIT) & GRCAN_MSG_DLC);
1409         slot[2] = 0;
1410         slot[3] = 0;
1411         for (i = 0; i < dlc; i++) {
1412                 j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1413                 shift = GRCAN_MSG_DATA_SHIFT(i);
1414                 slot[j] |= cf->data[i] << shift;
1415         }
1416
1417         /* Checking that channel has not been disabled. These cases
1418          * should never happen
1419          */
1420         txctrl = grcan_read_reg(&regs->txctrl);
1421         if (!(txctrl & GRCAN_TXCTRL_ENABLE))
1422                 netdev_err(dev, "tx channel spuriously disabled\n");
1423
1424         if (oneshotmode && !(txctrl & GRCAN_TXCTRL_SINGLE))
1425                 netdev_err(dev, "one-shot mode spuriously disabled\n");
1426
1427         /* Bug workaround for old version of grcan where updating txwr
1428          * in the same clock cycle as the controller updates txrd to
1429          * the current txwr could hang the can controller
1430          */
1431         if (priv->need_txbug_workaround) {
1432                 txrd = grcan_read_reg(&regs->txrd);
1433                 if (unlikely(grcan_ring_sub(txwr, txrd, dma->tx.size) == 1)) {
1434                         netdev_tx_t txstatus;
1435
1436                         err = grcan_txbug_workaround(dev, skb, txwr,
1437                                                      oneshotmode, &txstatus);
1438                         if (err)
1439                                 return txstatus;
1440                 }
1441         }
1442
1443         /* Prepare skb for echoing. This must be after the bug workaround above
1444          * as ownership of the skb is passed on by calling can_put_echo_skb.
1445          * Returning NETDEV_TX_BUSY or accessing skb or cf after a call to
1446          * can_put_echo_skb would be an error unless other measures are
1447          * taken.
1448          */
1449         priv->txdlc[slotindex] = cf->can_dlc; /* Store dlc for statistics */
1450         can_put_echo_skb(skb, dev, slotindex);
1451
1452         /* Make sure everything is written before allowing hardware to
1453          * read from the memory
1454          */
1455         wmb();
1456
1457         /* Update write pointer to start transmission */
1458         grcan_write_reg(&regs->txwr,
1459                         grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size));
1460
1461         return NETDEV_TX_OK;
1462 }
1463
1464 /* ========== Setting up sysfs interface and module parameters ========== */
1465
1466 #define GRCAN_NOT_BOOL(unsigned_val) ((unsigned_val) > 1)
1467
1468 #define GRCAN_MODULE_PARAM(name, mtype, valcheckf, desc)                \
1469         static void grcan_sanitize_##name(struct platform_device *pd)   \
1470         {                                                               \
1471                 struct grcan_device_config grcan_default_config         \
1472                         = GRCAN_DEFAULT_DEVICE_CONFIG;                  \
1473                 if (valcheckf(grcan_module_config.name)) {              \
1474                         dev_err(&pd->dev,                               \
1475                                 "Invalid module parameter value for "   \
1476                                 #name " - setting default\n");          \
1477                         grcan_module_config.name =                      \
1478                                 grcan_default_config.name;              \
1479                 }                                                       \
1480         }                                                               \
1481         module_param_named(name, grcan_module_config.name,              \
1482                            mtype, 0444);                                \
1483         MODULE_PARM_DESC(name, desc)
1484
1485 #define GRCAN_CONFIG_ATTR(name, desc)                                   \
1486         static ssize_t grcan_store_##name(struct device *sdev,          \
1487                                           struct device_attribute *att, \
1488                                           const char *buf,              \
1489                                           size_t count)                 \
1490         {                                                               \
1491                 struct net_device *dev = to_net_dev(sdev);              \
1492                 struct grcan_priv *priv = netdev_priv(dev);             \
1493                 u8 val;                                                 \
1494                 int ret;                                                \
1495                 if (dev->flags & IFF_UP)                                \
1496                         return -EBUSY;                                  \
1497                 ret = kstrtou8(buf, 0, &val);                           \
1498                 if (ret < 0 || val > 1)                                 \
1499                         return -EINVAL;                                 \
1500                 priv->config.name = val;                                \
1501                 return count;                                           \
1502         }                                                               \
1503         static ssize_t grcan_show_##name(struct device *sdev,           \
1504                                          struct device_attribute *att,  \
1505                                          char *buf)                     \
1506         {                                                               \
1507                 struct net_device *dev = to_net_dev(sdev);              \
1508                 struct grcan_priv *priv = netdev_priv(dev);             \
1509                 return sprintf(buf, "%d\n", priv->config.name);         \
1510         }                                                               \
1511         static DEVICE_ATTR(name, 0644,                                  \
1512                            grcan_show_##name,                           \
1513                            grcan_store_##name);                         \
1514         GRCAN_MODULE_PARAM(name, ushort, GRCAN_NOT_BOOL, desc)
1515
1516 /* The following configuration options are made available both via module
1517  * parameters and writable sysfs files. See the chapter about GRCAN in the
1518  * documentation for the GRLIB VHDL library for further details.
1519  */
1520 GRCAN_CONFIG_ATTR(enable0,
1521                   "Configuration of physical interface 0. Determines\n" \
1522                   "the \"Enable 0\" bit of the configuration register.\n" \
1523                   "Format: 0 | 1\nDefault: 0\n");
1524
1525 GRCAN_CONFIG_ATTR(enable1,
1526                   "Configuration of physical interface 1. Determines\n" \
1527                   "the \"Enable 1\" bit of the configuration register.\n" \
1528                   "Format: 0 | 1\nDefault: 0\n");
1529
1530 GRCAN_CONFIG_ATTR(select,
1531                   "Select which physical interface to use.\n"   \
1532                   "Format: 0 | 1\nDefault: 0\n");
1533
1534 /* The tx and rx buffer size configuration options are only available via module
1535  * parameters.
1536  */
1537 GRCAN_MODULE_PARAM(txsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1538                    "Sets the size of the tx buffer.\n"                  \
1539                    "Format: <unsigned int> where (txsize & ~0x1fffc0) == 0\n" \
1540                    "Default: 1024\n");
1541 GRCAN_MODULE_PARAM(rxsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1542                    "Sets the size of the rx buffer.\n"                  \
1543                    "Format: <unsigned int> where (size & ~0x1fffc0) == 0\n" \
1544                    "Default: 1024\n");
1545
1546 /* Function that makes sure that configuration done using
1547  * module parameters are set to valid values
1548  */
1549 static void grcan_sanitize_module_config(struct platform_device *ofdev)
1550 {
1551         grcan_sanitize_enable0(ofdev);
1552         grcan_sanitize_enable1(ofdev);
1553         grcan_sanitize_select(ofdev);
1554         grcan_sanitize_txsize(ofdev);
1555         grcan_sanitize_rxsize(ofdev);
1556 }
1557
1558 static const struct attribute *const sysfs_grcan_attrs[] = {
1559         /* Config attrs */
1560         &dev_attr_enable0.attr,
1561         &dev_attr_enable1.attr,
1562         &dev_attr_select.attr,
1563         NULL,
1564 };
1565
1566 static const struct attribute_group sysfs_grcan_group = {
1567         .name   = "grcan",
1568         .attrs  = (struct attribute **)sysfs_grcan_attrs,
1569 };
1570
1571 /* ========== Setting up the driver ========== */
1572
1573 static const struct net_device_ops grcan_netdev_ops = {
1574         .ndo_open       = grcan_open,
1575         .ndo_stop       = grcan_close,
1576         .ndo_start_xmit = grcan_start_xmit,
1577         .ndo_change_mtu = can_change_mtu,
1578 };
1579
1580 static int grcan_setup_netdev(struct platform_device *ofdev,
1581                               void __iomem *base,
1582                               int irq, u32 ambafreq, bool txbug)
1583 {
1584         struct net_device *dev;
1585         struct grcan_priv *priv;
1586         struct grcan_registers __iomem *regs;
1587         int err;
1588
1589         dev = alloc_candev(sizeof(struct grcan_priv), 0);
1590         if (!dev)
1591                 return -ENOMEM;
1592
1593         dev->irq = irq;
1594         dev->flags |= IFF_ECHO;
1595         dev->netdev_ops = &grcan_netdev_ops;
1596         dev->sysfs_groups[0] = &sysfs_grcan_group;
1597
1598         priv = netdev_priv(dev);
1599         memcpy(&priv->config, &grcan_module_config,
1600                sizeof(struct grcan_device_config));
1601         priv->dev = dev;
1602         priv->ofdev_dev = &ofdev->dev;
1603         priv->regs = base;
1604         priv->can.bittiming_const = &grcan_bittiming_const;
1605         priv->can.do_set_bittiming = grcan_set_bittiming;
1606         priv->can.do_set_mode = grcan_set_mode;
1607         priv->can.do_get_berr_counter = grcan_get_berr_counter;
1608         priv->can.clock.freq = ambafreq;
1609         priv->can.ctrlmode_supported =
1610                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_ONE_SHOT;
1611         priv->need_txbug_workaround = txbug;
1612
1613         /* Discover if triple sampling is supported by hardware */
1614         regs = priv->regs;
1615         grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
1616         grcan_set_bits(&regs->conf, GRCAN_CONF_SAM);
1617         if (grcan_read_bits(&regs->conf, GRCAN_CONF_SAM)) {
1618                 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
1619                 dev_dbg(&ofdev->dev, "Hardware supports triple-sampling\n");
1620         }
1621
1622         spin_lock_init(&priv->lock);
1623
1624         if (priv->need_txbug_workaround) {
1625                 timer_setup(&priv->rr_timer, grcan_running_reset, 0);
1626                 timer_setup(&priv->hang_timer, grcan_initiate_running_reset, 0);
1627         }
1628
1629         netif_napi_add(dev, &priv->napi, grcan_poll, GRCAN_NAPI_WEIGHT);
1630
1631         SET_NETDEV_DEV(dev, &ofdev->dev);
1632         dev_info(&ofdev->dev, "regs=0x%p, irq=%d, clock=%d\n",
1633                  priv->regs, dev->irq, priv->can.clock.freq);
1634
1635         err = register_candev(dev);
1636         if (err)
1637                 goto exit_free_candev;
1638
1639         platform_set_drvdata(ofdev, dev);
1640
1641         /* Reset device to allow bit-timing to be set. No need to call
1642          * grcan_reset at this stage. That is done in grcan_open.
1643          */
1644         grcan_write_reg(&regs->ctrl, GRCAN_CTRL_RESET);
1645
1646         return 0;
1647 exit_free_candev:
1648         free_candev(dev);
1649         return err;
1650 }
1651
1652 static int grcan_probe(struct platform_device *ofdev)
1653 {
1654         struct device_node *np = ofdev->dev.of_node;
1655         struct device_node *sysid_parent;
1656         struct resource *res;
1657         u32 sysid, ambafreq;
1658         int irq, err;
1659         void __iomem *base;
1660         bool txbug = true;
1661
1662         /* Compare GRLIB version number with the first that does not
1663          * have the tx bug (see start_xmit)
1664          */
1665         sysid_parent = of_find_node_by_path("/ambapp0");
1666         if (sysid_parent) {
1667                 err = of_property_read_u32(sysid_parent, "systemid", &sysid);
1668                 if (!err && ((sysid & GRLIB_VERSION_MASK) >=
1669                              GRCAN_TXBUG_SAFE_GRLIB_VERSION))
1670                         txbug = false;
1671                 of_node_put(sysid_parent);
1672         }
1673
1674         err = of_property_read_u32(np, "freq", &ambafreq);
1675         if (err) {
1676                 dev_err(&ofdev->dev, "unable to fetch \"freq\" property\n");
1677                 goto exit_error;
1678         }
1679
1680         res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1681         base = devm_ioremap_resource(&ofdev->dev, res);
1682         if (IS_ERR(base)) {
1683                 err = PTR_ERR(base);
1684                 goto exit_error;
1685         }
1686
1687         irq = irq_of_parse_and_map(np, GRCAN_IRQIX_IRQ);
1688         if (!irq) {
1689                 dev_err(&ofdev->dev, "no irq found\n");
1690                 err = -ENODEV;
1691                 goto exit_error;
1692         }
1693
1694         grcan_sanitize_module_config(ofdev);
1695
1696         err = grcan_setup_netdev(ofdev, base, irq, ambafreq, txbug);
1697         if (err)
1698                 goto exit_dispose_irq;
1699
1700         return 0;
1701
1702 exit_dispose_irq:
1703         irq_dispose_mapping(irq);
1704 exit_error:
1705         dev_err(&ofdev->dev,
1706                 "%s socket CAN driver initialization failed with error %d\n",
1707                 DRV_NAME, err);
1708         return err;
1709 }
1710
1711 static int grcan_remove(struct platform_device *ofdev)
1712 {
1713         struct net_device *dev = platform_get_drvdata(ofdev);
1714         struct grcan_priv *priv = netdev_priv(dev);
1715
1716         unregister_candev(dev); /* Will in turn call grcan_close */
1717
1718         irq_dispose_mapping(dev->irq);
1719         netif_napi_del(&priv->napi);
1720         free_candev(dev);
1721
1722         return 0;
1723 }
1724
1725 static const struct of_device_id grcan_match[] = {
1726         {.name = "GAISLER_GRCAN"},
1727         {.name = "01_03d"},
1728         {.name = "GAISLER_GRHCAN"},
1729         {.name = "01_034"},
1730         {},
1731 };
1732
1733 MODULE_DEVICE_TABLE(of, grcan_match);
1734
1735 static struct platform_driver grcan_driver = {
1736         .driver = {
1737                 .name = DRV_NAME,
1738                 .of_match_table = grcan_match,
1739         },
1740         .probe = grcan_probe,
1741         .remove = grcan_remove,
1742 };
1743
1744 module_platform_driver(grcan_driver);
1745
1746 MODULE_AUTHOR("Aeroflex Gaisler AB.");
1747 MODULE_DESCRIPTION("Socket CAN driver for Aeroflex Gaisler GRCAN");
1748 MODULE_LICENSE("GPL");