2 * Mediatek MT7530 DSA Switch driver
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <linux/etherdevice.h>
15 #include <linux/if_bridge.h>
16 #include <linux/iopoll.h>
17 #include <linux/mdio.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/netdevice.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_net.h>
24 #include <linux/of_platform.h>
25 #include <linux/phy.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/reset.h>
29 #include <linux/gpio/consumer.h>
34 /* String, offset, and register size in bytes if different from 4 bytes */
35 static const struct mt7530_mib_desc mt7530_mib[] = {
36 MIB_DESC(1, 0x00, "TxDrop"),
37 MIB_DESC(1, 0x04, "TxCrcErr"),
38 MIB_DESC(1, 0x08, "TxUnicast"),
39 MIB_DESC(1, 0x0c, "TxMulticast"),
40 MIB_DESC(1, 0x10, "TxBroadcast"),
41 MIB_DESC(1, 0x14, "TxCollision"),
42 MIB_DESC(1, 0x18, "TxSingleCollision"),
43 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
44 MIB_DESC(1, 0x20, "TxDeferred"),
45 MIB_DESC(1, 0x24, "TxLateCollision"),
46 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
47 MIB_DESC(1, 0x2c, "TxPause"),
48 MIB_DESC(1, 0x30, "TxPktSz64"),
49 MIB_DESC(1, 0x34, "TxPktSz65To127"),
50 MIB_DESC(1, 0x38, "TxPktSz128To255"),
51 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
52 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
53 MIB_DESC(1, 0x44, "Tx1024ToMax"),
54 MIB_DESC(2, 0x48, "TxBytes"),
55 MIB_DESC(1, 0x60, "RxDrop"),
56 MIB_DESC(1, 0x64, "RxFiltering"),
57 MIB_DESC(1, 0x68, "RxUnicast"),
58 MIB_DESC(1, 0x6c, "RxMulticast"),
59 MIB_DESC(1, 0x70, "RxBroadcast"),
60 MIB_DESC(1, 0x74, "RxAlignErr"),
61 MIB_DESC(1, 0x78, "RxCrcErr"),
62 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
63 MIB_DESC(1, 0x80, "RxFragErr"),
64 MIB_DESC(1, 0x84, "RxOverSzErr"),
65 MIB_DESC(1, 0x88, "RxJabberErr"),
66 MIB_DESC(1, 0x8c, "RxPause"),
67 MIB_DESC(1, 0x90, "RxPktSz64"),
68 MIB_DESC(1, 0x94, "RxPktSz65To127"),
69 MIB_DESC(1, 0x98, "RxPktSz128To255"),
70 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
71 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
72 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
73 MIB_DESC(2, 0xa8, "RxBytes"),
74 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
75 MIB_DESC(1, 0xb4, "RxIngressDrop"),
76 MIB_DESC(1, 0xb8, "RxArlDrop"),
80 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val)
84 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val);
87 "failed to priv write register\n");
92 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg)
97 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val);
100 "failed to priv read register\n");
108 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg,
113 val = mt7623_trgmii_read(priv, reg);
116 mt7623_trgmii_write(priv, reg, val);
120 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val)
122 mt7623_trgmii_rmw(priv, reg, 0, val);
126 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val)
128 mt7623_trgmii_rmw(priv, reg, val, 0);
132 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
134 struct mii_bus *bus = priv->bus;
137 /* Write the desired MMD Devad */
138 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
142 /* Write the desired MMD register address */
143 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
147 /* Select the Function : DATA with no post increment */
148 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
152 /* Read the content of the MMD's selected register */
153 value = bus->read(bus, 0, MII_MMD_DATA);
157 dev_err(&bus->dev, "failed to read mmd register\n");
163 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
166 struct mii_bus *bus = priv->bus;
169 /* Write the desired MMD Devad */
170 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
174 /* Write the desired MMD register address */
175 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
179 /* Select the Function : DATA with no post increment */
180 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
184 /* Write the data into MMD's selected register */
185 ret = bus->write(bus, 0, MII_MMD_DATA, data);
189 "failed to write mmd register\n");
194 core_write(struct mt7530_priv *priv, u32 reg, u32 val)
196 struct mii_bus *bus = priv->bus;
198 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
200 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
202 mutex_unlock(&bus->mdio_lock);
206 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
208 struct mii_bus *bus = priv->bus;
211 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
213 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
216 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
218 mutex_unlock(&bus->mdio_lock);
222 core_set(struct mt7530_priv *priv, u32 reg, u32 val)
224 core_rmw(priv, reg, 0, val);
228 core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
230 core_rmw(priv, reg, val, 0);
234 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
236 struct mii_bus *bus = priv->bus;
240 page = (reg >> 6) & 0x3ff;
241 r = (reg >> 2) & 0xf;
245 /* MT7530 uses 31 as the pseudo port */
246 ret = bus->write(bus, 0x1f, 0x1f, page);
250 ret = bus->write(bus, 0x1f, r, lo);
254 ret = bus->write(bus, 0x1f, 0x10, hi);
258 "failed to write mt7530 register\n");
263 mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
265 struct mii_bus *bus = priv->bus;
269 page = (reg >> 6) & 0x3ff;
270 r = (reg >> 2) & 0xf;
272 /* MT7530 uses 31 as the pseudo port */
273 ret = bus->write(bus, 0x1f, 0x1f, page);
276 "failed to read mt7530 register\n");
280 lo = bus->read(bus, 0x1f, r);
281 hi = bus->read(bus, 0x1f, 0x10);
283 return (hi << 16) | (lo & 0xffff);
287 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
289 struct mii_bus *bus = priv->bus;
291 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
293 mt7530_mii_write(priv, reg, val);
295 mutex_unlock(&bus->mdio_lock);
299 _mt7530_read(struct mt7530_dummy_poll *p)
301 struct mii_bus *bus = p->priv->bus;
304 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
306 val = mt7530_mii_read(p->priv, p->reg);
308 mutex_unlock(&bus->mdio_lock);
314 mt7530_read(struct mt7530_priv *priv, u32 reg)
316 struct mt7530_dummy_poll p;
318 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
319 return _mt7530_read(&p);
323 mt7530_rmw(struct mt7530_priv *priv, u32 reg,
326 struct mii_bus *bus = priv->bus;
329 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
331 val = mt7530_mii_read(priv, reg);
334 mt7530_mii_write(priv, reg, val);
336 mutex_unlock(&bus->mdio_lock);
340 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
342 mt7530_rmw(priv, reg, 0, val);
346 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
348 mt7530_rmw(priv, reg, val, 0);
352 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
356 struct mt7530_dummy_poll p;
358 /* Set the command operating upon the MAC address entries */
359 val = ATC_BUSY | ATC_MAT(0) | cmd;
360 mt7530_write(priv, MT7530_ATC, val);
362 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
363 ret = readx_poll_timeout(_mt7530_read, &p, val,
364 !(val & ATC_BUSY), 20, 20000);
366 dev_err(priv->dev, "reset timeout\n");
370 /* Additional sanity for read command if the specified
373 val = mt7530_read(priv, MT7530_ATC);
374 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
384 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
389 /* Read from ARL table into an array */
390 for (i = 0; i < 3; i++) {
391 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
393 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
394 __func__, __LINE__, i, reg[i]);
397 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
398 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
399 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
400 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
401 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
402 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
403 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
404 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
405 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
406 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
410 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
411 u8 port_mask, const u8 *mac,
417 reg[1] |= vid & CVID_MASK;
418 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
419 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
420 /* STATIC_ENT indicate that entry is static wouldn't
421 * be aged out and STATIC_EMP specified as erasing an
424 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
425 reg[1] |= mac[5] << MAC_BYTE_5;
426 reg[1] |= mac[4] << MAC_BYTE_4;
427 reg[0] |= mac[3] << MAC_BYTE_3;
428 reg[0] |= mac[2] << MAC_BYTE_2;
429 reg[0] |= mac[1] << MAC_BYTE_1;
430 reg[0] |= mac[0] << MAC_BYTE_0;
432 /* Write array into the ARL table */
433 for (i = 0; i < 3; i++)
434 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
438 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
440 struct mt7530_priv *priv = ds->priv;
441 u32 ncpo1, ssc_delta, trgint, i;
444 case PHY_INTERFACE_MODE_RGMII:
449 case PHY_INTERFACE_MODE_TRGMII:
455 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
459 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
460 P6_INTF_MODE(trgint));
462 /* Lower Tx Driving for TRGMII path */
463 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
464 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
465 TD_DM_DRVP(8) | TD_DM_DRVN(8));
467 /* Setup core clock for MT7530 */
469 /* Disable MT7530 core clock */
470 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
472 /* Disable PLL, since phy_device has not yet been created
473 * provided for phy_[read,write]_mmd_indirect is called, we
474 * provide our own core_write_mmd_indirect to complete this
477 core_write_mmd_indirect(priv,
482 /* Set core clock into 500Mhz */
483 core_write(priv, CORE_GSWPLL_GRP2,
484 RG_GSWPLL_POSDIV_500M(1) |
485 RG_GSWPLL_FBKDIV_500M(25));
488 core_write(priv, CORE_GSWPLL_GRP1,
490 RG_GSWPLL_POSDIV_200M(2) |
491 RG_GSWPLL_FBKDIV_200M(32));
493 /* Enable MT7530 core clock */
494 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
497 /* Setup the MT7530 TRGMII Tx Clock */
498 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
499 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
500 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
501 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
502 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
503 core_write(priv, CORE_PLL_GROUP4,
504 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
505 RG_SYSPLL_BIAS_LPF_EN);
506 core_write(priv, CORE_PLL_GROUP2,
507 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
508 RG_SYSPLL_POSDIV(1));
509 core_write(priv, CORE_PLL_GROUP7,
510 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
511 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
512 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
513 REG_GSWCK_EN | REG_TRGMIICK_EN);
516 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
517 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
518 RD_TAP_MASK, RD_TAP(16));
520 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
526 mt7623_pad_clk_setup(struct dsa_switch *ds)
528 struct mt7530_priv *priv = ds->priv;
531 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
532 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i),
533 TD_DM_DRVP(8) | TD_DM_DRVN(8));
535 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL);
536 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST);
542 mt7530_mib_reset(struct dsa_switch *ds)
544 struct mt7530_priv *priv = ds->priv;
546 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
547 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
551 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable)
553 u32 mask = PMCR_TX_EN | PMCR_RX_EN | PMCR_FORCE_LNK;
556 mt7530_set(priv, MT7530_PMCR_P(port), mask);
558 mt7530_clear(priv, MT7530_PMCR_P(port), mask);
561 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
563 struct mt7530_priv *priv = ds->priv;
565 return mdiobus_read_nested(priv->bus, port, regnum);
568 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
571 struct mt7530_priv *priv = ds->priv;
573 return mdiobus_write_nested(priv->bus, port, regnum, val);
577 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
582 if (stringset != ETH_SS_STATS)
585 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
586 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
591 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
594 struct mt7530_priv *priv = ds->priv;
595 const struct mt7530_mib_desc *mib;
599 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
600 mib = &mt7530_mib[i];
601 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
603 data[i] = mt7530_read(priv, reg);
604 if (mib->size == 2) {
605 hi = mt7530_read(priv, reg + 4);
612 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
614 if (sset != ETH_SS_STATS)
617 return ARRAY_SIZE(mt7530_mib);
620 static void mt7530_adjust_link(struct dsa_switch *ds, int port,
621 struct phy_device *phydev)
623 struct mt7530_priv *priv = ds->priv;
625 if (phy_is_pseudo_fixed_link(phydev)) {
626 dev_dbg(priv->dev, "phy-mode for master device = %x\n",
629 /* Setup TX circuit incluing relevant PAD and driving */
630 mt7530_pad_clk_setup(ds, phydev->interface);
632 /* Setup RX circuit, relevant PAD and driving on the host
633 * which must be placed after the setup on the device side is
636 mt7623_pad_clk_setup(ds);
638 u16 lcl_adv = 0, rmt_adv = 0;
640 u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
642 switch (phydev->speed) {
644 mcr |= PMCR_FORCE_SPEED_1000;
647 mcr |= PMCR_FORCE_SPEED_100;
652 mcr |= PMCR_FORCE_LNK;
654 if (phydev->duplex) {
655 mcr |= PMCR_FORCE_FDX;
658 rmt_adv = LPA_PAUSE_CAP;
659 if (phydev->asym_pause)
660 rmt_adv |= LPA_PAUSE_ASYM;
662 if (phydev->advertising & ADVERTISED_Pause)
663 lcl_adv |= ADVERTISE_PAUSE_CAP;
664 if (phydev->advertising & ADVERTISED_Asym_Pause)
665 lcl_adv |= ADVERTISE_PAUSE_ASYM;
667 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
669 if (flowctrl & FLOW_CTRL_TX)
670 mcr |= PMCR_TX_FC_EN;
671 if (flowctrl & FLOW_CTRL_RX)
672 mcr |= PMCR_RX_FC_EN;
674 mt7530_write(priv, MT7530_PMCR_P(port), mcr);
679 mt7530_cpu_port_enable(struct mt7530_priv *priv,
682 /* Enable Mediatek header mode on the cpu port */
683 mt7530_write(priv, MT7530_PVC_P(port),
686 /* Setup the MAC by default for the cpu port */
687 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
689 /* Unknown multicast frame forwarding to the cpu port */
690 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
692 /* CPU port gets connected to all user ports of
695 mt7530_write(priv, MT7530_PCR_P(port),
696 PCR_MATRIX(dsa_user_ports(priv->ds)));
702 mt7530_port_enable(struct dsa_switch *ds, int port,
703 struct phy_device *phy)
705 struct mt7530_priv *priv = ds->priv;
707 mutex_lock(&priv->reg_mutex);
709 /* Setup the MAC for the user port */
710 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK);
712 /* Allow the user port gets connected to the cpu port and also
713 * restore the port matrix if the port is the member of a certain
716 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
717 priv->ports[port].enable = true;
718 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
719 priv->ports[port].pm);
720 mt7530_port_set_status(priv, port, 1);
722 mutex_unlock(&priv->reg_mutex);
728 mt7530_port_disable(struct dsa_switch *ds, int port,
729 struct phy_device *phy)
731 struct mt7530_priv *priv = ds->priv;
733 mutex_lock(&priv->reg_mutex);
735 /* Clear up all port matrix which could be restored in the next
736 * enablement for the port.
738 priv->ports[port].enable = false;
739 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
741 mt7530_port_set_status(priv, port, 0);
743 mutex_unlock(&priv->reg_mutex);
747 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
749 struct mt7530_priv *priv = ds->priv;
753 case BR_STATE_DISABLED:
754 stp_state = MT7530_STP_DISABLED;
756 case BR_STATE_BLOCKING:
757 stp_state = MT7530_STP_BLOCKING;
759 case BR_STATE_LISTENING:
760 stp_state = MT7530_STP_LISTENING;
762 case BR_STATE_LEARNING:
763 stp_state = MT7530_STP_LEARNING;
765 case BR_STATE_FORWARDING:
767 stp_state = MT7530_STP_FORWARDING;
771 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
775 mt7530_port_bridge_join(struct dsa_switch *ds, int port,
776 struct net_device *bridge)
778 struct mt7530_priv *priv = ds->priv;
779 u32 port_bitmap = BIT(MT7530_CPU_PORT);
782 mutex_lock(&priv->reg_mutex);
784 for (i = 0; i < MT7530_NUM_PORTS; i++) {
785 /* Add this port to the port matrix of the other ports in the
786 * same bridge. If the port is disabled, port matrix is kept
787 * and not being setup until the port becomes enabled.
789 if (dsa_is_user_port(ds, i) && i != port) {
790 if (dsa_to_port(ds, i)->bridge_dev != bridge)
792 if (priv->ports[i].enable)
793 mt7530_set(priv, MT7530_PCR_P(i),
794 PCR_MATRIX(BIT(port)));
795 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
797 port_bitmap |= BIT(i);
801 /* Add the all other ports to this port matrix. */
802 if (priv->ports[port].enable)
803 mt7530_rmw(priv, MT7530_PCR_P(port),
804 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
805 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
807 mutex_unlock(&priv->reg_mutex);
813 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
815 struct mt7530_priv *priv = ds->priv;
816 bool all_user_ports_removed = true;
819 /* When a port is removed from the bridge, the port would be set up
820 * back to the default as is at initial boot which is a VLAN-unaware
823 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
824 MT7530_PORT_MATRIX_MODE);
825 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
826 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
827 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
829 priv->ports[port].vlan_filtering = false;
831 for (i = 0; i < MT7530_NUM_PORTS; i++) {
832 if (dsa_is_user_port(ds, i) &&
833 priv->ports[i].vlan_filtering) {
834 all_user_ports_removed = false;
839 /* CPU port also does the same thing until all user ports belonging to
840 * the CPU port get out of VLAN filtering mode.
842 if (all_user_ports_removed) {
843 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
844 PCR_MATRIX(dsa_user_ports(priv->ds)));
845 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
846 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
851 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
853 struct mt7530_priv *priv = ds->priv;
855 /* Trapped into security mode allows packet forwarding through VLAN
856 * table lookup. CPU port is set to fallback mode to let untagged
857 * frames pass through.
859 if (dsa_is_cpu_port(ds, port))
860 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
861 MT7530_PORT_FALLBACK_MODE);
863 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
864 MT7530_PORT_SECURITY_MODE);
866 /* Set the port as a user port which is to be able to recognize VID
867 * from incoming packets before fetching entry within the VLAN table.
869 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
870 VLAN_ATTR(MT7530_VLAN_USER) |
871 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
875 mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
876 struct net_device *bridge)
878 struct mt7530_priv *priv = ds->priv;
881 mutex_lock(&priv->reg_mutex);
883 for (i = 0; i < MT7530_NUM_PORTS; i++) {
884 /* Remove this port from the port matrix of the other ports
885 * in the same bridge. If the port is disabled, port matrix
886 * is kept and not being setup until the port becomes enabled.
887 * And the other port's port matrix cannot be broken when the
888 * other port is still a VLAN-aware port.
890 if (!priv->ports[i].vlan_filtering &&
891 dsa_is_user_port(ds, i) && i != port) {
892 if (dsa_to_port(ds, i)->bridge_dev != bridge)
894 if (priv->ports[i].enable)
895 mt7530_clear(priv, MT7530_PCR_P(i),
896 PCR_MATRIX(BIT(port)));
897 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
901 /* Set the cpu port to be the only one in the port matrix of
904 if (priv->ports[port].enable)
905 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
906 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
907 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
909 mt7530_port_set_vlan_unaware(ds, port);
911 mutex_unlock(&priv->reg_mutex);
915 mt7530_port_fdb_add(struct dsa_switch *ds, int port,
916 const unsigned char *addr, u16 vid)
918 struct mt7530_priv *priv = ds->priv;
920 u8 port_mask = BIT(port);
922 mutex_lock(&priv->reg_mutex);
923 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
924 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
925 mutex_unlock(&priv->reg_mutex);
931 mt7530_port_fdb_del(struct dsa_switch *ds, int port,
932 const unsigned char *addr, u16 vid)
934 struct mt7530_priv *priv = ds->priv;
936 u8 port_mask = BIT(port);
938 mutex_lock(&priv->reg_mutex);
939 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
940 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
941 mutex_unlock(&priv->reg_mutex);
947 mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
948 dsa_fdb_dump_cb_t *cb, void *data)
950 struct mt7530_priv *priv = ds->priv;
951 struct mt7530_fdb _fdb = { 0 };
952 int cnt = MT7530_NUM_FDB_RECORDS;
956 mutex_lock(&priv->reg_mutex);
958 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
963 if (rsp & ATC_SRCH_HIT) {
964 mt7530_fdb_read(priv, &_fdb);
965 if (_fdb.port_mask & BIT(port)) {
966 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
973 !(rsp & ATC_SRCH_END) &&
974 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
976 mutex_unlock(&priv->reg_mutex);
982 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
984 struct mt7530_dummy_poll p;
988 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
989 mt7530_write(priv, MT7530_VTCR, val);
991 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
992 ret = readx_poll_timeout(_mt7530_read, &p, val,
993 !(val & VTCR_BUSY), 20, 20000);
995 dev_err(priv->dev, "poll timeout\n");
999 val = mt7530_read(priv, MT7530_VTCR);
1000 if (val & VTCR_INVALID) {
1001 dev_err(priv->dev, "read VTCR invalid\n");
1009 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
1010 bool vlan_filtering)
1012 struct mt7530_priv *priv = ds->priv;
1014 priv->ports[port].vlan_filtering = vlan_filtering;
1016 if (vlan_filtering) {
1017 /* The port is being kept as VLAN-unaware port when bridge is
1018 * set up with vlan_filtering not being set, Otherwise, the
1019 * port and the corresponding CPU port is required the setup
1020 * for becoming a VLAN-aware port.
1022 mt7530_port_set_vlan_aware(ds, port);
1023 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
1030 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
1031 const struct switchdev_obj_port_vlan *vlan)
1033 /* nothing needed */
1039 mt7530_hw_vlan_add(struct mt7530_priv *priv,
1040 struct mt7530_hw_vlan_entry *entry)
1045 new_members = entry->old_members | BIT(entry->port) |
1046 BIT(MT7530_CPU_PORT);
1048 /* Validate the entry with independent learning, create egress tag per
1049 * VLAN and joining the port as one of the port members.
1051 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1052 mt7530_write(priv, MT7530_VAWD1, val);
1054 /* Decide whether adding tag or not for those outgoing packets from the
1055 * port inside the VLAN.
1057 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1058 MT7530_VLAN_EGRESS_TAG;
1059 mt7530_rmw(priv, MT7530_VAWD2,
1060 ETAG_CTRL_P_MASK(entry->port),
1061 ETAG_CTRL_P(entry->port, val));
1063 /* CPU port is always taken as a tagged port for serving more than one
1064 * VLANs across and also being applied with egress type stack mode for
1065 * that VLAN tags would be appended after hardware special tag used as
1068 mt7530_rmw(priv, MT7530_VAWD2,
1069 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1070 ETAG_CTRL_P(MT7530_CPU_PORT,
1071 MT7530_VLAN_EGRESS_STACK));
1075 mt7530_hw_vlan_del(struct mt7530_priv *priv,
1076 struct mt7530_hw_vlan_entry *entry)
1081 new_members = entry->old_members & ~BIT(entry->port);
1083 val = mt7530_read(priv, MT7530_VAWD1);
1084 if (!(val & VLAN_VALID)) {
1086 "Cannot be deleted due to invalid entry\n");
1090 /* If certain member apart from CPU port is still alive in the VLAN,
1091 * the entry would be kept valid. Otherwise, the entry is got to be
1094 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1095 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1097 mt7530_write(priv, MT7530_VAWD1, val);
1099 mt7530_write(priv, MT7530_VAWD1, 0);
1100 mt7530_write(priv, MT7530_VAWD2, 0);
1105 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1106 struct mt7530_hw_vlan_entry *entry,
1107 mt7530_vlan_op vlan_op)
1112 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1114 val = mt7530_read(priv, MT7530_VAWD1);
1116 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1118 /* Manipulate entry */
1119 vlan_op(priv, entry);
1121 /* Flush result to hardware */
1122 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1126 mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1127 const struct switchdev_obj_port_vlan *vlan)
1129 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1130 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1131 struct mt7530_hw_vlan_entry new_entry;
1132 struct mt7530_priv *priv = ds->priv;
1135 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1138 if (!priv->ports[port].vlan_filtering)
1141 mutex_lock(&priv->reg_mutex);
1143 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1144 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1145 mt7530_hw_vlan_update(priv, vid, &new_entry,
1146 mt7530_hw_vlan_add);
1150 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1151 G0_PORT_VID(vlan->vid_end));
1152 priv->ports[port].pvid = vlan->vid_end;
1155 mutex_unlock(&priv->reg_mutex);
1159 mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1160 const struct switchdev_obj_port_vlan *vlan)
1162 struct mt7530_hw_vlan_entry target_entry;
1163 struct mt7530_priv *priv = ds->priv;
1166 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1169 if (!priv->ports[port].vlan_filtering)
1172 mutex_lock(&priv->reg_mutex);
1174 pvid = priv->ports[port].pvid;
1175 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1176 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1177 mt7530_hw_vlan_update(priv, vid, &target_entry,
1178 mt7530_hw_vlan_del);
1180 /* PVID is being restored to the default whenever the PVID port
1181 * is being removed from the VLAN.
1184 pvid = G0_PORT_VID_DEF;
1187 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1188 priv->ports[port].pvid = pvid;
1190 mutex_unlock(&priv->reg_mutex);
1195 static enum dsa_tag_protocol
1196 mtk_get_tag_protocol(struct dsa_switch *ds, int port)
1198 struct mt7530_priv *priv = ds->priv;
1200 if (port != MT7530_CPU_PORT) {
1202 "port not matched with tagging CPU port\n");
1203 return DSA_TAG_PROTO_NONE;
1205 return DSA_TAG_PROTO_MTK;
1210 mt7530_setup(struct dsa_switch *ds)
1212 struct mt7530_priv *priv = ds->priv;
1215 struct device_node *dn;
1216 struct mt7530_dummy_poll p;
1218 /* The parent node of master netdev which holds the common system
1219 * controller also is the container for two GMACs nodes representing
1220 * as two netdev instances.
1222 dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent;
1223 priv->ethernet = syscon_node_to_regmap(dn);
1224 if (IS_ERR(priv->ethernet))
1225 return PTR_ERR(priv->ethernet);
1227 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1228 ret = regulator_enable(priv->core_pwr);
1231 "Failed to enable core power: %d\n", ret);
1235 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1236 ret = regulator_enable(priv->io_pwr);
1238 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1243 /* Reset whole chip through gpio pin or memory-mapped registers for
1244 * different type of hardware
1247 reset_control_assert(priv->rstc);
1248 usleep_range(1000, 1100);
1249 reset_control_deassert(priv->rstc);
1251 gpiod_set_value_cansleep(priv->reset, 0);
1252 usleep_range(1000, 1100);
1253 gpiod_set_value_cansleep(priv->reset, 1);
1256 /* Waiting for MT7530 got to stable */
1257 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1258 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1261 dev_err(priv->dev, "reset timeout\n");
1265 id = mt7530_read(priv, MT7530_CREV);
1266 id >>= CHIP_NAME_SHIFT;
1267 if (id != MT7530_ID) {
1268 dev_err(priv->dev, "chip %x can't be supported\n", id);
1272 /* Reset the switch through internal reset */
1273 mt7530_write(priv, MT7530_SYS_CTRL,
1274 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1277 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1278 val = mt7530_read(priv, MT7530_MHWTRAP);
1279 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1280 val |= MHWTRAP_MANUAL;
1281 mt7530_write(priv, MT7530_MHWTRAP, val);
1283 /* Enable and reset MIB counters */
1284 mt7530_mib_reset(ds);
1286 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1287 /* Disable forwarding by default on all ports */
1288 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1291 if (dsa_is_cpu_port(ds, i))
1292 mt7530_cpu_port_enable(priv, i);
1294 mt7530_port_disable(ds, i, NULL);
1296 /* Enable consistent egress tag */
1297 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1298 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1301 /* Flush the FDB table */
1302 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1309 static const struct dsa_switch_ops mt7530_switch_ops = {
1310 .get_tag_protocol = mtk_get_tag_protocol,
1311 .setup = mt7530_setup,
1312 .get_strings = mt7530_get_strings,
1313 .phy_read = mt7530_phy_read,
1314 .phy_write = mt7530_phy_write,
1315 .get_ethtool_stats = mt7530_get_ethtool_stats,
1316 .get_sset_count = mt7530_get_sset_count,
1317 .adjust_link = mt7530_adjust_link,
1318 .port_enable = mt7530_port_enable,
1319 .port_disable = mt7530_port_disable,
1320 .port_stp_state_set = mt7530_stp_state_set,
1321 .port_bridge_join = mt7530_port_bridge_join,
1322 .port_bridge_leave = mt7530_port_bridge_leave,
1323 .port_fdb_add = mt7530_port_fdb_add,
1324 .port_fdb_del = mt7530_port_fdb_del,
1325 .port_fdb_dump = mt7530_port_fdb_dump,
1326 .port_vlan_filtering = mt7530_port_vlan_filtering,
1327 .port_vlan_prepare = mt7530_port_vlan_prepare,
1328 .port_vlan_add = mt7530_port_vlan_add,
1329 .port_vlan_del = mt7530_port_vlan_del,
1333 mt7530_probe(struct mdio_device *mdiodev)
1335 struct mt7530_priv *priv;
1336 struct device_node *dn;
1338 dn = mdiodev->dev.of_node;
1340 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1344 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
1348 /* Use medatek,mcm property to distinguish hardware type that would
1349 * casues a little bit differences on power-on sequence.
1351 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1353 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1355 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1356 if (IS_ERR(priv->rstc)) {
1357 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1358 return PTR_ERR(priv->rstc);
1362 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1363 if (IS_ERR(priv->core_pwr))
1364 return PTR_ERR(priv->core_pwr);
1366 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1367 if (IS_ERR(priv->io_pwr))
1368 return PTR_ERR(priv->io_pwr);
1370 /* Not MCM that indicates switch works as the remote standalone
1371 * integrated circuit so the GPIO pin would be used to complete
1372 * the reset, otherwise memory-mapped register accessing used
1373 * through syscon provides in the case of MCM.
1376 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1378 if (IS_ERR(priv->reset)) {
1379 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1380 return PTR_ERR(priv->reset);
1384 priv->bus = mdiodev->bus;
1385 priv->dev = &mdiodev->dev;
1386 priv->ds->priv = priv;
1387 priv->ds->ops = &mt7530_switch_ops;
1388 mutex_init(&priv->reg_mutex);
1389 dev_set_drvdata(&mdiodev->dev, priv);
1391 return dsa_register_switch(priv->ds);
1395 mt7530_remove(struct mdio_device *mdiodev)
1397 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1400 ret = regulator_disable(priv->core_pwr);
1403 "Failed to disable core power: %d\n", ret);
1405 ret = regulator_disable(priv->io_pwr);
1407 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1410 dsa_unregister_switch(priv->ds);
1411 mutex_destroy(&priv->reg_mutex);
1414 static const struct of_device_id mt7530_of_match[] = {
1415 { .compatible = "mediatek,mt7530" },
1418 MODULE_DEVICE_TABLE(of, mt7530_of_match);
1420 static struct mdio_driver mt7530_mdio_driver = {
1421 .probe = mt7530_probe,
1422 .remove = mt7530_remove,
1425 .of_match_table = mt7530_of_match,
1429 mdio_module_driver(mt7530_mdio_driver);
1431 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1432 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1433 MODULE_LICENSE("GPL");