2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/platform_data/mv88e6xxx.h>
32 #include <linux/netdevice.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/phy.h>
35 #include <linux/phylink.h>
47 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
50 dev_err(chip->dev, "Switch registers lock not held!\n");
55 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
56 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
58 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
59 * is the only device connected to the SMI master. In this mode it responds to
60 * all 32 possible SMI addresses, and thus maps directly the internal devices.
62 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
63 * multiple devices to share the SMI interface. In this mode it responds to only
64 * 2 registers, used to indirectly access the internal SMI devices.
67 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
68 int addr, int reg, u16 *val)
73 return chip->smi_ops->read(chip, addr, reg, val);
76 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
77 int addr, int reg, u16 val)
82 return chip->smi_ops->write(chip, addr, reg, val);
85 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
86 int addr, int reg, u16 *val)
90 ret = mdiobus_read_nested(chip->bus, addr, reg);
99 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
100 int addr, int reg, u16 val)
104 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
111 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
112 .read = mv88e6xxx_smi_single_chip_read,
113 .write = mv88e6xxx_smi_single_chip_write,
116 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
121 for (i = 0; i < 16; i++) {
122 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
126 if ((ret & SMI_CMD_BUSY) == 0)
133 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
134 int addr, int reg, u16 *val)
138 /* Wait for the bus to become free. */
139 ret = mv88e6xxx_smi_multi_chip_wait(chip);
143 /* Transmit the read command. */
144 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
145 SMI_CMD_OP_22_READ | (addr << 5) | reg);
149 /* Wait for the read command to complete. */
150 ret = mv88e6xxx_smi_multi_chip_wait(chip);
155 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
164 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
165 int addr, int reg, u16 val)
169 /* Wait for the bus to become free. */
170 ret = mv88e6xxx_smi_multi_chip_wait(chip);
174 /* Transmit the data to write. */
175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
179 /* Transmit the write command. */
180 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
181 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
185 /* Wait for the write command to complete. */
186 ret = mv88e6xxx_smi_multi_chip_wait(chip);
193 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
194 .read = mv88e6xxx_smi_multi_chip_read,
195 .write = mv88e6xxx_smi_multi_chip_write,
198 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
202 assert_reg_lock(chip);
204 err = mv88e6xxx_smi_read(chip, addr, reg, val);
208 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
214 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
218 assert_reg_lock(chip);
220 err = mv88e6xxx_smi_write(chip, addr, reg, val);
224 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
230 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
232 struct mv88e6xxx_mdio_bus *mdio_bus;
234 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
239 return mdio_bus->bus;
242 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
244 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
245 unsigned int n = d->hwirq;
247 chip->g1_irq.masked |= (1 << n);
250 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
252 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
253 unsigned int n = d->hwirq;
255 chip->g1_irq.masked &= ~(1 << n);
258 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
260 unsigned int nhandled = 0;
261 unsigned int sub_irq;
267 mutex_lock(&chip->reg_lock);
268 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
269 mutex_unlock(&chip->reg_lock);
275 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
276 if (reg & (1 << n)) {
277 sub_irq = irq_find_mapping(chip->g1_irq.domain,
279 handle_nested_irq(sub_irq);
284 mutex_lock(&chip->reg_lock);
285 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
288 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
290 mutex_unlock(&chip->reg_lock);
293 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
294 } while (reg & ctl1);
297 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
300 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
302 struct mv88e6xxx_chip *chip = dev_id;
304 return mv88e6xxx_g1_irq_thread_work(chip);
307 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
309 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
311 mutex_lock(&chip->reg_lock);
314 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
316 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
317 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
321 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
326 reg |= (~chip->g1_irq.masked & mask);
328 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
333 mutex_unlock(&chip->reg_lock);
336 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
337 .name = "mv88e6xxx-g1",
338 .irq_mask = mv88e6xxx_g1_irq_mask,
339 .irq_unmask = mv88e6xxx_g1_irq_unmask,
340 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
341 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
344 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
346 irq_hw_number_t hwirq)
348 struct mv88e6xxx_chip *chip = d->host_data;
350 irq_set_chip_data(irq, d->host_data);
351 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
352 irq_set_noprobe(irq);
357 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
358 .map = mv88e6xxx_g1_irq_domain_map,
359 .xlate = irq_domain_xlate_twocell,
362 /* To be called with reg_lock held */
363 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
368 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
369 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
370 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
372 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
373 virq = irq_find_mapping(chip->g1_irq.domain, irq);
374 irq_dispose_mapping(virq);
377 irq_domain_remove(chip->g1_irq.domain);
380 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
383 * free_irq must be called without reg_lock taken because the irq
384 * handler takes this lock, too.
386 free_irq(chip->irq, chip);
388 mutex_lock(&chip->reg_lock);
389 mv88e6xxx_g1_irq_free_common(chip);
390 mutex_unlock(&chip->reg_lock);
393 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
398 chip->g1_irq.nirqs = chip->info->g1_irqs;
399 chip->g1_irq.domain = irq_domain_add_simple(
400 NULL, chip->g1_irq.nirqs, 0,
401 &mv88e6xxx_g1_irq_domain_ops, chip);
402 if (!chip->g1_irq.domain)
405 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
406 irq_create_mapping(chip->g1_irq.domain, irq);
408 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
409 chip->g1_irq.masked = ~0;
411 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
415 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
417 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
421 /* Reading the interrupt status clears (most of) them */
422 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
429 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
430 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
433 for (irq = 0; irq < 16; irq++) {
434 virq = irq_find_mapping(chip->g1_irq.domain, irq);
435 irq_dispose_mapping(virq);
438 irq_domain_remove(chip->g1_irq.domain);
443 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
445 static struct lock_class_key lock_key;
446 static struct lock_class_key request_key;
449 err = mv88e6xxx_g1_irq_setup_common(chip);
453 /* These lock classes tells lockdep that global 1 irqs are in
454 * a different category than their parent GPIO, so it won't
455 * report false recursion.
457 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
459 mutex_unlock(&chip->reg_lock);
460 err = request_threaded_irq(chip->irq, NULL,
461 mv88e6xxx_g1_irq_thread_fn,
463 dev_name(chip->dev), chip);
464 mutex_lock(&chip->reg_lock);
466 mv88e6xxx_g1_irq_free_common(chip);
471 static void mv88e6xxx_irq_poll(struct kthread_work *work)
473 struct mv88e6xxx_chip *chip = container_of(work,
474 struct mv88e6xxx_chip,
476 mv88e6xxx_g1_irq_thread_work(chip);
478 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
479 msecs_to_jiffies(100));
482 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
486 err = mv88e6xxx_g1_irq_setup_common(chip);
490 kthread_init_delayed_work(&chip->irq_poll_work,
493 chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
494 if (IS_ERR(chip->kworker))
495 return PTR_ERR(chip->kworker);
497 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
498 msecs_to_jiffies(100));
503 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
505 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
506 kthread_destroy_worker(chip->kworker);
508 mutex_lock(&chip->reg_lock);
509 mv88e6xxx_g1_irq_free_common(chip);
510 mutex_unlock(&chip->reg_lock);
513 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
517 for (i = 0; i < 16; i++) {
521 err = mv88e6xxx_read(chip, addr, reg, &val);
528 usleep_range(1000, 2000);
531 dev_err(chip->dev, "Timeout while waiting for switch\n");
535 /* Indirect write to single pointer-data register with an Update bit */
536 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
541 /* Wait until the previous operation is completed */
542 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
546 /* Set the Update bit to trigger a write operation */
547 val = BIT(15) | update;
549 return mv88e6xxx_write(chip, addr, reg, val);
552 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
553 int link, int speed, int duplex, int pause,
554 phy_interface_t mode)
558 if (!chip->info->ops->port_set_link)
561 /* Port's MAC control must not be changed unless the link is down */
562 err = chip->info->ops->port_set_link(chip, port, 0);
566 if (chip->info->ops->port_set_speed) {
567 err = chip->info->ops->port_set_speed(chip, port, speed);
568 if (err && err != -EOPNOTSUPP)
572 if (chip->info->ops->port_set_pause) {
573 err = chip->info->ops->port_set_pause(chip, port, pause);
578 if (chip->info->ops->port_set_duplex) {
579 err = chip->info->ops->port_set_duplex(chip, port, duplex);
580 if (err && err != -EOPNOTSUPP)
584 if (chip->info->ops->port_set_rgmii_delay) {
585 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
586 if (err && err != -EOPNOTSUPP)
590 if (chip->info->ops->port_set_cmode) {
591 err = chip->info->ops->port_set_cmode(chip, port, mode);
592 if (err && err != -EOPNOTSUPP)
598 if (chip->info->ops->port_set_link(chip, port, link))
599 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
604 /* We expect the switch to perform auto negotiation if there is a real
605 * phy. However, in the case of a fixed link phy, we force the port
606 * settings from the fixed link settings.
608 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
609 struct phy_device *phydev)
611 struct mv88e6xxx_chip *chip = ds->priv;
614 if (!phy_is_pseudo_fixed_link(phydev))
617 mutex_lock(&chip->reg_lock);
618 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
619 phydev->duplex, phydev->pause,
621 mutex_unlock(&chip->reg_lock);
623 if (err && err != -EOPNOTSUPP)
624 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
627 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
629 struct phylink_link_state *state)
631 if (!phy_interface_mode_is_8023z(state->interface)) {
632 /* 10M and 100M are only supported in non-802.3z mode */
633 phylink_set(mask, 10baseT_Half);
634 phylink_set(mask, 10baseT_Full);
635 phylink_set(mask, 100baseT_Half);
636 phylink_set(mask, 100baseT_Full);
640 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
642 struct phylink_link_state *state)
644 /* FIXME: if the port is in 1000Base-X mode, then it only supports
645 * 1000M FD speeds. In this case, CMODE will indicate 5.
647 phylink_set(mask, 1000baseT_Full);
648 phylink_set(mask, 1000baseX_Full);
650 mv88e6065_phylink_validate(chip, port, mask, state);
653 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
655 struct phylink_link_state *state)
657 /* No ethtool bits for 200Mbps */
658 phylink_set(mask, 1000baseT_Full);
659 phylink_set(mask, 1000baseX_Full);
661 mv88e6065_phylink_validate(chip, port, mask, state);
664 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
666 struct phylink_link_state *state)
669 phylink_set(mask, 2500baseX_Full);
671 /* No ethtool bits for 200Mbps */
672 phylink_set(mask, 1000baseT_Full);
673 phylink_set(mask, 1000baseX_Full);
675 mv88e6065_phylink_validate(chip, port, mask, state);
678 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
680 struct phylink_link_state *state)
683 phylink_set(mask, 10000baseT_Full);
684 phylink_set(mask, 10000baseKR_Full);
687 mv88e6390_phylink_validate(chip, port, mask, state);
690 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
691 unsigned long *supported,
692 struct phylink_link_state *state)
694 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
695 struct mv88e6xxx_chip *chip = ds->priv;
697 /* Allow all the expected bits */
698 phylink_set(mask, Autoneg);
699 phylink_set(mask, Pause);
700 phylink_set_port_modes(mask);
702 if (chip->info->ops->phylink_validate)
703 chip->info->ops->phylink_validate(chip, port, mask, state);
705 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
706 bitmap_and(state->advertising, state->advertising, mask,
707 __ETHTOOL_LINK_MODE_MASK_NBITS);
709 /* We can only operate at 2500BaseX or 1000BaseX. If requested
710 * to advertise both, only report advertising at 2500BaseX.
712 phylink_helper_basex_speed(state);
715 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
716 struct phylink_link_state *state)
718 struct mv88e6xxx_chip *chip = ds->priv;
721 mutex_lock(&chip->reg_lock);
722 if (chip->info->ops->port_link_state)
723 err = chip->info->ops->port_link_state(chip, port, state);
726 mutex_unlock(&chip->reg_lock);
731 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
733 const struct phylink_link_state *state)
735 struct mv88e6xxx_chip *chip = ds->priv;
736 int speed, duplex, link, pause, err;
738 if (mode == MLO_AN_PHY)
741 if (mode == MLO_AN_FIXED) {
742 link = LINK_FORCED_UP;
743 speed = state->speed;
744 duplex = state->duplex;
746 speed = SPEED_UNFORCED;
747 duplex = DUPLEX_UNFORCED;
748 link = LINK_UNFORCED;
750 pause = !!phylink_test(state->advertising, Pause);
752 mutex_lock(&chip->reg_lock);
753 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
755 mutex_unlock(&chip->reg_lock);
757 if (err && err != -EOPNOTSUPP)
758 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
761 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
763 struct mv88e6xxx_chip *chip = ds->priv;
766 mutex_lock(&chip->reg_lock);
767 err = chip->info->ops->port_set_link(chip, port, link);
768 mutex_unlock(&chip->reg_lock);
771 dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
774 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
776 phy_interface_t interface)
778 if (mode == MLO_AN_FIXED)
779 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
782 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
783 unsigned int mode, phy_interface_t interface,
784 struct phy_device *phydev)
786 if (mode == MLO_AN_FIXED)
787 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
790 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
792 if (!chip->info->ops->stats_snapshot)
795 return chip->info->ops->stats_snapshot(chip, port);
798 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
799 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
800 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
801 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
802 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
803 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
804 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
805 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
806 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
807 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
808 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
809 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
810 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
811 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
812 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
813 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
814 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
815 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
816 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
817 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
818 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
819 { "single", 4, 0x14, STATS_TYPE_BANK0, },
820 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
821 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
822 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
823 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
824 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
825 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
826 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
827 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
828 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
829 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
830 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
831 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
832 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
833 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
834 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
835 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
836 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
837 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
838 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
839 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
840 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
841 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
842 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
843 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
844 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
845 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
846 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
847 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
848 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
849 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
850 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
851 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
852 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
853 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
854 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
855 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
856 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
857 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
860 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
861 struct mv88e6xxx_hw_stat *s,
862 int port, u16 bank1_select,
872 case STATS_TYPE_PORT:
873 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
879 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
882 low |= ((u32)reg) << 16;
885 case STATS_TYPE_BANK1:
888 case STATS_TYPE_BANK0:
889 reg |= s->reg | histogram;
890 mv88e6xxx_g1_stats_read(chip, reg, &low);
892 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
897 value = (((u64)high) << 32) | low;
901 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
902 uint8_t *data, int types)
904 struct mv88e6xxx_hw_stat *stat;
907 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
908 stat = &mv88e6xxx_hw_stats[i];
909 if (stat->type & types) {
910 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
919 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
922 return mv88e6xxx_stats_get_strings(chip, data,
923 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
926 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
929 return mv88e6xxx_stats_get_strings(chip, data,
930 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
933 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
934 "atu_member_violation",
935 "atu_miss_violation",
936 "atu_full_violation",
937 "vtu_member_violation",
938 "vtu_miss_violation",
941 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
945 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
946 strlcpy(data + i * ETH_GSTRING_LEN,
947 mv88e6xxx_atu_vtu_stats_strings[i],
951 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
952 u32 stringset, uint8_t *data)
954 struct mv88e6xxx_chip *chip = ds->priv;
957 if (stringset != ETH_SS_STATS)
960 mutex_lock(&chip->reg_lock);
962 if (chip->info->ops->stats_get_strings)
963 count = chip->info->ops->stats_get_strings(chip, data);
965 if (chip->info->ops->serdes_get_strings) {
966 data += count * ETH_GSTRING_LEN;
967 count = chip->info->ops->serdes_get_strings(chip, port, data);
970 data += count * ETH_GSTRING_LEN;
971 mv88e6xxx_atu_vtu_get_strings(data);
973 mutex_unlock(&chip->reg_lock);
976 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
979 struct mv88e6xxx_hw_stat *stat;
982 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
983 stat = &mv88e6xxx_hw_stats[i];
984 if (stat->type & types)
990 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
992 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
996 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
998 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1002 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1004 struct mv88e6xxx_chip *chip = ds->priv;
1005 int serdes_count = 0;
1008 if (sset != ETH_SS_STATS)
1011 mutex_lock(&chip->reg_lock);
1012 if (chip->info->ops->stats_get_sset_count)
1013 count = chip->info->ops->stats_get_sset_count(chip);
1017 if (chip->info->ops->serdes_get_sset_count)
1018 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1020 if (serdes_count < 0) {
1021 count = serdes_count;
1024 count += serdes_count;
1025 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1028 mutex_unlock(&chip->reg_lock);
1033 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1034 uint64_t *data, int types,
1035 u16 bank1_select, u16 histogram)
1037 struct mv88e6xxx_hw_stat *stat;
1040 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1041 stat = &mv88e6xxx_hw_stats[i];
1042 if (stat->type & types) {
1043 mutex_lock(&chip->reg_lock);
1044 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1047 mutex_unlock(&chip->reg_lock);
1055 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1058 return mv88e6xxx_stats_get_stats(chip, port, data,
1059 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1060 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1063 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1066 return mv88e6xxx_stats_get_stats(chip, port, data,
1067 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1068 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1069 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1072 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1075 return mv88e6xxx_stats_get_stats(chip, port, data,
1076 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1077 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1081 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1084 *data++ = chip->ports[port].atu_member_violation;
1085 *data++ = chip->ports[port].atu_miss_violation;
1086 *data++ = chip->ports[port].atu_full_violation;
1087 *data++ = chip->ports[port].vtu_member_violation;
1088 *data++ = chip->ports[port].vtu_miss_violation;
1091 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1096 if (chip->info->ops->stats_get_stats)
1097 count = chip->info->ops->stats_get_stats(chip, port, data);
1099 mutex_lock(&chip->reg_lock);
1100 if (chip->info->ops->serdes_get_stats) {
1102 count = chip->info->ops->serdes_get_stats(chip, port, data);
1105 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1106 mutex_unlock(&chip->reg_lock);
1109 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1112 struct mv88e6xxx_chip *chip = ds->priv;
1115 mutex_lock(&chip->reg_lock);
1117 ret = mv88e6xxx_stats_snapshot(chip, port);
1118 mutex_unlock(&chip->reg_lock);
1123 mv88e6xxx_get_stats(chip, port, data);
1127 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1129 return 32 * sizeof(u16);
1132 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1133 struct ethtool_regs *regs, void *_p)
1135 struct mv88e6xxx_chip *chip = ds->priv;
1143 memset(p, 0xff, 32 * sizeof(u16));
1145 mutex_lock(&chip->reg_lock);
1147 for (i = 0; i < 32; i++) {
1149 err = mv88e6xxx_port_read(chip, port, i, ®);
1154 mutex_unlock(&chip->reg_lock);
1157 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1158 struct ethtool_eee *e)
1160 /* Nothing to do on the port's MAC */
1164 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1165 struct ethtool_eee *e)
1167 /* Nothing to do on the port's MAC */
1171 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1173 struct dsa_switch *ds = NULL;
1174 struct net_device *br;
1178 if (dev < DSA_MAX_SWITCHES)
1179 ds = chip->ds->dst->ds[dev];
1181 /* Prevent frames from unknown switch or port */
1182 if (!ds || port >= ds->num_ports)
1185 /* Frames from DSA links and CPU ports can egress any local port */
1186 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1187 return mv88e6xxx_port_mask(chip);
1189 br = ds->ports[port].bridge_dev;
1192 /* Frames from user ports can egress any local DSA links and CPU ports,
1193 * as well as any local member of their bridge group.
1195 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1196 if (dsa_is_cpu_port(chip->ds, i) ||
1197 dsa_is_dsa_port(chip->ds, i) ||
1198 (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1204 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1206 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1208 /* prevent frames from going back out of the port they came in on */
1209 output_ports &= ~BIT(port);
1211 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1214 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1217 struct mv88e6xxx_chip *chip = ds->priv;
1220 mutex_lock(&chip->reg_lock);
1221 err = mv88e6xxx_port_set_state(chip, port, state);
1222 mutex_unlock(&chip->reg_lock);
1225 dev_err(ds->dev, "p%d: failed to update state\n", port);
1228 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1232 if (chip->info->ops->ieee_pri_map) {
1233 err = chip->info->ops->ieee_pri_map(chip);
1238 if (chip->info->ops->ip_pri_map) {
1239 err = chip->info->ops->ip_pri_map(chip);
1247 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1252 if (!chip->info->global2_addr)
1255 /* Initialize the routing port to the 32 possible target devices */
1256 for (target = 0; target < 32; target++) {
1258 if (target < DSA_MAX_SWITCHES)
1259 if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
1260 port = chip->ds->rtable[target];
1262 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1267 if (chip->info->ops->set_cascade_port) {
1268 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1269 err = chip->info->ops->set_cascade_port(chip, port);
1274 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1281 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1283 /* Clear all trunk masks and mapping */
1284 if (chip->info->global2_addr)
1285 return mv88e6xxx_g2_trunk_clear(chip);
1290 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1292 if (chip->info->ops->rmu_disable)
1293 return chip->info->ops->rmu_disable(chip);
1298 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1300 if (chip->info->ops->pot_clear)
1301 return chip->info->ops->pot_clear(chip);
1306 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1308 if (chip->info->ops->mgmt_rsvd2cpu)
1309 return chip->info->ops->mgmt_rsvd2cpu(chip);
1314 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1318 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1322 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1326 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1329 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1334 if (!chip->info->ops->irl_init_all)
1337 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1338 /* Disable ingress rate limiting by resetting all per port
1339 * ingress rate limit resources to their initial state.
1341 err = chip->info->ops->irl_init_all(chip, port);
1349 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1351 if (chip->info->ops->set_switch_mac) {
1354 eth_random_addr(addr);
1356 return chip->info->ops->set_switch_mac(chip, addr);
1362 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1366 if (!mv88e6xxx_has_pvt(chip))
1369 /* Skip the local source device, which uses in-chip port VLAN */
1370 if (dev != chip->ds->index)
1371 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1373 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1376 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1381 if (!mv88e6xxx_has_pvt(chip))
1384 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1385 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1387 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1391 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1392 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1393 err = mv88e6xxx_pvt_map(chip, dev, port);
1402 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1404 struct mv88e6xxx_chip *chip = ds->priv;
1407 mutex_lock(&chip->reg_lock);
1408 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1409 mutex_unlock(&chip->reg_lock);
1412 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1415 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1417 if (!chip->info->max_vid)
1420 return mv88e6xxx_g1_vtu_flush(chip);
1423 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1424 struct mv88e6xxx_vtu_entry *entry)
1426 if (!chip->info->ops->vtu_getnext)
1429 return chip->info->ops->vtu_getnext(chip, entry);
1432 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1433 struct mv88e6xxx_vtu_entry *entry)
1435 if (!chip->info->ops->vtu_loadpurge)
1438 return chip->info->ops->vtu_loadpurge(chip, entry);
1441 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1443 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1444 struct mv88e6xxx_vtu_entry vlan = {
1445 .vid = chip->info->max_vid,
1449 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1451 /* Set every FID bit used by the (un)bridged ports */
1452 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1453 err = mv88e6xxx_port_get_fid(chip, i, fid);
1457 set_bit(*fid, fid_bitmap);
1460 /* Set every FID bit used by the VLAN entries */
1462 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1469 set_bit(vlan.fid, fid_bitmap);
1470 } while (vlan.vid < chip->info->max_vid);
1472 /* The reset value 0x000 is used to indicate that multiple address
1473 * databases are not needed. Return the next positive available.
1475 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1476 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1479 /* Clear the database */
1480 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1483 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1484 struct mv88e6xxx_vtu_entry *entry, bool new)
1491 entry->vid = vid - 1;
1492 entry->valid = false;
1494 err = mv88e6xxx_vtu_getnext(chip, entry);
1498 if (entry->vid == vid && entry->valid)
1504 /* Initialize a fresh VLAN entry */
1505 memset(entry, 0, sizeof(*entry));
1506 entry->valid = true;
1509 /* Exclude all ports */
1510 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1512 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1514 return mv88e6xxx_atu_new(chip, &entry->fid);
1517 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1521 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1522 u16 vid_begin, u16 vid_end)
1524 struct mv88e6xxx_chip *chip = ds->priv;
1525 struct mv88e6xxx_vtu_entry vlan = {
1526 .vid = vid_begin - 1,
1530 /* DSA and CPU ports have to be members of multiple vlans */
1531 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1537 mutex_lock(&chip->reg_lock);
1540 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1547 if (vlan.vid > vid_end)
1550 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1551 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1554 if (!ds->ports[i].slave)
1557 if (vlan.member[i] ==
1558 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1561 if (dsa_to_port(ds, i)->bridge_dev ==
1562 ds->ports[port].bridge_dev)
1563 break; /* same bridge, check next VLAN */
1565 if (!dsa_to_port(ds, i)->bridge_dev)
1568 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1570 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1574 } while (vlan.vid < vid_end);
1577 mutex_unlock(&chip->reg_lock);
1582 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1583 bool vlan_filtering)
1585 struct mv88e6xxx_chip *chip = ds->priv;
1586 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1587 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1590 if (!chip->info->max_vid)
1593 mutex_lock(&chip->reg_lock);
1594 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1595 mutex_unlock(&chip->reg_lock);
1601 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1602 const struct switchdev_obj_port_vlan *vlan)
1604 struct mv88e6xxx_chip *chip = ds->priv;
1607 if (!chip->info->max_vid)
1610 /* If the requested port doesn't belong to the same bridge as the VLAN
1611 * members, do not support it (yet) and fallback to software VLAN.
1613 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1618 /* We don't need any dynamic resource from the kernel (yet),
1619 * so skip the prepare phase.
1624 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1625 const unsigned char *addr, u16 vid,
1628 struct mv88e6xxx_vtu_entry vlan;
1629 struct mv88e6xxx_atu_entry entry;
1632 /* Null VLAN ID corresponds to the port private database */
1634 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1636 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1640 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1641 ether_addr_copy(entry.mac, addr);
1642 eth_addr_dec(entry.mac);
1644 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1648 /* Initialize a fresh ATU entry if it isn't found */
1649 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1650 !ether_addr_equal(entry.mac, addr)) {
1651 memset(&entry, 0, sizeof(entry));
1652 ether_addr_copy(entry.mac, addr);
1655 /* Purge the ATU entry only if no port is using it anymore */
1656 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1657 entry.portvec &= ~BIT(port);
1659 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1661 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1662 entry.portvec = BIT(port);
1664 entry.portvec |= BIT(port);
1666 entry.state = state;
1669 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1672 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1675 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1676 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1678 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1681 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1686 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1687 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1695 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1698 struct mv88e6xxx_vtu_entry vlan;
1701 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1705 vlan.member[port] = member;
1707 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1711 return mv88e6xxx_broadcast_setup(chip, vid);
1714 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1715 const struct switchdev_obj_port_vlan *vlan)
1717 struct mv88e6xxx_chip *chip = ds->priv;
1718 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1719 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1723 if (!chip->info->max_vid)
1726 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1727 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1729 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1731 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1733 mutex_lock(&chip->reg_lock);
1735 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1736 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1737 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1738 vid, untagged ? 'u' : 't');
1740 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1741 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1744 mutex_unlock(&chip->reg_lock);
1747 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1750 struct mv88e6xxx_vtu_entry vlan;
1753 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1757 /* Tell switchdev if this VLAN is handled in software */
1758 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1761 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1763 /* keep the VLAN unless all ports are excluded */
1765 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1766 if (vlan.member[i] !=
1767 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1773 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1777 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1780 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1781 const struct switchdev_obj_port_vlan *vlan)
1783 struct mv88e6xxx_chip *chip = ds->priv;
1787 if (!chip->info->max_vid)
1790 mutex_lock(&chip->reg_lock);
1792 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1796 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1797 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1802 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1809 mutex_unlock(&chip->reg_lock);
1814 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1815 const unsigned char *addr, u16 vid)
1817 struct mv88e6xxx_chip *chip = ds->priv;
1820 mutex_lock(&chip->reg_lock);
1821 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1822 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1823 mutex_unlock(&chip->reg_lock);
1828 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1829 const unsigned char *addr, u16 vid)
1831 struct mv88e6xxx_chip *chip = ds->priv;
1834 mutex_lock(&chip->reg_lock);
1835 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1836 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1837 mutex_unlock(&chip->reg_lock);
1842 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1843 u16 fid, u16 vid, int port,
1844 dsa_fdb_dump_cb_t *cb, void *data)
1846 struct mv88e6xxx_atu_entry addr;
1850 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1851 eth_broadcast_addr(addr.mac);
1854 mutex_lock(&chip->reg_lock);
1855 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1856 mutex_unlock(&chip->reg_lock);
1860 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1863 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1866 if (!is_unicast_ether_addr(addr.mac))
1869 is_static = (addr.state ==
1870 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1871 err = cb(addr.mac, vid, is_static, data);
1874 } while (!is_broadcast_ether_addr(addr.mac));
1879 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1880 dsa_fdb_dump_cb_t *cb, void *data)
1882 struct mv88e6xxx_vtu_entry vlan = {
1883 .vid = chip->info->max_vid,
1888 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1889 mutex_lock(&chip->reg_lock);
1890 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1891 mutex_unlock(&chip->reg_lock);
1896 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1900 /* Dump VLANs' Filtering Information Databases */
1902 mutex_lock(&chip->reg_lock);
1903 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1904 mutex_unlock(&chip->reg_lock);
1911 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1915 } while (vlan.vid < chip->info->max_vid);
1920 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1921 dsa_fdb_dump_cb_t *cb, void *data)
1923 struct mv88e6xxx_chip *chip = ds->priv;
1925 return mv88e6xxx_port_db_dump(chip, port, cb, data);
1928 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1929 struct net_device *br)
1931 struct dsa_switch *ds;
1936 /* Remap the Port VLAN of each local bridge group member */
1937 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1938 if (chip->ds->ports[port].bridge_dev == br) {
1939 err = mv88e6xxx_port_vlan_map(chip, port);
1945 if (!mv88e6xxx_has_pvt(chip))
1948 /* Remap the Port VLAN of each cross-chip bridge group member */
1949 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1950 ds = chip->ds->dst->ds[dev];
1954 for (port = 0; port < ds->num_ports; ++port) {
1955 if (ds->ports[port].bridge_dev == br) {
1956 err = mv88e6xxx_pvt_map(chip, dev, port);
1966 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1967 struct net_device *br)
1969 struct mv88e6xxx_chip *chip = ds->priv;
1972 mutex_lock(&chip->reg_lock);
1973 err = mv88e6xxx_bridge_map(chip, br);
1974 mutex_unlock(&chip->reg_lock);
1979 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1980 struct net_device *br)
1982 struct mv88e6xxx_chip *chip = ds->priv;
1984 mutex_lock(&chip->reg_lock);
1985 if (mv88e6xxx_bridge_map(chip, br) ||
1986 mv88e6xxx_port_vlan_map(chip, port))
1987 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1988 mutex_unlock(&chip->reg_lock);
1991 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1992 int port, struct net_device *br)
1994 struct mv88e6xxx_chip *chip = ds->priv;
1997 if (!mv88e6xxx_has_pvt(chip))
2000 mutex_lock(&chip->reg_lock);
2001 err = mv88e6xxx_pvt_map(chip, dev, port);
2002 mutex_unlock(&chip->reg_lock);
2007 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
2008 int port, struct net_device *br)
2010 struct mv88e6xxx_chip *chip = ds->priv;
2012 if (!mv88e6xxx_has_pvt(chip))
2015 mutex_lock(&chip->reg_lock);
2016 if (mv88e6xxx_pvt_map(chip, dev, port))
2017 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2018 mutex_unlock(&chip->reg_lock);
2021 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2023 if (chip->info->ops->reset)
2024 return chip->info->ops->reset(chip);
2029 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2031 struct gpio_desc *gpiod = chip->reset;
2033 /* If there is a GPIO connected to the reset pin, toggle it */
2035 gpiod_set_value_cansleep(gpiod, 1);
2036 usleep_range(10000, 20000);
2037 gpiod_set_value_cansleep(gpiod, 0);
2038 usleep_range(10000, 20000);
2042 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2046 /* Set all ports to the Disabled state */
2047 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2048 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2053 /* Wait for transmit queues to drain,
2054 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2056 usleep_range(2000, 4000);
2061 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2065 err = mv88e6xxx_disable_ports(chip);
2069 mv88e6xxx_hardware_reset(chip);
2071 return mv88e6xxx_software_reset(chip);
2074 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2075 enum mv88e6xxx_frame_mode frame,
2076 enum mv88e6xxx_egress_mode egress, u16 etype)
2080 if (!chip->info->ops->port_set_frame_mode)
2083 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2087 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2091 if (chip->info->ops->port_set_ether_type)
2092 return chip->info->ops->port_set_ether_type(chip, port, etype);
2097 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2099 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2100 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2101 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2104 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2106 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2107 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2108 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2111 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2113 return mv88e6xxx_set_port_mode(chip, port,
2114 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2115 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2119 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2121 if (dsa_is_dsa_port(chip->ds, port))
2122 return mv88e6xxx_set_port_mode_dsa(chip, port);
2124 if (dsa_is_user_port(chip->ds, port))
2125 return mv88e6xxx_set_port_mode_normal(chip, port);
2127 /* Setup CPU port mode depending on its supported tag format */
2128 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2129 return mv88e6xxx_set_port_mode_dsa(chip, port);
2131 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2132 return mv88e6xxx_set_port_mode_edsa(chip, port);
2137 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2139 bool message = dsa_is_dsa_port(chip->ds, port);
2141 return mv88e6xxx_port_set_message_port(chip, port, message);
2144 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2146 struct dsa_switch *ds = chip->ds;
2149 /* Upstream ports flood frames with unknown unicast or multicast DA */
2150 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2151 if (chip->info->ops->port_set_egress_floods)
2152 return chip->info->ops->port_set_egress_floods(chip, port,
2158 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2161 if (chip->info->ops->serdes_power)
2162 return chip->info->ops->serdes_power(chip, port, on);
2167 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2169 struct dsa_switch *ds = chip->ds;
2173 upstream_port = dsa_upstream_port(ds, port);
2174 if (chip->info->ops->port_set_upstream_port) {
2175 err = chip->info->ops->port_set_upstream_port(chip, port,
2181 if (port == upstream_port) {
2182 if (chip->info->ops->set_cpu_port) {
2183 err = chip->info->ops->set_cpu_port(chip,
2189 if (chip->info->ops->set_egress_port) {
2190 err = chip->info->ops->set_egress_port(chip,
2200 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2202 struct dsa_switch *ds = chip->ds;
2206 chip->ports[port].chip = chip;
2207 chip->ports[port].port = port;
2209 /* MAC Forcing register: don't force link, speed, duplex or flow control
2210 * state to any particular values on physical ports, but force the CPU
2211 * port and all DSA ports to their maximum bandwidth and full duplex.
2213 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2214 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2215 SPEED_MAX, DUPLEX_FULL,
2217 PHY_INTERFACE_MODE_NA);
2219 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2220 SPEED_UNFORCED, DUPLEX_UNFORCED,
2222 PHY_INTERFACE_MODE_NA);
2226 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2227 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2228 * tunneling, determine priority by looking at 802.1p and IP
2229 * priority fields (IP prio has precedence), and set STP state
2232 * If this is the CPU link, use DSA or EDSA tagging depending
2233 * on which tagging mode was configured.
2235 * If this is a link to another switch, use DSA tagging mode.
2237 * If this is the upstream port for this switch, enable
2238 * forwarding of unknown unicasts and multicasts.
2240 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2241 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2242 /* Forward any IPv4 IGMP or IPv6 MLD frames received
2243 * by a USER port to the CPU port to allow snooping.
2245 if (dsa_is_user_port(ds, port))
2246 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
2248 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2252 err = mv88e6xxx_setup_port_mode(chip, port);
2256 err = mv88e6xxx_setup_egress_floods(chip, port);
2260 /* Enable the SERDES interface for DSA and CPU ports. Normal
2261 * ports SERDES are enabled when the port is enabled, thus
2262 * saving a bit of power.
2264 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
2265 err = mv88e6xxx_serdes_power(chip, port, true);
2270 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2271 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2272 * untagged frames on this port, do a destination address lookup on all
2273 * received packets as usual, disable ARP mirroring and don't send a
2274 * copy of all transmitted/received frames on this port to the CPU.
2276 err = mv88e6xxx_port_set_map_da(chip, port);
2280 err = mv88e6xxx_setup_upstream_port(chip, port);
2284 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2285 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2289 if (chip->info->ops->port_set_jumbo_size) {
2290 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2295 /* Port Association Vector: when learning source addresses
2296 * of packets, add the address to the address database using
2297 * a port bitmap that has only the bit for this port set and
2298 * the other bits clear.
2301 /* Disable learning for CPU port */
2302 if (dsa_is_cpu_port(ds, port))
2305 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2310 /* Egress rate control 2: disable egress rate control. */
2311 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2316 if (chip->info->ops->port_pause_limit) {
2317 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2322 if (chip->info->ops->port_disable_learn_limit) {
2323 err = chip->info->ops->port_disable_learn_limit(chip, port);
2328 if (chip->info->ops->port_disable_pri_override) {
2329 err = chip->info->ops->port_disable_pri_override(chip, port);
2334 if (chip->info->ops->port_tag_remap) {
2335 err = chip->info->ops->port_tag_remap(chip, port);
2340 if (chip->info->ops->port_egress_rate_limiting) {
2341 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2346 err = mv88e6xxx_setup_message_port(chip, port);
2350 /* Port based VLAN map: give each port the same default address
2351 * database, and allow bidirectional communication between the
2352 * CPU and DSA port(s), and the other ports.
2354 err = mv88e6xxx_port_set_fid(chip, port, 0);
2358 err = mv88e6xxx_port_vlan_map(chip, port);
2362 /* Default VLAN ID and priority: don't set a default VLAN
2363 * ID, and set the default packet priority to zero.
2365 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2368 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2369 struct phy_device *phydev)
2371 struct mv88e6xxx_chip *chip = ds->priv;
2374 mutex_lock(&chip->reg_lock);
2376 err = mv88e6xxx_serdes_power(chip, port, true);
2378 if (!err && chip->info->ops->serdes_irq_setup)
2379 err = chip->info->ops->serdes_irq_setup(chip, port);
2381 mutex_unlock(&chip->reg_lock);
2386 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
2387 struct phy_device *phydev)
2389 struct mv88e6xxx_chip *chip = ds->priv;
2391 mutex_lock(&chip->reg_lock);
2393 if (chip->info->ops->serdes_irq_free)
2394 chip->info->ops->serdes_irq_free(chip, port);
2396 if (mv88e6xxx_serdes_power(chip, port, false))
2397 dev_err(chip->dev, "failed to power off SERDES\n");
2399 mutex_unlock(&chip->reg_lock);
2402 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2403 unsigned int ageing_time)
2405 struct mv88e6xxx_chip *chip = ds->priv;
2408 mutex_lock(&chip->reg_lock);
2409 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2410 mutex_unlock(&chip->reg_lock);
2415 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2419 /* Initialize the statistics unit */
2420 if (chip->info->ops->stats_set_histogram) {
2421 err = chip->info->ops->stats_set_histogram(chip);
2426 return mv88e6xxx_g1_stats_clear(chip);
2429 /* The mv88e6390 has some hidden registers used for debug and
2430 * development. The errata also makes use of them.
2432 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port,
2438 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT,
2439 PORT_RESERVED_1A, val);
2443 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE |
2444 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2447 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2448 PORT_RESERVED_1A, ctrl);
2451 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip)
2453 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT,
2454 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY);
2458 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port,
2464 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ |
2465 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2468 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2469 PORT_RESERVED_1A, ctrl);
2473 err = mv88e6390_hidden_wait(chip);
2477 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT,
2478 PORT_RESERVED_1A, val);
2481 /* Check if the errata has already been applied. */
2482 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2488 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2489 err = mv88e6390_hidden_read(chip, port, 0, &val);
2492 "Error reading hidden register: %d\n", err);
2502 /* The 6390 copper ports have an errata which require poking magic
2503 * values into undocumented hidden registers and then performing a
2506 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2511 if (mv88e6390_setup_errata_applied(chip))
2514 /* Set the ports into blocking mode */
2515 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2516 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2521 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2522 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0);
2527 return mv88e6xxx_software_reset(chip);
2530 static int mv88e6xxx_setup(struct dsa_switch *ds)
2532 struct mv88e6xxx_chip *chip = ds->priv;
2538 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2540 mutex_lock(&chip->reg_lock);
2542 if (chip->info->ops->setup_errata) {
2543 err = chip->info->ops->setup_errata(chip);
2548 /* Cache the cmode of each port. */
2549 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2550 if (chip->info->ops->port_get_cmode) {
2551 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2555 chip->ports[i].cmode = cmode;
2559 /* Setup Switch Port Registers */
2560 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2561 if (dsa_is_unused_port(ds, i))
2564 err = mv88e6xxx_setup_port(chip, i);
2569 err = mv88e6xxx_irl_setup(chip);
2573 err = mv88e6xxx_mac_setup(chip);
2577 err = mv88e6xxx_phy_setup(chip);
2581 err = mv88e6xxx_vtu_setup(chip);
2585 err = mv88e6xxx_pvt_setup(chip);
2589 err = mv88e6xxx_atu_setup(chip);
2593 err = mv88e6xxx_broadcast_setup(chip, 0);
2597 err = mv88e6xxx_pot_setup(chip);
2601 err = mv88e6xxx_rmu_setup(chip);
2605 err = mv88e6xxx_rsvd2cpu_setup(chip);
2609 err = mv88e6xxx_trunk_setup(chip);
2613 err = mv88e6xxx_devmap_setup(chip);
2617 err = mv88e6xxx_pri_setup(chip);
2621 /* Setup PTP Hardware Clock and timestamping */
2622 if (chip->info->ptp_support) {
2623 err = mv88e6xxx_ptp_setup(chip);
2627 err = mv88e6xxx_hwtstamp_setup(chip);
2632 err = mv88e6xxx_stats_setup(chip);
2637 mutex_unlock(&chip->reg_lock);
2642 /* prod_id for switch families which do not have a PHY model number */
2643 static const u16 family_prod_id_table[] = {
2644 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
2645 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
2648 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2650 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2651 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2656 if (!chip->info->ops->phy_read)
2659 mutex_lock(&chip->reg_lock);
2660 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2661 mutex_unlock(&chip->reg_lock);
2663 /* Some internal PHYs don't have a model number. */
2664 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
2665 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
2666 prod_id = family_prod_id_table[chip->info->family];
2668 val |= prod_id >> 4;
2671 return err ? err : val;
2674 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2676 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2677 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2680 if (!chip->info->ops->phy_write)
2683 mutex_lock(&chip->reg_lock);
2684 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2685 mutex_unlock(&chip->reg_lock);
2690 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2691 struct device_node *np,
2695 struct mv88e6xxx_mdio_bus *mdio_bus;
2696 struct mii_bus *bus;
2700 mutex_lock(&chip->reg_lock);
2701 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
2702 mutex_unlock(&chip->reg_lock);
2708 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2712 mdio_bus = bus->priv;
2713 mdio_bus->bus = bus;
2714 mdio_bus->chip = chip;
2715 INIT_LIST_HEAD(&mdio_bus->list);
2716 mdio_bus->external = external;
2719 bus->name = np->full_name;
2720 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2722 bus->name = "mv88e6xxx SMI";
2723 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2726 bus->read = mv88e6xxx_mdio_read;
2727 bus->write = mv88e6xxx_mdio_write;
2728 bus->parent = chip->dev;
2731 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2736 err = of_mdiobus_register(bus, np);
2738 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2739 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2744 list_add_tail(&mdio_bus->list, &chip->mdios);
2746 list_add(&mdio_bus->list, &chip->mdios);
2751 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2752 { .compatible = "marvell,mv88e6xxx-mdio-external",
2753 .data = (void *)true },
2757 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2760 struct mv88e6xxx_mdio_bus *mdio_bus;
2761 struct mii_bus *bus;
2763 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2764 bus = mdio_bus->bus;
2766 if (!mdio_bus->external)
2767 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2769 mdiobus_unregister(bus);
2773 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2774 struct device_node *np)
2776 const struct of_device_id *match;
2777 struct device_node *child;
2780 /* Always register one mdio bus for the internal/default mdio
2781 * bus. This maybe represented in the device tree, but is
2784 child = of_get_child_by_name(np, "mdio");
2785 err = mv88e6xxx_mdio_register(chip, child, false);
2790 /* Walk the device tree, and see if there are any other nodes
2791 * which say they are compatible with the external mdio
2794 for_each_available_child_of_node(np, child) {
2795 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2797 err = mv88e6xxx_mdio_register(chip, child, true);
2799 mv88e6xxx_mdios_unregister(chip);
2808 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2810 struct mv88e6xxx_chip *chip = ds->priv;
2812 return chip->eeprom_len;
2815 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2816 struct ethtool_eeprom *eeprom, u8 *data)
2818 struct mv88e6xxx_chip *chip = ds->priv;
2821 if (!chip->info->ops->get_eeprom)
2824 mutex_lock(&chip->reg_lock);
2825 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2826 mutex_unlock(&chip->reg_lock);
2831 eeprom->magic = 0xc3ec4951;
2836 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2837 struct ethtool_eeprom *eeprom, u8 *data)
2839 struct mv88e6xxx_chip *chip = ds->priv;
2842 if (!chip->info->ops->set_eeprom)
2845 if (eeprom->magic != 0xc3ec4951)
2848 mutex_lock(&chip->reg_lock);
2849 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2850 mutex_unlock(&chip->reg_lock);
2855 static const struct mv88e6xxx_ops mv88e6085_ops = {
2856 /* MV88E6XXX_FAMILY_6097 */
2857 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2858 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2859 .irl_init_all = mv88e6352_g2_irl_init_all,
2860 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2861 .phy_read = mv88e6185_phy_ppu_read,
2862 .phy_write = mv88e6185_phy_ppu_write,
2863 .port_set_link = mv88e6xxx_port_set_link,
2864 .port_set_duplex = mv88e6xxx_port_set_duplex,
2865 .port_set_speed = mv88e6185_port_set_speed,
2866 .port_tag_remap = mv88e6095_port_tag_remap,
2867 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2868 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2869 .port_set_ether_type = mv88e6351_port_set_ether_type,
2870 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2871 .port_pause_limit = mv88e6097_port_pause_limit,
2872 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2873 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2874 .port_link_state = mv88e6352_port_link_state,
2875 .port_get_cmode = mv88e6185_port_get_cmode,
2876 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2877 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2878 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2879 .stats_get_strings = mv88e6095_stats_get_strings,
2880 .stats_get_stats = mv88e6095_stats_get_stats,
2881 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2882 .set_egress_port = mv88e6095_g1_set_egress_port,
2883 .watchdog_ops = &mv88e6097_watchdog_ops,
2884 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2885 .pot_clear = mv88e6xxx_g2_pot_clear,
2886 .ppu_enable = mv88e6185_g1_ppu_enable,
2887 .ppu_disable = mv88e6185_g1_ppu_disable,
2888 .reset = mv88e6185_g1_reset,
2889 .rmu_disable = mv88e6085_g1_rmu_disable,
2890 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2891 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2892 .phylink_validate = mv88e6185_phylink_validate,
2895 static const struct mv88e6xxx_ops mv88e6095_ops = {
2896 /* MV88E6XXX_FAMILY_6095 */
2897 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2898 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2899 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2900 .phy_read = mv88e6185_phy_ppu_read,
2901 .phy_write = mv88e6185_phy_ppu_write,
2902 .port_set_link = mv88e6xxx_port_set_link,
2903 .port_set_duplex = mv88e6xxx_port_set_duplex,
2904 .port_set_speed = mv88e6185_port_set_speed,
2905 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2906 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2907 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2908 .port_link_state = mv88e6185_port_link_state,
2909 .port_get_cmode = mv88e6185_port_get_cmode,
2910 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2911 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2912 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2913 .stats_get_strings = mv88e6095_stats_get_strings,
2914 .stats_get_stats = mv88e6095_stats_get_stats,
2915 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2916 .ppu_enable = mv88e6185_g1_ppu_enable,
2917 .ppu_disable = mv88e6185_g1_ppu_disable,
2918 .reset = mv88e6185_g1_reset,
2919 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2920 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2921 .phylink_validate = mv88e6185_phylink_validate,
2924 static const struct mv88e6xxx_ops mv88e6097_ops = {
2925 /* MV88E6XXX_FAMILY_6097 */
2926 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2927 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2928 .irl_init_all = mv88e6352_g2_irl_init_all,
2929 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2930 .phy_read = mv88e6xxx_g2_smi_phy_read,
2931 .phy_write = mv88e6xxx_g2_smi_phy_write,
2932 .port_set_link = mv88e6xxx_port_set_link,
2933 .port_set_duplex = mv88e6xxx_port_set_duplex,
2934 .port_set_speed = mv88e6185_port_set_speed,
2935 .port_tag_remap = mv88e6095_port_tag_remap,
2936 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2937 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2938 .port_set_ether_type = mv88e6351_port_set_ether_type,
2939 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2940 .port_pause_limit = mv88e6097_port_pause_limit,
2941 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2942 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2943 .port_link_state = mv88e6352_port_link_state,
2944 .port_get_cmode = mv88e6185_port_get_cmode,
2945 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2946 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2947 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2948 .stats_get_strings = mv88e6095_stats_get_strings,
2949 .stats_get_stats = mv88e6095_stats_get_stats,
2950 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2951 .set_egress_port = mv88e6095_g1_set_egress_port,
2952 .watchdog_ops = &mv88e6097_watchdog_ops,
2953 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2954 .pot_clear = mv88e6xxx_g2_pot_clear,
2955 .reset = mv88e6352_g1_reset,
2956 .rmu_disable = mv88e6085_g1_rmu_disable,
2957 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2958 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2959 .phylink_validate = mv88e6185_phylink_validate,
2962 static const struct mv88e6xxx_ops mv88e6123_ops = {
2963 /* MV88E6XXX_FAMILY_6165 */
2964 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2965 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2966 .irl_init_all = mv88e6352_g2_irl_init_all,
2967 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2968 .phy_read = mv88e6xxx_g2_smi_phy_read,
2969 .phy_write = mv88e6xxx_g2_smi_phy_write,
2970 .port_set_link = mv88e6xxx_port_set_link,
2971 .port_set_duplex = mv88e6xxx_port_set_duplex,
2972 .port_set_speed = mv88e6185_port_set_speed,
2973 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2974 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2975 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2976 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2977 .port_link_state = mv88e6352_port_link_state,
2978 .port_get_cmode = mv88e6185_port_get_cmode,
2979 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2980 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2981 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2982 .stats_get_strings = mv88e6095_stats_get_strings,
2983 .stats_get_stats = mv88e6095_stats_get_stats,
2984 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2985 .set_egress_port = mv88e6095_g1_set_egress_port,
2986 .watchdog_ops = &mv88e6097_watchdog_ops,
2987 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2988 .pot_clear = mv88e6xxx_g2_pot_clear,
2989 .reset = mv88e6352_g1_reset,
2990 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2991 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2992 .phylink_validate = mv88e6185_phylink_validate,
2995 static const struct mv88e6xxx_ops mv88e6131_ops = {
2996 /* MV88E6XXX_FAMILY_6185 */
2997 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2998 .ip_pri_map = mv88e6085_g1_ip_pri_map,
2999 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3000 .phy_read = mv88e6185_phy_ppu_read,
3001 .phy_write = mv88e6185_phy_ppu_write,
3002 .port_set_link = mv88e6xxx_port_set_link,
3003 .port_set_duplex = mv88e6xxx_port_set_duplex,
3004 .port_set_speed = mv88e6185_port_set_speed,
3005 .port_tag_remap = mv88e6095_port_tag_remap,
3006 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3007 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3008 .port_set_ether_type = mv88e6351_port_set_ether_type,
3009 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3010 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3011 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3012 .port_pause_limit = mv88e6097_port_pause_limit,
3013 .port_set_pause = mv88e6185_port_set_pause,
3014 .port_link_state = mv88e6352_port_link_state,
3015 .port_get_cmode = mv88e6185_port_get_cmode,
3016 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3017 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3018 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3019 .stats_get_strings = mv88e6095_stats_get_strings,
3020 .stats_get_stats = mv88e6095_stats_get_stats,
3021 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3022 .set_egress_port = mv88e6095_g1_set_egress_port,
3023 .watchdog_ops = &mv88e6097_watchdog_ops,
3024 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3025 .ppu_enable = mv88e6185_g1_ppu_enable,
3026 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3027 .ppu_disable = mv88e6185_g1_ppu_disable,
3028 .reset = mv88e6185_g1_reset,
3029 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3030 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3031 .phylink_validate = mv88e6185_phylink_validate,
3034 static const struct mv88e6xxx_ops mv88e6141_ops = {
3035 /* MV88E6XXX_FAMILY_6341 */
3036 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3037 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3038 .irl_init_all = mv88e6352_g2_irl_init_all,
3039 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3040 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3041 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3042 .phy_read = mv88e6xxx_g2_smi_phy_read,
3043 .phy_write = mv88e6xxx_g2_smi_phy_write,
3044 .port_set_link = mv88e6xxx_port_set_link,
3045 .port_set_duplex = mv88e6xxx_port_set_duplex,
3046 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3047 .port_set_speed = mv88e6341_port_set_speed,
3048 .port_tag_remap = mv88e6095_port_tag_remap,
3049 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3050 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3051 .port_set_ether_type = mv88e6351_port_set_ether_type,
3052 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3053 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3054 .port_pause_limit = mv88e6097_port_pause_limit,
3055 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3056 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3057 .port_link_state = mv88e6352_port_link_state,
3058 .port_get_cmode = mv88e6352_port_get_cmode,
3059 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3060 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3061 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3062 .stats_get_strings = mv88e6320_stats_get_strings,
3063 .stats_get_stats = mv88e6390_stats_get_stats,
3064 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3065 .set_egress_port = mv88e6390_g1_set_egress_port,
3066 .watchdog_ops = &mv88e6390_watchdog_ops,
3067 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3068 .pot_clear = mv88e6xxx_g2_pot_clear,
3069 .reset = mv88e6352_g1_reset,
3070 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3071 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3072 .serdes_power = mv88e6341_serdes_power,
3073 .gpio_ops = &mv88e6352_gpio_ops,
3074 .phylink_validate = mv88e6390_phylink_validate,
3077 static const struct mv88e6xxx_ops mv88e6161_ops = {
3078 /* MV88E6XXX_FAMILY_6165 */
3079 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3080 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3081 .irl_init_all = mv88e6352_g2_irl_init_all,
3082 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3083 .phy_read = mv88e6xxx_g2_smi_phy_read,
3084 .phy_write = mv88e6xxx_g2_smi_phy_write,
3085 .port_set_link = mv88e6xxx_port_set_link,
3086 .port_set_duplex = mv88e6xxx_port_set_duplex,
3087 .port_set_speed = mv88e6185_port_set_speed,
3088 .port_tag_remap = mv88e6095_port_tag_remap,
3089 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3090 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3091 .port_set_ether_type = mv88e6351_port_set_ether_type,
3092 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3093 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3094 .port_pause_limit = mv88e6097_port_pause_limit,
3095 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3096 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3097 .port_link_state = mv88e6352_port_link_state,
3098 .port_get_cmode = mv88e6185_port_get_cmode,
3099 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3100 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3101 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3102 .stats_get_strings = mv88e6095_stats_get_strings,
3103 .stats_get_stats = mv88e6095_stats_get_stats,
3104 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3105 .set_egress_port = mv88e6095_g1_set_egress_port,
3106 .watchdog_ops = &mv88e6097_watchdog_ops,
3107 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3108 .pot_clear = mv88e6xxx_g2_pot_clear,
3109 .reset = mv88e6352_g1_reset,
3110 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3111 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3112 .avb_ops = &mv88e6165_avb_ops,
3113 .ptp_ops = &mv88e6165_ptp_ops,
3114 .phylink_validate = mv88e6185_phylink_validate,
3117 static const struct mv88e6xxx_ops mv88e6165_ops = {
3118 /* MV88E6XXX_FAMILY_6165 */
3119 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3120 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3121 .irl_init_all = mv88e6352_g2_irl_init_all,
3122 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3123 .phy_read = mv88e6165_phy_read,
3124 .phy_write = mv88e6165_phy_write,
3125 .port_set_link = mv88e6xxx_port_set_link,
3126 .port_set_duplex = mv88e6xxx_port_set_duplex,
3127 .port_set_speed = mv88e6185_port_set_speed,
3128 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3129 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3130 .port_link_state = mv88e6352_port_link_state,
3131 .port_get_cmode = mv88e6185_port_get_cmode,
3132 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3133 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3134 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3135 .stats_get_strings = mv88e6095_stats_get_strings,
3136 .stats_get_stats = mv88e6095_stats_get_stats,
3137 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3138 .set_egress_port = mv88e6095_g1_set_egress_port,
3139 .watchdog_ops = &mv88e6097_watchdog_ops,
3140 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3141 .pot_clear = mv88e6xxx_g2_pot_clear,
3142 .reset = mv88e6352_g1_reset,
3143 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3144 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3145 .avb_ops = &mv88e6165_avb_ops,
3146 .ptp_ops = &mv88e6165_ptp_ops,
3147 .phylink_validate = mv88e6185_phylink_validate,
3150 static const struct mv88e6xxx_ops mv88e6171_ops = {
3151 /* MV88E6XXX_FAMILY_6351 */
3152 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3153 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3154 .irl_init_all = mv88e6352_g2_irl_init_all,
3155 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3156 .phy_read = mv88e6xxx_g2_smi_phy_read,
3157 .phy_write = mv88e6xxx_g2_smi_phy_write,
3158 .port_set_link = mv88e6xxx_port_set_link,
3159 .port_set_duplex = mv88e6xxx_port_set_duplex,
3160 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3161 .port_set_speed = mv88e6185_port_set_speed,
3162 .port_tag_remap = mv88e6095_port_tag_remap,
3163 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3164 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3165 .port_set_ether_type = mv88e6351_port_set_ether_type,
3166 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3167 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3168 .port_pause_limit = mv88e6097_port_pause_limit,
3169 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3170 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3171 .port_link_state = mv88e6352_port_link_state,
3172 .port_get_cmode = mv88e6352_port_get_cmode,
3173 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3174 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3175 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3176 .stats_get_strings = mv88e6095_stats_get_strings,
3177 .stats_get_stats = mv88e6095_stats_get_stats,
3178 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3179 .set_egress_port = mv88e6095_g1_set_egress_port,
3180 .watchdog_ops = &mv88e6097_watchdog_ops,
3181 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3182 .pot_clear = mv88e6xxx_g2_pot_clear,
3183 .reset = mv88e6352_g1_reset,
3184 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3185 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3186 .phylink_validate = mv88e6185_phylink_validate,
3189 static const struct mv88e6xxx_ops mv88e6172_ops = {
3190 /* MV88E6XXX_FAMILY_6352 */
3191 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3192 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3193 .irl_init_all = mv88e6352_g2_irl_init_all,
3194 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3195 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3196 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3197 .phy_read = mv88e6xxx_g2_smi_phy_read,
3198 .phy_write = mv88e6xxx_g2_smi_phy_write,
3199 .port_set_link = mv88e6xxx_port_set_link,
3200 .port_set_duplex = mv88e6xxx_port_set_duplex,
3201 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3202 .port_set_speed = mv88e6352_port_set_speed,
3203 .port_tag_remap = mv88e6095_port_tag_remap,
3204 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3205 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3206 .port_set_ether_type = mv88e6351_port_set_ether_type,
3207 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3208 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3209 .port_pause_limit = mv88e6097_port_pause_limit,
3210 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3211 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3212 .port_link_state = mv88e6352_port_link_state,
3213 .port_get_cmode = mv88e6352_port_get_cmode,
3214 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3215 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3216 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3217 .stats_get_strings = mv88e6095_stats_get_strings,
3218 .stats_get_stats = mv88e6095_stats_get_stats,
3219 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3220 .set_egress_port = mv88e6095_g1_set_egress_port,
3221 .watchdog_ops = &mv88e6097_watchdog_ops,
3222 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3223 .pot_clear = mv88e6xxx_g2_pot_clear,
3224 .reset = mv88e6352_g1_reset,
3225 .rmu_disable = mv88e6352_g1_rmu_disable,
3226 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3227 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3228 .serdes_power = mv88e6352_serdes_power,
3229 .gpio_ops = &mv88e6352_gpio_ops,
3230 .phylink_validate = mv88e6352_phylink_validate,
3233 static const struct mv88e6xxx_ops mv88e6175_ops = {
3234 /* MV88E6XXX_FAMILY_6351 */
3235 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3236 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3237 .irl_init_all = mv88e6352_g2_irl_init_all,
3238 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3239 .phy_read = mv88e6xxx_g2_smi_phy_read,
3240 .phy_write = mv88e6xxx_g2_smi_phy_write,
3241 .port_set_link = mv88e6xxx_port_set_link,
3242 .port_set_duplex = mv88e6xxx_port_set_duplex,
3243 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3244 .port_set_speed = mv88e6185_port_set_speed,
3245 .port_tag_remap = mv88e6095_port_tag_remap,
3246 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3247 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3248 .port_set_ether_type = mv88e6351_port_set_ether_type,
3249 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3250 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3251 .port_pause_limit = mv88e6097_port_pause_limit,
3252 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3253 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3254 .port_link_state = mv88e6352_port_link_state,
3255 .port_get_cmode = mv88e6352_port_get_cmode,
3256 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3257 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3258 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3259 .stats_get_strings = mv88e6095_stats_get_strings,
3260 .stats_get_stats = mv88e6095_stats_get_stats,
3261 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3262 .set_egress_port = mv88e6095_g1_set_egress_port,
3263 .watchdog_ops = &mv88e6097_watchdog_ops,
3264 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3265 .pot_clear = mv88e6xxx_g2_pot_clear,
3266 .reset = mv88e6352_g1_reset,
3267 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3268 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3269 .phylink_validate = mv88e6185_phylink_validate,
3272 static const struct mv88e6xxx_ops mv88e6176_ops = {
3273 /* MV88E6XXX_FAMILY_6352 */
3274 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3275 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3276 .irl_init_all = mv88e6352_g2_irl_init_all,
3277 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3278 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3279 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3280 .phy_read = mv88e6xxx_g2_smi_phy_read,
3281 .phy_write = mv88e6xxx_g2_smi_phy_write,
3282 .port_set_link = mv88e6xxx_port_set_link,
3283 .port_set_duplex = mv88e6xxx_port_set_duplex,
3284 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3285 .port_set_speed = mv88e6352_port_set_speed,
3286 .port_tag_remap = mv88e6095_port_tag_remap,
3287 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3288 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3289 .port_set_ether_type = mv88e6351_port_set_ether_type,
3290 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3291 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3292 .port_pause_limit = mv88e6097_port_pause_limit,
3293 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3294 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3295 .port_link_state = mv88e6352_port_link_state,
3296 .port_get_cmode = mv88e6352_port_get_cmode,
3297 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3298 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3299 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3300 .stats_get_strings = mv88e6095_stats_get_strings,
3301 .stats_get_stats = mv88e6095_stats_get_stats,
3302 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3303 .set_egress_port = mv88e6095_g1_set_egress_port,
3304 .watchdog_ops = &mv88e6097_watchdog_ops,
3305 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3306 .pot_clear = mv88e6xxx_g2_pot_clear,
3307 .reset = mv88e6352_g1_reset,
3308 .rmu_disable = mv88e6352_g1_rmu_disable,
3309 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3310 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3311 .serdes_power = mv88e6352_serdes_power,
3312 .gpio_ops = &mv88e6352_gpio_ops,
3313 .phylink_validate = mv88e6352_phylink_validate,
3316 static const struct mv88e6xxx_ops mv88e6185_ops = {
3317 /* MV88E6XXX_FAMILY_6185 */
3318 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3319 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3320 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3321 .phy_read = mv88e6185_phy_ppu_read,
3322 .phy_write = mv88e6185_phy_ppu_write,
3323 .port_set_link = mv88e6xxx_port_set_link,
3324 .port_set_duplex = mv88e6xxx_port_set_duplex,
3325 .port_set_speed = mv88e6185_port_set_speed,
3326 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3327 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3328 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3329 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3330 .port_set_pause = mv88e6185_port_set_pause,
3331 .port_link_state = mv88e6185_port_link_state,
3332 .port_get_cmode = mv88e6185_port_get_cmode,
3333 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3334 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3335 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3336 .stats_get_strings = mv88e6095_stats_get_strings,
3337 .stats_get_stats = mv88e6095_stats_get_stats,
3338 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3339 .set_egress_port = mv88e6095_g1_set_egress_port,
3340 .watchdog_ops = &mv88e6097_watchdog_ops,
3341 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3342 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3343 .ppu_enable = mv88e6185_g1_ppu_enable,
3344 .ppu_disable = mv88e6185_g1_ppu_disable,
3345 .reset = mv88e6185_g1_reset,
3346 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3347 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3348 .phylink_validate = mv88e6185_phylink_validate,
3351 static const struct mv88e6xxx_ops mv88e6190_ops = {
3352 /* MV88E6XXX_FAMILY_6390 */
3353 .setup_errata = mv88e6390_setup_errata,
3354 .irl_init_all = mv88e6390_g2_irl_init_all,
3355 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3356 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3357 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3358 .phy_read = mv88e6xxx_g2_smi_phy_read,
3359 .phy_write = mv88e6xxx_g2_smi_phy_write,
3360 .port_set_link = mv88e6xxx_port_set_link,
3361 .port_set_duplex = mv88e6xxx_port_set_duplex,
3362 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3363 .port_set_speed = mv88e6390_port_set_speed,
3364 .port_tag_remap = mv88e6390_port_tag_remap,
3365 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3366 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3367 .port_set_ether_type = mv88e6351_port_set_ether_type,
3368 .port_pause_limit = mv88e6390_port_pause_limit,
3369 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3370 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3371 .port_link_state = mv88e6352_port_link_state,
3372 .port_get_cmode = mv88e6352_port_get_cmode,
3373 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3374 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3375 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3376 .stats_get_strings = mv88e6320_stats_get_strings,
3377 .stats_get_stats = mv88e6390_stats_get_stats,
3378 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3379 .set_egress_port = mv88e6390_g1_set_egress_port,
3380 .watchdog_ops = &mv88e6390_watchdog_ops,
3381 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3382 .pot_clear = mv88e6xxx_g2_pot_clear,
3383 .reset = mv88e6352_g1_reset,
3384 .rmu_disable = mv88e6390_g1_rmu_disable,
3385 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3386 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3387 .serdes_power = mv88e6390_serdes_power,
3388 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3389 .serdes_irq_free = mv88e6390_serdes_irq_free,
3390 .gpio_ops = &mv88e6352_gpio_ops,
3391 .phylink_validate = mv88e6390_phylink_validate,
3394 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3395 /* MV88E6XXX_FAMILY_6390 */
3396 .setup_errata = mv88e6390_setup_errata,
3397 .irl_init_all = mv88e6390_g2_irl_init_all,
3398 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3399 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3400 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3401 .phy_read = mv88e6xxx_g2_smi_phy_read,
3402 .phy_write = mv88e6xxx_g2_smi_phy_write,
3403 .port_set_link = mv88e6xxx_port_set_link,
3404 .port_set_duplex = mv88e6xxx_port_set_duplex,
3405 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3406 .port_set_speed = mv88e6390x_port_set_speed,
3407 .port_tag_remap = mv88e6390_port_tag_remap,
3408 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3409 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3410 .port_set_ether_type = mv88e6351_port_set_ether_type,
3411 .port_pause_limit = mv88e6390_port_pause_limit,
3412 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3413 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3414 .port_link_state = mv88e6352_port_link_state,
3415 .port_get_cmode = mv88e6352_port_get_cmode,
3416 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3417 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3418 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3419 .stats_get_strings = mv88e6320_stats_get_strings,
3420 .stats_get_stats = mv88e6390_stats_get_stats,
3421 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3422 .set_egress_port = mv88e6390_g1_set_egress_port,
3423 .watchdog_ops = &mv88e6390_watchdog_ops,
3424 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3425 .pot_clear = mv88e6xxx_g2_pot_clear,
3426 .reset = mv88e6352_g1_reset,
3427 .rmu_disable = mv88e6390_g1_rmu_disable,
3428 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3429 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3430 .serdes_power = mv88e6390x_serdes_power,
3431 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3432 .serdes_irq_free = mv88e6390_serdes_irq_free,
3433 .gpio_ops = &mv88e6352_gpio_ops,
3434 .phylink_validate = mv88e6390x_phylink_validate,
3437 static const struct mv88e6xxx_ops mv88e6191_ops = {
3438 /* MV88E6XXX_FAMILY_6390 */
3439 .setup_errata = mv88e6390_setup_errata,
3440 .irl_init_all = mv88e6390_g2_irl_init_all,
3441 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3442 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3443 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3444 .phy_read = mv88e6xxx_g2_smi_phy_read,
3445 .phy_write = mv88e6xxx_g2_smi_phy_write,
3446 .port_set_link = mv88e6xxx_port_set_link,
3447 .port_set_duplex = mv88e6xxx_port_set_duplex,
3448 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3449 .port_set_speed = mv88e6390_port_set_speed,
3450 .port_tag_remap = mv88e6390_port_tag_remap,
3451 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3452 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3453 .port_set_ether_type = mv88e6351_port_set_ether_type,
3454 .port_pause_limit = mv88e6390_port_pause_limit,
3455 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3456 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3457 .port_link_state = mv88e6352_port_link_state,
3458 .port_get_cmode = mv88e6352_port_get_cmode,
3459 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3460 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3461 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3462 .stats_get_strings = mv88e6320_stats_get_strings,
3463 .stats_get_stats = mv88e6390_stats_get_stats,
3464 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3465 .set_egress_port = mv88e6390_g1_set_egress_port,
3466 .watchdog_ops = &mv88e6390_watchdog_ops,
3467 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3468 .pot_clear = mv88e6xxx_g2_pot_clear,
3469 .reset = mv88e6352_g1_reset,
3470 .rmu_disable = mv88e6390_g1_rmu_disable,
3471 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3472 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3473 .serdes_power = mv88e6390_serdes_power,
3474 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3475 .serdes_irq_free = mv88e6390_serdes_irq_free,
3476 .avb_ops = &mv88e6390_avb_ops,
3477 .ptp_ops = &mv88e6352_ptp_ops,
3478 .phylink_validate = mv88e6390_phylink_validate,
3481 static const struct mv88e6xxx_ops mv88e6240_ops = {
3482 /* MV88E6XXX_FAMILY_6352 */
3483 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3484 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3485 .irl_init_all = mv88e6352_g2_irl_init_all,
3486 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3487 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3488 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3489 .phy_read = mv88e6xxx_g2_smi_phy_read,
3490 .phy_write = mv88e6xxx_g2_smi_phy_write,
3491 .port_set_link = mv88e6xxx_port_set_link,
3492 .port_set_duplex = mv88e6xxx_port_set_duplex,
3493 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3494 .port_set_speed = mv88e6352_port_set_speed,
3495 .port_tag_remap = mv88e6095_port_tag_remap,
3496 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3497 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3498 .port_set_ether_type = mv88e6351_port_set_ether_type,
3499 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3500 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3501 .port_pause_limit = mv88e6097_port_pause_limit,
3502 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3503 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3504 .port_link_state = mv88e6352_port_link_state,
3505 .port_get_cmode = mv88e6352_port_get_cmode,
3506 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3507 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3508 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3509 .stats_get_strings = mv88e6095_stats_get_strings,
3510 .stats_get_stats = mv88e6095_stats_get_stats,
3511 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3512 .set_egress_port = mv88e6095_g1_set_egress_port,
3513 .watchdog_ops = &mv88e6097_watchdog_ops,
3514 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3515 .pot_clear = mv88e6xxx_g2_pot_clear,
3516 .reset = mv88e6352_g1_reset,
3517 .rmu_disable = mv88e6352_g1_rmu_disable,
3518 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3519 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3520 .serdes_power = mv88e6352_serdes_power,
3521 .gpio_ops = &mv88e6352_gpio_ops,
3522 .avb_ops = &mv88e6352_avb_ops,
3523 .ptp_ops = &mv88e6352_ptp_ops,
3524 .phylink_validate = mv88e6352_phylink_validate,
3527 static const struct mv88e6xxx_ops mv88e6290_ops = {
3528 /* MV88E6XXX_FAMILY_6390 */
3529 .setup_errata = mv88e6390_setup_errata,
3530 .irl_init_all = mv88e6390_g2_irl_init_all,
3531 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3532 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3533 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3534 .phy_read = mv88e6xxx_g2_smi_phy_read,
3535 .phy_write = mv88e6xxx_g2_smi_phy_write,
3536 .port_set_link = mv88e6xxx_port_set_link,
3537 .port_set_duplex = mv88e6xxx_port_set_duplex,
3538 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3539 .port_set_speed = mv88e6390_port_set_speed,
3540 .port_tag_remap = mv88e6390_port_tag_remap,
3541 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3542 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3543 .port_set_ether_type = mv88e6351_port_set_ether_type,
3544 .port_pause_limit = mv88e6390_port_pause_limit,
3545 .port_set_cmode = mv88e6390x_port_set_cmode,
3546 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3547 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3548 .port_link_state = mv88e6352_port_link_state,
3549 .port_get_cmode = mv88e6352_port_get_cmode,
3550 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3551 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3552 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3553 .stats_get_strings = mv88e6320_stats_get_strings,
3554 .stats_get_stats = mv88e6390_stats_get_stats,
3555 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3556 .set_egress_port = mv88e6390_g1_set_egress_port,
3557 .watchdog_ops = &mv88e6390_watchdog_ops,
3558 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3559 .pot_clear = mv88e6xxx_g2_pot_clear,
3560 .reset = mv88e6352_g1_reset,
3561 .rmu_disable = mv88e6390_g1_rmu_disable,
3562 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3563 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3564 .serdes_power = mv88e6390_serdes_power,
3565 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3566 .serdes_irq_free = mv88e6390_serdes_irq_free,
3567 .gpio_ops = &mv88e6352_gpio_ops,
3568 .avb_ops = &mv88e6390_avb_ops,
3569 .ptp_ops = &mv88e6352_ptp_ops,
3570 .phylink_validate = mv88e6390_phylink_validate,
3573 static const struct mv88e6xxx_ops mv88e6320_ops = {
3574 /* MV88E6XXX_FAMILY_6320 */
3575 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3576 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3577 .irl_init_all = mv88e6352_g2_irl_init_all,
3578 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3579 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3580 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3581 .phy_read = mv88e6xxx_g2_smi_phy_read,
3582 .phy_write = mv88e6xxx_g2_smi_phy_write,
3583 .port_set_link = mv88e6xxx_port_set_link,
3584 .port_set_duplex = mv88e6xxx_port_set_duplex,
3585 .port_set_speed = mv88e6185_port_set_speed,
3586 .port_tag_remap = mv88e6095_port_tag_remap,
3587 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3588 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3589 .port_set_ether_type = mv88e6351_port_set_ether_type,
3590 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3591 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3592 .port_pause_limit = mv88e6097_port_pause_limit,
3593 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3594 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3595 .port_link_state = mv88e6352_port_link_state,
3596 .port_get_cmode = mv88e6352_port_get_cmode,
3597 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3598 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3599 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3600 .stats_get_strings = mv88e6320_stats_get_strings,
3601 .stats_get_stats = mv88e6320_stats_get_stats,
3602 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3603 .set_egress_port = mv88e6095_g1_set_egress_port,
3604 .watchdog_ops = &mv88e6390_watchdog_ops,
3605 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3606 .pot_clear = mv88e6xxx_g2_pot_clear,
3607 .reset = mv88e6352_g1_reset,
3608 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3609 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3610 .gpio_ops = &mv88e6352_gpio_ops,
3611 .avb_ops = &mv88e6352_avb_ops,
3612 .ptp_ops = &mv88e6352_ptp_ops,
3613 .phylink_validate = mv88e6185_phylink_validate,
3616 static const struct mv88e6xxx_ops mv88e6321_ops = {
3617 /* MV88E6XXX_FAMILY_6320 */
3618 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3619 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3620 .irl_init_all = mv88e6352_g2_irl_init_all,
3621 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3622 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3623 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3624 .phy_read = mv88e6xxx_g2_smi_phy_read,
3625 .phy_write = mv88e6xxx_g2_smi_phy_write,
3626 .port_set_link = mv88e6xxx_port_set_link,
3627 .port_set_duplex = mv88e6xxx_port_set_duplex,
3628 .port_set_speed = mv88e6185_port_set_speed,
3629 .port_tag_remap = mv88e6095_port_tag_remap,
3630 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3631 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3632 .port_set_ether_type = mv88e6351_port_set_ether_type,
3633 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3634 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3635 .port_pause_limit = mv88e6097_port_pause_limit,
3636 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3637 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3638 .port_link_state = mv88e6352_port_link_state,
3639 .port_get_cmode = mv88e6352_port_get_cmode,
3640 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3641 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3642 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3643 .stats_get_strings = mv88e6320_stats_get_strings,
3644 .stats_get_stats = mv88e6320_stats_get_stats,
3645 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3646 .set_egress_port = mv88e6095_g1_set_egress_port,
3647 .watchdog_ops = &mv88e6390_watchdog_ops,
3648 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3649 .reset = mv88e6352_g1_reset,
3650 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3651 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3652 .gpio_ops = &mv88e6352_gpio_ops,
3653 .avb_ops = &mv88e6352_avb_ops,
3654 .ptp_ops = &mv88e6352_ptp_ops,
3655 .phylink_validate = mv88e6185_phylink_validate,
3658 static const struct mv88e6xxx_ops mv88e6341_ops = {
3659 /* MV88E6XXX_FAMILY_6341 */
3660 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3661 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3662 .irl_init_all = mv88e6352_g2_irl_init_all,
3663 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3664 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3665 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3666 .phy_read = mv88e6xxx_g2_smi_phy_read,
3667 .phy_write = mv88e6xxx_g2_smi_phy_write,
3668 .port_set_link = mv88e6xxx_port_set_link,
3669 .port_set_duplex = mv88e6xxx_port_set_duplex,
3670 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3671 .port_set_speed = mv88e6341_port_set_speed,
3672 .port_tag_remap = mv88e6095_port_tag_remap,
3673 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3674 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3675 .port_set_ether_type = mv88e6351_port_set_ether_type,
3676 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3677 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3678 .port_pause_limit = mv88e6097_port_pause_limit,
3679 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3680 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3681 .port_link_state = mv88e6352_port_link_state,
3682 .port_get_cmode = mv88e6352_port_get_cmode,
3683 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3684 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3685 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3686 .stats_get_strings = mv88e6320_stats_get_strings,
3687 .stats_get_stats = mv88e6390_stats_get_stats,
3688 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3689 .set_egress_port = mv88e6390_g1_set_egress_port,
3690 .watchdog_ops = &mv88e6390_watchdog_ops,
3691 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3692 .pot_clear = mv88e6xxx_g2_pot_clear,
3693 .reset = mv88e6352_g1_reset,
3694 .rmu_disable = mv88e6390_g1_rmu_disable,
3695 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3696 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3697 .serdes_power = mv88e6341_serdes_power,
3698 .gpio_ops = &mv88e6352_gpio_ops,
3699 .avb_ops = &mv88e6390_avb_ops,
3700 .ptp_ops = &mv88e6352_ptp_ops,
3701 .phylink_validate = mv88e6390_phylink_validate,
3704 static const struct mv88e6xxx_ops mv88e6350_ops = {
3705 /* MV88E6XXX_FAMILY_6351 */
3706 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3707 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3708 .irl_init_all = mv88e6352_g2_irl_init_all,
3709 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3710 .phy_read = mv88e6xxx_g2_smi_phy_read,
3711 .phy_write = mv88e6xxx_g2_smi_phy_write,
3712 .port_set_link = mv88e6xxx_port_set_link,
3713 .port_set_duplex = mv88e6xxx_port_set_duplex,
3714 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3715 .port_set_speed = mv88e6185_port_set_speed,
3716 .port_tag_remap = mv88e6095_port_tag_remap,
3717 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3718 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3719 .port_set_ether_type = mv88e6351_port_set_ether_type,
3720 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3721 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3722 .port_pause_limit = mv88e6097_port_pause_limit,
3723 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3724 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3725 .port_link_state = mv88e6352_port_link_state,
3726 .port_get_cmode = mv88e6352_port_get_cmode,
3727 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3728 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3729 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3730 .stats_get_strings = mv88e6095_stats_get_strings,
3731 .stats_get_stats = mv88e6095_stats_get_stats,
3732 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3733 .set_egress_port = mv88e6095_g1_set_egress_port,
3734 .watchdog_ops = &mv88e6097_watchdog_ops,
3735 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3736 .pot_clear = mv88e6xxx_g2_pot_clear,
3737 .reset = mv88e6352_g1_reset,
3738 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3739 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3740 .phylink_validate = mv88e6185_phylink_validate,
3743 static const struct mv88e6xxx_ops mv88e6351_ops = {
3744 /* MV88E6XXX_FAMILY_6351 */
3745 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3746 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3747 .irl_init_all = mv88e6352_g2_irl_init_all,
3748 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3749 .phy_read = mv88e6xxx_g2_smi_phy_read,
3750 .phy_write = mv88e6xxx_g2_smi_phy_write,
3751 .port_set_link = mv88e6xxx_port_set_link,
3752 .port_set_duplex = mv88e6xxx_port_set_duplex,
3753 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3754 .port_set_speed = mv88e6185_port_set_speed,
3755 .port_tag_remap = mv88e6095_port_tag_remap,
3756 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3757 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3758 .port_set_ether_type = mv88e6351_port_set_ether_type,
3759 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3760 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3761 .port_pause_limit = mv88e6097_port_pause_limit,
3762 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3763 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3764 .port_link_state = mv88e6352_port_link_state,
3765 .port_get_cmode = mv88e6352_port_get_cmode,
3766 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3767 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3768 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3769 .stats_get_strings = mv88e6095_stats_get_strings,
3770 .stats_get_stats = mv88e6095_stats_get_stats,
3771 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3772 .set_egress_port = mv88e6095_g1_set_egress_port,
3773 .watchdog_ops = &mv88e6097_watchdog_ops,
3774 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3775 .pot_clear = mv88e6xxx_g2_pot_clear,
3776 .reset = mv88e6352_g1_reset,
3777 .rmu_disable = mv88e6390_g1_rmu_disable,
3778 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3779 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3780 .avb_ops = &mv88e6352_avb_ops,
3781 .ptp_ops = &mv88e6352_ptp_ops,
3782 .phylink_validate = mv88e6185_phylink_validate,
3785 static const struct mv88e6xxx_ops mv88e6352_ops = {
3786 /* MV88E6XXX_FAMILY_6352 */
3787 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3788 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3789 .irl_init_all = mv88e6352_g2_irl_init_all,
3790 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3791 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3792 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3793 .phy_read = mv88e6xxx_g2_smi_phy_read,
3794 .phy_write = mv88e6xxx_g2_smi_phy_write,
3795 .port_set_link = mv88e6xxx_port_set_link,
3796 .port_set_duplex = mv88e6xxx_port_set_duplex,
3797 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3798 .port_set_speed = mv88e6352_port_set_speed,
3799 .port_tag_remap = mv88e6095_port_tag_remap,
3800 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3801 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3802 .port_set_ether_type = mv88e6351_port_set_ether_type,
3803 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3804 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3805 .port_pause_limit = mv88e6097_port_pause_limit,
3806 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3807 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3808 .port_link_state = mv88e6352_port_link_state,
3809 .port_get_cmode = mv88e6352_port_get_cmode,
3810 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3811 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3812 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3813 .stats_get_strings = mv88e6095_stats_get_strings,
3814 .stats_get_stats = mv88e6095_stats_get_stats,
3815 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3816 .set_egress_port = mv88e6095_g1_set_egress_port,
3817 .watchdog_ops = &mv88e6097_watchdog_ops,
3818 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3819 .pot_clear = mv88e6xxx_g2_pot_clear,
3820 .reset = mv88e6352_g1_reset,
3821 .rmu_disable = mv88e6352_g1_rmu_disable,
3822 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3823 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3824 .serdes_power = mv88e6352_serdes_power,
3825 .gpio_ops = &mv88e6352_gpio_ops,
3826 .avb_ops = &mv88e6352_avb_ops,
3827 .ptp_ops = &mv88e6352_ptp_ops,
3828 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
3829 .serdes_get_strings = mv88e6352_serdes_get_strings,
3830 .serdes_get_stats = mv88e6352_serdes_get_stats,
3831 .phylink_validate = mv88e6352_phylink_validate,
3834 static const struct mv88e6xxx_ops mv88e6390_ops = {
3835 /* MV88E6XXX_FAMILY_6390 */
3836 .setup_errata = mv88e6390_setup_errata,
3837 .irl_init_all = mv88e6390_g2_irl_init_all,
3838 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3839 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3840 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3841 .phy_read = mv88e6xxx_g2_smi_phy_read,
3842 .phy_write = mv88e6xxx_g2_smi_phy_write,
3843 .port_set_link = mv88e6xxx_port_set_link,
3844 .port_set_duplex = mv88e6xxx_port_set_duplex,
3845 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3846 .port_set_speed = mv88e6390_port_set_speed,
3847 .port_tag_remap = mv88e6390_port_tag_remap,
3848 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3849 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3850 .port_set_ether_type = mv88e6351_port_set_ether_type,
3851 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3852 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3853 .port_pause_limit = mv88e6390_port_pause_limit,
3854 .port_set_cmode = mv88e6390x_port_set_cmode,
3855 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3856 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3857 .port_link_state = mv88e6352_port_link_state,
3858 .port_get_cmode = mv88e6352_port_get_cmode,
3859 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3860 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3861 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3862 .stats_get_strings = mv88e6320_stats_get_strings,
3863 .stats_get_stats = mv88e6390_stats_get_stats,
3864 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3865 .set_egress_port = mv88e6390_g1_set_egress_port,
3866 .watchdog_ops = &mv88e6390_watchdog_ops,
3867 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3868 .pot_clear = mv88e6xxx_g2_pot_clear,
3869 .reset = mv88e6352_g1_reset,
3870 .rmu_disable = mv88e6390_g1_rmu_disable,
3871 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3872 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3873 .serdes_power = mv88e6390_serdes_power,
3874 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3875 .serdes_irq_free = mv88e6390_serdes_irq_free,
3876 .gpio_ops = &mv88e6352_gpio_ops,
3877 .avb_ops = &mv88e6390_avb_ops,
3878 .ptp_ops = &mv88e6352_ptp_ops,
3879 .phylink_validate = mv88e6390_phylink_validate,
3882 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3883 /* MV88E6XXX_FAMILY_6390 */
3884 .setup_errata = mv88e6390_setup_errata,
3885 .irl_init_all = mv88e6390_g2_irl_init_all,
3886 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3887 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3888 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3889 .phy_read = mv88e6xxx_g2_smi_phy_read,
3890 .phy_write = mv88e6xxx_g2_smi_phy_write,
3891 .port_set_link = mv88e6xxx_port_set_link,
3892 .port_set_duplex = mv88e6xxx_port_set_duplex,
3893 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3894 .port_set_speed = mv88e6390x_port_set_speed,
3895 .port_tag_remap = mv88e6390_port_tag_remap,
3896 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3897 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3898 .port_set_ether_type = mv88e6351_port_set_ether_type,
3899 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3900 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3901 .port_pause_limit = mv88e6390_port_pause_limit,
3902 .port_set_cmode = mv88e6390x_port_set_cmode,
3903 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3904 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3905 .port_link_state = mv88e6352_port_link_state,
3906 .port_get_cmode = mv88e6352_port_get_cmode,
3907 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3908 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3909 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3910 .stats_get_strings = mv88e6320_stats_get_strings,
3911 .stats_get_stats = mv88e6390_stats_get_stats,
3912 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3913 .set_egress_port = mv88e6390_g1_set_egress_port,
3914 .watchdog_ops = &mv88e6390_watchdog_ops,
3915 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3916 .pot_clear = mv88e6xxx_g2_pot_clear,
3917 .reset = mv88e6352_g1_reset,
3918 .rmu_disable = mv88e6390_g1_rmu_disable,
3919 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3920 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3921 .serdes_power = mv88e6390x_serdes_power,
3922 .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3923 .serdes_irq_free = mv88e6390_serdes_irq_free,
3924 .gpio_ops = &mv88e6352_gpio_ops,
3925 .avb_ops = &mv88e6390_avb_ops,
3926 .ptp_ops = &mv88e6352_ptp_ops,
3927 .phylink_validate = mv88e6390x_phylink_validate,
3930 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3932 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3933 .family = MV88E6XXX_FAMILY_6097,
3934 .name = "Marvell 88E6085",
3935 .num_databases = 4096,
3937 .num_internal_phys = 5,
3939 .port_base_addr = 0x10,
3940 .phy_base_addr = 0x0,
3941 .global1_addr = 0x1b,
3942 .global2_addr = 0x1c,
3943 .age_time_coeff = 15000,
3946 .atu_move_port_mask = 0xf,
3949 .tag_protocol = DSA_TAG_PROTO_DSA,
3950 .ops = &mv88e6085_ops,
3954 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3955 .family = MV88E6XXX_FAMILY_6095,
3956 .name = "Marvell 88E6095/88E6095F",
3957 .num_databases = 256,
3959 .num_internal_phys = 0,
3961 .port_base_addr = 0x10,
3962 .phy_base_addr = 0x0,
3963 .global1_addr = 0x1b,
3964 .global2_addr = 0x1c,
3965 .age_time_coeff = 15000,
3967 .atu_move_port_mask = 0xf,
3969 .tag_protocol = DSA_TAG_PROTO_DSA,
3970 .ops = &mv88e6095_ops,
3974 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3975 .family = MV88E6XXX_FAMILY_6097,
3976 .name = "Marvell 88E6097/88E6097F",
3977 .num_databases = 4096,
3979 .num_internal_phys = 8,
3981 .port_base_addr = 0x10,
3982 .phy_base_addr = 0x0,
3983 .global1_addr = 0x1b,
3984 .global2_addr = 0x1c,
3985 .age_time_coeff = 15000,
3988 .atu_move_port_mask = 0xf,
3991 .tag_protocol = DSA_TAG_PROTO_EDSA,
3992 .ops = &mv88e6097_ops,
3996 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3997 .family = MV88E6XXX_FAMILY_6165,
3998 .name = "Marvell 88E6123",
3999 .num_databases = 4096,
4001 .num_internal_phys = 5,
4003 .port_base_addr = 0x10,
4004 .phy_base_addr = 0x0,
4005 .global1_addr = 0x1b,
4006 .global2_addr = 0x1c,
4007 .age_time_coeff = 15000,
4010 .atu_move_port_mask = 0xf,
4013 .tag_protocol = DSA_TAG_PROTO_EDSA,
4014 .ops = &mv88e6123_ops,
4018 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4019 .family = MV88E6XXX_FAMILY_6185,
4020 .name = "Marvell 88E6131",
4021 .num_databases = 256,
4023 .num_internal_phys = 0,
4025 .port_base_addr = 0x10,
4026 .phy_base_addr = 0x0,
4027 .global1_addr = 0x1b,
4028 .global2_addr = 0x1c,
4029 .age_time_coeff = 15000,
4031 .atu_move_port_mask = 0xf,
4033 .tag_protocol = DSA_TAG_PROTO_DSA,
4034 .ops = &mv88e6131_ops,
4038 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4039 .family = MV88E6XXX_FAMILY_6341,
4040 .name = "Marvell 88E6141",
4041 .num_databases = 4096,
4043 .num_internal_phys = 5,
4046 .port_base_addr = 0x10,
4047 .phy_base_addr = 0x10,
4048 .global1_addr = 0x1b,
4049 .global2_addr = 0x1c,
4050 .age_time_coeff = 3750,
4051 .atu_move_port_mask = 0x1f,
4056 .tag_protocol = DSA_TAG_PROTO_EDSA,
4057 .ops = &mv88e6141_ops,
4061 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4062 .family = MV88E6XXX_FAMILY_6165,
4063 .name = "Marvell 88E6161",
4064 .num_databases = 4096,
4066 .num_internal_phys = 5,
4068 .port_base_addr = 0x10,
4069 .phy_base_addr = 0x0,
4070 .global1_addr = 0x1b,
4071 .global2_addr = 0x1c,
4072 .age_time_coeff = 15000,
4075 .atu_move_port_mask = 0xf,
4078 .tag_protocol = DSA_TAG_PROTO_EDSA,
4079 .ptp_support = true,
4080 .ops = &mv88e6161_ops,
4084 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4085 .family = MV88E6XXX_FAMILY_6165,
4086 .name = "Marvell 88E6165",
4087 .num_databases = 4096,
4089 .num_internal_phys = 0,
4091 .port_base_addr = 0x10,
4092 .phy_base_addr = 0x0,
4093 .global1_addr = 0x1b,
4094 .global2_addr = 0x1c,
4095 .age_time_coeff = 15000,
4098 .atu_move_port_mask = 0xf,
4101 .tag_protocol = DSA_TAG_PROTO_DSA,
4102 .ptp_support = true,
4103 .ops = &mv88e6165_ops,
4107 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4108 .family = MV88E6XXX_FAMILY_6351,
4109 .name = "Marvell 88E6171",
4110 .num_databases = 4096,
4112 .num_internal_phys = 5,
4114 .port_base_addr = 0x10,
4115 .phy_base_addr = 0x0,
4116 .global1_addr = 0x1b,
4117 .global2_addr = 0x1c,
4118 .age_time_coeff = 15000,
4121 .atu_move_port_mask = 0xf,
4124 .tag_protocol = DSA_TAG_PROTO_EDSA,
4125 .ops = &mv88e6171_ops,
4129 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4130 .family = MV88E6XXX_FAMILY_6352,
4131 .name = "Marvell 88E6172",
4132 .num_databases = 4096,
4134 .num_internal_phys = 5,
4137 .port_base_addr = 0x10,
4138 .phy_base_addr = 0x0,
4139 .global1_addr = 0x1b,
4140 .global2_addr = 0x1c,
4141 .age_time_coeff = 15000,
4144 .atu_move_port_mask = 0xf,
4147 .tag_protocol = DSA_TAG_PROTO_EDSA,
4148 .ops = &mv88e6172_ops,
4152 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4153 .family = MV88E6XXX_FAMILY_6351,
4154 .name = "Marvell 88E6175",
4155 .num_databases = 4096,
4157 .num_internal_phys = 5,
4159 .port_base_addr = 0x10,
4160 .phy_base_addr = 0x0,
4161 .global1_addr = 0x1b,
4162 .global2_addr = 0x1c,
4163 .age_time_coeff = 15000,
4166 .atu_move_port_mask = 0xf,
4169 .tag_protocol = DSA_TAG_PROTO_EDSA,
4170 .ops = &mv88e6175_ops,
4174 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4175 .family = MV88E6XXX_FAMILY_6352,
4176 .name = "Marvell 88E6176",
4177 .num_databases = 4096,
4179 .num_internal_phys = 5,
4182 .port_base_addr = 0x10,
4183 .phy_base_addr = 0x0,
4184 .global1_addr = 0x1b,
4185 .global2_addr = 0x1c,
4186 .age_time_coeff = 15000,
4189 .atu_move_port_mask = 0xf,
4192 .tag_protocol = DSA_TAG_PROTO_EDSA,
4193 .ops = &mv88e6176_ops,
4197 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4198 .family = MV88E6XXX_FAMILY_6185,
4199 .name = "Marvell 88E6185",
4200 .num_databases = 256,
4202 .num_internal_phys = 0,
4204 .port_base_addr = 0x10,
4205 .phy_base_addr = 0x0,
4206 .global1_addr = 0x1b,
4207 .global2_addr = 0x1c,
4208 .age_time_coeff = 15000,
4210 .atu_move_port_mask = 0xf,
4212 .tag_protocol = DSA_TAG_PROTO_EDSA,
4213 .ops = &mv88e6185_ops,
4217 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4218 .family = MV88E6XXX_FAMILY_6390,
4219 .name = "Marvell 88E6190",
4220 .num_databases = 4096,
4221 .num_ports = 11, /* 10 + Z80 */
4222 .num_internal_phys = 9,
4225 .port_base_addr = 0x0,
4226 .phy_base_addr = 0x0,
4227 .global1_addr = 0x1b,
4228 .global2_addr = 0x1c,
4229 .tag_protocol = DSA_TAG_PROTO_DSA,
4230 .age_time_coeff = 3750,
4235 .atu_move_port_mask = 0x1f,
4236 .ops = &mv88e6190_ops,
4240 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4241 .family = MV88E6XXX_FAMILY_6390,
4242 .name = "Marvell 88E6190X",
4243 .num_databases = 4096,
4244 .num_ports = 11, /* 10 + Z80 */
4245 .num_internal_phys = 9,
4248 .port_base_addr = 0x0,
4249 .phy_base_addr = 0x0,
4250 .global1_addr = 0x1b,
4251 .global2_addr = 0x1c,
4252 .age_time_coeff = 3750,
4255 .atu_move_port_mask = 0x1f,
4258 .tag_protocol = DSA_TAG_PROTO_DSA,
4259 .ops = &mv88e6190x_ops,
4263 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4264 .family = MV88E6XXX_FAMILY_6390,
4265 .name = "Marvell 88E6191",
4266 .num_databases = 4096,
4267 .num_ports = 11, /* 10 + Z80 */
4268 .num_internal_phys = 9,
4270 .port_base_addr = 0x0,
4271 .phy_base_addr = 0x0,
4272 .global1_addr = 0x1b,
4273 .global2_addr = 0x1c,
4274 .age_time_coeff = 3750,
4277 .atu_move_port_mask = 0x1f,
4280 .tag_protocol = DSA_TAG_PROTO_DSA,
4281 .ptp_support = true,
4282 .ops = &mv88e6191_ops,
4286 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4287 .family = MV88E6XXX_FAMILY_6352,
4288 .name = "Marvell 88E6240",
4289 .num_databases = 4096,
4291 .num_internal_phys = 5,
4294 .port_base_addr = 0x10,
4295 .phy_base_addr = 0x0,
4296 .global1_addr = 0x1b,
4297 .global2_addr = 0x1c,
4298 .age_time_coeff = 15000,
4301 .atu_move_port_mask = 0xf,
4304 .tag_protocol = DSA_TAG_PROTO_EDSA,
4305 .ptp_support = true,
4306 .ops = &mv88e6240_ops,
4310 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4311 .family = MV88E6XXX_FAMILY_6390,
4312 .name = "Marvell 88E6290",
4313 .num_databases = 4096,
4314 .num_ports = 11, /* 10 + Z80 */
4315 .num_internal_phys = 9,
4318 .port_base_addr = 0x0,
4319 .phy_base_addr = 0x0,
4320 .global1_addr = 0x1b,
4321 .global2_addr = 0x1c,
4322 .age_time_coeff = 3750,
4325 .atu_move_port_mask = 0x1f,
4328 .tag_protocol = DSA_TAG_PROTO_DSA,
4329 .ptp_support = true,
4330 .ops = &mv88e6290_ops,
4334 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4335 .family = MV88E6XXX_FAMILY_6320,
4336 .name = "Marvell 88E6320",
4337 .num_databases = 4096,
4339 .num_internal_phys = 5,
4342 .port_base_addr = 0x10,
4343 .phy_base_addr = 0x0,
4344 .global1_addr = 0x1b,
4345 .global2_addr = 0x1c,
4346 .age_time_coeff = 15000,
4349 .atu_move_port_mask = 0xf,
4352 .tag_protocol = DSA_TAG_PROTO_EDSA,
4353 .ptp_support = true,
4354 .ops = &mv88e6320_ops,
4358 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
4359 .family = MV88E6XXX_FAMILY_6320,
4360 .name = "Marvell 88E6321",
4361 .num_databases = 4096,
4363 .num_internal_phys = 5,
4366 .port_base_addr = 0x10,
4367 .phy_base_addr = 0x0,
4368 .global1_addr = 0x1b,
4369 .global2_addr = 0x1c,
4370 .age_time_coeff = 15000,
4373 .atu_move_port_mask = 0xf,
4375 .tag_protocol = DSA_TAG_PROTO_EDSA,
4376 .ptp_support = true,
4377 .ops = &mv88e6321_ops,
4381 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
4382 .family = MV88E6XXX_FAMILY_6341,
4383 .name = "Marvell 88E6341",
4384 .num_databases = 4096,
4385 .num_internal_phys = 5,
4389 .port_base_addr = 0x10,
4390 .phy_base_addr = 0x10,
4391 .global1_addr = 0x1b,
4392 .global2_addr = 0x1c,
4393 .age_time_coeff = 3750,
4394 .atu_move_port_mask = 0x1f,
4399 .tag_protocol = DSA_TAG_PROTO_EDSA,
4400 .ptp_support = true,
4401 .ops = &mv88e6341_ops,
4405 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
4406 .family = MV88E6XXX_FAMILY_6351,
4407 .name = "Marvell 88E6350",
4408 .num_databases = 4096,
4410 .num_internal_phys = 5,
4412 .port_base_addr = 0x10,
4413 .phy_base_addr = 0x0,
4414 .global1_addr = 0x1b,
4415 .global2_addr = 0x1c,
4416 .age_time_coeff = 15000,
4419 .atu_move_port_mask = 0xf,
4422 .tag_protocol = DSA_TAG_PROTO_EDSA,
4423 .ops = &mv88e6350_ops,
4427 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
4428 .family = MV88E6XXX_FAMILY_6351,
4429 .name = "Marvell 88E6351",
4430 .num_databases = 4096,
4432 .num_internal_phys = 5,
4434 .port_base_addr = 0x10,
4435 .phy_base_addr = 0x0,
4436 .global1_addr = 0x1b,
4437 .global2_addr = 0x1c,
4438 .age_time_coeff = 15000,
4441 .atu_move_port_mask = 0xf,
4444 .tag_protocol = DSA_TAG_PROTO_EDSA,
4445 .ops = &mv88e6351_ops,
4449 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
4450 .family = MV88E6XXX_FAMILY_6352,
4451 .name = "Marvell 88E6352",
4452 .num_databases = 4096,
4454 .num_internal_phys = 5,
4457 .port_base_addr = 0x10,
4458 .phy_base_addr = 0x0,
4459 .global1_addr = 0x1b,
4460 .global2_addr = 0x1c,
4461 .age_time_coeff = 15000,
4464 .atu_move_port_mask = 0xf,
4467 .tag_protocol = DSA_TAG_PROTO_EDSA,
4468 .ptp_support = true,
4469 .ops = &mv88e6352_ops,
4472 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
4473 .family = MV88E6XXX_FAMILY_6390,
4474 .name = "Marvell 88E6390",
4475 .num_databases = 4096,
4476 .num_ports = 11, /* 10 + Z80 */
4477 .num_internal_phys = 9,
4480 .port_base_addr = 0x0,
4481 .phy_base_addr = 0x0,
4482 .global1_addr = 0x1b,
4483 .global2_addr = 0x1c,
4484 .age_time_coeff = 3750,
4487 .atu_move_port_mask = 0x1f,
4490 .tag_protocol = DSA_TAG_PROTO_DSA,
4491 .ptp_support = true,
4492 .ops = &mv88e6390_ops,
4495 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
4496 .family = MV88E6XXX_FAMILY_6390,
4497 .name = "Marvell 88E6390X",
4498 .num_databases = 4096,
4499 .num_ports = 11, /* 10 + Z80 */
4500 .num_internal_phys = 9,
4503 .port_base_addr = 0x0,
4504 .phy_base_addr = 0x0,
4505 .global1_addr = 0x1b,
4506 .global2_addr = 0x1c,
4507 .age_time_coeff = 3750,
4510 .atu_move_port_mask = 0x1f,
4513 .tag_protocol = DSA_TAG_PROTO_DSA,
4514 .ptp_support = true,
4515 .ops = &mv88e6390x_ops,
4519 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4523 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4524 if (mv88e6xxx_table[i].prod_num == prod_num)
4525 return &mv88e6xxx_table[i];
4530 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4532 const struct mv88e6xxx_info *info;
4533 unsigned int prod_num, rev;
4537 mutex_lock(&chip->reg_lock);
4538 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4539 mutex_unlock(&chip->reg_lock);
4543 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
4544 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
4546 info = mv88e6xxx_lookup_info(prod_num);
4550 /* Update the compatible info with the probed one */
4553 err = mv88e6xxx_g2_require(chip);
4557 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4558 chip->info->prod_num, chip->info->name, rev);
4563 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4565 struct mv88e6xxx_chip *chip;
4567 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4573 mutex_init(&chip->reg_lock);
4574 INIT_LIST_HEAD(&chip->mdios);
4579 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4580 struct mii_bus *bus, int sw_addr)
4583 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4584 else if (chip->info->multi_chip)
4585 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4590 chip->sw_addr = sw_addr;
4595 static void mv88e6xxx_ports_cmode_init(struct mv88e6xxx_chip *chip)
4599 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
4600 chip->ports[i].cmode = MV88E6XXX_PORT_STS_CMODE_INVALID;
4603 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4606 struct mv88e6xxx_chip *chip = ds->priv;
4608 return chip->info->tag_protocol;
4611 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4612 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4613 struct device *host_dev, int sw_addr,
4616 struct mv88e6xxx_chip *chip;
4617 struct mii_bus *bus;
4620 bus = dsa_host_dev_to_mii_bus(host_dev);
4624 chip = mv88e6xxx_alloc_chip(dsa_dev);
4628 /* Legacy SMI probing will only support chips similar to 88E6085 */
4629 chip->info = &mv88e6xxx_table[MV88E6085];
4631 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4635 err = mv88e6xxx_detect(chip);
4639 mv88e6xxx_ports_cmode_init(chip);
4641 mutex_lock(&chip->reg_lock);
4642 err = mv88e6xxx_switch_reset(chip);
4643 mutex_unlock(&chip->reg_lock);
4647 mv88e6xxx_phy_init(chip);
4649 err = mv88e6xxx_mdios_register(chip, NULL);
4655 return chip->info->name;
4657 devm_kfree(dsa_dev, chip);
4663 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4664 const struct switchdev_obj_port_mdb *mdb)
4666 /* We don't need any dynamic resource from the kernel (yet),
4667 * so skip the prepare phase.
4673 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4674 const struct switchdev_obj_port_mdb *mdb)
4676 struct mv88e6xxx_chip *chip = ds->priv;
4678 mutex_lock(&chip->reg_lock);
4679 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4680 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4681 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
4683 mutex_unlock(&chip->reg_lock);
4686 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4687 const struct switchdev_obj_port_mdb *mdb)
4689 struct mv88e6xxx_chip *chip = ds->priv;
4692 mutex_lock(&chip->reg_lock);
4693 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4694 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4695 mutex_unlock(&chip->reg_lock);
4700 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4701 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4702 .probe = mv88e6xxx_drv_probe,
4704 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4705 .setup = mv88e6xxx_setup,
4706 .adjust_link = mv88e6xxx_adjust_link,
4707 .phylink_validate = mv88e6xxx_validate,
4708 .phylink_mac_link_state = mv88e6xxx_link_state,
4709 .phylink_mac_config = mv88e6xxx_mac_config,
4710 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
4711 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
4712 .get_strings = mv88e6xxx_get_strings,
4713 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4714 .get_sset_count = mv88e6xxx_get_sset_count,
4715 .port_enable = mv88e6xxx_port_enable,
4716 .port_disable = mv88e6xxx_port_disable,
4717 .get_mac_eee = mv88e6xxx_get_mac_eee,
4718 .set_mac_eee = mv88e6xxx_set_mac_eee,
4719 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4720 .get_eeprom = mv88e6xxx_get_eeprom,
4721 .set_eeprom = mv88e6xxx_set_eeprom,
4722 .get_regs_len = mv88e6xxx_get_regs_len,
4723 .get_regs = mv88e6xxx_get_regs,
4724 .set_ageing_time = mv88e6xxx_set_ageing_time,
4725 .port_bridge_join = mv88e6xxx_port_bridge_join,
4726 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4727 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4728 .port_fast_age = mv88e6xxx_port_fast_age,
4729 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4730 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4731 .port_vlan_add = mv88e6xxx_port_vlan_add,
4732 .port_vlan_del = mv88e6xxx_port_vlan_del,
4733 .port_fdb_add = mv88e6xxx_port_fdb_add,
4734 .port_fdb_del = mv88e6xxx_port_fdb_del,
4735 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4736 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4737 .port_mdb_add = mv88e6xxx_port_mdb_add,
4738 .port_mdb_del = mv88e6xxx_port_mdb_del,
4739 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4740 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
4741 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
4742 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
4743 .port_txtstamp = mv88e6xxx_port_txtstamp,
4744 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
4745 .get_ts_info = mv88e6xxx_get_ts_info,
4748 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4749 .ops = &mv88e6xxx_switch_ops,
4752 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4754 struct device *dev = chip->dev;
4755 struct dsa_switch *ds;
4757 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4763 ds->ops = &mv88e6xxx_switch_ops;
4764 ds->ageing_time_min = chip->info->age_time_coeff;
4765 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4767 dev_set_drvdata(dev, ds);
4769 return dsa_register_switch(ds);
4772 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4774 dsa_unregister_switch(chip->ds);
4777 static const void *pdata_device_get_match_data(struct device *dev)
4779 const struct of_device_id *matches = dev->driver->of_match_table;
4780 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
4782 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
4784 if (!strcmp(pdata->compatible, matches->compatible))
4785 return matches->data;
4790 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4792 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
4793 const struct mv88e6xxx_info *compat_info = NULL;
4794 struct device *dev = &mdiodev->dev;
4795 struct device_node *np = dev->of_node;
4796 struct mv88e6xxx_chip *chip;
4804 compat_info = of_device_get_match_data(dev);
4807 compat_info = pdata_device_get_match_data(dev);
4812 for (port = 0; port < DSA_MAX_PORTS; port++) {
4813 if (!(pdata->enabled_ports & (1 << port)))
4815 if (strcmp(pdata->cd.port_names[port], "cpu"))
4817 pdata->cd.netdev[port] = &pdata->netdev->dev;
4825 chip = mv88e6xxx_alloc_chip(dev);
4831 chip->info = compat_info;
4833 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4837 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4838 if (IS_ERR(chip->reset)) {
4839 err = PTR_ERR(chip->reset);
4843 usleep_range(10000, 20000);
4845 err = mv88e6xxx_detect(chip);
4849 mv88e6xxx_ports_cmode_init(chip);
4850 mv88e6xxx_phy_init(chip);
4852 if (chip->info->ops->get_eeprom) {
4854 of_property_read_u32(np, "eeprom-length",
4857 chip->eeprom_len = pdata->eeprom_len;
4860 mutex_lock(&chip->reg_lock);
4861 err = mv88e6xxx_switch_reset(chip);
4862 mutex_unlock(&chip->reg_lock);
4866 chip->irq = of_irq_get(np, 0);
4867 if (chip->irq == -EPROBE_DEFER) {
4872 /* Has to be performed before the MDIO bus is created, because
4873 * the PHYs will link their interrupts to these interrupt
4876 mutex_lock(&chip->reg_lock);
4878 err = mv88e6xxx_g1_irq_setup(chip);
4880 err = mv88e6xxx_irq_poll_setup(chip);
4881 mutex_unlock(&chip->reg_lock);
4886 if (chip->info->g2_irqs > 0) {
4887 err = mv88e6xxx_g2_irq_setup(chip);
4892 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
4896 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
4898 goto out_g1_atu_prob_irq;
4900 err = mv88e6xxx_mdios_register(chip, np);
4902 goto out_g1_vtu_prob_irq;
4904 err = mv88e6xxx_register_switch(chip);
4911 mv88e6xxx_mdios_unregister(chip);
4912 out_g1_vtu_prob_irq:
4913 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4914 out_g1_atu_prob_irq:
4915 mv88e6xxx_g1_atu_prob_irq_free(chip);
4917 if (chip->info->g2_irqs > 0)
4918 mv88e6xxx_g2_irq_free(chip);
4921 mv88e6xxx_g1_irq_free(chip);
4923 mv88e6xxx_irq_poll_free(chip);
4926 dev_put(pdata->netdev);
4931 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4933 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4934 struct mv88e6xxx_chip *chip = ds->priv;
4936 if (chip->info->ptp_support) {
4937 mv88e6xxx_hwtstamp_free(chip);
4938 mv88e6xxx_ptp_free(chip);
4941 mv88e6xxx_phy_destroy(chip);
4942 mv88e6xxx_unregister_switch(chip);
4943 mv88e6xxx_mdios_unregister(chip);
4945 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4946 mv88e6xxx_g1_atu_prob_irq_free(chip);
4948 if (chip->info->g2_irqs > 0)
4949 mv88e6xxx_g2_irq_free(chip);
4952 mv88e6xxx_g1_irq_free(chip);
4954 mv88e6xxx_irq_poll_free(chip);
4957 static const struct of_device_id mv88e6xxx_of_match[] = {
4959 .compatible = "marvell,mv88e6085",
4960 .data = &mv88e6xxx_table[MV88E6085],
4963 .compatible = "marvell,mv88e6190",
4964 .data = &mv88e6xxx_table[MV88E6190],
4969 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4971 static struct mdio_driver mv88e6xxx_driver = {
4972 .probe = mv88e6xxx_probe,
4973 .remove = mv88e6xxx_remove,
4975 .name = "mv88e6085",
4976 .of_match_table = mv88e6xxx_of_match,
4980 static int __init mv88e6xxx_init(void)
4982 register_switch_driver(&mv88e6xxx_switch_drv);
4983 return mdio_driver_register(&mv88e6xxx_driver);
4985 module_init(mv88e6xxx_init);
4987 static void __exit mv88e6xxx_cleanup(void)
4989 mdio_driver_unregister(&mv88e6xxx_driver);
4990 unregister_switch_driver(&mv88e6xxx_switch_drv);
4992 module_exit(mv88e6xxx_cleanup);
4994 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4995 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4996 MODULE_LICENSE("GPL");