1 /* Altera Triple-Speed Ethernet MAC driver
2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
15 * Original driver contributed by SLS.
16 * Major updates contributed by GlobalLogic
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2, as published by the Free Software Foundation.
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
31 #include <linux/atomic.h>
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/if_vlan.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/mii.h>
41 #include <linux/netdevice.h>
42 #include <linux/of_device.h>
43 #include <linux/of_mdio.h>
44 #include <linux/of_net.h>
45 #include <linux/of_platform.h>
46 #include <linux/phy.h>
47 #include <linux/platform_device.h>
48 #include <linux/skbuff.h>
49 #include <asm/cacheflush.h>
51 #include "altera_utils.h"
52 #include "altera_tse.h"
53 #include "altera_sgdma.h"
54 #include "altera_msgdma.h"
56 static atomic_t instance_count = ATOMIC_INIT(~0);
57 /* Module parameters */
58 static int debug = -1;
59 module_param(debug, int, S_IRUGO | S_IWUSR);
60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
62 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
63 NETIF_MSG_LINK | NETIF_MSG_IFUP |
66 #define RX_DESCRIPTORS 64
67 static int dma_rx_num = RX_DESCRIPTORS;
68 module_param(dma_rx_num, int, S_IRUGO | S_IWUSR);
69 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
71 #define TX_DESCRIPTORS 64
72 static int dma_tx_num = TX_DESCRIPTORS;
73 module_param(dma_tx_num, int, S_IRUGO | S_IWUSR);
74 MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list");
79 /* Make sure DMA buffer size is larger than the max frame size
80 * plus some alignment offset and a VLAN header. If the max frame size is
81 * 1518, a VLAN header would be additional 4 bytes and additional
82 * headroom for alignment is 2 bytes, 2048 is just fine.
84 #define ALTERA_RXDMABUFFER_SIZE 2048
86 /* Allow network stack to resume queueing packets after we've
87 * finished transmitting at least 1/4 of the packets in the queue.
89 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
91 #define TXQUEUESTOP_THRESHHOLD 2
93 static const struct of_device_id altera_tse_ids[];
95 static inline u32 tse_tx_avail(struct altera_tse_private *priv)
97 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1;
100 /* PCS Register read/write functions
102 static u16 sgmii_pcs_read(struct altera_tse_private *priv, int regnum)
104 return csrrd32(priv->mac_dev,
105 tse_csroffs(mdio_phy0) + regnum * 4) & 0xffff;
108 static void sgmii_pcs_write(struct altera_tse_private *priv, int regnum,
111 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy0) + regnum * 4);
114 /* Check PCS scratch memory */
115 static int sgmii_pcs_scratch_test(struct altera_tse_private *priv, u16 value)
117 sgmii_pcs_write(priv, SGMII_PCS_SCRATCH, value);
118 return (sgmii_pcs_read(priv, SGMII_PCS_SCRATCH) == value);
121 /* MDIO specific functions
123 static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
125 struct net_device *ndev = bus->priv;
126 struct altera_tse_private *priv = netdev_priv(ndev);
128 /* set MDIO address */
129 csrwr32((mii_id & 0x1f), priv->mac_dev,
130 tse_csroffs(mdio_phy1_addr));
133 return csrrd32(priv->mac_dev,
134 tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff;
137 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
140 struct net_device *ndev = bus->priv;
141 struct altera_tse_private *priv = netdev_priv(ndev);
143 /* set MDIO address */
144 csrwr32((mii_id & 0x1f), priv->mac_dev,
145 tse_csroffs(mdio_phy1_addr));
148 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
152 static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
154 struct altera_tse_private *priv = netdev_priv(dev);
156 struct device_node *mdio_node = NULL;
157 struct mii_bus *mdio = NULL;
158 struct device_node *child_node = NULL;
160 for_each_child_of_node(priv->device->of_node, child_node) {
161 if (of_device_is_compatible(child_node, "altr,tse-mdio")) {
162 mdio_node = child_node;
168 netdev_dbg(dev, "FOUND MDIO subnode\n");
170 netdev_dbg(dev, "NO MDIO subnode\n");
174 mdio = mdiobus_alloc();
176 netdev_err(dev, "Error allocating MDIO bus\n");
181 mdio->name = ALTERA_TSE_RESOURCE_NAME;
182 mdio->read = &altera_tse_mdio_read;
183 mdio->write = &altera_tse_mdio_write;
184 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id);
187 mdio->parent = priv->device;
189 ret = of_mdiobus_register(mdio, mdio_node);
191 netdev_err(dev, "Cannot register MDIO bus %s\n",
195 of_node_put(mdio_node);
197 if (netif_msg_drv(priv))
198 netdev_info(dev, "MDIO bus %s: created\n", mdio->id);
206 of_node_put(mdio_node);
210 static void altera_tse_mdio_destroy(struct net_device *dev)
212 struct altera_tse_private *priv = netdev_priv(dev);
214 if (priv->mdio == NULL)
217 if (netif_msg_drv(priv))
218 netdev_info(dev, "MDIO bus %s: removed\n",
221 mdiobus_unregister(priv->mdio);
222 mdiobus_free(priv->mdio);
226 static int tse_init_rx_buffer(struct altera_tse_private *priv,
227 struct tse_buffer *rxbuffer, int len)
229 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len);
233 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data,
237 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) {
238 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
239 dev_kfree_skb_any(rxbuffer->skb);
242 rxbuffer->dma_addr &= (dma_addr_t)~3;
247 static void tse_free_rx_buffer(struct altera_tse_private *priv,
248 struct tse_buffer *rxbuffer)
250 struct sk_buff *skb = rxbuffer->skb;
251 dma_addr_t dma_addr = rxbuffer->dma_addr;
255 dma_unmap_single(priv->device, dma_addr,
258 dev_kfree_skb_any(skb);
259 rxbuffer->skb = NULL;
260 rxbuffer->dma_addr = 0;
264 /* Unmap and free Tx buffer resources
266 static void tse_free_tx_buffer(struct altera_tse_private *priv,
267 struct tse_buffer *buffer)
269 if (buffer->dma_addr) {
270 if (buffer->mapped_as_page)
271 dma_unmap_page(priv->device, buffer->dma_addr,
272 buffer->len, DMA_TO_DEVICE);
274 dma_unmap_single(priv->device, buffer->dma_addr,
275 buffer->len, DMA_TO_DEVICE);
276 buffer->dma_addr = 0;
279 dev_kfree_skb_any(buffer->skb);
284 static int alloc_init_skbufs(struct altera_tse_private *priv)
286 unsigned int rx_descs = priv->rx_ring_size;
287 unsigned int tx_descs = priv->tx_ring_size;
291 /* Create Rx ring buffer */
292 priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer),
297 /* Create Tx ring buffer */
298 priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer),
307 for (i = 0; i < rx_descs; i++) {
308 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i],
309 priv->rx_dma_buf_sz);
311 goto err_init_rx_buffers;
320 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
321 kfree(priv->tx_ring);
323 kfree(priv->rx_ring);
328 static void free_skbufs(struct net_device *dev)
330 struct altera_tse_private *priv = netdev_priv(dev);
331 unsigned int rx_descs = priv->rx_ring_size;
332 unsigned int tx_descs = priv->tx_ring_size;
335 /* Release the DMA TX/RX socket buffers */
336 for (i = 0; i < rx_descs; i++)
337 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
338 for (i = 0; i < tx_descs; i++)
339 tse_free_tx_buffer(priv, &priv->tx_ring[i]);
342 kfree(priv->tx_ring);
345 /* Reallocate the skb for the reception process
347 static inline void tse_rx_refill(struct altera_tse_private *priv)
349 unsigned int rxsize = priv->rx_ring_size;
353 for (; priv->rx_cons - priv->rx_prod > 0;
355 entry = priv->rx_prod % rxsize;
356 if (likely(priv->rx_ring[entry].skb == NULL)) {
357 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry],
358 priv->rx_dma_buf_sz);
359 if (unlikely(ret != 0))
361 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]);
366 /* Pull out the VLAN tag and fix up the packet
368 static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb)
370 struct ethhdr *eth_hdr;
372 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
373 !__vlan_get_tag(skb, &vid)) {
374 eth_hdr = (struct ethhdr *)skb->data;
375 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
376 skb_pull(skb, VLAN_HLEN);
377 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
381 /* Receive a packet: retrieve and pass over to upper levels
383 static int tse_rx(struct altera_tse_private *priv, int limit)
385 unsigned int count = 0;
386 unsigned int next_entry;
388 unsigned int entry = priv->rx_cons % priv->rx_ring_size;
393 /* Check for count < limit first as get_rx_status is changing
394 * the response-fifo so we must process the next packet
395 * after calling get_rx_status if a response is pending.
396 * (reading the last byte of the response pops the value from the fifo.)
398 while ((count < limit) &&
399 ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0)) {
400 pktstatus = rxstatus >> 16;
401 pktlength = rxstatus & 0xffff;
403 if ((pktstatus & 0xFF) || (pktlength == 0))
404 netdev_err(priv->dev,
405 "RCV pktstatus %08X pktlength %08X\n",
406 pktstatus, pktlength);
408 /* DMA trasfer from TSE starts with 2 aditional bytes for
409 * IP payload alignment. Status returned by get_rx_status()
410 * contains DMA transfer length. Packet is 2 bytes shorter.
415 next_entry = (++priv->rx_cons) % priv->rx_ring_size;
417 skb = priv->rx_ring[entry].skb;
418 if (unlikely(!skb)) {
419 netdev_err(priv->dev,
420 "%s: Inconsistent Rx descriptor chain\n",
422 priv->dev->stats.rx_dropped++;
425 priv->rx_ring[entry].skb = NULL;
427 skb_put(skb, pktlength);
429 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr,
430 priv->rx_ring[entry].len, DMA_FROM_DEVICE);
432 if (netif_msg_pktdata(priv)) {
433 netdev_info(priv->dev, "frame received %d bytes\n",
435 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET,
436 16, 1, skb->data, pktlength, true);
439 tse_rx_vlan(priv->dev, skb);
441 skb->protocol = eth_type_trans(skb, priv->dev);
442 skb_checksum_none_assert(skb);
444 napi_gro_receive(&priv->napi, skb);
446 priv->dev->stats.rx_packets++;
447 priv->dev->stats.rx_bytes += pktlength;
457 /* Reclaim resources after transmission completes
459 static int tse_tx_complete(struct altera_tse_private *priv)
461 unsigned int txsize = priv->tx_ring_size;
464 struct tse_buffer *tx_buff;
467 spin_lock(&priv->tx_lock);
469 ready = priv->dmaops->tx_completions(priv);
471 /* Free sent buffers */
472 while (ready && (priv->tx_cons != priv->tx_prod)) {
473 entry = priv->tx_cons % txsize;
474 tx_buff = &priv->tx_ring[entry];
476 if (netif_msg_tx_done(priv))
477 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n",
478 __func__, priv->tx_prod, priv->tx_cons);
480 if (likely(tx_buff->skb))
481 priv->dev->stats.tx_packets++;
483 tse_free_tx_buffer(priv, tx_buff);
490 if (unlikely(netif_queue_stopped(priv->dev) &&
491 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) {
492 if (netif_queue_stopped(priv->dev) &&
493 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) {
494 if (netif_msg_tx_done(priv))
495 netdev_dbg(priv->dev, "%s: restart transmit\n",
497 netif_wake_queue(priv->dev);
501 spin_unlock(&priv->tx_lock);
505 /* NAPI polling function
507 static int tse_poll(struct napi_struct *napi, int budget)
509 struct altera_tse_private *priv =
510 container_of(napi, struct altera_tse_private, napi);
512 unsigned long int flags;
514 tse_tx_complete(priv);
516 rxcomplete = tse_rx(priv, budget);
518 if (rxcomplete < budget) {
520 napi_complete_done(napi, rxcomplete);
522 netdev_dbg(priv->dev,
523 "NAPI Complete, did %d packets with budget %d\n",
526 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
527 priv->dmaops->enable_rxirq(priv);
528 priv->dmaops->enable_txirq(priv);
529 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
534 /* DMA TX & RX FIFO interrupt routing
536 static irqreturn_t altera_isr(int irq, void *dev_id)
538 struct net_device *dev = dev_id;
539 struct altera_tse_private *priv;
541 if (unlikely(!dev)) {
542 pr_err("%s: invalid dev pointer\n", __func__);
545 priv = netdev_priv(dev);
547 spin_lock(&priv->rxdma_irq_lock);
549 priv->dmaops->clear_rxirq(priv);
550 priv->dmaops->clear_txirq(priv);
551 spin_unlock(&priv->rxdma_irq_lock);
553 if (likely(napi_schedule_prep(&priv->napi))) {
554 spin_lock(&priv->rxdma_irq_lock);
555 priv->dmaops->disable_rxirq(priv);
556 priv->dmaops->disable_txirq(priv);
557 spin_unlock(&priv->rxdma_irq_lock);
558 __napi_schedule(&priv->napi);
565 /* Transmit a packet (called by the kernel). Dispatches
566 * either the SGDMA method for transmitting or the
567 * MSGDMA method, assumes no scatter/gather support,
568 * implying an assumption that there's only one
569 * physically contiguous fragment starting at
570 * skb->data, for length of skb_headlen(skb).
572 static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
574 struct altera_tse_private *priv = netdev_priv(dev);
575 unsigned int txsize = priv->tx_ring_size;
577 struct tse_buffer *buffer = NULL;
578 int nfrags = skb_shinfo(skb)->nr_frags;
579 unsigned int nopaged_len = skb_headlen(skb);
580 enum netdev_tx ret = NETDEV_TX_OK;
583 spin_lock_bh(&priv->tx_lock);
585 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) {
586 if (!netif_queue_stopped(dev)) {
587 netif_stop_queue(dev);
588 /* This is a hard error, log it. */
589 netdev_err(priv->dev,
590 "%s: Tx list full when queue awake\n",
593 ret = NETDEV_TX_BUSY;
597 /* Map the first skb fragment */
598 entry = priv->tx_prod % txsize;
599 buffer = &priv->tx_ring[entry];
601 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len,
603 if (dma_mapping_error(priv->device, dma_addr)) {
604 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
610 buffer->dma_addr = dma_addr;
611 buffer->len = nopaged_len;
613 priv->dmaops->tx_buffer(priv, buffer);
615 skb_tx_timestamp(skb);
618 dev->stats.tx_bytes += skb->len;
620 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) {
621 if (netif_msg_hw(priv))
622 netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
624 netif_stop_queue(dev);
628 spin_unlock_bh(&priv->tx_lock);
633 /* Called every time the controller might need to be made
634 * aware of new link state. The PHY code conveys this
635 * information through variables in the phydev structure, and this
636 * function converts those variables into the appropriate
637 * register values, and can bring down the device if needed.
639 static void altera_tse_adjust_link(struct net_device *dev)
641 struct altera_tse_private *priv = netdev_priv(dev);
642 struct phy_device *phydev = dev->phydev;
645 /* only change config if there is a link */
646 spin_lock(&priv->mac_cfg_lock);
648 /* Read old config */
649 u32 cfg_reg = ioread32(&priv->mac_dev->command_config);
652 if (phydev->duplex != priv->oldduplex) {
654 if (!(phydev->duplex))
655 cfg_reg |= MAC_CMDCFG_HD_ENA;
657 cfg_reg &= ~MAC_CMDCFG_HD_ENA;
659 netdev_dbg(priv->dev, "%s: Link duplex = 0x%x\n",
660 dev->name, phydev->duplex);
662 priv->oldduplex = phydev->duplex;
666 if (phydev->speed != priv->oldspeed) {
668 switch (phydev->speed) {
670 cfg_reg |= MAC_CMDCFG_ETH_SPEED;
671 cfg_reg &= ~MAC_CMDCFG_ENA_10;
674 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
675 cfg_reg &= ~MAC_CMDCFG_ENA_10;
678 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
679 cfg_reg |= MAC_CMDCFG_ENA_10;
682 if (netif_msg_link(priv))
683 netdev_warn(dev, "Speed (%d) is not 10/100/1000!\n",
687 priv->oldspeed = phydev->speed;
689 iowrite32(cfg_reg, &priv->mac_dev->command_config);
691 if (!priv->oldlink) {
695 } else if (priv->oldlink) {
699 priv->oldduplex = -1;
702 if (new_state && netif_msg_link(priv))
703 phy_print_status(phydev);
705 spin_unlock(&priv->mac_cfg_lock);
707 static struct phy_device *connect_local_phy(struct net_device *dev)
709 struct altera_tse_private *priv = netdev_priv(dev);
710 struct phy_device *phydev = NULL;
711 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
713 if (priv->phy_addr != POLL_PHY) {
714 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
715 priv->mdio->id, priv->phy_addr);
717 netdev_dbg(dev, "trying to attach to %s\n", phy_id_fmt);
719 phydev = phy_connect(dev, phy_id_fmt, &altera_tse_adjust_link,
721 if (IS_ERR(phydev)) {
722 netdev_err(dev, "Could not attach to PHY\n");
728 phydev = phy_find_first(priv->mdio);
729 if (phydev == NULL) {
730 netdev_err(dev, "No PHY found\n");
734 ret = phy_connect_direct(dev, phydev, &altera_tse_adjust_link,
737 netdev_err(dev, "Could not attach to PHY\n");
744 static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev)
746 struct altera_tse_private *priv = netdev_priv(dev);
747 struct device_node *np = priv->device->of_node;
750 priv->phy_iface = of_get_phy_mode(np);
752 /* Avoid get phy addr and create mdio if no phy is present */
753 if (!priv->phy_iface)
756 /* try to get PHY address from device tree, use PHY autodetection if
757 * no valid address is given
760 if (of_property_read_u32(priv->device->of_node, "phy-addr",
762 priv->phy_addr = POLL_PHY;
765 if (!((priv->phy_addr == POLL_PHY) ||
766 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) {
767 netdev_err(dev, "invalid phy-addr specified %d\n",
772 /* Create/attach to MDIO bus */
773 ret = altera_tse_mdio_create(dev,
774 atomic_add_return(1, &instance_count));
782 /* Initialize driver's PHY state, and attach to the PHY
784 static int init_phy(struct net_device *dev)
786 struct altera_tse_private *priv = netdev_priv(dev);
787 struct phy_device *phydev;
788 struct device_node *phynode;
789 bool fixed_link = false;
792 /* Avoid init phy in case of no phy present */
793 if (!priv->phy_iface)
798 priv->oldduplex = -1;
800 phynode = of_parse_phandle(priv->device->of_node, "phy-handle", 0);
803 /* check if a fixed-link is defined in device-tree */
804 if (of_phy_is_fixed_link(priv->device->of_node)) {
805 rc = of_phy_register_fixed_link(priv->device->of_node);
807 netdev_err(dev, "cannot register fixed PHY\n");
811 /* In the case of a fixed PHY, the DT node associated
812 * to the PHY is the Ethernet MAC DT node.
814 phynode = of_node_get(priv->device->of_node);
817 netdev_dbg(dev, "fixed-link detected\n");
818 phydev = of_phy_connect(dev, phynode,
819 &altera_tse_adjust_link,
822 netdev_dbg(dev, "no phy-handle found\n");
824 netdev_err(dev, "No phy-handle nor local mdio specified\n");
827 phydev = connect_local_phy(dev);
830 netdev_dbg(dev, "phy-handle found\n");
831 phydev = of_phy_connect(dev, phynode,
832 &altera_tse_adjust_link, 0, priv->phy_iface);
834 of_node_put(phynode);
837 netdev_err(dev, "Could not find the PHY\n");
839 of_phy_deregister_fixed_link(priv->device->of_node);
843 /* Stop Advertising 1000BASE Capability if interface is not GMII
844 * Note: Checkpatch throws CHECKs for the camel case defines below,
847 if ((priv->phy_iface == PHY_INTERFACE_MODE_MII) ||
848 (priv->phy_iface == PHY_INTERFACE_MODE_RMII))
849 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
850 SUPPORTED_1000baseT_Full);
852 /* Broken HW is sometimes missing the pull-up resistor on the
853 * MDIO line, which results in reads to non-existent devices returning
854 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
855 * device as well. If a fixed-link is used the phy_id is always 0.
856 * Note: phydev->phy_id is the result of reading the UID PHY registers.
858 if ((phydev->phy_id == 0) && !fixed_link) {
859 netdev_err(dev, "Bad PHY UID 0x%08x\n", phydev->phy_id);
860 phy_disconnect(phydev);
864 netdev_dbg(dev, "attached to PHY %d UID 0x%08x Link = %d\n",
865 phydev->mdio.addr, phydev->phy_id, phydev->link);
870 static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr)
875 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
876 lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
878 /* Set primary MAC address */
879 csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0));
880 csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1));
883 /* MAC software reset.
884 * When reset is triggered, the MAC function completes the current
885 * transmission or reception, and subsequently disables the transmit and
886 * receive logic, flushes the receive FIFO buffer, and resets the statistics
889 static int reset_mac(struct altera_tse_private *priv)
894 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
895 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
896 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
897 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
900 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
901 if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config),
902 MAC_CMDCFG_SW_RESET))
907 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
908 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
909 dat &= ~MAC_CMDCFG_SW_RESET;
910 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
916 /* Initialize MAC core registers
918 static int init_mac(struct altera_tse_private *priv)
920 unsigned int cmd = 0;
924 csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
925 priv->mac_dev, tse_csroffs(rx_section_empty));
927 csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev,
928 tse_csroffs(rx_section_full));
930 csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev,
931 tse_csroffs(rx_almost_empty));
933 csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev,
934 tse_csroffs(rx_almost_full));
937 csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
938 priv->mac_dev, tse_csroffs(tx_section_empty));
940 csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev,
941 tse_csroffs(tx_section_full));
943 csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev,
944 tse_csroffs(tx_almost_empty));
946 csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev,
947 tse_csroffs(tx_almost_full));
949 /* MAC Address Configuration */
950 tse_update_mac_addr(priv, priv->dev->dev_addr);
952 /* MAC Function Configuration */
953 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
954 csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length));
956 csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev,
957 tse_csroffs(tx_ipg_length));
959 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
962 tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat),
963 ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
965 tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat),
966 ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
967 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
969 /* Set the MAC options */
970 cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config));
971 cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */
972 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */
973 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames
976 cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
977 cmd &= ~MAC_CMDCFG_TX_ENA;
978 cmd &= ~MAC_CMDCFG_RX_ENA;
980 /* Default speed and duplex setting, full/100 */
981 cmd &= ~MAC_CMDCFG_HD_ENA;
982 cmd &= ~MAC_CMDCFG_ETH_SPEED;
983 cmd &= ~MAC_CMDCFG_ENA_10;
985 csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config));
987 csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev,
988 tse_csroffs(pause_quanta));
990 if (netif_msg_hw(priv))
991 dev_dbg(priv->device,
992 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd);
997 /* Start/stop MAC transmission logic
999 static void tse_set_mac(struct altera_tse_private *priv, bool enable)
1001 u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config));
1004 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
1006 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
1008 csrwr32(value, priv->mac_dev, tse_csroffs(command_config));
1013 static int tse_change_mtu(struct net_device *dev, int new_mtu)
1015 if (netif_running(dev)) {
1016 netdev_err(dev, "must be stopped to change its MTU\n");
1021 netdev_update_features(dev);
1026 static void altera_tse_set_mcfilter(struct net_device *dev)
1028 struct altera_tse_private *priv = netdev_priv(dev);
1030 struct netdev_hw_addr *ha;
1032 /* clear the hash filter */
1033 for (i = 0; i < 64; i++)
1034 csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1036 netdev_for_each_mc_addr(ha, dev) {
1037 unsigned int hash = 0;
1040 for (mac_octet = 5; mac_octet >= 0; mac_octet--) {
1041 unsigned char xor_bit = 0;
1042 unsigned char octet = ha->addr[mac_octet];
1043 unsigned int bitshift;
1045 for (bitshift = 0; bitshift < 8; bitshift++)
1046 xor_bit ^= ((octet >> bitshift) & 0x01);
1048 hash = (hash << 1) | xor_bit;
1050 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4);
1055 static void altera_tse_set_mcfilterall(struct net_device *dev)
1057 struct altera_tse_private *priv = netdev_priv(dev);
1060 /* set the hash filter */
1061 for (i = 0; i < 64; i++)
1062 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1065 /* Set or clear the multicast filter for this adaptor
1067 static void tse_set_rx_mode_hashfilter(struct net_device *dev)
1069 struct altera_tse_private *priv = netdev_priv(dev);
1071 spin_lock(&priv->mac_cfg_lock);
1073 if (dev->flags & IFF_PROMISC)
1074 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1075 MAC_CMDCFG_PROMIS_EN);
1077 if (dev->flags & IFF_ALLMULTI)
1078 altera_tse_set_mcfilterall(dev);
1080 altera_tse_set_mcfilter(dev);
1082 spin_unlock(&priv->mac_cfg_lock);
1085 /* Set or clear the multicast filter for this adaptor
1087 static void tse_set_rx_mode(struct net_device *dev)
1089 struct altera_tse_private *priv = netdev_priv(dev);
1091 spin_lock(&priv->mac_cfg_lock);
1093 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
1094 !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
1095 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1096 MAC_CMDCFG_PROMIS_EN);
1098 tse_clear_bit(priv->mac_dev, tse_csroffs(command_config),
1099 MAC_CMDCFG_PROMIS_EN);
1101 spin_unlock(&priv->mac_cfg_lock);
1104 /* Initialise (if necessary) the SGMII PCS component
1106 static int init_sgmii_pcs(struct net_device *dev)
1108 struct altera_tse_private *priv = netdev_priv(dev);
1110 unsigned int tmp_reg = 0;
1112 if (priv->phy_iface != PHY_INTERFACE_MODE_SGMII)
1113 return 0; /* Nothing to do, not in SGMII mode */
1115 /* The TSE SGMII PCS block looks a little like a PHY, it is
1116 * mapped into the zeroth MDIO space of the MAC and it has
1117 * ID registers like a PHY would. Sadly this is often
1118 * configured to zeroes, so don't be surprised if it does
1122 if (sgmii_pcs_scratch_test(priv, 0x0000) &&
1123 sgmii_pcs_scratch_test(priv, 0xffff) &&
1124 sgmii_pcs_scratch_test(priv, 0xa5a5) &&
1125 sgmii_pcs_scratch_test(priv, 0x5a5a)) {
1126 netdev_info(dev, "PCS PHY ID: 0x%04x%04x\n",
1127 sgmii_pcs_read(priv, MII_PHYSID1),
1128 sgmii_pcs_read(priv, MII_PHYSID2));
1130 netdev_err(dev, "SGMII PCS Scratch memory test failed.\n");
1134 /* Starting on page 5-29 of the MegaCore Function User Guide
1135 * Set SGMII Link timer to 1.6ms
1137 sgmii_pcs_write(priv, SGMII_PCS_LINK_TIMER_0, 0x0D40);
1138 sgmii_pcs_write(priv, SGMII_PCS_LINK_TIMER_1, 0x03);
1140 /* Enable SGMII Interface and Enable SGMII Auto Negotiation */
1141 sgmii_pcs_write(priv, SGMII_PCS_IF_MODE, 0x3);
1143 /* Enable Autonegotiation */
1144 tmp_reg = sgmii_pcs_read(priv, MII_BMCR);
1145 tmp_reg |= (BMCR_SPEED1000 | BMCR_FULLDPLX | BMCR_ANENABLE);
1146 sgmii_pcs_write(priv, MII_BMCR, tmp_reg);
1148 /* Reset PCS block */
1149 tmp_reg |= BMCR_RESET;
1150 sgmii_pcs_write(priv, MII_BMCR, tmp_reg);
1151 for (n = 0; n < SGMII_PCS_SW_RESET_TIMEOUT; n++) {
1152 if (!(sgmii_pcs_read(priv, MII_BMCR) & BMCR_RESET)) {
1153 netdev_info(dev, "SGMII PCS block initialised OK\n");
1159 /* We failed to reset the block, return a timeout */
1160 netdev_err(dev, "SGMII PCS block reset failed.\n");
1164 /* Open and initialize the interface
1166 static int tse_open(struct net_device *dev)
1168 struct altera_tse_private *priv = netdev_priv(dev);
1171 unsigned long int flags;
1173 /* Reset and configure TSE MAC and probe associated PHY */
1174 ret = priv->dmaops->init_dma(priv);
1176 netdev_err(dev, "Cannot initialize DMA\n");
1180 if (netif_msg_ifup(priv))
1181 netdev_warn(dev, "device MAC address %pM\n",
1184 if ((priv->revision < 0xd00) || (priv->revision > 0xe00))
1185 netdev_warn(dev, "TSE revision %x\n", priv->revision);
1187 spin_lock(&priv->mac_cfg_lock);
1188 /* no-op if MAC not operating in SGMII mode*/
1189 ret = init_sgmii_pcs(dev);
1192 "Cannot init the SGMII PCS (error: %d)\n", ret);
1193 spin_unlock(&priv->mac_cfg_lock);
1197 ret = reset_mac(priv);
1198 /* Note that reset_mac will fail if the clocks are gated by the PHY
1199 * due to the PHY being put into isolation or power down mode.
1200 * This is not an error if reset fails due to no clock.
1203 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1205 ret = init_mac(priv);
1206 spin_unlock(&priv->mac_cfg_lock);
1208 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret);
1209 goto alloc_skbuf_error;
1212 priv->dmaops->reset_dma(priv);
1214 /* Create and initialize the TX/RX descriptors chains. */
1215 priv->rx_ring_size = dma_rx_num;
1216 priv->tx_ring_size = dma_tx_num;
1217 ret = alloc_init_skbufs(priv);
1219 netdev_err(dev, "DMA descriptors initialization failed\n");
1220 goto alloc_skbuf_error;
1224 /* Register RX interrupt */
1225 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED,
1228 netdev_err(dev, "Unable to register RX interrupt %d\n",
1233 /* Register TX interrupt */
1234 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED,
1237 netdev_err(dev, "Unable to register TX interrupt %d\n",
1239 goto tx_request_irq_error;
1242 /* Enable DMA interrupts */
1243 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1244 priv->dmaops->enable_rxirq(priv);
1245 priv->dmaops->enable_txirq(priv);
1247 /* Setup RX descriptor chain */
1248 for (i = 0; i < priv->rx_ring_size; i++)
1249 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]);
1251 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1254 phy_start(dev->phydev);
1256 napi_enable(&priv->napi);
1257 netif_start_queue(dev);
1259 priv->dmaops->start_rxdma(priv);
1261 /* Start MAC Rx/Tx */
1262 spin_lock(&priv->mac_cfg_lock);
1263 tse_set_mac(priv, true);
1264 spin_unlock(&priv->mac_cfg_lock);
1268 tx_request_irq_error:
1269 free_irq(priv->rx_irq, dev);
1277 /* Stop TSE MAC interface and put the device in an inactive state
1279 static int tse_shutdown(struct net_device *dev)
1281 struct altera_tse_private *priv = netdev_priv(dev);
1283 unsigned long int flags;
1287 phy_stop(dev->phydev);
1289 netif_stop_queue(dev);
1290 napi_disable(&priv->napi);
1292 /* Disable DMA interrupts */
1293 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1294 priv->dmaops->disable_rxirq(priv);
1295 priv->dmaops->disable_txirq(priv);
1296 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1298 /* Free the IRQ lines */
1299 free_irq(priv->rx_irq, dev);
1300 free_irq(priv->tx_irq, dev);
1302 /* disable and reset the MAC, empties fifo */
1303 spin_lock(&priv->mac_cfg_lock);
1304 spin_lock(&priv->tx_lock);
1306 ret = reset_mac(priv);
1307 /* Note that reset_mac will fail if the clocks are gated by the PHY
1308 * due to the PHY being put into isolation or power down mode.
1309 * This is not an error if reset fails due to no clock.
1312 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1313 priv->dmaops->reset_dma(priv);
1316 spin_unlock(&priv->tx_lock);
1317 spin_unlock(&priv->mac_cfg_lock);
1319 priv->dmaops->uninit_dma(priv);
1324 static struct net_device_ops altera_tse_netdev_ops = {
1325 .ndo_open = tse_open,
1326 .ndo_stop = tse_shutdown,
1327 .ndo_start_xmit = tse_start_xmit,
1328 .ndo_set_mac_address = eth_mac_addr,
1329 .ndo_set_rx_mode = tse_set_rx_mode,
1330 .ndo_change_mtu = tse_change_mtu,
1331 .ndo_validate_addr = eth_validate_addr,
1334 static int request_and_map(struct platform_device *pdev, const char *name,
1335 struct resource **res, void __iomem **ptr)
1337 struct resource *region;
1338 struct device *device = &pdev->dev;
1340 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
1342 dev_err(device, "resource %s not defined\n", name);
1346 region = devm_request_mem_region(device, (*res)->start,
1347 resource_size(*res), dev_name(device));
1348 if (region == NULL) {
1349 dev_err(device, "unable to request %s\n", name);
1353 *ptr = devm_ioremap_nocache(device, region->start,
1354 resource_size(region));
1356 dev_err(device, "ioremap_nocache of %s failed!", name);
1363 /* Probe Altera TSE MAC device
1365 static int altera_tse_probe(struct platform_device *pdev)
1367 struct net_device *ndev;
1369 struct resource *control_port;
1370 struct resource *dma_res;
1371 struct altera_tse_private *priv;
1372 const unsigned char *macaddr;
1373 void __iomem *descmap;
1374 const struct of_device_id *of_id = NULL;
1376 ndev = alloc_etherdev(sizeof(struct altera_tse_private));
1378 dev_err(&pdev->dev, "Could not allocate network device\n");
1382 SET_NETDEV_DEV(ndev, &pdev->dev);
1384 priv = netdev_priv(ndev);
1385 priv->device = &pdev->dev;
1387 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1389 of_id = of_match_device(altera_tse_ids, &pdev->dev);
1392 priv->dmaops = (struct altera_dmaops *)of_id->data;
1396 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) {
1397 /* Get the mapped address to the SGDMA descriptor memory */
1398 ret = request_and_map(pdev, "s1", &dma_res, &descmap);
1400 goto err_free_netdev;
1402 /* Start of that memory is for transmit descriptors */
1403 priv->tx_dma_desc = descmap;
1405 /* First half is for tx descriptors, other half for tx */
1406 priv->txdescmem = resource_size(dma_res)/2;
1408 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start;
1410 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap +
1412 priv->rxdescmem = resource_size(dma_res)/2;
1413 priv->rxdescmem_busaddr = dma_res->start;
1414 priv->rxdescmem_busaddr += priv->txdescmem;
1416 if (upper_32_bits(priv->rxdescmem_busaddr)) {
1417 dev_dbg(priv->device,
1418 "SGDMA bus addresses greater than 32-bits\n");
1420 goto err_free_netdev;
1422 if (upper_32_bits(priv->txdescmem_busaddr)) {
1423 dev_dbg(priv->device,
1424 "SGDMA bus addresses greater than 32-bits\n");
1426 goto err_free_netdev;
1428 } else if (priv->dmaops &&
1429 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) {
1430 ret = request_and_map(pdev, "rx_resp", &dma_res,
1431 &priv->rx_dma_resp);
1433 goto err_free_netdev;
1435 ret = request_and_map(pdev, "tx_desc", &dma_res,
1436 &priv->tx_dma_desc);
1438 goto err_free_netdev;
1440 priv->txdescmem = resource_size(dma_res);
1441 priv->txdescmem_busaddr = dma_res->start;
1443 ret = request_and_map(pdev, "rx_desc", &dma_res,
1444 &priv->rx_dma_desc);
1446 goto err_free_netdev;
1448 priv->rxdescmem = resource_size(dma_res);
1449 priv->rxdescmem_busaddr = dma_res->start;
1453 goto err_free_netdev;
1456 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask))) {
1457 dma_set_coherent_mask(priv->device,
1458 DMA_BIT_MASK(priv->dmaops->dmamask));
1459 } else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32))) {
1460 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32));
1463 goto err_free_netdev;
1466 /* MAC address space */
1467 ret = request_and_map(pdev, "control_port", &control_port,
1468 (void __iomem **)&priv->mac_dev);
1470 goto err_free_netdev;
1472 /* xSGDMA Rx Dispatcher address space */
1473 ret = request_and_map(pdev, "rx_csr", &dma_res,
1476 goto err_free_netdev;
1479 /* xSGDMA Tx Dispatcher address space */
1480 ret = request_and_map(pdev, "tx_csr", &dma_res,
1483 goto err_free_netdev;
1487 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq");
1488 if (priv->rx_irq == -ENXIO) {
1489 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n");
1491 goto err_free_netdev;
1495 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq");
1496 if (priv->tx_irq == -ENXIO) {
1497 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n");
1499 goto err_free_netdev;
1502 /* get FIFO depths from device tree */
1503 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1504 &priv->rx_fifo_depth)) {
1505 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n");
1507 goto err_free_netdev;
1510 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1511 &priv->tx_fifo_depth)) {
1512 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n");
1514 goto err_free_netdev;
1517 /* get hash filter settings for this instance */
1519 of_property_read_bool(pdev->dev.of_node,
1520 "altr,has-hash-multicast-filter");
1522 /* Set hash filter to not set for now until the
1523 * multicast filter receive issue is debugged
1525 priv->hash_filter = 0;
1527 /* get supplemental address settings for this instance */
1528 priv->added_unicast =
1529 of_property_read_bool(pdev->dev.of_node,
1530 "altr,has-supplementary-unicast");
1532 priv->dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN;
1533 /* Max MTU is 1500, ETH_DATA_LEN */
1534 priv->dev->max_mtu = ETH_DATA_LEN;
1536 /* Get the max mtu from the device tree. Note that the
1537 * "max-frame-size" parameter is actually max mtu. Definition
1538 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1540 of_property_read_u32(pdev->dev.of_node, "max-frame-size",
1541 &priv->dev->max_mtu);
1543 /* The DMA buffer size already accounts for an alignment bias
1544 * to avoid unaligned access exceptions for the NIOS processor,
1546 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;
1548 /* get default MAC address from device tree */
1549 macaddr = of_get_mac_address(pdev->dev.of_node);
1551 ether_addr_copy(ndev->dev_addr, macaddr);
1553 eth_hw_addr_random(ndev);
1555 /* get phy addr and create mdio */
1556 ret = altera_tse_phy_get_addr_mdio_create(ndev);
1559 goto err_free_netdev;
1561 /* initialize netdev */
1562 ndev->mem_start = control_port->start;
1563 ndev->mem_end = control_port->end;
1564 ndev->netdev_ops = &altera_tse_netdev_ops;
1565 altera_tse_set_ethtool_ops(ndev);
1567 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode;
1569 if (priv->hash_filter)
1570 altera_tse_netdev_ops.ndo_set_rx_mode =
1571 tse_set_rx_mode_hashfilter;
1573 /* Scatter/gather IO is not supported,
1574 * so it is turned off
1576 ndev->hw_features &= ~NETIF_F_SG;
1577 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1579 /* VLAN offloading of tagging, stripping and filtering is not
1580 * supported by hardware, but driver will accommodate the
1581 * extra 4-byte VLAN tag for processing by upper layers
1583 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1585 /* setup NAPI interface */
1586 netif_napi_add(ndev, &priv->napi, tse_poll, NAPI_POLL_WEIGHT);
1588 spin_lock_init(&priv->mac_cfg_lock);
1589 spin_lock_init(&priv->tx_lock);
1590 spin_lock_init(&priv->rxdma_irq_lock);
1592 netif_carrier_off(ndev);
1593 ret = register_netdev(ndev);
1595 dev_err(&pdev->dev, "failed to register TSE net device\n");
1596 goto err_register_netdev;
1599 platform_set_drvdata(pdev, ndev);
1601 priv->revision = ioread32(&priv->mac_dev->megacore_revision);
1603 if (netif_msg_probe(priv))
1604 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1605 (priv->revision >> 8) & 0xff,
1606 priv->revision & 0xff,
1607 (unsigned long) control_port->start, priv->rx_irq,
1610 ret = init_phy(ndev);
1612 netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret);
1618 unregister_netdev(ndev);
1619 err_register_netdev:
1620 netif_napi_del(&priv->napi);
1621 altera_tse_mdio_destroy(ndev);
1627 /* Remove Altera TSE MAC device
1629 static int altera_tse_remove(struct platform_device *pdev)
1631 struct net_device *ndev = platform_get_drvdata(pdev);
1632 struct altera_tse_private *priv = netdev_priv(ndev);
1635 phy_disconnect(ndev->phydev);
1637 if (of_phy_is_fixed_link(priv->device->of_node))
1638 of_phy_deregister_fixed_link(priv->device->of_node);
1641 platform_set_drvdata(pdev, NULL);
1642 altera_tse_mdio_destroy(ndev);
1643 unregister_netdev(ndev);
1649 static const struct altera_dmaops altera_dtype_sgdma = {
1650 .altera_dtype = ALTERA_DTYPE_SGDMA,
1652 .reset_dma = sgdma_reset,
1653 .enable_txirq = sgdma_enable_txirq,
1654 .enable_rxirq = sgdma_enable_rxirq,
1655 .disable_txirq = sgdma_disable_txirq,
1656 .disable_rxirq = sgdma_disable_rxirq,
1657 .clear_txirq = sgdma_clear_txirq,
1658 .clear_rxirq = sgdma_clear_rxirq,
1659 .tx_buffer = sgdma_tx_buffer,
1660 .tx_completions = sgdma_tx_completions,
1661 .add_rx_desc = sgdma_add_rx_desc,
1662 .get_rx_status = sgdma_rx_status,
1663 .init_dma = sgdma_initialize,
1664 .uninit_dma = sgdma_uninitialize,
1665 .start_rxdma = sgdma_start_rxdma,
1668 static const struct altera_dmaops altera_dtype_msgdma = {
1669 .altera_dtype = ALTERA_DTYPE_MSGDMA,
1671 .reset_dma = msgdma_reset,
1672 .enable_txirq = msgdma_enable_txirq,
1673 .enable_rxirq = msgdma_enable_rxirq,
1674 .disable_txirq = msgdma_disable_txirq,
1675 .disable_rxirq = msgdma_disable_rxirq,
1676 .clear_txirq = msgdma_clear_txirq,
1677 .clear_rxirq = msgdma_clear_rxirq,
1678 .tx_buffer = msgdma_tx_buffer,
1679 .tx_completions = msgdma_tx_completions,
1680 .add_rx_desc = msgdma_add_rx_desc,
1681 .get_rx_status = msgdma_rx_status,
1682 .init_dma = msgdma_initialize,
1683 .uninit_dma = msgdma_uninitialize,
1684 .start_rxdma = msgdma_start_rxdma,
1687 static const struct of_device_id altera_tse_ids[] = {
1688 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
1689 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
1690 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
1693 MODULE_DEVICE_TABLE(of, altera_tse_ids);
1695 static struct platform_driver altera_tse_driver = {
1696 .probe = altera_tse_probe,
1697 .remove = altera_tse_remove,
1701 .name = ALTERA_TSE_RESOURCE_NAME,
1702 .of_match_table = altera_tse_ids,
1706 module_platform_driver(altera_tse_driver);
1708 MODULE_AUTHOR("Altera Corporation");
1709 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1710 MODULE_LICENSE("GPL v2");