1 /* Altera Triple-Speed Ethernet MAC driver
2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
15 * Original driver contributed by SLS.
16 * Major updates contributed by GlobalLogic
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2, as published by the Free Software Foundation.
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
31 #include <linux/atomic.h>
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/if_vlan.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/of_device.h>
42 #include <linux/of_mdio.h>
43 #include <linux/of_net.h>
44 #include <linux/of_platform.h>
45 #include <linux/phy.h>
46 #include <linux/platform_device.h>
47 #include <linux/skbuff.h>
48 #include <asm/cacheflush.h>
50 #include "altera_utils.h"
51 #include "altera_tse.h"
52 #include "altera_sgdma.h"
53 #include "altera_msgdma.h"
55 static atomic_t instance_count = ATOMIC_INIT(~0);
56 /* Module parameters */
57 static int debug = -1;
58 module_param(debug, int, S_IRUGO | S_IWUSR);
59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
61 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
62 NETIF_MSG_LINK | NETIF_MSG_IFUP |
65 #define RX_DESCRIPTORS 64
66 static int dma_rx_num = RX_DESCRIPTORS;
67 module_param(dma_rx_num, int, S_IRUGO | S_IWUSR);
68 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
70 #define TX_DESCRIPTORS 64
71 static int dma_tx_num = TX_DESCRIPTORS;
72 module_param(dma_tx_num, int, S_IRUGO | S_IWUSR);
73 MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list");
78 /* Make sure DMA buffer size is larger than the max frame size
79 * plus some alignment offset and a VLAN header. If the max frame size is
80 * 1518, a VLAN header would be additional 4 bytes and additional
81 * headroom for alignment is 2 bytes, 2048 is just fine.
83 #define ALTERA_RXDMABUFFER_SIZE 2048
85 /* Allow network stack to resume queueing packets after we've
86 * finished transmitting at least 1/4 of the packets in the queue.
88 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
90 #define TXQUEUESTOP_THRESHHOLD 2
92 static const struct of_device_id altera_tse_ids[];
94 static inline u32 tse_tx_avail(struct altera_tse_private *priv)
96 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1;
99 /* MDIO specific functions
101 static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
103 struct net_device *ndev = bus->priv;
104 struct altera_tse_private *priv = netdev_priv(ndev);
106 /* set MDIO address */
107 csrwr32((mii_id & 0x1f), priv->mac_dev,
108 tse_csroffs(mdio_phy1_addr));
111 return csrrd32(priv->mac_dev,
112 tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff;
115 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
118 struct net_device *ndev = bus->priv;
119 struct altera_tse_private *priv = netdev_priv(ndev);
121 /* set MDIO address */
122 csrwr32((mii_id & 0x1f), priv->mac_dev,
123 tse_csroffs(mdio_phy1_addr));
126 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
130 static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
132 struct altera_tse_private *priv = netdev_priv(dev);
135 struct device_node *mdio_node = NULL;
136 struct mii_bus *mdio = NULL;
137 struct device_node *child_node = NULL;
139 for_each_child_of_node(priv->device->of_node, child_node) {
140 if (of_device_is_compatible(child_node, "altr,tse-mdio")) {
141 mdio_node = child_node;
147 netdev_dbg(dev, "FOUND MDIO subnode\n");
149 netdev_dbg(dev, "NO MDIO subnode\n");
153 mdio = mdiobus_alloc();
155 netdev_err(dev, "Error allocating MDIO bus\n");
159 mdio->name = ALTERA_TSE_RESOURCE_NAME;
160 mdio->read = &altera_tse_mdio_read;
161 mdio->write = &altera_tse_mdio_write;
162 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id);
164 mdio->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
165 if (mdio->irq == NULL) {
169 for (i = 0; i < PHY_MAX_ADDR; i++)
170 mdio->irq[i] = PHY_POLL;
173 mdio->parent = priv->device;
175 ret = of_mdiobus_register(mdio, mdio_node);
177 netdev_err(dev, "Cannot register MDIO bus %s\n",
179 goto out_free_mdio_irq;
182 if (netif_msg_drv(priv))
183 netdev_info(dev, "MDIO bus %s: created\n", mdio->id);
195 static void altera_tse_mdio_destroy(struct net_device *dev)
197 struct altera_tse_private *priv = netdev_priv(dev);
199 if (priv->mdio == NULL)
202 if (netif_msg_drv(priv))
203 netdev_info(dev, "MDIO bus %s: removed\n",
206 mdiobus_unregister(priv->mdio);
207 kfree(priv->mdio->irq);
208 mdiobus_free(priv->mdio);
212 static int tse_init_rx_buffer(struct altera_tse_private *priv,
213 struct tse_buffer *rxbuffer, int len)
215 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len);
219 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data,
223 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) {
224 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
225 dev_kfree_skb_any(rxbuffer->skb);
228 rxbuffer->dma_addr &= (dma_addr_t)~3;
233 static void tse_free_rx_buffer(struct altera_tse_private *priv,
234 struct tse_buffer *rxbuffer)
236 struct sk_buff *skb = rxbuffer->skb;
237 dma_addr_t dma_addr = rxbuffer->dma_addr;
241 dma_unmap_single(priv->device, dma_addr,
244 dev_kfree_skb_any(skb);
245 rxbuffer->skb = NULL;
246 rxbuffer->dma_addr = 0;
250 /* Unmap and free Tx buffer resources
252 static void tse_free_tx_buffer(struct altera_tse_private *priv,
253 struct tse_buffer *buffer)
255 if (buffer->dma_addr) {
256 if (buffer->mapped_as_page)
257 dma_unmap_page(priv->device, buffer->dma_addr,
258 buffer->len, DMA_TO_DEVICE);
260 dma_unmap_single(priv->device, buffer->dma_addr,
261 buffer->len, DMA_TO_DEVICE);
262 buffer->dma_addr = 0;
265 dev_kfree_skb_any(buffer->skb);
270 static int alloc_init_skbufs(struct altera_tse_private *priv)
272 unsigned int rx_descs = priv->rx_ring_size;
273 unsigned int tx_descs = priv->tx_ring_size;
277 /* Create Rx ring buffer */
278 priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer),
283 /* Create Tx ring buffer */
284 priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer),
293 for (i = 0; i < rx_descs; i++) {
294 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i],
295 priv->rx_dma_buf_sz);
297 goto err_init_rx_buffers;
306 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
307 kfree(priv->tx_ring);
309 kfree(priv->rx_ring);
314 static void free_skbufs(struct net_device *dev)
316 struct altera_tse_private *priv = netdev_priv(dev);
317 unsigned int rx_descs = priv->rx_ring_size;
318 unsigned int tx_descs = priv->tx_ring_size;
321 /* Release the DMA TX/RX socket buffers */
322 for (i = 0; i < rx_descs; i++)
323 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
324 for (i = 0; i < tx_descs; i++)
325 tse_free_tx_buffer(priv, &priv->tx_ring[i]);
328 kfree(priv->tx_ring);
331 /* Reallocate the skb for the reception process
333 static inline void tse_rx_refill(struct altera_tse_private *priv)
335 unsigned int rxsize = priv->rx_ring_size;
339 for (; priv->rx_cons - priv->rx_prod > 0;
341 entry = priv->rx_prod % rxsize;
342 if (likely(priv->rx_ring[entry].skb == NULL)) {
343 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry],
344 priv->rx_dma_buf_sz);
345 if (unlikely(ret != 0))
347 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]);
352 /* Pull out the VLAN tag and fix up the packet
354 static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb)
356 struct ethhdr *eth_hdr;
358 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
359 !__vlan_get_tag(skb, &vid)) {
360 eth_hdr = (struct ethhdr *)skb->data;
361 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
362 skb_pull(skb, VLAN_HLEN);
363 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
367 /* Receive a packet: retrieve and pass over to upper levels
369 static int tse_rx(struct altera_tse_private *priv, int limit)
371 unsigned int count = 0;
372 unsigned int next_entry;
374 unsigned int entry = priv->rx_cons % priv->rx_ring_size;
379 /* Check for count < limit first as get_rx_status is changing
380 * the response-fifo so we must process the next packet
381 * after calling get_rx_status if a response is pending.
382 * (reading the last byte of the response pops the value from the fifo.)
384 while ((count < limit) &&
385 ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0)) {
386 pktstatus = rxstatus >> 16;
387 pktlength = rxstatus & 0xffff;
389 if ((pktstatus & 0xFF) || (pktlength == 0))
390 netdev_err(priv->dev,
391 "RCV pktstatus %08X pktlength %08X\n",
392 pktstatus, pktlength);
394 /* DMA trasfer from TSE starts with 2 aditional bytes for
395 * IP payload alignment. Status returned by get_rx_status()
396 * contains DMA transfer length. Packet is 2 bytes shorter.
401 next_entry = (++priv->rx_cons) % priv->rx_ring_size;
403 skb = priv->rx_ring[entry].skb;
404 if (unlikely(!skb)) {
405 netdev_err(priv->dev,
406 "%s: Inconsistent Rx descriptor chain\n",
408 priv->dev->stats.rx_dropped++;
411 priv->rx_ring[entry].skb = NULL;
413 skb_put(skb, pktlength);
415 /* make cache consistent with receive packet buffer */
416 dma_sync_single_for_cpu(priv->device,
417 priv->rx_ring[entry].dma_addr,
418 priv->rx_ring[entry].len,
421 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr,
422 priv->rx_ring[entry].len, DMA_FROM_DEVICE);
424 if (netif_msg_pktdata(priv)) {
425 netdev_info(priv->dev, "frame received %d bytes\n",
427 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET,
428 16, 1, skb->data, pktlength, true);
431 tse_rx_vlan(priv->dev, skb);
433 skb->protocol = eth_type_trans(skb, priv->dev);
434 skb_checksum_none_assert(skb);
436 napi_gro_receive(&priv->napi, skb);
438 priv->dev->stats.rx_packets++;
439 priv->dev->stats.rx_bytes += pktlength;
449 /* Reclaim resources after transmission completes
451 static int tse_tx_complete(struct altera_tse_private *priv)
453 unsigned int txsize = priv->tx_ring_size;
456 struct tse_buffer *tx_buff;
459 spin_lock(&priv->tx_lock);
461 ready = priv->dmaops->tx_completions(priv);
463 /* Free sent buffers */
464 while (ready && (priv->tx_cons != priv->tx_prod)) {
465 entry = priv->tx_cons % txsize;
466 tx_buff = &priv->tx_ring[entry];
468 if (netif_msg_tx_done(priv))
469 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n",
470 __func__, priv->tx_prod, priv->tx_cons);
472 if (likely(tx_buff->skb))
473 priv->dev->stats.tx_packets++;
475 tse_free_tx_buffer(priv, tx_buff);
482 if (unlikely(netif_queue_stopped(priv->dev) &&
483 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) {
484 netif_tx_lock(priv->dev);
485 if (netif_queue_stopped(priv->dev) &&
486 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) {
487 if (netif_msg_tx_done(priv))
488 netdev_dbg(priv->dev, "%s: restart transmit\n",
490 netif_wake_queue(priv->dev);
492 netif_tx_unlock(priv->dev);
495 spin_unlock(&priv->tx_lock);
499 /* NAPI polling function
501 static int tse_poll(struct napi_struct *napi, int budget)
503 struct altera_tse_private *priv =
504 container_of(napi, struct altera_tse_private, napi);
506 unsigned long int flags;
508 tse_tx_complete(priv);
510 rxcomplete = tse_rx(priv, budget);
512 if (rxcomplete < budget) {
516 netdev_dbg(priv->dev,
517 "NAPI Complete, did %d packets with budget %d\n",
520 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
521 priv->dmaops->enable_rxirq(priv);
522 priv->dmaops->enable_txirq(priv);
523 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
528 /* DMA TX & RX FIFO interrupt routing
530 static irqreturn_t altera_isr(int irq, void *dev_id)
532 struct net_device *dev = dev_id;
533 struct altera_tse_private *priv;
535 if (unlikely(!dev)) {
536 pr_err("%s: invalid dev pointer\n", __func__);
539 priv = netdev_priv(dev);
541 spin_lock(&priv->rxdma_irq_lock);
543 priv->dmaops->clear_rxirq(priv);
544 priv->dmaops->clear_txirq(priv);
545 spin_unlock(&priv->rxdma_irq_lock);
547 if (likely(napi_schedule_prep(&priv->napi))) {
548 spin_lock(&priv->rxdma_irq_lock);
549 priv->dmaops->disable_rxirq(priv);
550 priv->dmaops->disable_txirq(priv);
551 spin_unlock(&priv->rxdma_irq_lock);
552 __napi_schedule(&priv->napi);
559 /* Transmit a packet (called by the kernel). Dispatches
560 * either the SGDMA method for transmitting or the
561 * MSGDMA method, assumes no scatter/gather support,
562 * implying an assumption that there's only one
563 * physically contiguous fragment starting at
564 * skb->data, for length of skb_headlen(skb).
566 static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
568 struct altera_tse_private *priv = netdev_priv(dev);
569 unsigned int txsize = priv->tx_ring_size;
571 struct tse_buffer *buffer = NULL;
572 int nfrags = skb_shinfo(skb)->nr_frags;
573 unsigned int nopaged_len = skb_headlen(skb);
574 enum netdev_tx ret = NETDEV_TX_OK;
577 spin_lock_bh(&priv->tx_lock);
579 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) {
580 if (!netif_queue_stopped(dev)) {
581 netif_stop_queue(dev);
582 /* This is a hard error, log it. */
583 netdev_err(priv->dev,
584 "%s: Tx list full when queue awake\n",
587 ret = NETDEV_TX_BUSY;
591 /* Map the first skb fragment */
592 entry = priv->tx_prod % txsize;
593 buffer = &priv->tx_ring[entry];
595 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len,
597 if (dma_mapping_error(priv->device, dma_addr)) {
598 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
604 buffer->dma_addr = dma_addr;
605 buffer->len = nopaged_len;
607 /* Push data out of the cache hierarchy into main memory */
608 dma_sync_single_for_device(priv->device, buffer->dma_addr,
609 buffer->len, DMA_TO_DEVICE);
611 priv->dmaops->tx_buffer(priv, buffer);
613 skb_tx_timestamp(skb);
616 dev->stats.tx_bytes += skb->len;
618 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) {
619 if (netif_msg_hw(priv))
620 netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
622 netif_stop_queue(dev);
626 spin_unlock_bh(&priv->tx_lock);
631 /* Called every time the controller might need to be made
632 * aware of new link state. The PHY code conveys this
633 * information through variables in the phydev structure, and this
634 * function converts those variables into the appropriate
635 * register values, and can bring down the device if needed.
637 static void altera_tse_adjust_link(struct net_device *dev)
639 struct altera_tse_private *priv = netdev_priv(dev);
640 struct phy_device *phydev = priv->phydev;
643 /* only change config if there is a link */
644 spin_lock(&priv->mac_cfg_lock);
646 /* Read old config */
647 u32 cfg_reg = ioread32(&priv->mac_dev->command_config);
650 if (phydev->duplex != priv->oldduplex) {
652 if (!(phydev->duplex))
653 cfg_reg |= MAC_CMDCFG_HD_ENA;
655 cfg_reg &= ~MAC_CMDCFG_HD_ENA;
657 netdev_dbg(priv->dev, "%s: Link duplex = 0x%x\n",
658 dev->name, phydev->duplex);
660 priv->oldduplex = phydev->duplex;
664 if (phydev->speed != priv->oldspeed) {
666 switch (phydev->speed) {
668 cfg_reg |= MAC_CMDCFG_ETH_SPEED;
669 cfg_reg &= ~MAC_CMDCFG_ENA_10;
672 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
673 cfg_reg &= ~MAC_CMDCFG_ENA_10;
676 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
677 cfg_reg |= MAC_CMDCFG_ENA_10;
680 if (netif_msg_link(priv))
681 netdev_warn(dev, "Speed (%d) is not 10/100/1000!\n",
685 priv->oldspeed = phydev->speed;
687 iowrite32(cfg_reg, &priv->mac_dev->command_config);
689 if (!priv->oldlink) {
693 } else if (priv->oldlink) {
697 priv->oldduplex = -1;
700 if (new_state && netif_msg_link(priv))
701 phy_print_status(phydev);
703 spin_unlock(&priv->mac_cfg_lock);
705 static struct phy_device *connect_local_phy(struct net_device *dev)
707 struct altera_tse_private *priv = netdev_priv(dev);
708 struct phy_device *phydev = NULL;
709 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
711 if (priv->phy_addr != POLL_PHY) {
712 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
713 priv->mdio->id, priv->phy_addr);
715 netdev_dbg(dev, "trying to attach to %s\n", phy_id_fmt);
717 phydev = phy_connect(dev, phy_id_fmt, &altera_tse_adjust_link,
719 if (IS_ERR(phydev)) {
720 netdev_err(dev, "Could not attach to PHY\n");
726 phydev = phy_find_first(priv->mdio);
727 if (phydev == NULL) {
728 netdev_err(dev, "No PHY found\n");
732 ret = phy_connect_direct(dev, phydev, &altera_tse_adjust_link,
735 netdev_err(dev, "Could not attach to PHY\n");
742 static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev)
744 struct altera_tse_private *priv = netdev_priv(dev);
745 struct device_node *np = priv->device->of_node;
748 priv->phy_iface = of_get_phy_mode(np);
750 /* Avoid get phy addr and create mdio if no phy is present */
751 if (!priv->phy_iface)
754 /* try to get PHY address from device tree, use PHY autodetection if
755 * no valid address is given
758 if (of_property_read_u32(priv->device->of_node, "phy-addr",
760 priv->phy_addr = POLL_PHY;
763 if (!((priv->phy_addr == POLL_PHY) ||
764 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) {
765 netdev_err(dev, "invalid phy-addr specified %d\n",
770 /* Create/attach to MDIO bus */
771 ret = altera_tse_mdio_create(dev,
772 atomic_add_return(1, &instance_count));
780 /* Initialize driver's PHY state, and attach to the PHY
782 static int init_phy(struct net_device *dev)
784 struct altera_tse_private *priv = netdev_priv(dev);
785 struct phy_device *phydev;
786 struct device_node *phynode;
787 bool fixed_link = false;
790 /* Avoid init phy in case of no phy present */
791 if (!priv->phy_iface)
796 priv->oldduplex = -1;
798 phynode = of_parse_phandle(priv->device->of_node, "phy-handle", 0);
801 /* check if a fixed-link is defined in device-tree */
802 if (of_phy_is_fixed_link(priv->device->of_node)) {
803 rc = of_phy_register_fixed_link(priv->device->of_node);
805 netdev_err(dev, "cannot register fixed PHY\n");
809 /* In the case of a fixed PHY, the DT node associated
810 * to the PHY is the Ethernet MAC DT node.
812 phynode = of_node_get(priv->device->of_node);
815 netdev_dbg(dev, "fixed-link detected\n");
816 phydev = of_phy_connect(dev, phynode,
817 &altera_tse_adjust_link,
820 netdev_dbg(dev, "no phy-handle found\n");
822 netdev_err(dev, "No phy-handle nor local mdio specified\n");
825 phydev = connect_local_phy(dev);
828 netdev_dbg(dev, "phy-handle found\n");
829 phydev = of_phy_connect(dev, phynode,
830 &altera_tse_adjust_link, 0, priv->phy_iface);
834 netdev_err(dev, "Could not find the PHY\n");
838 /* Stop Advertising 1000BASE Capability if interface is not GMII
839 * Note: Checkpatch throws CHECKs for the camel case defines below,
842 if ((priv->phy_iface == PHY_INTERFACE_MODE_MII) ||
843 (priv->phy_iface == PHY_INTERFACE_MODE_RMII))
844 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
845 SUPPORTED_1000baseT_Full);
847 /* Broken HW is sometimes missing the pull-up resistor on the
848 * MDIO line, which results in reads to non-existent devices returning
849 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
850 * device as well. If a fixed-link is used the phy_id is always 0.
851 * Note: phydev->phy_id is the result of reading the UID PHY registers.
853 if ((phydev->phy_id == 0) && !fixed_link) {
854 netdev_err(dev, "Bad PHY UID 0x%08x\n", phydev->phy_id);
855 phy_disconnect(phydev);
859 netdev_dbg(dev, "attached to PHY %d UID 0x%08x Link = %d\n",
860 phydev->addr, phydev->phy_id, phydev->link);
862 priv->phydev = phydev;
866 static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr)
871 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
872 lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
874 /* Set primary MAC address */
875 csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0));
876 csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1));
879 /* MAC software reset.
880 * When reset is triggered, the MAC function completes the current
881 * transmission or reception, and subsequently disables the transmit and
882 * receive logic, flushes the receive FIFO buffer, and resets the statistics
885 static int reset_mac(struct altera_tse_private *priv)
890 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
891 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
892 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
893 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
896 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
897 if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config),
898 MAC_CMDCFG_SW_RESET))
903 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
904 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
905 dat &= ~MAC_CMDCFG_SW_RESET;
906 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
912 /* Initialize MAC core registers
914 static int init_mac(struct altera_tse_private *priv)
916 unsigned int cmd = 0;
920 csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
921 priv->mac_dev, tse_csroffs(rx_section_empty));
923 csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev,
924 tse_csroffs(rx_section_full));
926 csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev,
927 tse_csroffs(rx_almost_empty));
929 csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev,
930 tse_csroffs(rx_almost_full));
933 csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
934 priv->mac_dev, tse_csroffs(tx_section_empty));
936 csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev,
937 tse_csroffs(tx_section_full));
939 csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev,
940 tse_csroffs(tx_almost_empty));
942 csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev,
943 tse_csroffs(tx_almost_full));
945 /* MAC Address Configuration */
946 tse_update_mac_addr(priv, priv->dev->dev_addr);
948 /* MAC Function Configuration */
949 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
950 csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length));
952 csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev,
953 tse_csroffs(tx_ipg_length));
955 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
958 tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat),
959 ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
961 tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat),
962 ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
963 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
965 /* Set the MAC options */
966 cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config));
967 cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */
968 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */
969 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames
972 cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
973 cmd &= ~MAC_CMDCFG_TX_ENA;
974 cmd &= ~MAC_CMDCFG_RX_ENA;
976 /* Default speed and duplex setting, full/100 */
977 cmd &= ~MAC_CMDCFG_HD_ENA;
978 cmd &= ~MAC_CMDCFG_ETH_SPEED;
979 cmd &= ~MAC_CMDCFG_ENA_10;
981 csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config));
983 csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev,
984 tse_csroffs(pause_quanta));
986 if (netif_msg_hw(priv))
987 dev_dbg(priv->device,
988 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd);
993 /* Start/stop MAC transmission logic
995 static void tse_set_mac(struct altera_tse_private *priv, bool enable)
997 u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config));
1000 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
1002 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
1004 csrwr32(value, priv->mac_dev, tse_csroffs(command_config));
1009 static int tse_change_mtu(struct net_device *dev, int new_mtu)
1011 struct altera_tse_private *priv = netdev_priv(dev);
1012 unsigned int max_mtu = priv->max_mtu;
1013 unsigned int min_mtu = ETH_ZLEN + ETH_FCS_LEN;
1015 if (netif_running(dev)) {
1016 netdev_err(dev, "must be stopped to change its MTU\n");
1020 if ((new_mtu < min_mtu) || (new_mtu > max_mtu)) {
1021 netdev_err(dev, "invalid MTU, max MTU is: %u\n", max_mtu);
1026 netdev_update_features(dev);
1031 static void altera_tse_set_mcfilter(struct net_device *dev)
1033 struct altera_tse_private *priv = netdev_priv(dev);
1035 struct netdev_hw_addr *ha;
1037 /* clear the hash filter */
1038 for (i = 0; i < 64; i++)
1039 csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1041 netdev_for_each_mc_addr(ha, dev) {
1042 unsigned int hash = 0;
1045 for (mac_octet = 5; mac_octet >= 0; mac_octet--) {
1046 unsigned char xor_bit = 0;
1047 unsigned char octet = ha->addr[mac_octet];
1048 unsigned int bitshift;
1050 for (bitshift = 0; bitshift < 8; bitshift++)
1051 xor_bit ^= ((octet >> bitshift) & 0x01);
1053 hash = (hash << 1) | xor_bit;
1055 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4);
1060 static void altera_tse_set_mcfilterall(struct net_device *dev)
1062 struct altera_tse_private *priv = netdev_priv(dev);
1065 /* set the hash filter */
1066 for (i = 0; i < 64; i++)
1067 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1070 /* Set or clear the multicast filter for this adaptor
1072 static void tse_set_rx_mode_hashfilter(struct net_device *dev)
1074 struct altera_tse_private *priv = netdev_priv(dev);
1076 spin_lock(&priv->mac_cfg_lock);
1078 if (dev->flags & IFF_PROMISC)
1079 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1080 MAC_CMDCFG_PROMIS_EN);
1082 if (dev->flags & IFF_ALLMULTI)
1083 altera_tse_set_mcfilterall(dev);
1085 altera_tse_set_mcfilter(dev);
1087 spin_unlock(&priv->mac_cfg_lock);
1090 /* Set or clear the multicast filter for this adaptor
1092 static void tse_set_rx_mode(struct net_device *dev)
1094 struct altera_tse_private *priv = netdev_priv(dev);
1096 spin_lock(&priv->mac_cfg_lock);
1098 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
1099 !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
1100 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1101 MAC_CMDCFG_PROMIS_EN);
1103 tse_clear_bit(priv->mac_dev, tse_csroffs(command_config),
1104 MAC_CMDCFG_PROMIS_EN);
1106 spin_unlock(&priv->mac_cfg_lock);
1109 /* Open and initialize the interface
1111 static int tse_open(struct net_device *dev)
1113 struct altera_tse_private *priv = netdev_priv(dev);
1116 unsigned long int flags;
1118 /* Reset and configure TSE MAC and probe associated PHY */
1119 ret = priv->dmaops->init_dma(priv);
1121 netdev_err(dev, "Cannot initialize DMA\n");
1125 if (netif_msg_ifup(priv))
1126 netdev_warn(dev, "device MAC address %pM\n",
1129 if ((priv->revision < 0xd00) || (priv->revision > 0xe00))
1130 netdev_warn(dev, "TSE revision %x\n", priv->revision);
1132 spin_lock(&priv->mac_cfg_lock);
1133 ret = reset_mac(priv);
1134 /* Note that reset_mac will fail if the clocks are gated by the PHY
1135 * due to the PHY being put into isolation or power down mode.
1136 * This is not an error if reset fails due to no clock.
1139 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1141 ret = init_mac(priv);
1142 spin_unlock(&priv->mac_cfg_lock);
1144 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret);
1145 goto alloc_skbuf_error;
1148 priv->dmaops->reset_dma(priv);
1150 /* Create and initialize the TX/RX descriptors chains. */
1151 priv->rx_ring_size = dma_rx_num;
1152 priv->tx_ring_size = dma_tx_num;
1153 ret = alloc_init_skbufs(priv);
1155 netdev_err(dev, "DMA descriptors initialization failed\n");
1156 goto alloc_skbuf_error;
1160 /* Register RX interrupt */
1161 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED,
1164 netdev_err(dev, "Unable to register RX interrupt %d\n",
1169 /* Register TX interrupt */
1170 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED,
1173 netdev_err(dev, "Unable to register TX interrupt %d\n",
1175 goto tx_request_irq_error;
1178 /* Enable DMA interrupts */
1179 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1180 priv->dmaops->enable_rxirq(priv);
1181 priv->dmaops->enable_txirq(priv);
1183 /* Setup RX descriptor chain */
1184 for (i = 0; i < priv->rx_ring_size; i++)
1185 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]);
1187 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1190 phy_start(priv->phydev);
1192 napi_enable(&priv->napi);
1193 netif_start_queue(dev);
1195 priv->dmaops->start_rxdma(priv);
1197 /* Start MAC Rx/Tx */
1198 spin_lock(&priv->mac_cfg_lock);
1199 tse_set_mac(priv, true);
1200 spin_unlock(&priv->mac_cfg_lock);
1204 tx_request_irq_error:
1205 free_irq(priv->rx_irq, dev);
1213 /* Stop TSE MAC interface and put the device in an inactive state
1215 static int tse_shutdown(struct net_device *dev)
1217 struct altera_tse_private *priv = netdev_priv(dev);
1219 unsigned long int flags;
1223 phy_stop(priv->phydev);
1225 netif_stop_queue(dev);
1226 napi_disable(&priv->napi);
1228 /* Disable DMA interrupts */
1229 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1230 priv->dmaops->disable_rxirq(priv);
1231 priv->dmaops->disable_txirq(priv);
1232 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1234 /* Free the IRQ lines */
1235 free_irq(priv->rx_irq, dev);
1236 free_irq(priv->tx_irq, dev);
1238 /* disable and reset the MAC, empties fifo */
1239 spin_lock(&priv->mac_cfg_lock);
1240 spin_lock(&priv->tx_lock);
1242 ret = reset_mac(priv);
1243 /* Note that reset_mac will fail if the clocks are gated by the PHY
1244 * due to the PHY being put into isolation or power down mode.
1245 * This is not an error if reset fails due to no clock.
1248 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1249 priv->dmaops->reset_dma(priv);
1252 spin_unlock(&priv->tx_lock);
1253 spin_unlock(&priv->mac_cfg_lock);
1255 priv->dmaops->uninit_dma(priv);
1260 static struct net_device_ops altera_tse_netdev_ops = {
1261 .ndo_open = tse_open,
1262 .ndo_stop = tse_shutdown,
1263 .ndo_start_xmit = tse_start_xmit,
1264 .ndo_set_mac_address = eth_mac_addr,
1265 .ndo_set_rx_mode = tse_set_rx_mode,
1266 .ndo_change_mtu = tse_change_mtu,
1267 .ndo_validate_addr = eth_validate_addr,
1270 static int request_and_map(struct platform_device *pdev, const char *name,
1271 struct resource **res, void __iomem **ptr)
1273 struct resource *region;
1274 struct device *device = &pdev->dev;
1276 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
1278 dev_err(device, "resource %s not defined\n", name);
1282 region = devm_request_mem_region(device, (*res)->start,
1283 resource_size(*res), dev_name(device));
1284 if (region == NULL) {
1285 dev_err(device, "unable to request %s\n", name);
1289 *ptr = devm_ioremap_nocache(device, region->start,
1290 resource_size(region));
1292 dev_err(device, "ioremap_nocache of %s failed!", name);
1299 /* Probe Altera TSE MAC device
1301 static int altera_tse_probe(struct platform_device *pdev)
1303 struct net_device *ndev;
1305 struct resource *control_port;
1306 struct resource *dma_res;
1307 struct altera_tse_private *priv;
1308 const unsigned char *macaddr;
1309 void __iomem *descmap;
1310 const struct of_device_id *of_id = NULL;
1312 ndev = alloc_etherdev(sizeof(struct altera_tse_private));
1314 dev_err(&pdev->dev, "Could not allocate network device\n");
1318 SET_NETDEV_DEV(ndev, &pdev->dev);
1320 priv = netdev_priv(ndev);
1321 priv->device = &pdev->dev;
1323 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1325 of_id = of_match_device(altera_tse_ids, &pdev->dev);
1328 priv->dmaops = (struct altera_dmaops *)of_id->data;
1332 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) {
1333 /* Get the mapped address to the SGDMA descriptor memory */
1334 ret = request_and_map(pdev, "s1", &dma_res, &descmap);
1336 goto err_free_netdev;
1338 /* Start of that memory is for transmit descriptors */
1339 priv->tx_dma_desc = descmap;
1341 /* First half is for tx descriptors, other half for tx */
1342 priv->txdescmem = resource_size(dma_res)/2;
1344 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start;
1346 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap +
1348 priv->rxdescmem = resource_size(dma_res)/2;
1349 priv->rxdescmem_busaddr = dma_res->start;
1350 priv->rxdescmem_busaddr += priv->txdescmem;
1352 if (upper_32_bits(priv->rxdescmem_busaddr)) {
1353 dev_dbg(priv->device,
1354 "SGDMA bus addresses greater than 32-bits\n");
1355 goto err_free_netdev;
1357 if (upper_32_bits(priv->txdescmem_busaddr)) {
1358 dev_dbg(priv->device,
1359 "SGDMA bus addresses greater than 32-bits\n");
1360 goto err_free_netdev;
1362 } else if (priv->dmaops &&
1363 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) {
1364 ret = request_and_map(pdev, "rx_resp", &dma_res,
1365 &priv->rx_dma_resp);
1367 goto err_free_netdev;
1369 ret = request_and_map(pdev, "tx_desc", &dma_res,
1370 &priv->tx_dma_desc);
1372 goto err_free_netdev;
1374 priv->txdescmem = resource_size(dma_res);
1375 priv->txdescmem_busaddr = dma_res->start;
1377 ret = request_and_map(pdev, "rx_desc", &dma_res,
1378 &priv->rx_dma_desc);
1380 goto err_free_netdev;
1382 priv->rxdescmem = resource_size(dma_res);
1383 priv->rxdescmem_busaddr = dma_res->start;
1386 goto err_free_netdev;
1389 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask)))
1390 dma_set_coherent_mask(priv->device,
1391 DMA_BIT_MASK(priv->dmaops->dmamask));
1392 else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32)))
1393 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32));
1395 goto err_free_netdev;
1397 /* MAC address space */
1398 ret = request_and_map(pdev, "control_port", &control_port,
1399 (void __iomem **)&priv->mac_dev);
1401 goto err_free_netdev;
1403 /* xSGDMA Rx Dispatcher address space */
1404 ret = request_and_map(pdev, "rx_csr", &dma_res,
1407 goto err_free_netdev;
1410 /* xSGDMA Tx Dispatcher address space */
1411 ret = request_and_map(pdev, "tx_csr", &dma_res,
1414 goto err_free_netdev;
1418 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq");
1419 if (priv->rx_irq == -ENXIO) {
1420 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n");
1422 goto err_free_netdev;
1426 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq");
1427 if (priv->tx_irq == -ENXIO) {
1428 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n");
1430 goto err_free_netdev;
1433 /* get FIFO depths from device tree */
1434 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1435 &priv->rx_fifo_depth)) {
1436 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n");
1438 goto err_free_netdev;
1441 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1442 &priv->tx_fifo_depth)) {
1443 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n");
1445 goto err_free_netdev;
1448 /* get hash filter settings for this instance */
1450 of_property_read_bool(pdev->dev.of_node,
1451 "altr,has-hash-multicast-filter");
1453 /* Set hash filter to not set for now until the
1454 * multicast filter receive issue is debugged
1456 priv->hash_filter = 0;
1458 /* get supplemental address settings for this instance */
1459 priv->added_unicast =
1460 of_property_read_bool(pdev->dev.of_node,
1461 "altr,has-supplementary-unicast");
1463 /* Max MTU is 1500, ETH_DATA_LEN */
1464 priv->max_mtu = ETH_DATA_LEN;
1466 /* Get the max mtu from the device tree. Note that the
1467 * "max-frame-size" parameter is actually max mtu. Definition
1468 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1470 of_property_read_u32(pdev->dev.of_node, "max-frame-size",
1473 /* The DMA buffer size already accounts for an alignment bias
1474 * to avoid unaligned access exceptions for the NIOS processor,
1476 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;
1478 /* get default MAC address from device tree */
1479 macaddr = of_get_mac_address(pdev->dev.of_node);
1481 ether_addr_copy(ndev->dev_addr, macaddr);
1483 eth_hw_addr_random(ndev);
1485 /* get phy addr and create mdio */
1486 ret = altera_tse_phy_get_addr_mdio_create(ndev);
1489 goto err_free_netdev;
1491 /* initialize netdev */
1492 ndev->mem_start = control_port->start;
1493 ndev->mem_end = control_port->end;
1494 ndev->netdev_ops = &altera_tse_netdev_ops;
1495 altera_tse_set_ethtool_ops(ndev);
1497 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode;
1499 if (priv->hash_filter)
1500 altera_tse_netdev_ops.ndo_set_rx_mode =
1501 tse_set_rx_mode_hashfilter;
1503 /* Scatter/gather IO is not supported,
1504 * so it is turned off
1506 ndev->hw_features &= ~NETIF_F_SG;
1507 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1509 /* VLAN offloading of tagging, stripping and filtering is not
1510 * supported by hardware, but driver will accommodate the
1511 * extra 4-byte VLAN tag for processing by upper layers
1513 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1515 /* setup NAPI interface */
1516 netif_napi_add(ndev, &priv->napi, tse_poll, NAPI_POLL_WEIGHT);
1518 spin_lock_init(&priv->mac_cfg_lock);
1519 spin_lock_init(&priv->tx_lock);
1520 spin_lock_init(&priv->rxdma_irq_lock);
1522 netif_carrier_off(ndev);
1523 ret = register_netdev(ndev);
1525 dev_err(&pdev->dev, "failed to register TSE net device\n");
1526 goto err_register_netdev;
1529 platform_set_drvdata(pdev, ndev);
1531 priv->revision = ioread32(&priv->mac_dev->megacore_revision);
1533 if (netif_msg_probe(priv))
1534 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1535 (priv->revision >> 8) & 0xff,
1536 priv->revision & 0xff,
1537 (unsigned long) control_port->start, priv->rx_irq,
1540 ret = init_phy(ndev);
1542 netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret);
1548 unregister_netdev(ndev);
1549 err_register_netdev:
1550 netif_napi_del(&priv->napi);
1551 altera_tse_mdio_destroy(ndev);
1557 /* Remove Altera TSE MAC device
1559 static int altera_tse_remove(struct platform_device *pdev)
1561 struct net_device *ndev = platform_get_drvdata(pdev);
1562 struct altera_tse_private *priv = netdev_priv(ndev);
1565 phy_disconnect(priv->phydev);
1567 platform_set_drvdata(pdev, NULL);
1568 altera_tse_mdio_destroy(ndev);
1569 unregister_netdev(ndev);
1575 static const struct altera_dmaops altera_dtype_sgdma = {
1576 .altera_dtype = ALTERA_DTYPE_SGDMA,
1578 .reset_dma = sgdma_reset,
1579 .enable_txirq = sgdma_enable_txirq,
1580 .enable_rxirq = sgdma_enable_rxirq,
1581 .disable_txirq = sgdma_disable_txirq,
1582 .disable_rxirq = sgdma_disable_rxirq,
1583 .clear_txirq = sgdma_clear_txirq,
1584 .clear_rxirq = sgdma_clear_rxirq,
1585 .tx_buffer = sgdma_tx_buffer,
1586 .tx_completions = sgdma_tx_completions,
1587 .add_rx_desc = sgdma_add_rx_desc,
1588 .get_rx_status = sgdma_rx_status,
1589 .init_dma = sgdma_initialize,
1590 .uninit_dma = sgdma_uninitialize,
1591 .start_rxdma = sgdma_start_rxdma,
1594 static const struct altera_dmaops altera_dtype_msgdma = {
1595 .altera_dtype = ALTERA_DTYPE_MSGDMA,
1597 .reset_dma = msgdma_reset,
1598 .enable_txirq = msgdma_enable_txirq,
1599 .enable_rxirq = msgdma_enable_rxirq,
1600 .disable_txirq = msgdma_disable_txirq,
1601 .disable_rxirq = msgdma_disable_rxirq,
1602 .clear_txirq = msgdma_clear_txirq,
1603 .clear_rxirq = msgdma_clear_rxirq,
1604 .tx_buffer = msgdma_tx_buffer,
1605 .tx_completions = msgdma_tx_completions,
1606 .add_rx_desc = msgdma_add_rx_desc,
1607 .get_rx_status = msgdma_rx_status,
1608 .init_dma = msgdma_initialize,
1609 .uninit_dma = msgdma_uninitialize,
1610 .start_rxdma = msgdma_start_rxdma,
1613 static const struct of_device_id altera_tse_ids[] = {
1614 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
1615 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
1616 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
1619 MODULE_DEVICE_TABLE(of, altera_tse_ids);
1621 static struct platform_driver altera_tse_driver = {
1622 .probe = altera_tse_probe,
1623 .remove = altera_tse_remove,
1627 .name = ALTERA_TSE_RESOURCE_NAME,
1628 .of_match_table = altera_tse_ids,
1632 module_platform_driver(altera_tse_driver);
1634 MODULE_AUTHOR("Altera Corporation");
1635 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1636 MODULE_LICENSE("GPL v2");