1 /* Altera Triple-Speed Ethernet MAC driver
2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
15 * Original driver contributed by SLS.
16 * Major updates contributed by GlobalLogic
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2, as published by the Free Software Foundation.
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
31 #include <linux/atomic.h>
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/if_vlan.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/of_device.h>
42 #include <linux/of_mdio.h>
43 #include <linux/of_net.h>
44 #include <linux/of_platform.h>
45 #include <linux/phy.h>
46 #include <linux/platform_device.h>
47 #include <linux/skbuff.h>
48 #include <asm/cacheflush.h>
50 #include "altera_utils.h"
51 #include "altera_tse.h"
52 #include "altera_sgdma.h"
53 #include "altera_msgdma.h"
55 static atomic_t instance_count = ATOMIC_INIT(~0);
56 /* Module parameters */
57 static int debug = -1;
58 module_param(debug, int, S_IRUGO | S_IWUSR);
59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
61 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
62 NETIF_MSG_LINK | NETIF_MSG_IFUP |
65 #define RX_DESCRIPTORS 64
66 static int dma_rx_num = RX_DESCRIPTORS;
67 module_param(dma_rx_num, int, S_IRUGO | S_IWUSR);
68 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
70 #define TX_DESCRIPTORS 64
71 static int dma_tx_num = TX_DESCRIPTORS;
72 module_param(dma_tx_num, int, S_IRUGO | S_IWUSR);
73 MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list");
78 /* Make sure DMA buffer size is larger than the max frame size
79 * plus some alignment offset and a VLAN header. If the max frame size is
80 * 1518, a VLAN header would be additional 4 bytes and additional
81 * headroom for alignment is 2 bytes, 2048 is just fine.
83 #define ALTERA_RXDMABUFFER_SIZE 2048
85 /* Allow network stack to resume queueing packets after we've
86 * finished transmitting at least 1/4 of the packets in the queue.
88 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
90 #define TXQUEUESTOP_THRESHHOLD 2
92 static const struct of_device_id altera_tse_ids[];
94 static inline u32 tse_tx_avail(struct altera_tse_private *priv)
96 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1;
99 /* MDIO specific functions
101 static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
103 struct net_device *ndev = bus->priv;
104 struct altera_tse_private *priv = netdev_priv(ndev);
106 /* set MDIO address */
107 csrwr32((mii_id & 0x1f), priv->mac_dev,
108 tse_csroffs(mdio_phy1_addr));
111 return csrrd32(priv->mac_dev,
112 tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff;
115 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
118 struct net_device *ndev = bus->priv;
119 struct altera_tse_private *priv = netdev_priv(ndev);
121 /* set MDIO address */
122 csrwr32((mii_id & 0x1f), priv->mac_dev,
123 tse_csroffs(mdio_phy1_addr));
126 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
130 static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
132 struct altera_tse_private *priv = netdev_priv(dev);
134 struct device_node *mdio_node = NULL;
135 struct mii_bus *mdio = NULL;
136 struct device_node *child_node = NULL;
138 for_each_child_of_node(priv->device->of_node, child_node) {
139 if (of_device_is_compatible(child_node, "altr,tse-mdio")) {
140 mdio_node = child_node;
146 netdev_dbg(dev, "FOUND MDIO subnode\n");
148 netdev_dbg(dev, "NO MDIO subnode\n");
152 mdio = mdiobus_alloc();
154 netdev_err(dev, "Error allocating MDIO bus\n");
158 mdio->name = ALTERA_TSE_RESOURCE_NAME;
159 mdio->read = &altera_tse_mdio_read;
160 mdio->write = &altera_tse_mdio_write;
161 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id);
164 mdio->parent = priv->device;
166 ret = of_mdiobus_register(mdio, mdio_node);
168 netdev_err(dev, "Cannot register MDIO bus %s\n",
173 if (netif_msg_drv(priv))
174 netdev_info(dev, "MDIO bus %s: created\n", mdio->id);
184 static void altera_tse_mdio_destroy(struct net_device *dev)
186 struct altera_tse_private *priv = netdev_priv(dev);
188 if (priv->mdio == NULL)
191 if (netif_msg_drv(priv))
192 netdev_info(dev, "MDIO bus %s: removed\n",
195 mdiobus_unregister(priv->mdio);
196 mdiobus_free(priv->mdio);
200 static int tse_init_rx_buffer(struct altera_tse_private *priv,
201 struct tse_buffer *rxbuffer, int len)
203 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len);
207 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data,
211 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) {
212 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
213 dev_kfree_skb_any(rxbuffer->skb);
216 rxbuffer->dma_addr &= (dma_addr_t)~3;
221 static void tse_free_rx_buffer(struct altera_tse_private *priv,
222 struct tse_buffer *rxbuffer)
224 struct sk_buff *skb = rxbuffer->skb;
225 dma_addr_t dma_addr = rxbuffer->dma_addr;
229 dma_unmap_single(priv->device, dma_addr,
232 dev_kfree_skb_any(skb);
233 rxbuffer->skb = NULL;
234 rxbuffer->dma_addr = 0;
238 /* Unmap and free Tx buffer resources
240 static void tse_free_tx_buffer(struct altera_tse_private *priv,
241 struct tse_buffer *buffer)
243 if (buffer->dma_addr) {
244 if (buffer->mapped_as_page)
245 dma_unmap_page(priv->device, buffer->dma_addr,
246 buffer->len, DMA_TO_DEVICE);
248 dma_unmap_single(priv->device, buffer->dma_addr,
249 buffer->len, DMA_TO_DEVICE);
250 buffer->dma_addr = 0;
253 dev_kfree_skb_any(buffer->skb);
258 static int alloc_init_skbufs(struct altera_tse_private *priv)
260 unsigned int rx_descs = priv->rx_ring_size;
261 unsigned int tx_descs = priv->tx_ring_size;
265 /* Create Rx ring buffer */
266 priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer),
271 /* Create Tx ring buffer */
272 priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer),
281 for (i = 0; i < rx_descs; i++) {
282 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i],
283 priv->rx_dma_buf_sz);
285 goto err_init_rx_buffers;
294 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
295 kfree(priv->tx_ring);
297 kfree(priv->rx_ring);
302 static void free_skbufs(struct net_device *dev)
304 struct altera_tse_private *priv = netdev_priv(dev);
305 unsigned int rx_descs = priv->rx_ring_size;
306 unsigned int tx_descs = priv->tx_ring_size;
309 /* Release the DMA TX/RX socket buffers */
310 for (i = 0; i < rx_descs; i++)
311 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
312 for (i = 0; i < tx_descs; i++)
313 tse_free_tx_buffer(priv, &priv->tx_ring[i]);
316 kfree(priv->tx_ring);
319 /* Reallocate the skb for the reception process
321 static inline void tse_rx_refill(struct altera_tse_private *priv)
323 unsigned int rxsize = priv->rx_ring_size;
327 for (; priv->rx_cons - priv->rx_prod > 0;
329 entry = priv->rx_prod % rxsize;
330 if (likely(priv->rx_ring[entry].skb == NULL)) {
331 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry],
332 priv->rx_dma_buf_sz);
333 if (unlikely(ret != 0))
335 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]);
340 /* Pull out the VLAN tag and fix up the packet
342 static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb)
344 struct ethhdr *eth_hdr;
346 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
347 !__vlan_get_tag(skb, &vid)) {
348 eth_hdr = (struct ethhdr *)skb->data;
349 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
350 skb_pull(skb, VLAN_HLEN);
351 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
355 /* Receive a packet: retrieve and pass over to upper levels
357 static int tse_rx(struct altera_tse_private *priv, int limit)
359 unsigned int count = 0;
360 unsigned int next_entry;
362 unsigned int entry = priv->rx_cons % priv->rx_ring_size;
367 /* Check for count < limit first as get_rx_status is changing
368 * the response-fifo so we must process the next packet
369 * after calling get_rx_status if a response is pending.
370 * (reading the last byte of the response pops the value from the fifo.)
372 while ((count < limit) &&
373 ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0)) {
374 pktstatus = rxstatus >> 16;
375 pktlength = rxstatus & 0xffff;
377 if ((pktstatus & 0xFF) || (pktlength == 0))
378 netdev_err(priv->dev,
379 "RCV pktstatus %08X pktlength %08X\n",
380 pktstatus, pktlength);
382 /* DMA trasfer from TSE starts with 2 aditional bytes for
383 * IP payload alignment. Status returned by get_rx_status()
384 * contains DMA transfer length. Packet is 2 bytes shorter.
389 next_entry = (++priv->rx_cons) % priv->rx_ring_size;
391 skb = priv->rx_ring[entry].skb;
392 if (unlikely(!skb)) {
393 netdev_err(priv->dev,
394 "%s: Inconsistent Rx descriptor chain\n",
396 priv->dev->stats.rx_dropped++;
399 priv->rx_ring[entry].skb = NULL;
401 skb_put(skb, pktlength);
403 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr,
404 priv->rx_ring[entry].len, DMA_FROM_DEVICE);
406 if (netif_msg_pktdata(priv)) {
407 netdev_info(priv->dev, "frame received %d bytes\n",
409 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET,
410 16, 1, skb->data, pktlength, true);
413 tse_rx_vlan(priv->dev, skb);
415 skb->protocol = eth_type_trans(skb, priv->dev);
416 skb_checksum_none_assert(skb);
418 napi_gro_receive(&priv->napi, skb);
420 priv->dev->stats.rx_packets++;
421 priv->dev->stats.rx_bytes += pktlength;
431 /* Reclaim resources after transmission completes
433 static int tse_tx_complete(struct altera_tse_private *priv)
435 unsigned int txsize = priv->tx_ring_size;
438 struct tse_buffer *tx_buff;
441 spin_lock(&priv->tx_lock);
443 ready = priv->dmaops->tx_completions(priv);
445 /* Free sent buffers */
446 while (ready && (priv->tx_cons != priv->tx_prod)) {
447 entry = priv->tx_cons % txsize;
448 tx_buff = &priv->tx_ring[entry];
450 if (netif_msg_tx_done(priv))
451 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n",
452 __func__, priv->tx_prod, priv->tx_cons);
454 if (likely(tx_buff->skb))
455 priv->dev->stats.tx_packets++;
457 tse_free_tx_buffer(priv, tx_buff);
464 if (unlikely(netif_queue_stopped(priv->dev) &&
465 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) {
466 if (netif_queue_stopped(priv->dev) &&
467 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) {
468 if (netif_msg_tx_done(priv))
469 netdev_dbg(priv->dev, "%s: restart transmit\n",
471 netif_wake_queue(priv->dev);
475 spin_unlock(&priv->tx_lock);
479 /* NAPI polling function
481 static int tse_poll(struct napi_struct *napi, int budget)
483 struct altera_tse_private *priv =
484 container_of(napi, struct altera_tse_private, napi);
486 unsigned long int flags;
488 tse_tx_complete(priv);
490 rxcomplete = tse_rx(priv, budget);
492 if (rxcomplete < budget) {
496 netdev_dbg(priv->dev,
497 "NAPI Complete, did %d packets with budget %d\n",
500 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
501 priv->dmaops->enable_rxirq(priv);
502 priv->dmaops->enable_txirq(priv);
503 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
508 /* DMA TX & RX FIFO interrupt routing
510 static irqreturn_t altera_isr(int irq, void *dev_id)
512 struct net_device *dev = dev_id;
513 struct altera_tse_private *priv;
515 if (unlikely(!dev)) {
516 pr_err("%s: invalid dev pointer\n", __func__);
519 priv = netdev_priv(dev);
521 spin_lock(&priv->rxdma_irq_lock);
523 priv->dmaops->clear_rxirq(priv);
524 priv->dmaops->clear_txirq(priv);
525 spin_unlock(&priv->rxdma_irq_lock);
527 if (likely(napi_schedule_prep(&priv->napi))) {
528 spin_lock(&priv->rxdma_irq_lock);
529 priv->dmaops->disable_rxirq(priv);
530 priv->dmaops->disable_txirq(priv);
531 spin_unlock(&priv->rxdma_irq_lock);
532 __napi_schedule(&priv->napi);
539 /* Transmit a packet (called by the kernel). Dispatches
540 * either the SGDMA method for transmitting or the
541 * MSGDMA method, assumes no scatter/gather support,
542 * implying an assumption that there's only one
543 * physically contiguous fragment starting at
544 * skb->data, for length of skb_headlen(skb).
546 static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
548 struct altera_tse_private *priv = netdev_priv(dev);
549 unsigned int txsize = priv->tx_ring_size;
551 struct tse_buffer *buffer = NULL;
552 int nfrags = skb_shinfo(skb)->nr_frags;
553 unsigned int nopaged_len = skb_headlen(skb);
554 enum netdev_tx ret = NETDEV_TX_OK;
557 spin_lock_bh(&priv->tx_lock);
559 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) {
560 if (!netif_queue_stopped(dev)) {
561 netif_stop_queue(dev);
562 /* This is a hard error, log it. */
563 netdev_err(priv->dev,
564 "%s: Tx list full when queue awake\n",
567 ret = NETDEV_TX_BUSY;
571 /* Map the first skb fragment */
572 entry = priv->tx_prod % txsize;
573 buffer = &priv->tx_ring[entry];
575 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len,
577 if (dma_mapping_error(priv->device, dma_addr)) {
578 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
584 buffer->dma_addr = dma_addr;
585 buffer->len = nopaged_len;
587 priv->dmaops->tx_buffer(priv, buffer);
589 skb_tx_timestamp(skb);
592 dev->stats.tx_bytes += skb->len;
594 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) {
595 if (netif_msg_hw(priv))
596 netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
598 netif_stop_queue(dev);
602 spin_unlock_bh(&priv->tx_lock);
607 /* Called every time the controller might need to be made
608 * aware of new link state. The PHY code conveys this
609 * information through variables in the phydev structure, and this
610 * function converts those variables into the appropriate
611 * register values, and can bring down the device if needed.
613 static void altera_tse_adjust_link(struct net_device *dev)
615 struct altera_tse_private *priv = netdev_priv(dev);
616 struct phy_device *phydev = dev->phydev;
619 /* only change config if there is a link */
620 spin_lock(&priv->mac_cfg_lock);
622 /* Read old config */
623 u32 cfg_reg = ioread32(&priv->mac_dev->command_config);
626 if (phydev->duplex != priv->oldduplex) {
628 if (!(phydev->duplex))
629 cfg_reg |= MAC_CMDCFG_HD_ENA;
631 cfg_reg &= ~MAC_CMDCFG_HD_ENA;
633 netdev_dbg(priv->dev, "%s: Link duplex = 0x%x\n",
634 dev->name, phydev->duplex);
636 priv->oldduplex = phydev->duplex;
640 if (phydev->speed != priv->oldspeed) {
642 switch (phydev->speed) {
644 cfg_reg |= MAC_CMDCFG_ETH_SPEED;
645 cfg_reg &= ~MAC_CMDCFG_ENA_10;
648 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
649 cfg_reg &= ~MAC_CMDCFG_ENA_10;
652 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
653 cfg_reg |= MAC_CMDCFG_ENA_10;
656 if (netif_msg_link(priv))
657 netdev_warn(dev, "Speed (%d) is not 10/100/1000!\n",
661 priv->oldspeed = phydev->speed;
663 iowrite32(cfg_reg, &priv->mac_dev->command_config);
665 if (!priv->oldlink) {
669 } else if (priv->oldlink) {
673 priv->oldduplex = -1;
676 if (new_state && netif_msg_link(priv))
677 phy_print_status(phydev);
679 spin_unlock(&priv->mac_cfg_lock);
681 static struct phy_device *connect_local_phy(struct net_device *dev)
683 struct altera_tse_private *priv = netdev_priv(dev);
684 struct phy_device *phydev = NULL;
685 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
687 if (priv->phy_addr != POLL_PHY) {
688 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
689 priv->mdio->id, priv->phy_addr);
691 netdev_dbg(dev, "trying to attach to %s\n", phy_id_fmt);
693 phydev = phy_connect(dev, phy_id_fmt, &altera_tse_adjust_link,
695 if (IS_ERR(phydev)) {
696 netdev_err(dev, "Could not attach to PHY\n");
702 phydev = phy_find_first(priv->mdio);
703 if (phydev == NULL) {
704 netdev_err(dev, "No PHY found\n");
708 ret = phy_connect_direct(dev, phydev, &altera_tse_adjust_link,
711 netdev_err(dev, "Could not attach to PHY\n");
718 static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev)
720 struct altera_tse_private *priv = netdev_priv(dev);
721 struct device_node *np = priv->device->of_node;
724 priv->phy_iface = of_get_phy_mode(np);
726 /* Avoid get phy addr and create mdio if no phy is present */
727 if (!priv->phy_iface)
730 /* try to get PHY address from device tree, use PHY autodetection if
731 * no valid address is given
734 if (of_property_read_u32(priv->device->of_node, "phy-addr",
736 priv->phy_addr = POLL_PHY;
739 if (!((priv->phy_addr == POLL_PHY) ||
740 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) {
741 netdev_err(dev, "invalid phy-addr specified %d\n",
746 /* Create/attach to MDIO bus */
747 ret = altera_tse_mdio_create(dev,
748 atomic_add_return(1, &instance_count));
756 /* Initialize driver's PHY state, and attach to the PHY
758 static int init_phy(struct net_device *dev)
760 struct altera_tse_private *priv = netdev_priv(dev);
761 struct phy_device *phydev;
762 struct device_node *phynode;
763 bool fixed_link = false;
766 /* Avoid init phy in case of no phy present */
767 if (!priv->phy_iface)
772 priv->oldduplex = -1;
774 phynode = of_parse_phandle(priv->device->of_node, "phy-handle", 0);
777 /* check if a fixed-link is defined in device-tree */
778 if (of_phy_is_fixed_link(priv->device->of_node)) {
779 rc = of_phy_register_fixed_link(priv->device->of_node);
781 netdev_err(dev, "cannot register fixed PHY\n");
785 /* In the case of a fixed PHY, the DT node associated
786 * to the PHY is the Ethernet MAC DT node.
788 phynode = of_node_get(priv->device->of_node);
791 netdev_dbg(dev, "fixed-link detected\n");
792 phydev = of_phy_connect(dev, phynode,
793 &altera_tse_adjust_link,
796 netdev_dbg(dev, "no phy-handle found\n");
798 netdev_err(dev, "No phy-handle nor local mdio specified\n");
801 phydev = connect_local_phy(dev);
804 netdev_dbg(dev, "phy-handle found\n");
805 phydev = of_phy_connect(dev, phynode,
806 &altera_tse_adjust_link, 0, priv->phy_iface);
808 of_node_put(phynode);
811 netdev_err(dev, "Could not find the PHY\n");
813 of_phy_deregister_fixed_link(priv->device->of_node);
817 /* Stop Advertising 1000BASE Capability if interface is not GMII
818 * Note: Checkpatch throws CHECKs for the camel case defines below,
821 if ((priv->phy_iface == PHY_INTERFACE_MODE_MII) ||
822 (priv->phy_iface == PHY_INTERFACE_MODE_RMII))
823 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
824 SUPPORTED_1000baseT_Full);
826 /* Broken HW is sometimes missing the pull-up resistor on the
827 * MDIO line, which results in reads to non-existent devices returning
828 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
829 * device as well. If a fixed-link is used the phy_id is always 0.
830 * Note: phydev->phy_id is the result of reading the UID PHY registers.
832 if ((phydev->phy_id == 0) && !fixed_link) {
833 netdev_err(dev, "Bad PHY UID 0x%08x\n", phydev->phy_id);
834 phy_disconnect(phydev);
838 netdev_dbg(dev, "attached to PHY %d UID 0x%08x Link = %d\n",
839 phydev->mdio.addr, phydev->phy_id, phydev->link);
844 static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr)
849 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
850 lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
852 /* Set primary MAC address */
853 csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0));
854 csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1));
857 /* MAC software reset.
858 * When reset is triggered, the MAC function completes the current
859 * transmission or reception, and subsequently disables the transmit and
860 * receive logic, flushes the receive FIFO buffer, and resets the statistics
863 static int reset_mac(struct altera_tse_private *priv)
868 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
869 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
870 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
871 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
874 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
875 if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config),
876 MAC_CMDCFG_SW_RESET))
881 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
882 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
883 dat &= ~MAC_CMDCFG_SW_RESET;
884 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
890 /* Initialize MAC core registers
892 static int init_mac(struct altera_tse_private *priv)
894 unsigned int cmd = 0;
898 csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
899 priv->mac_dev, tse_csroffs(rx_section_empty));
901 csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev,
902 tse_csroffs(rx_section_full));
904 csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev,
905 tse_csroffs(rx_almost_empty));
907 csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev,
908 tse_csroffs(rx_almost_full));
911 csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
912 priv->mac_dev, tse_csroffs(tx_section_empty));
914 csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev,
915 tse_csroffs(tx_section_full));
917 csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev,
918 tse_csroffs(tx_almost_empty));
920 csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev,
921 tse_csroffs(tx_almost_full));
923 /* MAC Address Configuration */
924 tse_update_mac_addr(priv, priv->dev->dev_addr);
926 /* MAC Function Configuration */
927 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
928 csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length));
930 csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev,
931 tse_csroffs(tx_ipg_length));
933 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
936 tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat),
937 ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
939 tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat),
940 ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
941 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
943 /* Set the MAC options */
944 cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config));
945 cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */
946 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */
947 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames
950 cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
951 cmd &= ~MAC_CMDCFG_TX_ENA;
952 cmd &= ~MAC_CMDCFG_RX_ENA;
954 /* Default speed and duplex setting, full/100 */
955 cmd &= ~MAC_CMDCFG_HD_ENA;
956 cmd &= ~MAC_CMDCFG_ETH_SPEED;
957 cmd &= ~MAC_CMDCFG_ENA_10;
959 csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config));
961 csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev,
962 tse_csroffs(pause_quanta));
964 if (netif_msg_hw(priv))
965 dev_dbg(priv->device,
966 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd);
971 /* Start/stop MAC transmission logic
973 static void tse_set_mac(struct altera_tse_private *priv, bool enable)
975 u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config));
978 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
980 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
982 csrwr32(value, priv->mac_dev, tse_csroffs(command_config));
987 static int tse_change_mtu(struct net_device *dev, int new_mtu)
989 struct altera_tse_private *priv = netdev_priv(dev);
990 unsigned int max_mtu = priv->max_mtu;
991 unsigned int min_mtu = ETH_ZLEN + ETH_FCS_LEN;
993 if (netif_running(dev)) {
994 netdev_err(dev, "must be stopped to change its MTU\n");
998 if ((new_mtu < min_mtu) || (new_mtu > max_mtu)) {
999 netdev_err(dev, "invalid MTU, max MTU is: %u\n", max_mtu);
1004 netdev_update_features(dev);
1009 static void altera_tse_set_mcfilter(struct net_device *dev)
1011 struct altera_tse_private *priv = netdev_priv(dev);
1013 struct netdev_hw_addr *ha;
1015 /* clear the hash filter */
1016 for (i = 0; i < 64; i++)
1017 csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1019 netdev_for_each_mc_addr(ha, dev) {
1020 unsigned int hash = 0;
1023 for (mac_octet = 5; mac_octet >= 0; mac_octet--) {
1024 unsigned char xor_bit = 0;
1025 unsigned char octet = ha->addr[mac_octet];
1026 unsigned int bitshift;
1028 for (bitshift = 0; bitshift < 8; bitshift++)
1029 xor_bit ^= ((octet >> bitshift) & 0x01);
1031 hash = (hash << 1) | xor_bit;
1033 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4);
1038 static void altera_tse_set_mcfilterall(struct net_device *dev)
1040 struct altera_tse_private *priv = netdev_priv(dev);
1043 /* set the hash filter */
1044 for (i = 0; i < 64; i++)
1045 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1048 /* Set or clear the multicast filter for this adaptor
1050 static void tse_set_rx_mode_hashfilter(struct net_device *dev)
1052 struct altera_tse_private *priv = netdev_priv(dev);
1054 spin_lock(&priv->mac_cfg_lock);
1056 if (dev->flags & IFF_PROMISC)
1057 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1058 MAC_CMDCFG_PROMIS_EN);
1060 if (dev->flags & IFF_ALLMULTI)
1061 altera_tse_set_mcfilterall(dev);
1063 altera_tse_set_mcfilter(dev);
1065 spin_unlock(&priv->mac_cfg_lock);
1068 /* Set or clear the multicast filter for this adaptor
1070 static void tse_set_rx_mode(struct net_device *dev)
1072 struct altera_tse_private *priv = netdev_priv(dev);
1074 spin_lock(&priv->mac_cfg_lock);
1076 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
1077 !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
1078 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1079 MAC_CMDCFG_PROMIS_EN);
1081 tse_clear_bit(priv->mac_dev, tse_csroffs(command_config),
1082 MAC_CMDCFG_PROMIS_EN);
1084 spin_unlock(&priv->mac_cfg_lock);
1087 /* Open and initialize the interface
1089 static int tse_open(struct net_device *dev)
1091 struct altera_tse_private *priv = netdev_priv(dev);
1094 unsigned long int flags;
1096 /* Reset and configure TSE MAC and probe associated PHY */
1097 ret = priv->dmaops->init_dma(priv);
1099 netdev_err(dev, "Cannot initialize DMA\n");
1103 if (netif_msg_ifup(priv))
1104 netdev_warn(dev, "device MAC address %pM\n",
1107 if ((priv->revision < 0xd00) || (priv->revision > 0xe00))
1108 netdev_warn(dev, "TSE revision %x\n", priv->revision);
1110 spin_lock(&priv->mac_cfg_lock);
1111 ret = reset_mac(priv);
1112 /* Note that reset_mac will fail if the clocks are gated by the PHY
1113 * due to the PHY being put into isolation or power down mode.
1114 * This is not an error if reset fails due to no clock.
1117 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1119 ret = init_mac(priv);
1120 spin_unlock(&priv->mac_cfg_lock);
1122 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret);
1123 goto alloc_skbuf_error;
1126 priv->dmaops->reset_dma(priv);
1128 /* Create and initialize the TX/RX descriptors chains. */
1129 priv->rx_ring_size = dma_rx_num;
1130 priv->tx_ring_size = dma_tx_num;
1131 ret = alloc_init_skbufs(priv);
1133 netdev_err(dev, "DMA descriptors initialization failed\n");
1134 goto alloc_skbuf_error;
1138 /* Register RX interrupt */
1139 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED,
1142 netdev_err(dev, "Unable to register RX interrupt %d\n",
1147 /* Register TX interrupt */
1148 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED,
1151 netdev_err(dev, "Unable to register TX interrupt %d\n",
1153 goto tx_request_irq_error;
1156 /* Enable DMA interrupts */
1157 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1158 priv->dmaops->enable_rxirq(priv);
1159 priv->dmaops->enable_txirq(priv);
1161 /* Setup RX descriptor chain */
1162 for (i = 0; i < priv->rx_ring_size; i++)
1163 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]);
1165 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1168 phy_start(dev->phydev);
1170 napi_enable(&priv->napi);
1171 netif_start_queue(dev);
1173 priv->dmaops->start_rxdma(priv);
1175 /* Start MAC Rx/Tx */
1176 spin_lock(&priv->mac_cfg_lock);
1177 tse_set_mac(priv, true);
1178 spin_unlock(&priv->mac_cfg_lock);
1182 tx_request_irq_error:
1183 free_irq(priv->rx_irq, dev);
1191 /* Stop TSE MAC interface and put the device in an inactive state
1193 static int tse_shutdown(struct net_device *dev)
1195 struct altera_tse_private *priv = netdev_priv(dev);
1197 unsigned long int flags;
1201 phy_stop(dev->phydev);
1203 netif_stop_queue(dev);
1204 napi_disable(&priv->napi);
1206 /* Disable DMA interrupts */
1207 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1208 priv->dmaops->disable_rxirq(priv);
1209 priv->dmaops->disable_txirq(priv);
1210 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1212 /* Free the IRQ lines */
1213 free_irq(priv->rx_irq, dev);
1214 free_irq(priv->tx_irq, dev);
1216 /* disable and reset the MAC, empties fifo */
1217 spin_lock(&priv->mac_cfg_lock);
1218 spin_lock(&priv->tx_lock);
1220 ret = reset_mac(priv);
1221 /* Note that reset_mac will fail if the clocks are gated by the PHY
1222 * due to the PHY being put into isolation or power down mode.
1223 * This is not an error if reset fails due to no clock.
1226 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1227 priv->dmaops->reset_dma(priv);
1230 spin_unlock(&priv->tx_lock);
1231 spin_unlock(&priv->mac_cfg_lock);
1233 priv->dmaops->uninit_dma(priv);
1238 static struct net_device_ops altera_tse_netdev_ops = {
1239 .ndo_open = tse_open,
1240 .ndo_stop = tse_shutdown,
1241 .ndo_start_xmit = tse_start_xmit,
1242 .ndo_set_mac_address = eth_mac_addr,
1243 .ndo_set_rx_mode = tse_set_rx_mode,
1244 .ndo_change_mtu = tse_change_mtu,
1245 .ndo_validate_addr = eth_validate_addr,
1248 static int request_and_map(struct platform_device *pdev, const char *name,
1249 struct resource **res, void __iomem **ptr)
1251 struct resource *region;
1252 struct device *device = &pdev->dev;
1254 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
1256 dev_err(device, "resource %s not defined\n", name);
1260 region = devm_request_mem_region(device, (*res)->start,
1261 resource_size(*res), dev_name(device));
1262 if (region == NULL) {
1263 dev_err(device, "unable to request %s\n", name);
1267 *ptr = devm_ioremap_nocache(device, region->start,
1268 resource_size(region));
1270 dev_err(device, "ioremap_nocache of %s failed!", name);
1277 /* Probe Altera TSE MAC device
1279 static int altera_tse_probe(struct platform_device *pdev)
1281 struct net_device *ndev;
1283 struct resource *control_port;
1284 struct resource *dma_res;
1285 struct altera_tse_private *priv;
1286 const unsigned char *macaddr;
1287 void __iomem *descmap;
1288 const struct of_device_id *of_id = NULL;
1290 ndev = alloc_etherdev(sizeof(struct altera_tse_private));
1292 dev_err(&pdev->dev, "Could not allocate network device\n");
1296 SET_NETDEV_DEV(ndev, &pdev->dev);
1298 priv = netdev_priv(ndev);
1299 priv->device = &pdev->dev;
1301 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1303 of_id = of_match_device(altera_tse_ids, &pdev->dev);
1306 priv->dmaops = (struct altera_dmaops *)of_id->data;
1310 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) {
1311 /* Get the mapped address to the SGDMA descriptor memory */
1312 ret = request_and_map(pdev, "s1", &dma_res, &descmap);
1314 goto err_free_netdev;
1316 /* Start of that memory is for transmit descriptors */
1317 priv->tx_dma_desc = descmap;
1319 /* First half is for tx descriptors, other half for tx */
1320 priv->txdescmem = resource_size(dma_res)/2;
1322 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start;
1324 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap +
1326 priv->rxdescmem = resource_size(dma_res)/2;
1327 priv->rxdescmem_busaddr = dma_res->start;
1328 priv->rxdescmem_busaddr += priv->txdescmem;
1330 if (upper_32_bits(priv->rxdescmem_busaddr)) {
1331 dev_dbg(priv->device,
1332 "SGDMA bus addresses greater than 32-bits\n");
1333 goto err_free_netdev;
1335 if (upper_32_bits(priv->txdescmem_busaddr)) {
1336 dev_dbg(priv->device,
1337 "SGDMA bus addresses greater than 32-bits\n");
1338 goto err_free_netdev;
1340 } else if (priv->dmaops &&
1341 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) {
1342 ret = request_and_map(pdev, "rx_resp", &dma_res,
1343 &priv->rx_dma_resp);
1345 goto err_free_netdev;
1347 ret = request_and_map(pdev, "tx_desc", &dma_res,
1348 &priv->tx_dma_desc);
1350 goto err_free_netdev;
1352 priv->txdescmem = resource_size(dma_res);
1353 priv->txdescmem_busaddr = dma_res->start;
1355 ret = request_and_map(pdev, "rx_desc", &dma_res,
1356 &priv->rx_dma_desc);
1358 goto err_free_netdev;
1360 priv->rxdescmem = resource_size(dma_res);
1361 priv->rxdescmem_busaddr = dma_res->start;
1365 goto err_free_netdev;
1368 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask))) {
1369 dma_set_coherent_mask(priv->device,
1370 DMA_BIT_MASK(priv->dmaops->dmamask));
1371 } else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32))) {
1372 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32));
1375 goto err_free_netdev;
1378 /* MAC address space */
1379 ret = request_and_map(pdev, "control_port", &control_port,
1380 (void __iomem **)&priv->mac_dev);
1382 goto err_free_netdev;
1384 /* xSGDMA Rx Dispatcher address space */
1385 ret = request_and_map(pdev, "rx_csr", &dma_res,
1388 goto err_free_netdev;
1391 /* xSGDMA Tx Dispatcher address space */
1392 ret = request_and_map(pdev, "tx_csr", &dma_res,
1395 goto err_free_netdev;
1399 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq");
1400 if (priv->rx_irq == -ENXIO) {
1401 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n");
1403 goto err_free_netdev;
1407 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq");
1408 if (priv->tx_irq == -ENXIO) {
1409 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n");
1411 goto err_free_netdev;
1414 /* get FIFO depths from device tree */
1415 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1416 &priv->rx_fifo_depth)) {
1417 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n");
1419 goto err_free_netdev;
1422 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1423 &priv->tx_fifo_depth)) {
1424 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n");
1426 goto err_free_netdev;
1429 /* get hash filter settings for this instance */
1431 of_property_read_bool(pdev->dev.of_node,
1432 "altr,has-hash-multicast-filter");
1434 /* Set hash filter to not set for now until the
1435 * multicast filter receive issue is debugged
1437 priv->hash_filter = 0;
1439 /* get supplemental address settings for this instance */
1440 priv->added_unicast =
1441 of_property_read_bool(pdev->dev.of_node,
1442 "altr,has-supplementary-unicast");
1444 /* Max MTU is 1500, ETH_DATA_LEN */
1445 priv->max_mtu = ETH_DATA_LEN;
1447 /* Get the max mtu from the device tree. Note that the
1448 * "max-frame-size" parameter is actually max mtu. Definition
1449 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1451 of_property_read_u32(pdev->dev.of_node, "max-frame-size",
1454 /* The DMA buffer size already accounts for an alignment bias
1455 * to avoid unaligned access exceptions for the NIOS processor,
1457 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;
1459 /* get default MAC address from device tree */
1460 macaddr = of_get_mac_address(pdev->dev.of_node);
1462 ether_addr_copy(ndev->dev_addr, macaddr);
1464 eth_hw_addr_random(ndev);
1466 /* get phy addr and create mdio */
1467 ret = altera_tse_phy_get_addr_mdio_create(ndev);
1470 goto err_free_netdev;
1472 /* initialize netdev */
1473 ndev->mem_start = control_port->start;
1474 ndev->mem_end = control_port->end;
1475 ndev->netdev_ops = &altera_tse_netdev_ops;
1476 altera_tse_set_ethtool_ops(ndev);
1478 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode;
1480 if (priv->hash_filter)
1481 altera_tse_netdev_ops.ndo_set_rx_mode =
1482 tse_set_rx_mode_hashfilter;
1484 /* Scatter/gather IO is not supported,
1485 * so it is turned off
1487 ndev->hw_features &= ~NETIF_F_SG;
1488 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1490 /* VLAN offloading of tagging, stripping and filtering is not
1491 * supported by hardware, but driver will accommodate the
1492 * extra 4-byte VLAN tag for processing by upper layers
1494 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1496 /* setup NAPI interface */
1497 netif_napi_add(ndev, &priv->napi, tse_poll, NAPI_POLL_WEIGHT);
1499 spin_lock_init(&priv->mac_cfg_lock);
1500 spin_lock_init(&priv->tx_lock);
1501 spin_lock_init(&priv->rxdma_irq_lock);
1503 netif_carrier_off(ndev);
1504 ret = register_netdev(ndev);
1506 dev_err(&pdev->dev, "failed to register TSE net device\n");
1507 goto err_register_netdev;
1510 platform_set_drvdata(pdev, ndev);
1512 priv->revision = ioread32(&priv->mac_dev->megacore_revision);
1514 if (netif_msg_probe(priv))
1515 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1516 (priv->revision >> 8) & 0xff,
1517 priv->revision & 0xff,
1518 (unsigned long) control_port->start, priv->rx_irq,
1521 ret = init_phy(ndev);
1523 netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret);
1529 unregister_netdev(ndev);
1530 err_register_netdev:
1531 netif_napi_del(&priv->napi);
1532 altera_tse_mdio_destroy(ndev);
1538 /* Remove Altera TSE MAC device
1540 static int altera_tse_remove(struct platform_device *pdev)
1542 struct net_device *ndev = platform_get_drvdata(pdev);
1543 struct altera_tse_private *priv = netdev_priv(ndev);
1546 phy_disconnect(ndev->phydev);
1548 if (of_phy_is_fixed_link(priv->device->of_node))
1549 of_phy_deregister_fixed_link(priv->device->of_node);
1552 platform_set_drvdata(pdev, NULL);
1553 altera_tse_mdio_destroy(ndev);
1554 unregister_netdev(ndev);
1560 static const struct altera_dmaops altera_dtype_sgdma = {
1561 .altera_dtype = ALTERA_DTYPE_SGDMA,
1563 .reset_dma = sgdma_reset,
1564 .enable_txirq = sgdma_enable_txirq,
1565 .enable_rxirq = sgdma_enable_rxirq,
1566 .disable_txirq = sgdma_disable_txirq,
1567 .disable_rxirq = sgdma_disable_rxirq,
1568 .clear_txirq = sgdma_clear_txirq,
1569 .clear_rxirq = sgdma_clear_rxirq,
1570 .tx_buffer = sgdma_tx_buffer,
1571 .tx_completions = sgdma_tx_completions,
1572 .add_rx_desc = sgdma_add_rx_desc,
1573 .get_rx_status = sgdma_rx_status,
1574 .init_dma = sgdma_initialize,
1575 .uninit_dma = sgdma_uninitialize,
1576 .start_rxdma = sgdma_start_rxdma,
1579 static const struct altera_dmaops altera_dtype_msgdma = {
1580 .altera_dtype = ALTERA_DTYPE_MSGDMA,
1582 .reset_dma = msgdma_reset,
1583 .enable_txirq = msgdma_enable_txirq,
1584 .enable_rxirq = msgdma_enable_rxirq,
1585 .disable_txirq = msgdma_disable_txirq,
1586 .disable_rxirq = msgdma_disable_rxirq,
1587 .clear_txirq = msgdma_clear_txirq,
1588 .clear_rxirq = msgdma_clear_rxirq,
1589 .tx_buffer = msgdma_tx_buffer,
1590 .tx_completions = msgdma_tx_completions,
1591 .add_rx_desc = msgdma_add_rx_desc,
1592 .get_rx_status = msgdma_rx_status,
1593 .init_dma = msgdma_initialize,
1594 .uninit_dma = msgdma_uninitialize,
1595 .start_rxdma = msgdma_start_rxdma,
1598 static const struct of_device_id altera_tse_ids[] = {
1599 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
1600 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
1601 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
1604 MODULE_DEVICE_TABLE(of, altera_tse_ids);
1606 static struct platform_driver altera_tse_driver = {
1607 .probe = altera_tse_probe,
1608 .remove = altera_tse_remove,
1612 .name = ALTERA_TSE_RESOURCE_NAME,
1613 .of_match_table = altera_tse_ids,
1617 module_platform_driver(altera_tse_driver);
1619 MODULE_AUTHOR("Altera Corporation");
1620 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1621 MODULE_LICENSE("GPL v2");