drivers/net/ethernet/amd/xgbe/xgbe-drv.c

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #include <linux/module.h>
 118 #include <linux/spinlock.h>
 119 #include <linux/tcp.h>
 120 #include <linux/if_vlan.h>
 121 #include <linux/interrupt.h>
 122 #include <net/busy_poll.h>
 123 #include <linux/clk.h>
 124 #include <linux/if_ether.h>
 125 #include <linux/net_tstamp.h>
 126 #include <linux/phy.h>
 127 #include <net/vxlan.h>
 128
 129 #include "xgbe.h"
 130 #include "xgbe-common.h"
 131
 132 static unsigned int ecc_sec_info_threshold = 10;
 133 static unsigned int ecc_sec_warn_threshold = 10000;
 134 static unsigned int ecc_sec_period = 600;
 135 static unsigned int ecc_ded_threshold = 2;
 136 static unsigned int ecc_ded_period = 600;
 137
 138 #ifdef CONFIG_AMD_XGBE_HAVE_ECC
 139 /* Only expose the ECC parameters if supported */
 140 module_param(ecc_sec_info_threshold, uint, 0644);
 141 MODULE_PARM_DESC(ecc_sec_info_threshold,
 142                  " ECC corrected error informational threshold setting");
 143
 144 module_param(ecc_sec_warn_threshold, uint, 0644);
 145 MODULE_PARM_DESC(ecc_sec_warn_threshold,
 146                  " ECC corrected error warning threshold setting");
 147
 148 module_param(ecc_sec_period, uint, 0644);
 149 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
 150
 151 module_param(ecc_ded_threshold, uint, 0644);
 152 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
 153
 154 module_param(ecc_ded_period, uint, 0644);
 155 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
 156 #endif
 157
 158 static int xgbe_one_poll(struct napi_struct *, int);
 159 static int xgbe_all_poll(struct napi_struct *, int);
 160 static void xgbe_stop(struct xgbe_prv_data *);
 161
 162 static void *xgbe_alloc_node(size_t size, int node)
 163 {
 164         void *mem;
 165
 166         mem = kzalloc_node(size, GFP_KERNEL, node);
 167         if (!mem)
 168                 mem = kzalloc(size, GFP_KERNEL);
 169
 170         return mem;
 171 }
 172
 173 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
 174 {
 175         unsigned int i;
 176
 177         for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
 178                 if (!pdata->channel[i])
 179                         continue;
 180
 181                 kfree(pdata->channel[i]->rx_ring);
 182                 kfree(pdata->channel[i]->tx_ring);
 183                 kfree(pdata->channel[i]);
 184
 185                 pdata->channel[i] = NULL;
 186         }
 187
 188         pdata->channel_count = 0;
 189 }
 190
 191 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
 192 {
 193         struct xgbe_channel *channel;
 194         struct xgbe_ring *ring;
 195         unsigned int count, i;
 196         unsigned int cpu;
 197         int node;
 198
 199         count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
 200         for (i = 0; i < count; i++) {
 201                 /* Attempt to use a CPU on the node the device is on */
 202                 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
 203
 204                 /* Set the allocation node based on the returned CPU */
 205                 node = cpu_to_node(cpu);
 206
 207                 channel = xgbe_alloc_node(sizeof(*channel), node);
 208                 if (!channel)
 209                         goto err_mem;
 210                 pdata->channel[i] = channel;
 211
 212                 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
 213                 channel->pdata = pdata;
 214                 channel->queue_index = i;
 215                 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
 216                                     (DMA_CH_INC * i);
 217                 channel->node = node;
 218                 cpumask_set_cpu(cpu, &channel->affinity_mask);
 219
 220                 if (pdata->per_channel_irq)
 221                         channel->dma_irq = pdata->channel_irq[i];
 222
 223                 if (i < pdata->tx_ring_count) {
 224                         ring = xgbe_alloc_node(sizeof(*ring), node);
 225                         if (!ring)
 226                                 goto err_mem;
 227
 228                         spin_lock_init(&ring->lock);
 229                         ring->node = node;
 230
 231                         channel->tx_ring = ring;
 232                 }
 233
 234                 if (i < pdata->rx_ring_count) {
 235                         ring = xgbe_alloc_node(sizeof(*ring), node);
 236                         if (!ring)
 237                                 goto err_mem;
 238
 239                         spin_lock_init(&ring->lock);
 240                         ring->node = node;
 241
 242                         channel->rx_ring = ring;
 243                 }
 244
 245                 netif_dbg(pdata, drv, pdata->netdev,
 246                           "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
 247
 248                 netif_dbg(pdata, drv, pdata->netdev,
 249                           "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
 250                           channel->name, channel->dma_regs, channel->dma_irq,
 251                           channel->tx_ring, channel->rx_ring);
 252         }
 253
 254         pdata->channel_count = count;
 255
 256         return 0;
 257
 258 err_mem:
 259         xgbe_free_channels(pdata);
 260
 261         return -ENOMEM;
 262 }
 263
 264 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
 265 {
 266         return (ring->rdesc_count - (ring->cur - ring->dirty));
 267 }
 268
 269 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
 270 {
 271         return (ring->cur - ring->dirty);
 272 }
 273
 274 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
 275                                     struct xgbe_ring *ring, unsigned int count)
 276 {
 277         struct xgbe_prv_data *pdata = channel->pdata;
 278
 279         if (count > xgbe_tx_avail_desc(ring)) {
 280                 netif_info(pdata, drv, pdata->netdev,
 281                            "Tx queue stopped, not enough descriptors available\n");
 282                 netif_stop_subqueue(pdata->netdev, channel->queue_index);
 283                 ring->tx.queue_stopped = 1;
 284
 285                 /* If we haven't notified the hardware because of xmit_more
 286                  * support, tell it now
 287                  */
 288                 if (ring->tx.xmit_more)
 289                         pdata->hw_if.tx_start_xmit(channel, ring);
 290
 291                 return NETDEV_TX_BUSY;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
 298 {
 299         unsigned int rx_buf_size;
 300
 301         rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
 302         rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
 303
 304         rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
 305                       ~(XGBE_RX_BUF_ALIGN - 1);
 306
 307         return rx_buf_size;
 308 }
 309
 310 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
 311                                   struct xgbe_channel *channel)
 312 {
 313         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 314         enum xgbe_int int_id;
 315
 316         if (channel->tx_ring && channel->rx_ring)
 317                 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 318         else if (channel->tx_ring)
 319                 int_id = XGMAC_INT_DMA_CH_SR_TI;
 320         else if (channel->rx_ring)
 321                 int_id = XGMAC_INT_DMA_CH_SR_RI;
 322         else
 323                 return;
 324
 325         hw_if->enable_int(channel, int_id);
 326 }
 327
 328 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
 329 {
 330         unsigned int i;
 331
 332         for (i = 0; i < pdata->channel_count; i++)
 333                 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
 334 }
 335
 336 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
 337                                    struct xgbe_channel *channel)
 338 {
 339         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 340         enum xgbe_int int_id;
 341
 342         if (channel->tx_ring && channel->rx_ring)
 343                 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 344         else if (channel->tx_ring)
 345                 int_id = XGMAC_INT_DMA_CH_SR_TI;
 346         else if (channel->rx_ring)
 347                 int_id = XGMAC_INT_DMA_CH_SR_RI;
 348         else
 349                 return;
 350
 351         hw_if->disable_int(channel, int_id);
 352 }
 353
 354 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
 355 {
 356         unsigned int i;
 357
 358         for (i = 0; i < pdata->channel_count; i++)
 359                 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
 360 }
 361
 362 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
 363                          unsigned int *count, const char *area)
 364 {
 365         if (time_before(jiffies, *period)) {
 366                 (*count)++;
 367         } else {
 368                 *period = jiffies + (ecc_sec_period * HZ);
 369                 *count = 1;
 370         }
 371
 372         if (*count > ecc_sec_info_threshold)
 373                 dev_warn_once(pdata->dev,
 374                               "%s ECC corrected errors exceed informational threshold\n",
 375                               area);
 376
 377         if (*count > ecc_sec_warn_threshold) {
 378                 dev_warn_once(pdata->dev,
 379                               "%s ECC corrected errors exceed warning threshold\n",
 380                               area);
 381                 return true;
 382         }
 383
 384         return false;
 385 }
 386
 387 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
 388                          unsigned int *count, const char *area)
 389 {
 390         if (time_before(jiffies, *period)) {
 391                 (*count)++;
 392         } else {
 393                 *period = jiffies + (ecc_ded_period * HZ);
 394                 *count = 1;
 395         }
 396
 397         if (*count > ecc_ded_threshold) {
 398                 netdev_alert(pdata->netdev,
 399                              "%s ECC detected errors exceed threshold\n",
 400                              area);
 401                 return true;
 402         }
 403
 404         return false;
 405 }
 406
 407 static void xgbe_ecc_isr_task(unsigned long data)
 408 {
 409         struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
 410         unsigned int ecc_isr;
 411         bool stop = false;
 412
 413         /* Mask status with only the interrupts we care about */
 414         ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
 415         ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
 416         netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
 417
 418         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
 419                 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
 420                                      &pdata->tx_ded_count, "TX fifo");
 421         }
 422
 423         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
 424                 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
 425                                      &pdata->rx_ded_count, "RX fifo");
 426         }
 427
 428         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
 429                 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
 430                                      &pdata->desc_ded_count,
 431                                      "descriptor cache");
 432         }
 433
 434         if (stop) {
 435                 pdata->hw_if.disable_ecc_ded(pdata);
 436                 schedule_work(&pdata->stopdev_work);
 437                 goto out;
 438         }
 439
 440         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
 441                 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
 442                                  &pdata->tx_sec_count, "TX fifo"))
 443                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
 444         }
 445
 446         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
 447                 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
 448                                  &pdata->rx_sec_count, "RX fifo"))
 449                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
 450
 451         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
 452                 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
 453                                  &pdata->desc_sec_count, "descriptor cache"))
 454                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
 455
 456 out:
 457         /* Clear all ECC interrupts */
 458         XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
 459
 460         /* Reissue interrupt if status is not clear */
 461         if (pdata->vdata->irq_reissue_support)
 462                 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
 463 }
 464
 465 static irqreturn_t xgbe_ecc_isr(int irq, void *data)
 466 {
 467         struct xgbe_prv_data *pdata = data;
 468
 469         if (pdata->isr_as_tasklet)
 470                 tasklet_schedule(&pdata->tasklet_ecc);
 471         else
 472                 xgbe_ecc_isr_task((unsigned long)pdata);
 473
 474         return IRQ_HANDLED;
 475 }
 476
 477 static void xgbe_isr_task(unsigned long data)
 478 {
 479         struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
 480         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 481         struct xgbe_channel *channel;
 482         unsigned int dma_isr, dma_ch_isr;
 483         unsigned int mac_isr, mac_tssr, mac_mdioisr;
 484         unsigned int i;
 485
 486         /* The DMA interrupt status register also reports MAC and MTL
 487          * interrupts. So for polling mode, we just need to check for
 488          * this register to be non-zero
 489          */
 490         dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
 491         if (!dma_isr)
 492                 goto isr_done;
 493
 494         netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
 495
 496         for (i = 0; i < pdata->channel_count; i++) {
 497                 if (!(dma_isr & (1 << i)))
 498                         continue;
 499
 500                 channel = pdata->channel[i];
 501
 502                 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
 503                 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
 504                           i, dma_ch_isr);
 505
 506                 /* The TI or RI interrupt bits may still be set even if using
 507                  * per channel DMA interrupts. Check to be sure those are not
 508                  * enabled before using the private data napi structure.
 509                  */
 510                 if (!pdata->per_channel_irq &&
 511                     (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
 512                      XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
 513                         if (napi_schedule_prep(&pdata->napi)) {
 514                                 /* Disable Tx and Rx interrupts */
 515                                 xgbe_disable_rx_tx_ints(pdata);
 516
 517                                 /* Turn on polling */
 518                                 __napi_schedule(&pdata->napi);
 519                         }
 520                 } else {
 521                         /* Don't clear Rx/Tx status if doing per channel DMA
 522                          * interrupts, these will be cleared by the ISR for
 523                          * per channel DMA interrupts.
 524                          */
 525                         XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
 526                         XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
 527                 }
 528
 529                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
 530                         pdata->ext_stats.rx_buffer_unavailable++;
 531
 532                 /* Restart the device on a Fatal Bus Error */
 533                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
 534                         schedule_work(&pdata->restart_work);
 535
 536                 /* Clear interrupt signals */
 537                 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
 538         }
 539
 540         if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
 541                 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
 542
 543                 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
 544                           mac_isr);
 545
 546                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
 547                         hw_if->tx_mmc_int(pdata);
 548
 549                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
 550                         hw_if->rx_mmc_int(pdata);
 551
 552                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
 553                         mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
 554
 555                         netif_dbg(pdata, intr, pdata->netdev,
 556                                   "MAC_TSSR=%#010x\n", mac_tssr);
 557
 558                         if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
 559                                 /* Read Tx Timestamp to clear interrupt */
 560                                 pdata->tx_tstamp =
 561                                         hw_if->get_tx_tstamp(pdata);
 562                                 queue_work(pdata->dev_workqueue,
 563                                            &pdata->tx_tstamp_work);
 564                         }
 565                 }
 566
 567                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
 568                         mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
 569
 570                         netif_dbg(pdata, intr, pdata->netdev,
 571                                   "MAC_MDIOISR=%#010x\n", mac_mdioisr);
 572
 573                         if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
 574                                            SNGLCOMPINT))
 575                                 complete(&pdata->mdio_complete);
 576                 }
 577         }
 578
 579 isr_done:
 580         /* If there is not a separate AN irq, handle it here */
 581         if (pdata->dev_irq == pdata->an_irq)
 582                 pdata->phy_if.an_isr(pdata);
 583
 584         /* If there is not a separate ECC irq, handle it here */
 585         if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
 586                 xgbe_ecc_isr_task((unsigned long)pdata);
 587
 588         /* If there is not a separate I2C irq, handle it here */
 589         if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
 590                 pdata->i2c_if.i2c_isr(pdata);
 591
 592         /* Reissue interrupt if status is not clear */
 593         if (pdata->vdata->irq_reissue_support) {
 594                 unsigned int reissue_mask;
 595
 596                 reissue_mask = 1 << 0;
 597                 if (!pdata->per_channel_irq)
 598                         reissue_mask |= 0xffff << 4;
 599
 600                 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
 601         }
 602 }
 603
 604 static irqreturn_t xgbe_isr(int irq, void *data)
 605 {
 606         struct xgbe_prv_data *pdata = data;
 607
 608         if (pdata->isr_as_tasklet)
 609                 tasklet_schedule(&pdata->tasklet_dev);
 610         else
 611                 xgbe_isr_task((unsigned long)pdata);
 612
 613         return IRQ_HANDLED;
 614 }
 615
 616 static irqreturn_t xgbe_dma_isr(int irq, void *data)
 617 {
 618         struct xgbe_channel *channel = data;
 619         struct xgbe_prv_data *pdata = channel->pdata;
 620         unsigned int dma_status;
 621
 622         /* Per channel DMA interrupts are enabled, so we use the per
 623          * channel napi structure and not the private data napi structure
 624          */
 625         if (napi_schedule_prep(&channel->napi)) {
 626                 /* Disable Tx and Rx interrupts */
 627                 if (pdata->channel_irq_mode)
 628                         xgbe_disable_rx_tx_int(pdata, channel);
 629                 else
 630                         disable_irq_nosync(channel->dma_irq);
 631
 632                 /* Turn on polling */
 633                 __napi_schedule_irqoff(&channel->napi);
 634         }
 635
 636         /* Clear Tx/Rx signals */
 637         dma_status = 0;
 638         XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
 639         XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
 640         XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
 641
 642         return IRQ_HANDLED;
 643 }
 644
 645 static void xgbe_tx_timer(struct timer_list *t)
 646 {
 647         struct xgbe_channel *channel = from_timer(channel, t, tx_timer);
 648         struct xgbe_prv_data *pdata = channel->pdata;
 649         struct napi_struct *napi;
 650
 651         DBGPR("-->xgbe_tx_timer\n");
 652
 653         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
 654
 655         if (napi_schedule_prep(napi)) {
 656                 /* Disable Tx and Rx interrupts */
 657                 if (pdata->per_channel_irq)
 658                         if (pdata->channel_irq_mode)
 659                                 xgbe_disable_rx_tx_int(pdata, channel);
 660                         else
 661                                 disable_irq_nosync(channel->dma_irq);
 662                 else
 663                         xgbe_disable_rx_tx_ints(pdata);
 664
 665                 /* Turn on polling */
 666                 __napi_schedule(napi);
 667         }
 668
 669         channel->tx_timer_active = 0;
 670
 671         DBGPR("<--xgbe_tx_timer\n");
 672 }
 673
 674 static void xgbe_service(struct work_struct *work)
 675 {
 676         struct xgbe_prv_data *pdata = container_of(work,
 677                                                    struct xgbe_prv_data,
 678                                                    service_work);
 679
 680         pdata->phy_if.phy_status(pdata);
 681 }
 682
 683 static void xgbe_service_timer(struct timer_list *t)
 684 {
 685         struct xgbe_prv_data *pdata = from_timer(pdata, t, service_timer);
 686
 687         queue_work(pdata->dev_workqueue, &pdata->service_work);
 688
 689         mod_timer(&pdata->service_timer, jiffies + HZ);
 690 }
 691
 692 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
 693 {
 694         struct xgbe_channel *channel;
 695         unsigned int i;
 696
 697         timer_setup(&pdata->service_timer, xgbe_service_timer, 0);
 698
 699         for (i = 0; i < pdata->channel_count; i++) {
 700                 channel = pdata->channel[i];
 701                 if (!channel->tx_ring)
 702                         break;
 703
 704                 timer_setup(&channel->tx_timer, xgbe_tx_timer, 0);
 705         }
 706 }
 707
 708 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
 709 {
 710         mod_timer(&pdata->service_timer, jiffies + HZ);
 711 }
 712
 713 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
 714 {
 715         struct xgbe_channel *channel;
 716         unsigned int i;
 717
 718         del_timer_sync(&pdata->service_timer);
 719
 720         for (i = 0; i < pdata->channel_count; i++) {
 721                 channel = pdata->channel[i];
 722                 if (!channel->tx_ring)
 723                         break;
 724
 725                 /* Deactivate the Tx timer */
 726                 del_timer_sync(&channel->tx_timer);
 727                 channel->tx_timer_active = 0;
 728         }
 729 }
 730
 731 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
 732 {
 733         unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
 734         struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
 735
 736         mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
 737         mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
 738         mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
 739
 740         memset(hw_feat, 0, sizeof(*hw_feat));
 741
 742         hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
 743
 744         /* Hardware feature register 0 */
 745         hw_feat->gmii        = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
 746         hw_feat->vlhash      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
 747         hw_feat->sma         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
 748         hw_feat->rwk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
 749         hw_feat->mgk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
 750         hw_feat->mmc         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
 751         hw_feat->aoe         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
 752         hw_feat->ts          = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
 753         hw_feat->eee         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
 754         hw_feat->tx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
 755         hw_feat->rx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
 756         hw_feat->addn_mac    = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
 757                                               ADDMACADRSEL);
 758         hw_feat->ts_src      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
 759         hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
 760         hw_feat->vxn         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
 761
 762         /* Hardware feature register 1 */
 763         hw_feat->rx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 764                                                 RXFIFOSIZE);
 765         hw_feat->tx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 766                                                 TXFIFOSIZE);
 767         hw_feat->adv_ts_hi     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
 768         hw_feat->dma_width     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
 769         hw_feat->dcb           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
 770         hw_feat->sph           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
 771         hw_feat->tso           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
 772         hw_feat->dma_debug     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
 773         hw_feat->rss           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
 774         hw_feat->tc_cnt        = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
 775         hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 776                                                   HASHTBLSZ);
 777         hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 778                                                   L3L4FNUM);
 779
 780         /* Hardware feature register 2 */
 781         hw_feat->rx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
 782         hw_feat->tx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
 783         hw_feat->rx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
 784         hw_feat->tx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
 785         hw_feat->pps_out_num  = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
 786         hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
 787
 788         /* Translate the Hash Table size into actual number */
 789         switch (hw_feat->hash_table_size) {
 790         case 0:
 791                 break;
 792         case 1:
 793                 hw_feat->hash_table_size = 64;
 794                 break;
 795         case 2:
 796                 hw_feat->hash_table_size = 128;
 797                 break;
 798         case 3:
 799                 hw_feat->hash_table_size = 256;
 800                 break;
 801         }
 802
 803         /* Translate the address width setting into actual number */
 804         switch (hw_feat->dma_width) {
 805         case 0:
 806                 hw_feat->dma_width = 32;
 807                 break;
 808         case 1:
 809                 hw_feat->dma_width = 40;
 810                 break;
 811         case 2:
 812                 hw_feat->dma_width = 48;
 813                 break;
 814         default:
 815                 hw_feat->dma_width = 32;
 816         }
 817
 818         /* The Queue, Channel and TC counts are zero based so increment them
 819          * to get the actual number
 820          */
 821         hw_feat->rx_q_cnt++;
 822         hw_feat->tx_q_cnt++;
 823         hw_feat->rx_ch_cnt++;
 824         hw_feat->tx_ch_cnt++;
 825         hw_feat->tc_cnt++;
 826
 827         /* Translate the fifo sizes into actual numbers */
 828         hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
 829         hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
 830
 831         if (netif_msg_probe(pdata)) {
 832                 dev_dbg(pdata->dev, "Hardware features:\n");
 833
 834                 /* Hardware feature register 0 */
 835                 dev_dbg(pdata->dev, "  1GbE support              : %s\n",
 836                         hw_feat->gmii ? "yes" : "no");
 837                 dev_dbg(pdata->dev, "  VLAN hash filter          : %s\n",
 838                         hw_feat->vlhash ? "yes" : "no");
 839                 dev_dbg(pdata->dev, "  MDIO interface            : %s\n",
 840                         hw_feat->sma ? "yes" : "no");
 841                 dev_dbg(pdata->dev, "  Wake-up packet support    : %s\n",
 842                         hw_feat->rwk ? "yes" : "no");
 843                 dev_dbg(pdata->dev, "  Magic packet support      : %s\n",
 844                         hw_feat->mgk ? "yes" : "no");
 845                 dev_dbg(pdata->dev, "  Management counters       : %s\n",
 846                         hw_feat->mmc ? "yes" : "no");
 847                 dev_dbg(pdata->dev, "  ARP offload               : %s\n",
 848                         hw_feat->aoe ? "yes" : "no");
 849                 dev_dbg(pdata->dev, "  IEEE 1588-2008 Timestamp  : %s\n",
 850                         hw_feat->ts ? "yes" : "no");
 851                 dev_dbg(pdata->dev, "  Energy Efficient Ethernet : %s\n",
 852                         hw_feat->eee ? "yes" : "no");
 853                 dev_dbg(pdata->dev, "  TX checksum offload       : %s\n",
 854                         hw_feat->tx_coe ? "yes" : "no");
 855                 dev_dbg(pdata->dev, "  RX checksum offload       : %s\n",
 856                         hw_feat->rx_coe ? "yes" : "no");
 857                 dev_dbg(pdata->dev, "  Additional MAC addresses  : %u\n",
 858                         hw_feat->addn_mac);
 859                 dev_dbg(pdata->dev, "  Timestamp source          : %s\n",
 860                         (hw_feat->ts_src == 1) ? "internal" :
 861                         (hw_feat->ts_src == 2) ? "external" :
 862                         (hw_feat->ts_src == 3) ? "internal/external" : "n/a");
 863                 dev_dbg(pdata->dev, "  SA/VLAN insertion         : %s\n",
 864                         hw_feat->sa_vlan_ins ? "yes" : "no");
 865                 dev_dbg(pdata->dev, "  VXLAN/NVGRE support       : %s\n",
 866                         hw_feat->vxn ? "yes" : "no");
 867
 868                 /* Hardware feature register 1 */
 869                 dev_dbg(pdata->dev, "  RX fifo size              : %u\n",
 870                         hw_feat->rx_fifo_size);
 871                 dev_dbg(pdata->dev, "  TX fifo size              : %u\n",
 872                         hw_feat->tx_fifo_size);
 873                 dev_dbg(pdata->dev, "  IEEE 1588 high word       : %s\n",
 874                         hw_feat->adv_ts_hi ? "yes" : "no");
 875                 dev_dbg(pdata->dev, "  DMA width                 : %u\n",
 876                         hw_feat->dma_width);
 877                 dev_dbg(pdata->dev, "  Data Center Bridging      : %s\n",
 878                         hw_feat->dcb ? "yes" : "no");
 879                 dev_dbg(pdata->dev, "  Split header              : %s\n",
 880                         hw_feat->sph ? "yes" : "no");
 881                 dev_dbg(pdata->dev, "  TCP Segmentation Offload  : %s\n",
 882                         hw_feat->tso ? "yes" : "no");
 883                 dev_dbg(pdata->dev, "  Debug memory interface    : %s\n",
 884                         hw_feat->dma_debug ? "yes" : "no");
 885                 dev_dbg(pdata->dev, "  Receive Side Scaling      : %s\n",
 886                         hw_feat->rss ? "yes" : "no");
 887                 dev_dbg(pdata->dev, "  Traffic Class count       : %u\n",
 888                         hw_feat->tc_cnt);
 889                 dev_dbg(pdata->dev, "  Hash table size           : %u\n",
 890                         hw_feat->hash_table_size);
 891                 dev_dbg(pdata->dev, "  L3/L4 Filters             : %u\n",
 892                         hw_feat->l3l4_filter_num);
 893
 894                 /* Hardware feature register 2 */
 895                 dev_dbg(pdata->dev, "  RX queue count            : %u\n",
 896                         hw_feat->rx_q_cnt);
 897                 dev_dbg(pdata->dev, "  TX queue count            : %u\n",
 898                         hw_feat->tx_q_cnt);
 899                 dev_dbg(pdata->dev, "  RX DMA channel count      : %u\n",
 900                         hw_feat->rx_ch_cnt);
 901                 dev_dbg(pdata->dev, "  TX DMA channel count      : %u\n",
 902                         hw_feat->rx_ch_cnt);
 903                 dev_dbg(pdata->dev, "  PPS outputs               : %u\n",
 904                         hw_feat->pps_out_num);
 905                 dev_dbg(pdata->dev, "  Auxiliary snapshot inputs : %u\n",
 906                         hw_feat->aux_snap_num);
 907         }
 908 }
 909
 910 static void xgbe_disable_vxlan_offloads(struct xgbe_prv_data *pdata)
 911 {
 912         struct net_device *netdev = pdata->netdev;
 913
 914         if (!pdata->vxlan_offloads_set)
 915                 return;
 916
 917         netdev_info(netdev, "disabling VXLAN offloads\n");
 918
 919         netdev->hw_enc_features &= ~(NETIF_F_SG |
 920                                      NETIF_F_IP_CSUM |
 921                                      NETIF_F_IPV6_CSUM |
 922                                      NETIF_F_RXCSUM |
 923                                      NETIF_F_TSO |
 924                                      NETIF_F_TSO6 |
 925                                      NETIF_F_GRO |
 926                                      NETIF_F_GSO_UDP_TUNNEL |
 927                                      NETIF_F_GSO_UDP_TUNNEL_CSUM);
 928
 929         netdev->features &= ~(NETIF_F_GSO_UDP_TUNNEL |
 930                               NETIF_F_GSO_UDP_TUNNEL_CSUM);
 931
 932         pdata->vxlan_offloads_set = 0;
 933 }
 934
 935 static void xgbe_disable_vxlan_hw(struct xgbe_prv_data *pdata)
 936 {
 937         if (!pdata->vxlan_port_set)
 938                 return;
 939
 940         pdata->hw_if.disable_vxlan(pdata);
 941
 942         pdata->vxlan_port_set = 0;
 943         pdata->vxlan_port = 0;
 944 }
 945
 946 static void xgbe_disable_vxlan_accel(struct xgbe_prv_data *pdata)
 947 {
 948         xgbe_disable_vxlan_offloads(pdata);
 949
 950         xgbe_disable_vxlan_hw(pdata);
 951 }
 952
 953 static void xgbe_enable_vxlan_offloads(struct xgbe_prv_data *pdata)
 954 {
 955         struct net_device *netdev = pdata->netdev;
 956
 957         if (pdata->vxlan_offloads_set)
 958                 return;
 959
 960         netdev_info(netdev, "enabling VXLAN offloads\n");
 961
 962         netdev->hw_enc_features |= NETIF_F_SG |
 963                                    NETIF_F_IP_CSUM |
 964                                    NETIF_F_IPV6_CSUM |
 965                                    NETIF_F_RXCSUM |
 966                                    NETIF_F_TSO |
 967                                    NETIF_F_TSO6 |
 968                                    NETIF_F_GRO |
 969                                    pdata->vxlan_features;
 970
 971         netdev->features |= pdata->vxlan_features;
 972
 973         pdata->vxlan_offloads_set = 1;
 974 }
 975
 976 static void xgbe_enable_vxlan_hw(struct xgbe_prv_data *pdata)
 977 {
 978         struct xgbe_vxlan_data *vdata;
 979
 980         if (pdata->vxlan_port_set)
 981                 return;
 982
 983         if (list_empty(&pdata->vxlan_ports))
 984                 return;
 985
 986         vdata = list_first_entry(&pdata->vxlan_ports,
 987                                  struct xgbe_vxlan_data, list);
 988
 989         pdata->vxlan_port_set = 1;
 990         pdata->vxlan_port = be16_to_cpu(vdata->port);
 991
 992         pdata->hw_if.enable_vxlan(pdata);
 993 }
 994
 995 static void xgbe_enable_vxlan_accel(struct xgbe_prv_data *pdata)
 996 {
 997         /* VXLAN acceleration desired? */
 998         if (!pdata->vxlan_features)
 999                 return;
1000
1001         /* VXLAN acceleration possible? */
1002         if (pdata->vxlan_force_disable)
1003                 return;
1004
1005         xgbe_enable_vxlan_hw(pdata);
1006
1007         xgbe_enable_vxlan_offloads(pdata);
1008 }
1009
1010 static void xgbe_reset_vxlan_accel(struct xgbe_prv_data *pdata)
1011 {
1012         xgbe_disable_vxlan_hw(pdata);
1013
1014         if (pdata->vxlan_features)
1015                 xgbe_enable_vxlan_offloads(pdata);
1016
1017         pdata->vxlan_force_disable = 0;
1018 }
1019
1020 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
1021 {
1022         struct xgbe_channel *channel;
1023         unsigned int i;
1024
1025         if (pdata->per_channel_irq) {
1026                 for (i = 0; i < pdata->channel_count; i++) {
1027                         channel = pdata->channel[i];
1028                         if (add)
1029                                 netif_napi_add(pdata->netdev, &channel->napi,
1030                                                xgbe_one_poll, NAPI_POLL_WEIGHT);
1031
1032                         napi_enable(&channel->napi);
1033                 }
1034         } else {
1035                 if (add)
1036                         netif_napi_add(pdata->netdev, &pdata->napi,
1037                                        xgbe_all_poll, NAPI_POLL_WEIGHT);
1038
1039                 napi_enable(&pdata->napi);
1040         }
1041 }
1042
1043 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
1044 {
1045         struct xgbe_channel *channel;
1046         unsigned int i;
1047
1048         if (pdata->per_channel_irq) {
1049                 for (i = 0; i < pdata->channel_count; i++) {
1050                         channel = pdata->channel[i];
1051                         napi_disable(&channel->napi);
1052
1053                         if (del)
1054                                 netif_napi_del(&channel->napi);
1055                 }
1056         } else {
1057                 napi_disable(&pdata->napi);
1058
1059                 if (del)
1060                         netif_napi_del(&pdata->napi);
1061         }
1062 }
1063
1064 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
1065 {
1066         struct xgbe_channel *channel;
1067         struct net_device *netdev = pdata->netdev;
1068         unsigned int i;
1069         int ret;
1070
1071         tasklet_init(&pdata->tasklet_dev, xgbe_isr_task, (unsigned long)pdata);
1072         tasklet_init(&pdata->tasklet_ecc, xgbe_ecc_isr_task,
1073                      (unsigned long)pdata);
1074
1075         ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
1076                                netdev_name(netdev), pdata);
1077         if (ret) {
1078                 netdev_alert(netdev, "error requesting irq %d\n",
1079                              pdata->dev_irq);
1080                 return ret;
1081         }
1082
1083         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
1084                 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
1085                                        0, pdata->ecc_name, pdata);
1086                 if (ret) {
1087                         netdev_alert(netdev, "error requesting ecc irq %d\n",
1088                                      pdata->ecc_irq);
1089                         goto err_dev_irq;
1090                 }
1091         }
1092
1093         if (!pdata->per_channel_irq)
1094                 return 0;
1095
1096         for (i = 0; i < pdata->channel_count; i++) {
1097                 channel = pdata->channel[i];
1098                 snprintf(channel->dma_irq_name,
1099                          sizeof(channel->dma_irq_name) - 1,
1100                          "%s-TxRx-%u", netdev_name(netdev),
1101                          channel->queue_index);
1102
1103                 ret = devm_request_irq(pdata->dev, channel->dma_irq,
1104                                        xgbe_dma_isr, 0,
1105                                        channel->dma_irq_name, channel);
1106                 if (ret) {
1107                         netdev_alert(netdev, "error requesting irq %d\n",
1108                                      channel->dma_irq);
1109                         goto err_dma_irq;
1110                 }
1111
1112                 irq_set_affinity_hint(channel->dma_irq,
1113                                       &channel->affinity_mask);
1114         }
1115
1116         return 0;
1117
1118 err_dma_irq:
1119         /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1120         for (i--; i < pdata->channel_count; i--) {
1121                 channel = pdata->channel[i];
1122
1123                 irq_set_affinity_hint(channel->dma_irq, NULL);
1124                 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1125         }
1126
1127         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1128                 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1129
1130 err_dev_irq:
1131         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1132
1133         return ret;
1134 }
1135
1136 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
1137 {
1138         struct xgbe_channel *channel;
1139         unsigned int i;
1140
1141         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1142
1143         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1144                 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1145
1146         if (!pdata->per_channel_irq)
1147                 return;
1148
1149         for (i = 0; i < pdata->channel_count; i++) {
1150                 channel = pdata->channel[i];
1151
1152                 irq_set_affinity_hint(channel->dma_irq, NULL);
1153                 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1154         }
1155 }
1156
1157 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
1158 {
1159         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1160
1161         DBGPR("-->xgbe_init_tx_coalesce\n");
1162
1163         pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
1164         pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
1165
1166         hw_if->config_tx_coalesce(pdata);
1167
1168         DBGPR("<--xgbe_init_tx_coalesce\n");
1169 }
1170
1171 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1172 {
1173         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1174
1175         DBGPR("-->xgbe_init_rx_coalesce\n");
1176
1177         pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
1178         pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
1179         pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1180
1181         hw_if->config_rx_coalesce(pdata);
1182
1183         DBGPR("<--xgbe_init_rx_coalesce\n");
1184 }
1185
1186 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
1187 {
1188         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1189         struct xgbe_ring *ring;
1190         struct xgbe_ring_data *rdata;
1191         unsigned int i, j;
1192
1193         DBGPR("-->xgbe_free_tx_data\n");
1194
1195         for (i = 0; i < pdata->channel_count; i++) {
1196                 ring = pdata->channel[i]->tx_ring;
1197                 if (!ring)
1198                         break;
1199
1200                 for (j = 0; j < ring->rdesc_count; j++) {
1201                         rdata = XGBE_GET_DESC_DATA(ring, j);
1202                         desc_if->unmap_rdata(pdata, rdata);
1203                 }
1204         }
1205
1206         DBGPR("<--xgbe_free_tx_data\n");
1207 }
1208
1209 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
1210 {
1211         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1212         struct xgbe_ring *ring;
1213         struct xgbe_ring_data *rdata;
1214         unsigned int i, j;
1215
1216         DBGPR("-->xgbe_free_rx_data\n");
1217
1218         for (i = 0; i < pdata->channel_count; i++) {
1219                 ring = pdata->channel[i]->rx_ring;
1220                 if (!ring)
1221                         break;
1222
1223                 for (j = 0; j < ring->rdesc_count; j++) {
1224                         rdata = XGBE_GET_DESC_DATA(ring, j);
1225                         desc_if->unmap_rdata(pdata, rdata);
1226                 }
1227         }
1228
1229         DBGPR("<--xgbe_free_rx_data\n");
1230 }
1231
1232 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1233 {
1234         pdata->phy_link = -1;
1235         pdata->phy_speed = SPEED_UNKNOWN;
1236
1237         return pdata->phy_if.phy_reset(pdata);
1238 }
1239
1240 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
1241 {
1242         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1243         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1244         unsigned long flags;
1245
1246         DBGPR("-->xgbe_powerdown\n");
1247
1248         if (!netif_running(netdev) ||
1249             (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
1250                 netdev_alert(netdev, "Device is already powered down\n");
1251                 DBGPR("<--xgbe_powerdown\n");
1252                 return -EINVAL;
1253         }
1254
1255         spin_lock_irqsave(&pdata->lock, flags);
1256
1257         if (caller == XGMAC_DRIVER_CONTEXT)
1258                 netif_device_detach(netdev);
1259
1260         netif_tx_stop_all_queues(netdev);
1261
1262         xgbe_stop_timers(pdata);
1263         flush_workqueue(pdata->dev_workqueue);
1264
1265         hw_if->powerdown_tx(pdata);
1266         hw_if->powerdown_rx(pdata);
1267
1268         xgbe_napi_disable(pdata, 0);
1269
1270         pdata->power_down = 1;
1271
1272         spin_unlock_irqrestore(&pdata->lock, flags);
1273
1274         DBGPR("<--xgbe_powerdown\n");
1275
1276         return 0;
1277 }
1278
1279 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
1280 {
1281         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1282         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1283         unsigned long flags;
1284
1285         DBGPR("-->xgbe_powerup\n");
1286
1287         if (!netif_running(netdev) ||
1288             (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
1289                 netdev_alert(netdev, "Device is already powered up\n");
1290                 DBGPR("<--xgbe_powerup\n");
1291                 return -EINVAL;
1292         }
1293
1294         spin_lock_irqsave(&pdata->lock, flags);
1295
1296         pdata->power_down = 0;
1297
1298         xgbe_napi_enable(pdata, 0);
1299
1300         hw_if->powerup_tx(pdata);
1301         hw_if->powerup_rx(pdata);
1302
1303         if (caller == XGMAC_DRIVER_CONTEXT)
1304                 netif_device_attach(netdev);
1305
1306         netif_tx_start_all_queues(netdev);
1307
1308         xgbe_start_timers(pdata);
1309
1310         spin_unlock_irqrestore(&pdata->lock, flags);
1311
1312         DBGPR("<--xgbe_powerup\n");
1313
1314         return 0;
1315 }
1316
1317 static void xgbe_free_memory(struct xgbe_prv_data *pdata)
1318 {
1319         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1320
1321         /* Free the ring descriptors and buffers */
1322         desc_if->free_ring_resources(pdata);
1323
1324         /* Free the channel and ring structures */
1325         xgbe_free_channels(pdata);
1326 }
1327
1328 static int xgbe_alloc_memory(struct xgbe_prv_data *pdata)
1329 {
1330         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1331         struct net_device *netdev = pdata->netdev;
1332         int ret;
1333
1334         if (pdata->new_tx_ring_count) {
1335                 pdata->tx_ring_count = pdata->new_tx_ring_count;
1336                 pdata->tx_q_count = pdata->tx_ring_count;
1337                 pdata->new_tx_ring_count = 0;
1338         }
1339
1340         if (pdata->new_rx_ring_count) {
1341                 pdata->rx_ring_count = pdata->new_rx_ring_count;
1342                 pdata->new_rx_ring_count = 0;
1343         }
1344
1345         /* Calculate the Rx buffer size before allocating rings */
1346         pdata->rx_buf_size = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1347
1348         /* Allocate the channel and ring structures */
1349         ret = xgbe_alloc_channels(pdata);
1350         if (ret)
1351                 return ret;
1352
1353         /* Allocate the ring descriptors and buffers */
1354         ret = desc_if->alloc_ring_resources(pdata);
1355         if (ret)
1356                 goto err_channels;
1357
1358         /* Initialize the service and Tx timers */
1359         xgbe_init_timers(pdata);
1360
1361         return 0;
1362
1363 err_channels:
1364         xgbe_free_memory(pdata);
1365
1366         return ret;
1367 }
1368
1369 static int xgbe_start(struct xgbe_prv_data *pdata)
1370 {
1371         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1372         struct xgbe_phy_if *phy_if = &pdata->phy_if;
1373         struct net_device *netdev = pdata->netdev;
1374         unsigned int i;
1375         int ret;
1376
1377         /* Set the number of queues */
1378         ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
1379         if (ret) {
1380                 netdev_err(netdev, "error setting real tx queue count\n");
1381                 return ret;
1382         }
1383
1384         ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
1385         if (ret) {
1386                 netdev_err(netdev, "error setting real rx queue count\n");
1387                 return ret;
1388         }
1389
1390         /* Set RSS lookup table data for programming */
1391         for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1392                 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1393                                i % pdata->rx_ring_count);
1394
1395         ret = hw_if->init(pdata);
1396         if (ret)
1397                 return ret;
1398
1399         xgbe_napi_enable(pdata, 1);
1400
1401         ret = xgbe_request_irqs(pdata);
1402         if (ret)
1403                 goto err_napi;
1404
1405         ret = phy_if->phy_start(pdata);
1406         if (ret)
1407                 goto err_irqs;
1408
1409         hw_if->enable_tx(pdata);
1410         hw_if->enable_rx(pdata);
1411
1412         udp_tunnel_get_rx_info(netdev);
1413
1414         netif_tx_start_all_queues(netdev);
1415
1416         xgbe_start_timers(pdata);
1417         queue_work(pdata->dev_workqueue, &pdata->service_work);
1418
1419         clear_bit(XGBE_STOPPED, &pdata->dev_state);
1420
1421         return 0;
1422
1423 err_irqs:
1424         xgbe_free_irqs(pdata);
1425
1426 err_napi:
1427         xgbe_napi_disable(pdata, 1);
1428
1429         hw_if->exit(pdata);
1430
1431         return ret;
1432 }
1433
1434 static void xgbe_stop(struct xgbe_prv_data *pdata)
1435 {
1436         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1437         struct xgbe_phy_if *phy_if = &pdata->phy_if;
1438         struct xgbe_channel *channel;
1439         struct net_device *netdev = pdata->netdev;
1440         struct netdev_queue *txq;
1441         unsigned int i;
1442
1443         DBGPR("-->xgbe_stop\n");
1444
1445         if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1446                 return;
1447
1448         netif_tx_stop_all_queues(netdev);
1449         netif_carrier_off(pdata->netdev);
1450
1451         xgbe_stop_timers(pdata);
1452         flush_workqueue(pdata->dev_workqueue);
1453
1454         xgbe_reset_vxlan_accel(pdata);
1455
1456         hw_if->disable_tx(pdata);
1457         hw_if->disable_rx(pdata);
1458
1459         phy_if->phy_stop(pdata);
1460
1461         xgbe_free_irqs(pdata);
1462
1463         xgbe_napi_disable(pdata, 1);
1464
1465         hw_if->exit(pdata);
1466
1467         for (i = 0; i < pdata->channel_count; i++) {
1468                 channel = pdata->channel[i];
1469                 if (!channel->tx_ring)
1470                         continue;
1471
1472                 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1473                 netdev_tx_reset_queue(txq);
1474         }
1475
1476         set_bit(XGBE_STOPPED, &pdata->dev_state);
1477
1478         DBGPR("<--xgbe_stop\n");
1479 }
1480
1481 static void xgbe_stopdev(struct work_struct *work)
1482 {
1483         struct xgbe_prv_data *pdata = container_of(work,
1484                                                    struct xgbe_prv_data,
1485                                                    stopdev_work);
1486
1487         rtnl_lock();
1488
1489         xgbe_stop(pdata);
1490
1491         xgbe_free_tx_data(pdata);
1492         xgbe_free_rx_data(pdata);
1493
1494         rtnl_unlock();
1495
1496         netdev_alert(pdata->netdev, "device stopped\n");
1497 }
1498
1499 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata)
1500 {
1501         /* If not running, "restart" will happen on open */
1502         if (!netif_running(pdata->netdev))
1503                 return;
1504
1505         xgbe_stop(pdata);
1506
1507         xgbe_free_memory(pdata);
1508         xgbe_alloc_memory(pdata);
1509
1510         xgbe_start(pdata);
1511 }
1512
1513 void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1514 {
1515         /* If not running, "restart" will happen on open */
1516         if (!netif_running(pdata->netdev))
1517                 return;
1518
1519         xgbe_stop(pdata);
1520
1521         xgbe_free_tx_data(pdata);
1522         xgbe_free_rx_data(pdata);
1523
1524         xgbe_start(pdata);
1525 }
1526
1527 static void xgbe_restart(struct work_struct *work)
1528 {
1529         struct xgbe_prv_data *pdata = container_of(work,
1530                                                    struct xgbe_prv_data,
1531                                                    restart_work);
1532
1533         rtnl_lock();
1534
1535         xgbe_restart_dev(pdata);
1536
1537         rtnl_unlock();
1538 }
1539
1540 static void xgbe_tx_tstamp(struct work_struct *work)
1541 {
1542         struct xgbe_prv_data *pdata = container_of(work,
1543                                                    struct xgbe_prv_data,
1544                                                    tx_tstamp_work);
1545         struct skb_shared_hwtstamps hwtstamps;
1546         u64 nsec;
1547         unsigned long flags;
1548
1549         spin_lock_irqsave(&pdata->tstamp_lock, flags);
1550         if (!pdata->tx_tstamp_skb)
1551                 goto unlock;
1552
1553         if (pdata->tx_tstamp) {
1554                 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1555                                             pdata->tx_tstamp);
1556
1557                 memset(&hwtstamps, 0, sizeof(hwtstamps));
1558                 hwtstamps.hwtstamp = ns_to_ktime(nsec);
1559                 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1560         }
1561
1562         dev_kfree_skb_any(pdata->tx_tstamp_skb);
1563
1564         pdata->tx_tstamp_skb = NULL;
1565
1566 unlock:
1567         spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1568 }
1569
1570 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1571                                       struct ifreq *ifreq)
1572 {
1573         if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1574                          sizeof(pdata->tstamp_config)))
1575                 return -EFAULT;
1576
1577         return 0;
1578 }
1579
1580 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1581                                       struct ifreq *ifreq)
1582 {
1583         struct hwtstamp_config config;
1584         unsigned int mac_tscr;
1585
1586         if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1587                 return -EFAULT;
1588
1589         if (config.flags)
1590                 return -EINVAL;
1591
1592         mac_tscr = 0;
1593
1594         switch (config.tx_type) {
1595         case HWTSTAMP_TX_OFF:
1596                 break;
1597
1598         case HWTSTAMP_TX_ON:
1599                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1600                 break;
1601
1602         default:
1603                 return -ERANGE;
1604         }
1605
1606         switch (config.rx_filter) {
1607         case HWTSTAMP_FILTER_NONE:
1608                 break;
1609
1610         case HWTSTAMP_FILTER_NTP_ALL:
1611         case HWTSTAMP_FILTER_ALL:
1612                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1613                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1614                 break;
1615
1616         /* PTP v2, UDP, any kind of event packet */
1617         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1618                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1619         /* PTP v1, UDP, any kind of event packet */
1620         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1621                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1622                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1623                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1624                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1625                 break;
1626
1627         /* PTP v2, UDP, Sync packet */
1628         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1629                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1630         /* PTP v1, UDP, Sync packet */
1631         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1632                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1633                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1634                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1635                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1636                 break;
1637
1638         /* PTP v2, UDP, Delay_req packet */
1639         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1640                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1641         /* PTP v1, UDP, Delay_req packet */
1642         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1643                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1644                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1645                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1646                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1647                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1648                 break;
1649
1650         /* 802.AS1, Ethernet, any kind of event packet */
1651         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1652                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1653                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1654                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1655                 break;
1656
1657         /* 802.AS1, Ethernet, Sync packet */
1658         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1659                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1660                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1661                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1662                 break;
1663
1664         /* 802.AS1, Ethernet, Delay_req packet */
1665         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1666                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1667                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1668                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1669                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1670                 break;
1671
1672         /* PTP v2/802.AS1, any layer, any kind of event packet */
1673         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1674                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1675                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1676                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1677                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1678                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1679                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1680                 break;
1681
1682         /* PTP v2/802.AS1, any layer, Sync packet */
1683         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1684                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1685                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1686                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1687                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1688                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1689                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1690                 break;
1691
1692         /* PTP v2/802.AS1, any layer, Delay_req packet */
1693         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1694                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1695                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1696                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1697                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1698                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1699                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1700                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1701                 break;
1702
1703         default:
1704                 return -ERANGE;
1705         }
1706
1707         pdata->hw_if.config_tstamp(pdata, mac_tscr);
1708
1709         memcpy(&pdata->tstamp_config, &config, sizeof(config));
1710
1711         return 0;
1712 }
1713
1714 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1715                                 struct sk_buff *skb,
1716                                 struct xgbe_packet_data *packet)
1717 {
1718         unsigned long flags;
1719
1720         if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1721                 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1722                 if (pdata->tx_tstamp_skb) {
1723                         /* Another timestamp in progress, ignore this one */
1724                         XGMAC_SET_BITS(packet->attributes,
1725                                        TX_PACKET_ATTRIBUTES, PTP, 0);
1726                 } else {
1727                         pdata->tx_tstamp_skb = skb_get(skb);
1728                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1729                 }
1730                 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1731         }
1732
1733         skb_tx_timestamp(skb);
1734 }
1735
1736 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1737 {
1738         if (skb_vlan_tag_present(skb))
1739                 packet->vlan_ctag = skb_vlan_tag_get(skb);
1740 }
1741
1742 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1743 {
1744         int ret;
1745
1746         if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1747                             TSO_ENABLE))
1748                 return 0;
1749
1750         ret = skb_cow_head(skb, 0);
1751         if (ret)
1752                 return ret;
1753
1754         if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1755                 packet->header_len = skb_inner_transport_offset(skb) +
1756                                      inner_tcp_hdrlen(skb);
1757                 packet->tcp_header_len = inner_tcp_hdrlen(skb);
1758         } else {
1759                 packet->header_len = skb_transport_offset(skb) +
1760                                      tcp_hdrlen(skb);
1761                 packet->tcp_header_len = tcp_hdrlen(skb);
1762         }
1763         packet->tcp_payload_len = skb->len - packet->header_len;
1764         packet->mss = skb_shinfo(skb)->gso_size;
1765
1766         DBGPR("  packet->header_len=%u\n", packet->header_len);
1767         DBGPR("  packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1768               packet->tcp_header_len, packet->tcp_payload_len);
1769         DBGPR("  packet->mss=%u\n", packet->mss);
1770
1771         /* Update the number of packets that will ultimately be transmitted
1772          * along with the extra bytes for each extra packet
1773          */
1774         packet->tx_packets = skb_shinfo(skb)->gso_segs;
1775         packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1776
1777         return 0;
1778 }
1779
1780 static bool xgbe_is_vxlan(struct xgbe_prv_data *pdata, struct sk_buff *skb)
1781 {
1782         struct xgbe_vxlan_data *vdata;
1783
1784         if (pdata->vxlan_force_disable)
1785                 return false;
1786
1787         if (!skb->encapsulation)
1788                 return false;
1789
1790         if (skb->ip_summed != CHECKSUM_PARTIAL)
1791                 return false;
1792
1793         switch (skb->protocol) {
1794         case htons(ETH_P_IP):
1795                 if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1796                         return false;
1797                 break;
1798
1799         case htons(ETH_P_IPV6):
1800                 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1801                         return false;
1802                 break;
1803
1804         default:
1805                 return false;
1806         }
1807
1808         /* See if we have the UDP port in our list */
1809         list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
1810                 if ((skb->protocol == htons(ETH_P_IP)) &&
1811                     (vdata->sa_family == AF_INET) &&
1812                     (vdata->port == udp_hdr(skb)->dest))
1813                         return true;
1814                 else if ((skb->protocol == htons(ETH_P_IPV6)) &&
1815                          (vdata->sa_family == AF_INET6) &&
1816                          (vdata->port == udp_hdr(skb)->dest))
1817                         return true;
1818         }
1819
1820         return false;
1821 }
1822
1823 static int xgbe_is_tso(struct sk_buff *skb)
1824 {
1825         if (skb->ip_summed != CHECKSUM_PARTIAL)
1826                 return 0;
1827
1828         if (!skb_is_gso(skb))
1829                 return 0;
1830
1831         DBGPR("  TSO packet to be processed\n");
1832
1833         return 1;
1834 }
1835
1836 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1837                              struct xgbe_ring *ring, struct sk_buff *skb,
1838                              struct xgbe_packet_data *packet)
1839 {
1840         struct skb_frag_struct *frag;
1841         unsigned int context_desc;
1842         unsigned int len;
1843         unsigned int i;
1844
1845         packet->skb = skb;
1846
1847         context_desc = 0;
1848         packet->rdesc_count = 0;
1849
1850         packet->tx_packets = 1;
1851         packet->tx_bytes = skb->len;
1852
1853         if (xgbe_is_tso(skb)) {
1854                 /* TSO requires an extra descriptor if mss is different */
1855                 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1856                         context_desc = 1;
1857                         packet->rdesc_count++;
1858                 }
1859
1860                 /* TSO requires an extra descriptor for TSO header */
1861                 packet->rdesc_count++;
1862
1863                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1864                                TSO_ENABLE, 1);
1865                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1866                                CSUM_ENABLE, 1);
1867         } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1868                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1869                                CSUM_ENABLE, 1);
1870
1871         if (xgbe_is_vxlan(pdata, skb))
1872                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1873                                VXLAN, 1);
1874
1875         if (skb_vlan_tag_present(skb)) {
1876                 /* VLAN requires an extra descriptor if tag is different */
1877                 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1878                         /* We can share with the TSO context descriptor */
1879                         if (!context_desc) {
1880                                 context_desc = 1;
1881                                 packet->rdesc_count++;
1882                         }
1883
1884                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1885                                VLAN_CTAG, 1);
1886         }
1887
1888         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1889             (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1890                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1891                                PTP, 1);
1892
1893         for (len = skb_headlen(skb); len;) {
1894                 packet->rdesc_count++;
1895                 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1896         }
1897
1898         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1899                 frag = &skb_shinfo(skb)->frags[i];
1900                 for (len = skb_frag_size(frag); len; ) {
1901                         packet->rdesc_count++;
1902                         len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1903                 }
1904         }
1905 }
1906
1907 static int xgbe_open(struct net_device *netdev)
1908 {
1909         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1910         int ret;
1911
1912         /* Create the various names based on netdev name */
1913         snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1914                  netdev_name(netdev));
1915
1916         snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1917                  netdev_name(netdev));
1918
1919         snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1920                  netdev_name(netdev));
1921
1922         /* Create workqueues */
1923         pdata->dev_workqueue =
1924                 create_singlethread_workqueue(netdev_name(netdev));
1925         if (!pdata->dev_workqueue) {
1926                 netdev_err(netdev, "device workqueue creation failed\n");
1927                 return -ENOMEM;
1928         }
1929
1930         pdata->an_workqueue =
1931                 create_singlethread_workqueue(pdata->an_name);
1932         if (!pdata->an_workqueue) {
1933                 netdev_err(netdev, "phy workqueue creation failed\n");
1934                 ret = -ENOMEM;
1935                 goto err_dev_wq;
1936         }
1937
1938         /* Reset the phy settings */
1939         ret = xgbe_phy_reset(pdata);
1940         if (ret)
1941                 goto err_an_wq;
1942
1943         /* Enable the clocks */
1944         ret = clk_prepare_enable(pdata->sysclk);
1945         if (ret) {
1946                 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1947                 goto err_an_wq;
1948         }
1949
1950         ret = clk_prepare_enable(pdata->ptpclk);
1951         if (ret) {
1952                 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1953                 goto err_sysclk;
1954         }
1955
1956         INIT_WORK(&pdata->service_work, xgbe_service);
1957         INIT_WORK(&pdata->restart_work, xgbe_restart);
1958         INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1959         INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1960
1961         ret = xgbe_alloc_memory(pdata);
1962         if (ret)
1963                 goto err_ptpclk;
1964
1965         ret = xgbe_start(pdata);
1966         if (ret)
1967                 goto err_mem;
1968
1969         clear_bit(XGBE_DOWN, &pdata->dev_state);
1970
1971         return 0;
1972
1973 err_mem:
1974         xgbe_free_memory(pdata);
1975
1976 err_ptpclk:
1977         clk_disable_unprepare(pdata->ptpclk);
1978
1979 err_sysclk:
1980         clk_disable_unprepare(pdata->sysclk);
1981
1982 err_an_wq:
1983         destroy_workqueue(pdata->an_workqueue);
1984
1985 err_dev_wq:
1986         destroy_workqueue(pdata->dev_workqueue);
1987
1988         return ret;
1989 }
1990
1991 static int xgbe_close(struct net_device *netdev)
1992 {
1993         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1994
1995         /* Stop the device */
1996         xgbe_stop(pdata);
1997
1998         xgbe_free_memory(pdata);
1999
2000         /* Disable the clocks */
2001         clk_disable_unprepare(pdata->ptpclk);
2002         clk_disable_unprepare(pdata->sysclk);
2003
2004         flush_workqueue(pdata->an_workqueue);
2005         destroy_workqueue(pdata->an_workqueue);
2006
2007         flush_workqueue(pdata->dev_workqueue);
2008         destroy_workqueue(pdata->dev_workqueue);
2009
2010         set_bit(XGBE_DOWN, &pdata->dev_state);
2011
2012         return 0;
2013 }
2014
2015 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
2016 {
2017         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2018         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2019         struct xgbe_desc_if *desc_if = &pdata->desc_if;
2020         struct xgbe_channel *channel;
2021         struct xgbe_ring *ring;
2022         struct xgbe_packet_data *packet;
2023         struct netdev_queue *txq;
2024         netdev_tx_t ret;
2025
2026         DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
2027
2028         channel = pdata->channel[skb->queue_mapping];
2029         txq = netdev_get_tx_queue(netdev, channel->queue_index);
2030         ring = channel->tx_ring;
2031         packet = &ring->packet_data;
2032
2033         ret = NETDEV_TX_OK;
2034
2035         if (skb->len == 0) {
2036                 netif_err(pdata, tx_err, netdev,
2037                           "empty skb received from stack\n");
2038                 dev_kfree_skb_any(skb);
2039                 goto tx_netdev_return;
2040         }
2041
2042         /* Calculate preliminary packet info */
2043         memset(packet, 0, sizeof(*packet));
2044         xgbe_packet_info(pdata, ring, skb, packet);
2045
2046         /* Check that there are enough descriptors available */
2047         ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
2048         if (ret)
2049                 goto tx_netdev_return;
2050
2051         ret = xgbe_prep_tso(skb, packet);
2052         if (ret) {
2053                 netif_err(pdata, tx_err, netdev,
2054                           "error processing TSO packet\n");
2055                 dev_kfree_skb_any(skb);
2056                 goto tx_netdev_return;
2057         }
2058         xgbe_prep_vlan(skb, packet);
2059
2060         if (!desc_if->map_tx_skb(channel, skb)) {
2061                 dev_kfree_skb_any(skb);
2062                 goto tx_netdev_return;
2063         }
2064
2065         xgbe_prep_tx_tstamp(pdata, skb, packet);
2066
2067         /* Report on the actual number of bytes (to be) sent */
2068         netdev_tx_sent_queue(txq, packet->tx_bytes);
2069
2070         /* Configure required descriptor fields for transmission */
2071         hw_if->dev_xmit(channel);
2072
2073         if (netif_msg_pktdata(pdata))
2074                 xgbe_print_pkt(netdev, skb, true);
2075
2076         /* Stop the queue in advance if there may not be enough descriptors */
2077         xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
2078
2079         ret = NETDEV_TX_OK;
2080
2081 tx_netdev_return:
2082         return ret;
2083 }
2084
2085 static void xgbe_set_rx_mode(struct net_device *netdev)
2086 {
2087         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2088         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2089
2090         DBGPR("-->xgbe_set_rx_mode\n");
2091
2092         hw_if->config_rx_mode(pdata);
2093
2094         DBGPR("<--xgbe_set_rx_mode\n");
2095 }
2096
2097 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
2098 {
2099         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2100         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2101         struct sockaddr *saddr = addr;
2102
2103         DBGPR("-->xgbe_set_mac_address\n");
2104
2105         if (!is_valid_ether_addr(saddr->sa_data))
2106                 return -EADDRNOTAVAIL;
2107
2108         memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
2109
2110         hw_if->set_mac_address(pdata, netdev->dev_addr);
2111
2112         DBGPR("<--xgbe_set_mac_address\n");
2113
2114         return 0;
2115 }
2116
2117 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
2118 {
2119         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2120         int ret;
2121
2122         switch (cmd) {
2123         case SIOCGHWTSTAMP:
2124                 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
2125                 break;
2126
2127         case SIOCSHWTSTAMP:
2128                 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
2129                 break;
2130
2131         default:
2132                 ret = -EOPNOTSUPP;
2133         }
2134
2135         return ret;
2136 }
2137
2138 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
2139 {
2140         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2141         int ret;
2142
2143         DBGPR("-->xgbe_change_mtu\n");
2144
2145         ret = xgbe_calc_rx_buf_size(netdev, mtu);
2146         if (ret < 0)
2147                 return ret;
2148
2149         pdata->rx_buf_size = ret;
2150         netdev->mtu = mtu;
2151
2152         xgbe_restart_dev(pdata);
2153
2154         DBGPR("<--xgbe_change_mtu\n");
2155
2156         return 0;
2157 }
2158
2159 static void xgbe_tx_timeout(struct net_device *netdev)
2160 {
2161         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2162
2163         netdev_warn(netdev, "tx timeout, device restarting\n");
2164         schedule_work(&pdata->restart_work);
2165 }
2166
2167 static void xgbe_get_stats64(struct net_device *netdev,
2168                              struct rtnl_link_stats64 *s)
2169 {
2170         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2171         struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2172
2173         DBGPR("-->%s\n", __func__);
2174
2175         pdata->hw_if.read_mmc_stats(pdata);
2176
2177         s->rx_packets = pstats->rxframecount_gb;
2178         s->rx_bytes = pstats->rxoctetcount_gb;
2179         s->rx_errors = pstats->rxframecount_gb -
2180                        pstats->rxbroadcastframes_g -
2181                        pstats->rxmulticastframes_g -
2182                        pstats->rxunicastframes_g;
2183         s->multicast = pstats->rxmulticastframes_g;
2184         s->rx_length_errors = pstats->rxlengtherror;
2185         s->rx_crc_errors = pstats->rxcrcerror;
2186         s->rx_fifo_errors = pstats->rxfifooverflow;
2187
2188         s->tx_packets = pstats->txframecount_gb;
2189         s->tx_bytes = pstats->txoctetcount_gb;
2190         s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
2191         s->tx_dropped = netdev->stats.tx_dropped;
2192
2193         DBGPR("<--%s\n", __func__);
2194 }
2195
2196 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
2197                                 u16 vid)
2198 {
2199         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2200         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2201
2202         DBGPR("-->%s\n", __func__);
2203
2204         set_bit(vid, pdata->active_vlans);
2205         hw_if->update_vlan_hash_table(pdata);
2206
2207         DBGPR("<--%s\n", __func__);
2208
2209         return 0;
2210 }
2211
2212 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
2213                                  u16 vid)
2214 {
2215         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2216         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2217
2218         DBGPR("-->%s\n", __func__);
2219
2220         clear_bit(vid, pdata->active_vlans);
2221         hw_if->update_vlan_hash_table(pdata);
2222
2223         DBGPR("<--%s\n", __func__);
2224
2225         return 0;
2226 }
2227
2228 #ifdef CONFIG_NET_POLL_CONTROLLER
2229 static void xgbe_poll_controller(struct net_device *netdev)
2230 {
2231         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2232         struct xgbe_channel *channel;
2233         unsigned int i;
2234
2235         DBGPR("-->xgbe_poll_controller\n");
2236
2237         if (pdata->per_channel_irq) {
2238                 for (i = 0; i < pdata->channel_count; i++) {
2239                         channel = pdata->channel[i];
2240                         xgbe_dma_isr(channel->dma_irq, channel);
2241                 }
2242         } else {
2243                 disable_irq(pdata->dev_irq);
2244                 xgbe_isr(pdata->dev_irq, pdata);
2245                 enable_irq(pdata->dev_irq);
2246         }
2247
2248         DBGPR("<--xgbe_poll_controller\n");
2249 }
2250 #endif /* End CONFIG_NET_POLL_CONTROLLER */
2251
2252 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
2253                          void *type_data)
2254 {
2255         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2256         struct tc_mqprio_qopt *mqprio = type_data;
2257         u8 tc;
2258
2259         if (type != TC_SETUP_QDISC_MQPRIO)
2260                 return -EOPNOTSUPP;
2261
2262         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2263         tc = mqprio->num_tc;
2264
2265         if (tc > pdata->hw_feat.tc_cnt)
2266                 return -EINVAL;
2267
2268         pdata->num_tcs = tc;
2269         pdata->hw_if.config_tc(pdata);
2270
2271         return 0;
2272 }
2273
2274 static netdev_features_t xgbe_fix_features(struct net_device *netdev,
2275                                            netdev_features_t features)
2276 {
2277         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2278         netdev_features_t vxlan_base, vxlan_mask;
2279
2280         vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
2281         vxlan_mask = vxlan_base | NETIF_F_GSO_UDP_TUNNEL_CSUM;
2282
2283         pdata->vxlan_features = features & vxlan_mask;
2284
2285         /* Only fix VXLAN-related features */
2286         if (!pdata->vxlan_features)
2287                 return features;
2288
2289         /* If VXLAN isn't supported then clear any features:
2290          *   This is needed because NETIF_F_RX_UDP_TUNNEL_PORT gets
2291          *   automatically set if ndo_udp_tunnel_add is set.
2292          */
2293         if (!pdata->hw_feat.vxn)
2294                 return features & ~vxlan_mask;
2295
2296         /* VXLAN CSUM requires VXLAN base */
2297         if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
2298             !(features & NETIF_F_GSO_UDP_TUNNEL)) {
2299                 netdev_notice(netdev,
2300                               "forcing tx udp tunnel support\n");
2301                 features |= NETIF_F_GSO_UDP_TUNNEL;
2302         }
2303
2304         /* Can't do one without doing the other */
2305         if ((features & vxlan_base) != vxlan_base) {
2306                 netdev_notice(netdev,
2307                               "forcing both tx and rx udp tunnel support\n");
2308                 features |= vxlan_base;
2309         }
2310
2311         if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2312                 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
2313                         netdev_notice(netdev,
2314                                       "forcing tx udp tunnel checksumming on\n");
2315                         features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2316                 }
2317         } else {
2318                 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
2319                         netdev_notice(netdev,
2320                                       "forcing tx udp tunnel checksumming off\n");
2321                         features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
2322                 }
2323         }
2324
2325         pdata->vxlan_features = features & vxlan_mask;
2326
2327         /* Adjust UDP Tunnel based on current state */
2328         if (pdata->vxlan_force_disable) {
2329                 netdev_notice(netdev,
2330                               "VXLAN acceleration disabled, turning off udp tunnel features\n");
2331                 features &= ~vxlan_mask;
2332         }
2333
2334         return features;
2335 }
2336
2337 static int xgbe_set_features(struct net_device *netdev,
2338                              netdev_features_t features)
2339 {
2340         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2341         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2342         netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
2343         netdev_features_t udp_tunnel;
2344         int ret = 0;
2345
2346         rxhash = pdata->netdev_features & NETIF_F_RXHASH;
2347         rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
2348         rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
2349         rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
2350         udp_tunnel = pdata->netdev_features & NETIF_F_GSO_UDP_TUNNEL;
2351
2352         if ((features & NETIF_F_RXHASH) && !rxhash)
2353                 ret = hw_if->enable_rss(pdata);
2354         else if (!(features & NETIF_F_RXHASH) && rxhash)
2355                 ret = hw_if->disable_rss(pdata);
2356         if (ret)
2357                 return ret;
2358
2359         if ((features & NETIF_F_RXCSUM) && !rxcsum)
2360                 hw_if->enable_rx_csum(pdata);
2361         else if (!(features & NETIF_F_RXCSUM) && rxcsum)
2362                 hw_if->disable_rx_csum(pdata);
2363
2364         if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
2365                 hw_if->enable_rx_vlan_stripping(pdata);
2366         else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
2367                 hw_if->disable_rx_vlan_stripping(pdata);
2368
2369         if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
2370                 hw_if->enable_rx_vlan_filtering(pdata);
2371         else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
2372                 hw_if->disable_rx_vlan_filtering(pdata);
2373
2374         if ((features & NETIF_F_GSO_UDP_TUNNEL) && !udp_tunnel)
2375                 xgbe_enable_vxlan_accel(pdata);
2376         else if (!(features & NETIF_F_GSO_UDP_TUNNEL) && udp_tunnel)
2377                 xgbe_disable_vxlan_accel(pdata);
2378
2379         pdata->netdev_features = features;
2380
2381         DBGPR("<--xgbe_set_features\n");
2382
2383         return 0;
2384 }
2385
2386 static void xgbe_udp_tunnel_add(struct net_device *netdev,
2387                                 struct udp_tunnel_info *ti)
2388 {
2389         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2390         struct xgbe_vxlan_data *vdata;
2391
2392         if (!pdata->hw_feat.vxn)
2393                 return;
2394
2395         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2396                 return;
2397
2398         pdata->vxlan_port_count++;
2399
2400         netif_dbg(pdata, drv, netdev,
2401                   "adding VXLAN tunnel, family=%hx/port=%hx\n",
2402                   ti->sa_family, be16_to_cpu(ti->port));
2403
2404         if (pdata->vxlan_force_disable)
2405                 return;
2406
2407         vdata = kzalloc(sizeof(*vdata), GFP_ATOMIC);
2408         if (!vdata) {
2409                 /* Can no longer properly track VXLAN ports */
2410                 pdata->vxlan_force_disable = 1;
2411                 netif_dbg(pdata, drv, netdev,
2412                           "internal error, disabling VXLAN accelerations\n");
2413
2414                 xgbe_disable_vxlan_accel(pdata);
2415
2416                 return;
2417         }
2418         vdata->sa_family = ti->sa_family;
2419         vdata->port = ti->port;
2420
2421         list_add_tail(&vdata->list, &pdata->vxlan_ports);
2422
2423         /* First port added? */
2424         if (pdata->vxlan_port_count == 1) {
2425                 xgbe_enable_vxlan_accel(pdata);
2426
2427                 return;
2428         }
2429 }
2430
2431 static void xgbe_udp_tunnel_del(struct net_device *netdev,
2432                                 struct udp_tunnel_info *ti)
2433 {
2434         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2435         struct xgbe_vxlan_data *vdata;
2436
2437         if (!pdata->hw_feat.vxn)
2438                 return;
2439
2440         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2441                 return;
2442
2443         netif_dbg(pdata, drv, netdev,
2444                   "deleting VXLAN tunnel, family=%hx/port=%hx\n",
2445                   ti->sa_family, be16_to_cpu(ti->port));
2446
2447         /* Don't need safe version since loop terminates with deletion */
2448         list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
2449                 if (vdata->sa_family != ti->sa_family)
2450                         continue;
2451
2452                 if (vdata->port != ti->port)
2453                         continue;
2454
2455                 list_del(&vdata->list);
2456                 kfree(vdata);
2457
2458                 break;
2459         }
2460
2461         pdata->vxlan_port_count--;
2462         if (!pdata->vxlan_port_count) {
2463                 xgbe_reset_vxlan_accel(pdata);
2464
2465                 return;
2466         }
2467
2468         if (pdata->vxlan_force_disable)
2469                 return;
2470
2471         /* See if VXLAN tunnel id needs to be changed */
2472         vdata = list_first_entry(&pdata->vxlan_ports,
2473                                  struct xgbe_vxlan_data, list);
2474         if (pdata->vxlan_port == be16_to_cpu(vdata->port))
2475                 return;
2476
2477         pdata->vxlan_port = be16_to_cpu(vdata->port);
2478         pdata->hw_if.set_vxlan_id(pdata);
2479 }
2480
2481 static netdev_features_t xgbe_features_check(struct sk_buff *skb,
2482                                              struct net_device *netdev,
2483                                              netdev_features_t features)
2484 {
2485         features = vlan_features_check(skb, features);
2486         features = vxlan_features_check(skb, features);
2487
2488         return features;
2489 }
2490
2491 static const struct net_device_ops xgbe_netdev_ops = {
2492         .ndo_open               = xgbe_open,
2493         .ndo_stop               = xgbe_close,
2494         .ndo_start_xmit         = xgbe_xmit,
2495         .ndo_set_rx_mode        = xgbe_set_rx_mode,
2496         .ndo_set_mac_address    = xgbe_set_mac_address,
2497         .ndo_validate_addr      = eth_validate_addr,
2498         .ndo_do_ioctl           = xgbe_ioctl,
2499         .ndo_change_mtu         = xgbe_change_mtu,
2500         .ndo_tx_timeout         = xgbe_tx_timeout,
2501         .ndo_get_stats64        = xgbe_get_stats64,
2502         .ndo_vlan_rx_add_vid    = xgbe_vlan_rx_add_vid,
2503         .ndo_vlan_rx_kill_vid   = xgbe_vlan_rx_kill_vid,
2504 #ifdef CONFIG_NET_POLL_CONTROLLER
2505         .ndo_poll_controller    = xgbe_poll_controller,
2506 #endif
2507         .ndo_setup_tc           = xgbe_setup_tc,
2508         .ndo_fix_features       = xgbe_fix_features,
2509         .ndo_set_features       = xgbe_set_features,
2510         .ndo_udp_tunnel_add     = xgbe_udp_tunnel_add,
2511         .ndo_udp_tunnel_del     = xgbe_udp_tunnel_del,
2512         .ndo_features_check     = xgbe_features_check,
2513 };
2514
2515 const struct net_device_ops *xgbe_get_netdev_ops(void)
2516 {
2517         return &xgbe_netdev_ops;
2518 }
2519
2520 static void xgbe_rx_refresh(struct xgbe_channel *channel)
2521 {
2522         struct xgbe_prv_data *pdata = channel->pdata;
2523         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2524         struct xgbe_desc_if *desc_if = &pdata->desc_if;
2525         struct xgbe_ring *ring = channel->rx_ring;
2526         struct xgbe_ring_data *rdata;
2527
2528         while (ring->dirty != ring->cur) {
2529                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2530
2531                 /* Reset rdata values */
2532                 desc_if->unmap_rdata(pdata, rdata);
2533
2534                 if (desc_if->map_rx_buffer(pdata, ring, rdata))
2535                         break;
2536
2537                 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
2538
2539                 ring->dirty++;
2540         }
2541
2542         /* Make sure everything is written before the register write */
2543         wmb();
2544
2545         /* Update the Rx Tail Pointer Register with address of
2546          * the last cleaned entry */
2547         rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
2548         XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2549                           lower_32_bits(rdata->rdesc_dma));
2550 }
2551
2552 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2553                                        struct napi_struct *napi,
2554                                        struct xgbe_ring_data *rdata,
2555                                        unsigned int len)
2556 {
2557         struct sk_buff *skb;
2558         u8 *packet;
2559
2560         skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
2561         if (!skb)
2562                 return NULL;
2563
2564         /* Pull in the header buffer which may contain just the header
2565          * or the header plus data
2566          */
2567         dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2568                                       rdata->rx.hdr.dma_off,
2569                                       rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
2570
2571         packet = page_address(rdata->rx.hdr.pa.pages) +
2572                  rdata->rx.hdr.pa.pages_offset;
2573         skb_copy_to_linear_data(skb, packet, len);
2574         skb_put(skb, len);
2575
2576         return skb;
2577 }
2578
2579 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2580                                      struct xgbe_packet_data *packet)
2581 {
2582         /* Always zero if not the first descriptor */
2583         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2584                 return 0;
2585
2586         /* First descriptor with split header, return header length */
2587         if (rdata->rx.hdr_len)
2588                 return rdata->rx.hdr_len;
2589
2590         /* First descriptor but not the last descriptor and no split header,
2591          * so the full buffer was used
2592          */
2593         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2594                 return rdata->rx.hdr.dma_len;
2595
2596         /* First descriptor and last descriptor and no split header, so
2597          * calculate how much of the buffer was used
2598          */
2599         return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2600 }
2601
2602 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2603                                      struct xgbe_packet_data *packet,
2604                                      unsigned int len)
2605 {
2606         /* Always the full buffer if not the last descriptor */
2607         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2608                 return rdata->rx.buf.dma_len;
2609
2610         /* Last descriptor so calculate how much of the buffer was used
2611          * for the last bit of data
2612          */
2613         return rdata->rx.len - len;
2614 }
2615
2616 static int xgbe_tx_poll(struct xgbe_channel *channel)
2617 {
2618         struct xgbe_prv_data *pdata = channel->pdata;
2619         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2620         struct xgbe_desc_if *desc_if = &pdata->desc_if;
2621         struct xgbe_ring *ring = channel->tx_ring;
2622         struct xgbe_ring_data *rdata;
2623         struct xgbe_ring_desc *rdesc;
2624         struct net_device *netdev = pdata->netdev;
2625         struct netdev_queue *txq;
2626         int processed = 0;
2627         unsigned int tx_packets = 0, tx_bytes = 0;
2628         unsigned int cur;
2629
2630         DBGPR("-->xgbe_tx_poll\n");
2631
2632         /* Nothing to do if there isn't a Tx ring for this channel */
2633         if (!ring)
2634                 return 0;
2635
2636         cur = ring->cur;
2637
2638         /* Be sure we get ring->cur before accessing descriptor data */
2639         smp_rmb();
2640
2641         txq = netdev_get_tx_queue(netdev, channel->queue_index);
2642
2643         while ((processed < XGBE_TX_DESC_MAX_PROC) &&
2644                (ring->dirty != cur)) {
2645                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2646                 rdesc = rdata->rdesc;
2647
2648                 if (!hw_if->tx_complete(rdesc))
2649                         break;
2650
2651                 /* Make sure descriptor fields are read after reading the OWN
2652                  * bit */
2653                 dma_rmb();
2654
2655                 if (netif_msg_tx_done(pdata))
2656                         xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
2657
2658                 if (hw_if->is_last_desc(rdesc)) {
2659                         tx_packets += rdata->tx.packets;
2660                         tx_bytes += rdata->tx.bytes;
2661                 }
2662
2663                 /* Free the SKB and reset the descriptor for re-use */
2664                 desc_if->unmap_rdata(pdata, rdata);
2665                 hw_if->tx_desc_reset(rdata);
2666
2667                 processed++;
2668                 ring->dirty++;
2669         }
2670
2671         if (!processed)
2672                 return 0;
2673
2674         netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2675
2676         if ((ring->tx.queue_stopped == 1) &&
2677             (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
2678                 ring->tx.queue_stopped = 0;
2679                 netif_tx_wake_queue(txq);
2680         }
2681
2682         DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2683
2684         return processed;
2685 }
2686
2687 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2688 {
2689         struct xgbe_prv_data *pdata = channel->pdata;
2690         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2691         struct xgbe_ring *ring = channel->rx_ring;
2692         struct xgbe_ring_data *rdata;
2693         struct xgbe_packet_data *packet;
2694         struct net_device *netdev = pdata->netdev;
2695         struct napi_struct *napi;
2696         struct sk_buff *skb;
2697         struct skb_shared_hwtstamps *hwtstamps;
2698         unsigned int last, error, context_next, context;
2699         unsigned int len, buf1_len, buf2_len, max_len;
2700         unsigned int received = 0;
2701         int packet_count = 0;
2702
2703         DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2704
2705         /* Nothing to do if there isn't a Rx ring for this channel */
2706         if (!ring)
2707                 return 0;
2708
2709         last = 0;
2710         context_next = 0;
2711
2712         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2713
2714         rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2715         packet = &ring->packet_data;
2716         while (packet_count < budget) {
2717                 DBGPR("  cur = %d\n", ring->cur);
2718
2719                 /* First time in loop see if we need to restore state */
2720                 if (!received && rdata->state_saved) {
2721                         skb = rdata->state.skb;
2722                         error = rdata->state.error;
2723                         len = rdata->state.len;
2724                 } else {
2725                         memset(packet, 0, sizeof(*packet));
2726                         skb = NULL;
2727                         error = 0;
2728                         len = 0;
2729                 }
2730
2731 read_again:
2732                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2733
2734                 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
2735                         xgbe_rx_refresh(channel);
2736
2737                 if (hw_if->dev_read(channel))
2738                         break;
2739
2740                 received++;
2741                 ring->cur++;
2742
2743                 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2744                                       LAST);
2745                 context_next = XGMAC_GET_BITS(packet->attributes,
2746                                               RX_PACKET_ATTRIBUTES,
2747                                               CONTEXT_NEXT);
2748                 context = XGMAC_GET_BITS(packet->attributes,
2749                                          RX_PACKET_ATTRIBUTES,
2750                                          CONTEXT);
2751
2752                 /* Earlier error, just drain the remaining data */
2753                 if ((!last || context_next) && error)
2754                         goto read_again;
2755
2756                 if (error || packet->errors) {
2757                         if (packet->errors)
2758                                 netif_err(pdata, rx_err, netdev,
2759                                           "error in received packet\n");
2760                         dev_kfree_skb(skb);
2761                         goto next_packet;
2762                 }
2763
2764                 if (!context) {
2765                         /* Get the data length in the descriptor buffers */
2766                         buf1_len = xgbe_rx_buf1_len(rdata, packet);
2767                         len += buf1_len;
2768                         buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2769                         len += buf2_len;
2770
2771                         if (buf2_len > rdata->rx.buf.dma_len) {
2772                                 /* Hardware inconsistency within the descriptors
2773                                  * that has resulted in a length underflow.
2774                                  */
2775                                 error = 1;
2776                                 goto skip_data;
2777                         }
2778
2779                         if (!skb) {
2780                                 skb = xgbe_create_skb(pdata, napi, rdata,
2781                                                       buf1_len);
2782                                 if (!skb) {
2783                                         error = 1;
2784                                         goto skip_data;
2785                                 }
2786                         }
2787
2788                         if (buf2_len) {
2789                                 dma_sync_single_range_for_cpu(pdata->dev,
2790                                                         rdata->rx.buf.dma_base,
2791                                                         rdata->rx.buf.dma_off,
2792                                                         rdata->rx.buf.dma_len,
2793                                                         DMA_FROM_DEVICE);
2794
2795                                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2796                                                 rdata->rx.buf.pa.pages,
2797                                                 rdata->rx.buf.pa.pages_offset,
2798                                                 buf2_len,
2799                                                 rdata->rx.buf.dma_len);
2800                                 rdata->rx.buf.pa.pages = NULL;
2801                         }
2802                 }
2803
2804 skip_data:
2805                 if (!last || context_next)
2806                         goto read_again;
2807
2808                 if (!skb || error) {
2809                         dev_kfree_skb(skb);
2810                         goto next_packet;
2811                 }
2812
2813                 /* Be sure we don't exceed the configured MTU */
2814                 max_len = netdev->mtu + ETH_HLEN;
2815                 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2816                     (skb->protocol == htons(ETH_P_8021Q)))
2817                         max_len += VLAN_HLEN;
2818
2819                 if (skb->len > max_len) {
2820                         netif_err(pdata, rx_err, netdev,
2821                                   "packet length exceeds configured MTU\n");
2822                         dev_kfree_skb(skb);
2823                         goto next_packet;
2824                 }
2825
2826                 if (netif_msg_pktdata(pdata))
2827                         xgbe_print_pkt(netdev, skb, false);
2828
2829                 skb_checksum_none_assert(skb);
2830                 if (XGMAC_GET_BITS(packet->attributes,
2831                                    RX_PACKET_ATTRIBUTES, CSUM_DONE))
2832                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2833
2834                 if (XGMAC_GET_BITS(packet->attributes,
2835                                    RX_PACKET_ATTRIBUTES, TNP)) {
2836                         skb->encapsulation = 1;
2837
2838                         if (XGMAC_GET_BITS(packet->attributes,
2839                                            RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2840                                 skb->csum_level = 1;
2841                 }
2842
2843                 if (XGMAC_GET_BITS(packet->attributes,
2844                                    RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2845                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2846                                                packet->vlan_ctag);
2847
2848                 if (XGMAC_GET_BITS(packet->attributes,
2849                                    RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2850                         u64 nsec;
2851
2852                         nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2853                                                     packet->rx_tstamp);
2854                         hwtstamps = skb_hwtstamps(skb);
2855                         hwtstamps->hwtstamp = ns_to_ktime(nsec);
2856                 }
2857
2858                 if (XGMAC_GET_BITS(packet->attributes,
2859                                    RX_PACKET_ATTRIBUTES, RSS_HASH))
2860                         skb_set_hash(skb, packet->rss_hash,
2861                                      packet->rss_hash_type);
2862
2863                 skb->dev = netdev;
2864                 skb->protocol = eth_type_trans(skb, netdev);
2865                 skb_record_rx_queue(skb, channel->queue_index);
2866
2867                 napi_gro_receive(napi, skb);
2868
2869 next_packet:
2870                 packet_count++;
2871         }
2872
2873         /* Check if we need to save state before leaving */
2874         if (received && (!last || context_next)) {
2875                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2876                 rdata->state_saved = 1;
2877                 rdata->state.skb = skb;
2878                 rdata->state.len = len;
2879                 rdata->state.error = error;
2880         }
2881
2882         DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2883
2884         return packet_count;
2885 }
2886
2887 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2888 {
2889         struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2890                                                     napi);
2891         struct xgbe_prv_data *pdata = channel->pdata;
2892         int processed = 0;
2893
2894         DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2895
2896         /* Cleanup Tx ring first */
2897         xgbe_tx_poll(channel);
2898
2899         /* Process Rx ring next */
2900         processed = xgbe_rx_poll(channel, budget);
2901
2902         /* If we processed everything, we are done */
2903         if ((processed < budget) && napi_complete_done(napi, processed)) {
2904                 /* Enable Tx and Rx interrupts */
2905                 if (pdata->channel_irq_mode)
2906                         xgbe_enable_rx_tx_int(pdata, channel);
2907                 else
2908                         enable_irq(channel->dma_irq);
2909         }
2910
2911         DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2912
2913         return processed;
2914 }
2915
2916 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2917 {
2918         struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2919                                                    napi);
2920         struct xgbe_channel *channel;
2921         int ring_budget;
2922         int processed, last_processed;
2923         unsigned int i;
2924
2925         DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2926
2927         processed = 0;
2928         ring_budget = budget / pdata->rx_ring_count;
2929         do {
2930                 last_processed = processed;
2931
2932                 for (i = 0; i < pdata->channel_count; i++) {
2933                         channel = pdata->channel[i];
2934
2935                         /* Cleanup Tx ring first */
2936                         xgbe_tx_poll(channel);
2937
2938                         /* Process Rx ring next */
2939                         if (ring_budget > (budget - processed))
2940                                 ring_budget = budget - processed;
2941                         processed += xgbe_rx_poll(channel, ring_budget);
2942                 }
2943         } while ((processed < budget) && (processed != last_processed));
2944
2945         /* If we processed everything, we are done */
2946         if ((processed < budget) && napi_complete_done(napi, processed)) {
2947                 /* Enable Tx and Rx interrupts */
2948                 xgbe_enable_rx_tx_ints(pdata);
2949         }
2950
2951         DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2952
2953         return processed;
2954 }
2955
2956 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2957                        unsigned int idx, unsigned int count, unsigned int flag)
2958 {
2959         struct xgbe_ring_data *rdata;
2960         struct xgbe_ring_desc *rdesc;
2961
2962         while (count--) {
2963                 rdata = XGBE_GET_DESC_DATA(ring, idx);
2964                 rdesc = rdata->rdesc;
2965                 netdev_dbg(pdata->netdev,
2966                            "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2967                            (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2968                            le32_to_cpu(rdesc->desc0),
2969                            le32_to_cpu(rdesc->desc1),
2970                            le32_to_cpu(rdesc->desc2),
2971                            le32_to_cpu(rdesc->desc3));
2972                 idx++;
2973         }
2974 }
2975
2976 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2977                        unsigned int idx)
2978 {
2979         struct xgbe_ring_data *rdata;
2980         struct xgbe_ring_desc *rdesc;
2981
2982         rdata = XGBE_GET_DESC_DATA(ring, idx);
2983         rdesc = rdata->rdesc;
2984         netdev_dbg(pdata->netdev,
2985                    "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2986                    idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2987                    le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2988 }
2989
2990 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2991 {
2992         struct ethhdr *eth = (struct ethhdr *)skb->data;
2993         unsigned char buffer[128];
2994         unsigned int i;
2995
2996         netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2997
2998         netdev_dbg(netdev, "%s packet of %d bytes\n",
2999                    (tx_rx ? "TX" : "RX"), skb->len);
3000
3001         netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
3002         netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
3003         netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
3004
3005         for (i = 0; i < skb->len; i += 32) {
3006                 unsigned int len = min(skb->len - i, 32U);
3007
3008                 hex_dump_to_buffer(&skb->data[i], len, 32, 1,
3009                                    buffer, sizeof(buffer), false);
3010                 netdev_dbg(netdev, "  %#06x: %s\n", i, buffer);
3011         }
3012
3013         netdev_dbg(netdev, "\n************** SKB dump ****************\n");
3014 }