drivers/net/ethernet/amd/xgbe/xgbe-drv.c

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #include <linux/module.h>
 118 #include <linux/spinlock.h>
 119 #include <linux/tcp.h>
 120 #include <linux/if_vlan.h>
 121 #include <linux/interrupt.h>
 122 #include <net/busy_poll.h>
 123 #include <linux/clk.h>
 124 #include <linux/if_ether.h>
 125 #include <linux/net_tstamp.h>
 126 #include <linux/phy.h>
 127 #include <net/vxlan.h>
 128
 129 #include "xgbe.h"
 130 #include "xgbe-common.h"
 131
 132 static unsigned int ecc_sec_info_threshold = 10;
 133 static unsigned int ecc_sec_warn_threshold = 10000;
 134 static unsigned int ecc_sec_period = 600;
 135 static unsigned int ecc_ded_threshold = 2;
 136 static unsigned int ecc_ded_period = 600;
 137
 138 #ifdef CONFIG_AMD_XGBE_HAVE_ECC
 139 /* Only expose the ECC parameters if supported */
 140 module_param(ecc_sec_info_threshold, uint, 0644);
 141 MODULE_PARM_DESC(ecc_sec_info_threshold,
 142                  " ECC corrected error informational threshold setting");
 143
 144 module_param(ecc_sec_warn_threshold, uint, 0644);
 145 MODULE_PARM_DESC(ecc_sec_warn_threshold,
 146                  " ECC corrected error warning threshold setting");
 147
 148 module_param(ecc_sec_period, uint, 0644);
 149 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
 150
 151 module_param(ecc_ded_threshold, uint, 0644);
 152 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
 153
 154 module_param(ecc_ded_period, uint, 0644);
 155 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
 156 #endif
 157
 158 static int xgbe_one_poll(struct napi_struct *, int);
 159 static int xgbe_all_poll(struct napi_struct *, int);
 160 static void xgbe_stop(struct xgbe_prv_data *);
 161
 162 static void *xgbe_alloc_node(size_t size, int node)
 163 {
 164         void *mem;
 165
 166         mem = kzalloc_node(size, GFP_KERNEL, node);
 167         if (!mem)
 168                 mem = kzalloc(size, GFP_KERNEL);
 169
 170         return mem;
 171 }
 172
 173 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
 174 {
 175         unsigned int i;
 176
 177         for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
 178                 if (!pdata->channel[i])
 179                         continue;
 180
 181                 kfree(pdata->channel[i]->rx_ring);
 182                 kfree(pdata->channel[i]->tx_ring);
 183                 kfree(pdata->channel[i]);
 184
 185                 pdata->channel[i] = NULL;
 186         }
 187
 188         pdata->channel_count = 0;
 189 }
 190
 191 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
 192 {
 193         struct xgbe_channel *channel;
 194         struct xgbe_ring *ring;
 195         unsigned int count, i;
 196         unsigned int cpu;
 197         int node;
 198
 199         count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
 200         for (i = 0; i < count; i++) {
 201                 /* Attempt to use a CPU on the node the device is on */
 202                 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
 203
 204                 /* Set the allocation node based on the returned CPU */
 205                 node = cpu_to_node(cpu);
 206
 207                 channel = xgbe_alloc_node(sizeof(*channel), node);
 208                 if (!channel)
 209                         goto err_mem;
 210                 pdata->channel[i] = channel;
 211
 212                 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
 213                 channel->pdata = pdata;
 214                 channel->queue_index = i;
 215                 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
 216                                     (DMA_CH_INC * i);
 217                 channel->node = node;
 218                 cpumask_set_cpu(cpu, &channel->affinity_mask);
 219
 220                 if (pdata->per_channel_irq)
 221                         channel->dma_irq = pdata->channel_irq[i];
 222
 223                 if (i < pdata->tx_ring_count) {
 224                         ring = xgbe_alloc_node(sizeof(*ring), node);
 225                         if (!ring)
 226                                 goto err_mem;
 227
 228                         spin_lock_init(&ring->lock);
 229                         ring->node = node;
 230
 231                         channel->tx_ring = ring;
 232                 }
 233
 234                 if (i < pdata->rx_ring_count) {
 235                         ring = xgbe_alloc_node(sizeof(*ring), node);
 236                         if (!ring)
 237                                 goto err_mem;
 238
 239                         spin_lock_init(&ring->lock);
 240                         ring->node = node;
 241
 242                         channel->rx_ring = ring;
 243                 }
 244
 245                 netif_dbg(pdata, drv, pdata->netdev,
 246                           "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
 247
 248                 netif_dbg(pdata, drv, pdata->netdev,
 249                           "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
 250                           channel->name, channel->dma_regs, channel->dma_irq,
 251                           channel->tx_ring, channel->rx_ring);
 252         }
 253
 254         pdata->channel_count = count;
 255
 256         return 0;
 257
 258 err_mem:
 259         xgbe_free_channels(pdata);
 260
 261         return -ENOMEM;
 262 }
 263
 264 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
 265 {
 266         return (ring->rdesc_count - (ring->cur - ring->dirty));
 267 }
 268
 269 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
 270 {
 271         return (ring->cur - ring->dirty);
 272 }
 273
 274 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
 275                                     struct xgbe_ring *ring, unsigned int count)
 276 {
 277         struct xgbe_prv_data *pdata = channel->pdata;
 278
 279         if (count > xgbe_tx_avail_desc(ring)) {
 280                 netif_info(pdata, drv, pdata->netdev,
 281                            "Tx queue stopped, not enough descriptors available\n");
 282                 netif_stop_subqueue(pdata->netdev, channel->queue_index);
 283                 ring->tx.queue_stopped = 1;
 284
 285                 /* If we haven't notified the hardware because of xmit_more
 286                  * support, tell it now
 287                  */
 288                 if (ring->tx.xmit_more)
 289                         pdata->hw_if.tx_start_xmit(channel, ring);
 290
 291                 return NETDEV_TX_BUSY;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
 298 {
 299         unsigned int rx_buf_size;
 300
 301         rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
 302         rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
 303
 304         rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
 305                       ~(XGBE_RX_BUF_ALIGN - 1);
 306
 307         return rx_buf_size;
 308 }
 309
 310 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
 311                                   struct xgbe_channel *channel)
 312 {
 313         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 314         enum xgbe_int int_id;
 315
 316         if (channel->tx_ring && channel->rx_ring)
 317                 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 318         else if (channel->tx_ring)
 319                 int_id = XGMAC_INT_DMA_CH_SR_TI;
 320         else if (channel->rx_ring)
 321                 int_id = XGMAC_INT_DMA_CH_SR_RI;
 322         else
 323                 return;
 324
 325         hw_if->enable_int(channel, int_id);
 326 }
 327
 328 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
 329 {
 330         unsigned int i;
 331
 332         for (i = 0; i < pdata->channel_count; i++)
 333                 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
 334 }
 335
 336 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
 337                                    struct xgbe_channel *channel)
 338 {
 339         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 340         enum xgbe_int int_id;
 341
 342         if (channel->tx_ring && channel->rx_ring)
 343                 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 344         else if (channel->tx_ring)
 345                 int_id = XGMAC_INT_DMA_CH_SR_TI;
 346         else if (channel->rx_ring)
 347                 int_id = XGMAC_INT_DMA_CH_SR_RI;
 348         else
 349                 return;
 350
 351         hw_if->disable_int(channel, int_id);
 352 }
 353
 354 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
 355 {
 356         unsigned int i;
 357
 358         for (i = 0; i < pdata->channel_count; i++)
 359                 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
 360 }
 361
 362 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
 363                          unsigned int *count, const char *area)
 364 {
 365         if (time_before(jiffies, *period)) {
 366                 (*count)++;
 367         } else {
 368                 *period = jiffies + (ecc_sec_period * HZ);
 369                 *count = 1;
 370         }
 371
 372         if (*count > ecc_sec_info_threshold)
 373                 dev_warn_once(pdata->dev,
 374                               "%s ECC corrected errors exceed informational threshold\n",
 375                               area);
 376
 377         if (*count > ecc_sec_warn_threshold) {
 378                 dev_warn_once(pdata->dev,
 379                               "%s ECC corrected errors exceed warning threshold\n",
 380                               area);
 381                 return true;
 382         }
 383
 384         return false;
 385 }
 386
 387 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
 388                          unsigned int *count, const char *area)
 389 {
 390         if (time_before(jiffies, *period)) {
 391                 (*count)++;
 392         } else {
 393                 *period = jiffies + (ecc_ded_period * HZ);
 394                 *count = 1;
 395         }
 396
 397         if (*count > ecc_ded_threshold) {
 398                 netdev_alert(pdata->netdev,
 399                              "%s ECC detected errors exceed threshold\n",
 400                              area);
 401                 return true;
 402         }
 403
 404         return false;
 405 }
 406
 407 static void xgbe_ecc_isr_task(unsigned long data)
 408 {
 409         struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
 410         unsigned int ecc_isr;
 411         bool stop = false;
 412
 413         /* Mask status with only the interrupts we care about */
 414         ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
 415         ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
 416         netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
 417
 418         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
 419                 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
 420                                      &pdata->tx_ded_count, "TX fifo");
 421         }
 422
 423         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
 424                 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
 425                                      &pdata->rx_ded_count, "RX fifo");
 426         }
 427
 428         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
 429                 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
 430                                      &pdata->desc_ded_count,
 431                                      "descriptor cache");
 432         }
 433
 434         if (stop) {
 435                 pdata->hw_if.disable_ecc_ded(pdata);
 436                 schedule_work(&pdata->stopdev_work);
 437                 goto out;
 438         }
 439
 440         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
 441                 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
 442                                  &pdata->tx_sec_count, "TX fifo"))
 443                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
 444         }
 445
 446         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
 447                 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
 448                                  &pdata->rx_sec_count, "RX fifo"))
 449                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
 450
 451         if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
 452                 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
 453                                  &pdata->desc_sec_count, "descriptor cache"))
 454                         pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
 455
 456 out:
 457         /* Clear all ECC interrupts */
 458         XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
 459
 460         /* Reissue interrupt if status is not clear */
 461         if (pdata->vdata->irq_reissue_support)
 462                 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
 463 }
 464
 465 static irqreturn_t xgbe_ecc_isr(int irq, void *data)
 466 {
 467         struct xgbe_prv_data *pdata = data;
 468
 469         if (pdata->isr_as_tasklet)
 470                 tasklet_schedule(&pdata->tasklet_ecc);
 471         else
 472                 xgbe_ecc_isr_task((unsigned long)pdata);
 473
 474         return IRQ_HANDLED;
 475 }
 476
 477 static void xgbe_isr_task(unsigned long data)
 478 {
 479         struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
 480         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 481         struct xgbe_channel *channel;
 482         unsigned int dma_isr, dma_ch_isr;
 483         unsigned int mac_isr, mac_tssr, mac_mdioisr;
 484         unsigned int i;
 485
 486         /* The DMA interrupt status register also reports MAC and MTL
 487          * interrupts. So for polling mode, we just need to check for
 488          * this register to be non-zero
 489          */
 490         dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
 491         if (!dma_isr)
 492                 goto isr_done;
 493
 494         netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
 495
 496         for (i = 0; i < pdata->channel_count; i++) {
 497                 if (!(dma_isr & (1 << i)))
 498                         continue;
 499
 500                 channel = pdata->channel[i];
 501
 502                 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
 503                 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
 504                           i, dma_ch_isr);
 505
 506                 /* The TI or RI interrupt bits may still be set even if using
 507                  * per channel DMA interrupts. Check to be sure those are not
 508                  * enabled before using the private data napi structure.
 509                  */
 510                 if (!pdata->per_channel_irq &&
 511                     (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
 512                      XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
 513                         if (napi_schedule_prep(&pdata->napi)) {
 514                                 /* Disable Tx and Rx interrupts */
 515                                 xgbe_disable_rx_tx_ints(pdata);
 516
 517                                 /* Turn on polling */
 518                                 __napi_schedule(&pdata->napi);
 519                         }
 520                 } else {
 521                         /* Don't clear Rx/Tx status if doing per channel DMA
 522                          * interrupts, these will be cleared by the ISR for
 523                          * per channel DMA interrupts.
 524                          */
 525                         XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
 526                         XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
 527                 }
 528
 529                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
 530                         pdata->ext_stats.rx_buffer_unavailable++;
 531
 532                 /* Restart the device on a Fatal Bus Error */
 533                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
 534                         schedule_work(&pdata->restart_work);
 535
 536                 /* Clear interrupt signals */
 537                 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
 538         }
 539
 540         if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
 541                 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
 542
 543                 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
 544                           mac_isr);
 545
 546                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
 547                         hw_if->tx_mmc_int(pdata);
 548
 549                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
 550                         hw_if->rx_mmc_int(pdata);
 551
 552                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
 553                         mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
 554
 555                         netif_dbg(pdata, intr, pdata->netdev,
 556                                   "MAC_TSSR=%#010x\n", mac_tssr);
 557
 558                         if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
 559                                 /* Read Tx Timestamp to clear interrupt */
 560                                 pdata->tx_tstamp =
 561                                         hw_if->get_tx_tstamp(pdata);
 562                                 queue_work(pdata->dev_workqueue,
 563                                            &pdata->tx_tstamp_work);
 564                         }
 565                 }
 566
 567                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
 568                         mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
 569
 570                         netif_dbg(pdata, intr, pdata->netdev,
 571                                   "MAC_MDIOISR=%#010x\n", mac_mdioisr);
 572
 573                         if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
 574                                            SNGLCOMPINT))
 575                                 complete(&pdata->mdio_complete);
 576                 }
 577         }
 578
 579 isr_done:
 580         /* If there is not a separate AN irq, handle it here */
 581         if (pdata->dev_irq == pdata->an_irq)
 582                 pdata->phy_if.an_isr(pdata);
 583
 584         /* If there is not a separate ECC irq, handle it here */
 585         if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
 586                 xgbe_ecc_isr_task((unsigned long)pdata);
 587
 588         /* If there is not a separate I2C irq, handle it here */
 589         if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
 590                 pdata->i2c_if.i2c_isr(pdata);
 591
 592         /* Reissue interrupt if status is not clear */
 593         if (pdata->vdata->irq_reissue_support) {
 594                 unsigned int reissue_mask;
 595
 596                 reissue_mask = 1 << 0;
 597                 if (!pdata->per_channel_irq)
 598                         reissue_mask |= 0xffff << 4;
 599
 600                 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
 601         }
 602 }
 603
 604 static irqreturn_t xgbe_isr(int irq, void *data)
 605 {
 606         struct xgbe_prv_data *pdata = data;
 607
 608         if (pdata->isr_as_tasklet)
 609                 tasklet_schedule(&pdata->tasklet_dev);
 610         else
 611                 xgbe_isr_task((unsigned long)pdata);
 612
 613         return IRQ_HANDLED;
 614 }
 615
 616 static irqreturn_t xgbe_dma_isr(int irq, void *data)
 617 {
 618         struct xgbe_channel *channel = data;
 619         struct xgbe_prv_data *pdata = channel->pdata;
 620         unsigned int dma_status;
 621
 622         /* Per channel DMA interrupts are enabled, so we use the per
 623          * channel napi structure and not the private data napi structure
 624          */
 625         if (napi_schedule_prep(&channel->napi)) {
 626                 /* Disable Tx and Rx interrupts */
 627                 if (pdata->channel_irq_mode)
 628                         xgbe_disable_rx_tx_int(pdata, channel);
 629                 else
 630                         disable_irq_nosync(channel->dma_irq);
 631
 632                 /* Turn on polling */
 633                 __napi_schedule_irqoff(&channel->napi);
 634         }
 635
 636         /* Clear Tx/Rx signals */
 637         dma_status = 0;
 638         XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
 639         XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
 640         XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
 641
 642         return IRQ_HANDLED;
 643 }
 644
 645 static void xgbe_tx_timer(struct timer_list *t)
 646 {
 647         struct xgbe_channel *channel = from_timer(channel, t, tx_timer);
 648         struct xgbe_prv_data *pdata = channel->pdata;
 649         struct napi_struct *napi;
 650
 651         DBGPR("-->xgbe_tx_timer\n");
 652
 653         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
 654
 655         if (napi_schedule_prep(napi)) {
 656                 /* Disable Tx and Rx interrupts */
 657                 if (pdata->per_channel_irq)
 658                         if (pdata->channel_irq_mode)
 659                                 xgbe_disable_rx_tx_int(pdata, channel);
 660                         else
 661                                 disable_irq_nosync(channel->dma_irq);
 662                 else
 663                         xgbe_disable_rx_tx_ints(pdata);
 664
 665                 /* Turn on polling */
 666                 __napi_schedule(napi);
 667         }
 668
 669         channel->tx_timer_active = 0;
 670
 671         DBGPR("<--xgbe_tx_timer\n");
 672 }
 673
 674 static void xgbe_service(struct work_struct *work)
 675 {
 676         struct xgbe_prv_data *pdata = container_of(work,
 677                                                    struct xgbe_prv_data,
 678                                                    service_work);
 679
 680         pdata->phy_if.phy_status(pdata);
 681 }
 682
 683 static void xgbe_service_timer(struct timer_list *t)
 684 {
 685         struct xgbe_prv_data *pdata = from_timer(pdata, t, service_timer);
 686
 687         queue_work(pdata->dev_workqueue, &pdata->service_work);
 688
 689         mod_timer(&pdata->service_timer, jiffies + HZ);
 690 }
 691
 692 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
 693 {
 694         struct xgbe_channel *channel;
 695         unsigned int i;
 696
 697         timer_setup(&pdata->service_timer, xgbe_service_timer, 0);
 698
 699         for (i = 0; i < pdata->channel_count; i++) {
 700                 channel = pdata->channel[i];
 701                 if (!channel->tx_ring)
 702                         break;
 703
 704                 timer_setup(&channel->tx_timer, xgbe_tx_timer, 0);
 705         }
 706 }
 707
 708 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
 709 {
 710         mod_timer(&pdata->service_timer, jiffies + HZ);
 711 }
 712
 713 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
 714 {
 715         struct xgbe_channel *channel;
 716         unsigned int i;
 717
 718         del_timer_sync(&pdata->service_timer);
 719
 720         for (i = 0; i < pdata->channel_count; i++) {
 721                 channel = pdata->channel[i];
 722                 if (!channel->tx_ring)
 723                         break;
 724
 725                 /* Deactivate the Tx timer */
 726                 del_timer_sync(&channel->tx_timer);
 727                 channel->tx_timer_active = 0;
 728         }
 729 }
 730
 731 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
 732 {
 733         unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
 734         struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
 735
 736         mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
 737         mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
 738         mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
 739
 740         memset(hw_feat, 0, sizeof(*hw_feat));
 741
 742         hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
 743
 744         /* Hardware feature register 0 */
 745         hw_feat->gmii        = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
 746         hw_feat->vlhash      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
 747         hw_feat->sma         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
 748         hw_feat->rwk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
 749         hw_feat->mgk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
 750         hw_feat->mmc         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
 751         hw_feat->aoe         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
 752         hw_feat->ts          = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
 753         hw_feat->eee         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
 754         hw_feat->tx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
 755         hw_feat->rx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
 756         hw_feat->addn_mac    = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
 757                                               ADDMACADRSEL);
 758         hw_feat->ts_src      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
 759         hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
 760         hw_feat->vxn         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
 761
 762         /* Hardware feature register 1 */
 763         hw_feat->rx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 764                                                 RXFIFOSIZE);
 765         hw_feat->tx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 766                                                 TXFIFOSIZE);
 767         hw_feat->adv_ts_hi     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
 768         hw_feat->dma_width     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
 769         hw_feat->dcb           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
 770         hw_feat->sph           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
 771         hw_feat->tso           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
 772         hw_feat->dma_debug     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
 773         hw_feat->rss           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
 774         hw_feat->tc_cnt        = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
 775         hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 776                                                   HASHTBLSZ);
 777         hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 778                                                   L3L4FNUM);
 779
 780         /* Hardware feature register 2 */
 781         hw_feat->rx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
 782         hw_feat->tx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
 783         hw_feat->rx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
 784         hw_feat->tx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
 785         hw_feat->pps_out_num  = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
 786         hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
 787
 788         /* Translate the Hash Table size into actual number */
 789         switch (hw_feat->hash_table_size) {
 790         case 0:
 791                 break;
 792         case 1:
 793                 hw_feat->hash_table_size = 64;
 794                 break;
 795         case 2:
 796                 hw_feat->hash_table_size = 128;
 797                 break;
 798         case 3:
 799                 hw_feat->hash_table_size = 256;
 800                 break;
 801         }
 802
 803         /* Translate the address width setting into actual number */
 804         switch (hw_feat->dma_width) {
 805         case 0:
 806                 hw_feat->dma_width = 32;
 807                 break;
 808         case 1:
 809                 hw_feat->dma_width = 40;
 810                 break;
 811         case 2:
 812                 hw_feat->dma_width = 48;
 813                 break;
 814         default:
 815                 hw_feat->dma_width = 32;
 816         }
 817
 818         /* The Queue, Channel and TC counts are zero based so increment them
 819          * to get the actual number
 820          */
 821         hw_feat->rx_q_cnt++;
 822         hw_feat->tx_q_cnt++;
 823         hw_feat->rx_ch_cnt++;
 824         hw_feat->tx_ch_cnt++;
 825         hw_feat->tc_cnt++;
 826
 827         /* Translate the fifo sizes into actual numbers */
 828         hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
 829         hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
 830
 831         if (netif_msg_probe(pdata)) {
 832                 dev_dbg(pdata->dev, "Hardware features:\n");
 833
 834                 /* Hardware feature register 0 */
 835                 dev_dbg(pdata->dev, "  1GbE support              : %s\n",
 836                         hw_feat->gmii ? "yes" : "no");
 837                 dev_dbg(pdata->dev, "  VLAN hash filter          : %s\n",
 838                         hw_feat->vlhash ? "yes" : "no");
 839                 dev_dbg(pdata->dev, "  MDIO interface            : %s\n",
 840                         hw_feat->sma ? "yes" : "no");
 841                 dev_dbg(pdata->dev, "  Wake-up packet support    : %s\n",
 842                         hw_feat->rwk ? "yes" : "no");
 843                 dev_dbg(pdata->dev, "  Magic packet support      : %s\n",
 844                         hw_feat->mgk ? "yes" : "no");
 845                 dev_dbg(pdata->dev, "  Management counters       : %s\n",
 846                         hw_feat->mmc ? "yes" : "no");
 847                 dev_dbg(pdata->dev, "  ARP offload               : %s\n",
 848                         hw_feat->aoe ? "yes" : "no");
 849                 dev_dbg(pdata->dev, "  IEEE 1588-2008 Timestamp  : %s\n",
 850                         hw_feat->ts ? "yes" : "no");
 851                 dev_dbg(pdata->dev, "  Energy Efficient Ethernet : %s\n",
 852                         hw_feat->eee ? "yes" : "no");
 853                 dev_dbg(pdata->dev, "  TX checksum offload       : %s\n",
 854                         hw_feat->tx_coe ? "yes" : "no");
 855                 dev_dbg(pdata->dev, "  RX checksum offload       : %s\n",
 856                         hw_feat->rx_coe ? "yes" : "no");
 857                 dev_dbg(pdata->dev, "  Additional MAC addresses  : %u\n",
 858                         hw_feat->addn_mac);
 859                 dev_dbg(pdata->dev, "  Timestamp source          : %s\n",
 860                         (hw_feat->ts_src == 1) ? "internal" :
 861                         (hw_feat->ts_src == 2) ? "external" :
 862                         (hw_feat->ts_src == 3) ? "internal/external" : "n/a");
 863                 dev_dbg(pdata->dev, "  SA/VLAN insertion         : %s\n",
 864                         hw_feat->sa_vlan_ins ? "yes" : "no");
 865                 dev_dbg(pdata->dev, "  VXLAN/NVGRE support       : %s\n",
 866                         hw_feat->vxn ? "yes" : "no");
 867
 868                 /* Hardware feature register 1 */
 869                 dev_dbg(pdata->dev, "  RX fifo size              : %u\n",
 870                         hw_feat->rx_fifo_size);
 871                 dev_dbg(pdata->dev, "  TX fifo size              : %u\n",
 872                         hw_feat->tx_fifo_size);
 873                 dev_dbg(pdata->dev, "  IEEE 1588 high word       : %s\n",
 874                         hw_feat->adv_ts_hi ? "yes" : "no");
 875                 dev_dbg(pdata->dev, "  DMA width                 : %u\n",
 876                         hw_feat->dma_width);
 877                 dev_dbg(pdata->dev, "  Data Center Bridging      : %s\n",
 878                         hw_feat->dcb ? "yes" : "no");
 879                 dev_dbg(pdata->dev, "  Split header              : %s\n",
 880                         hw_feat->sph ? "yes" : "no");
 881                 dev_dbg(pdata->dev, "  TCP Segmentation Offload  : %s\n",
 882                         hw_feat->tso ? "yes" : "no");
 883                 dev_dbg(pdata->dev, "  Debug memory interface    : %s\n",
 884                         hw_feat->dma_debug ? "yes" : "no");
 885                 dev_dbg(pdata->dev, "  Receive Side Scaling      : %s\n",
 886                         hw_feat->rss ? "yes" : "no");
 887                 dev_dbg(pdata->dev, "  Traffic Class count       : %u\n",
 888                         hw_feat->tc_cnt);
 889                 dev_dbg(pdata->dev, "  Hash table size           : %u\n",
 890                         hw_feat->hash_table_size);
 891                 dev_dbg(pdata->dev, "  L3/L4 Filters             : %u\n",
 892                         hw_feat->l3l4_filter_num);
 893
 894                 /* Hardware feature register 2 */
 895                 dev_dbg(pdata->dev, "  RX queue count            : %u\n",
 896                         hw_feat->rx_q_cnt);
 897                 dev_dbg(pdata->dev, "  TX queue count            : %u\n",
 898                         hw_feat->tx_q_cnt);
 899                 dev_dbg(pdata->dev, "  RX DMA channel count      : %u\n",
 900                         hw_feat->rx_ch_cnt);
 901                 dev_dbg(pdata->dev, "  TX DMA channel count      : %u\n",
 902                         hw_feat->rx_ch_cnt);
 903                 dev_dbg(pdata->dev, "  PPS outputs               : %u\n",
 904                         hw_feat->pps_out_num);
 905                 dev_dbg(pdata->dev, "  Auxiliary snapshot inputs : %u\n",
 906                         hw_feat->aux_snap_num);
 907         }
 908 }
 909
 910 static void xgbe_disable_vxlan_offloads(struct xgbe_prv_data *pdata)
 911 {
 912         struct net_device *netdev = pdata->netdev;
 913
 914         if (!pdata->vxlan_offloads_set)
 915                 return;
 916
 917         netdev_info(netdev, "disabling VXLAN offloads\n");
 918
 919         netdev->hw_enc_features &= ~(NETIF_F_SG |
 920                                      NETIF_F_IP_CSUM |
 921                                      NETIF_F_IPV6_CSUM |
 922                                      NETIF_F_RXCSUM |
 923                                      NETIF_F_TSO |
 924                                      NETIF_F_TSO6 |
 925                                      NETIF_F_GRO |
 926                                      NETIF_F_GSO_UDP_TUNNEL |
 927                                      NETIF_F_GSO_UDP_TUNNEL_CSUM);
 928
 929         netdev->features &= ~(NETIF_F_GSO_UDP_TUNNEL |
 930                               NETIF_F_GSO_UDP_TUNNEL_CSUM);
 931
 932         pdata->vxlan_offloads_set = 0;
 933 }
 934
 935 static void xgbe_disable_vxlan_hw(struct xgbe_prv_data *pdata)
 936 {
 937         if (!pdata->vxlan_port_set)
 938                 return;
 939
 940         pdata->hw_if.disable_vxlan(pdata);
 941
 942         pdata->vxlan_port_set = 0;
 943         pdata->vxlan_port = 0;
 944 }
 945
 946 static void xgbe_disable_vxlan_accel(struct xgbe_prv_data *pdata)
 947 {
 948         xgbe_disable_vxlan_offloads(pdata);
 949
 950         xgbe_disable_vxlan_hw(pdata);
 951 }
 952
 953 static void xgbe_enable_vxlan_offloads(struct xgbe_prv_data *pdata)
 954 {
 955         struct net_device *netdev = pdata->netdev;
 956
 957         if (pdata->vxlan_offloads_set)
 958                 return;
 959
 960         netdev_info(netdev, "enabling VXLAN offloads\n");
 961
 962         netdev->hw_enc_features |= NETIF_F_SG |
 963                                    NETIF_F_IP_CSUM |
 964                                    NETIF_F_IPV6_CSUM |
 965                                    NETIF_F_RXCSUM |
 966                                    NETIF_F_TSO |
 967                                    NETIF_F_TSO6 |
 968                                    NETIF_F_GRO |
 969                                    pdata->vxlan_features;
 970
 971         netdev->features |= pdata->vxlan_features;
 972
 973         pdata->vxlan_offloads_set = 1;
 974 }
 975
 976 static void xgbe_enable_vxlan_hw(struct xgbe_prv_data *pdata)
 977 {
 978         struct xgbe_vxlan_data *vdata;
 979
 980         if (pdata->vxlan_port_set)
 981                 return;
 982
 983         if (list_empty(&pdata->vxlan_ports))
 984                 return;
 985
 986         vdata = list_first_entry(&pdata->vxlan_ports,
 987                                  struct xgbe_vxlan_data, list);
 988
 989         pdata->vxlan_port_set = 1;
 990         pdata->vxlan_port = be16_to_cpu(vdata->port);
 991
 992         pdata->hw_if.enable_vxlan(pdata);
 993 }
 994
 995 static void xgbe_enable_vxlan_accel(struct xgbe_prv_data *pdata)
 996 {
 997         /* VXLAN acceleration desired? */
 998         if (!pdata->vxlan_features)
 999                 return;
1000
1001         /* VXLAN acceleration possible? */
1002         if (pdata->vxlan_force_disable)
1003                 return;
1004
1005         xgbe_enable_vxlan_hw(pdata);
1006
1007         xgbe_enable_vxlan_offloads(pdata);
1008 }
1009
1010 static void xgbe_reset_vxlan_accel(struct xgbe_prv_data *pdata)
1011 {
1012         xgbe_disable_vxlan_hw(pdata);
1013
1014         if (pdata->vxlan_features)
1015                 xgbe_enable_vxlan_offloads(pdata);
1016
1017         pdata->vxlan_force_disable = 0;
1018 }
1019
1020 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
1021 {
1022         struct xgbe_channel *channel;
1023         unsigned int i;
1024
1025         if (pdata->per_channel_irq) {
1026                 for (i = 0; i < pdata->channel_count; i++) {
1027                         channel = pdata->channel[i];
1028                         if (add)
1029                                 netif_napi_add(pdata->netdev, &channel->napi,
1030                                                xgbe_one_poll, NAPI_POLL_WEIGHT);
1031
1032                         napi_enable(&channel->napi);
1033                 }
1034         } else {
1035                 if (add)
1036                         netif_napi_add(pdata->netdev, &pdata->napi,
1037                                        xgbe_all_poll, NAPI_POLL_WEIGHT);
1038
1039                 napi_enable(&pdata->napi);
1040         }
1041 }
1042
1043 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
1044 {
1045         struct xgbe_channel *channel;
1046         unsigned int i;
1047
1048         if (pdata->per_channel_irq) {
1049                 for (i = 0; i < pdata->channel_count; i++) {
1050                         channel = pdata->channel[i];
1051                         napi_disable(&channel->napi);
1052
1053                         if (del)
1054                                 netif_napi_del(&channel->napi);
1055                 }
1056         } else {
1057                 napi_disable(&pdata->napi);
1058
1059                 if (del)
1060                         netif_napi_del(&pdata->napi);
1061         }
1062 }
1063
1064 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
1065 {
1066         struct xgbe_channel *channel;
1067         struct net_device *netdev = pdata->netdev;
1068         unsigned int i;
1069         int ret;
1070
1071         tasklet_init(&pdata->tasklet_dev, xgbe_isr_task, (unsigned long)pdata);
1072         tasklet_init(&pdata->tasklet_ecc, xgbe_ecc_isr_task,
1073                      (unsigned long)pdata);
1074
1075         ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
1076                                netdev_name(netdev), pdata);
1077         if (ret) {
1078                 netdev_alert(netdev, "error requesting irq %d\n",
1079                              pdata->dev_irq);
1080                 return ret;
1081         }
1082
1083         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
1084                 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
1085                                        0, pdata->ecc_name, pdata);
1086                 if (ret) {
1087                         netdev_alert(netdev, "error requesting ecc irq %d\n",
1088                                      pdata->ecc_irq);
1089                         goto err_dev_irq;
1090                 }
1091         }
1092
1093         if (!pdata->per_channel_irq)
1094                 return 0;
1095
1096         for (i = 0; i < pdata->channel_count; i++) {
1097                 channel = pdata->channel[i];
1098                 snprintf(channel->dma_irq_name,
1099                          sizeof(channel->dma_irq_name) - 1,
1100                          "%s-TxRx-%u", netdev_name(netdev),
1101                          channel->queue_index);
1102
1103                 ret = devm_request_irq(pdata->dev, channel->dma_irq,
1104                                        xgbe_dma_isr, 0,
1105                                        channel->dma_irq_name, channel);
1106                 if (ret) {
1107                         netdev_alert(netdev, "error requesting irq %d\n",
1108                                      channel->dma_irq);
1109                         goto err_dma_irq;
1110                 }
1111
1112                 irq_set_affinity_hint(channel->dma_irq,
1113                                       &channel->affinity_mask);
1114         }
1115
1116         return 0;
1117
1118 err_dma_irq:
1119         /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1120         for (i--; i < pdata->channel_count; i--) {
1121                 channel = pdata->channel[i];
1122
1123                 irq_set_affinity_hint(channel->dma_irq, NULL);
1124                 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1125         }
1126
1127         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1128                 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1129
1130 err_dev_irq:
1131         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1132
1133         return ret;
1134 }
1135
1136 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
1137 {
1138         struct xgbe_channel *channel;
1139         unsigned int i;
1140
1141         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1142
1143         tasklet_kill(&pdata->tasklet_dev);
1144         tasklet_kill(&pdata->tasklet_ecc);
1145
1146         if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1147                 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1148
1149         if (!pdata->per_channel_irq)
1150                 return;
1151
1152         for (i = 0; i < pdata->channel_count; i++) {
1153                 channel = pdata->channel[i];
1154
1155                 irq_set_affinity_hint(channel->dma_irq, NULL);
1156                 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1157         }
1158 }
1159
1160 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
1161 {
1162         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1163
1164         DBGPR("-->xgbe_init_tx_coalesce\n");
1165
1166         pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
1167         pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
1168
1169         hw_if->config_tx_coalesce(pdata);
1170
1171         DBGPR("<--xgbe_init_tx_coalesce\n");
1172 }
1173
1174 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1175 {
1176         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1177
1178         DBGPR("-->xgbe_init_rx_coalesce\n");
1179
1180         pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
1181         pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
1182         pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1183
1184         hw_if->config_rx_coalesce(pdata);
1185
1186         DBGPR("<--xgbe_init_rx_coalesce\n");
1187 }
1188
1189 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
1190 {
1191         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1192         struct xgbe_ring *ring;
1193         struct xgbe_ring_data *rdata;
1194         unsigned int i, j;
1195
1196         DBGPR("-->xgbe_free_tx_data\n");
1197
1198         for (i = 0; i < pdata->channel_count; i++) {
1199                 ring = pdata->channel[i]->tx_ring;
1200                 if (!ring)
1201                         break;
1202
1203                 for (j = 0; j < ring->rdesc_count; j++) {
1204                         rdata = XGBE_GET_DESC_DATA(ring, j);
1205                         desc_if->unmap_rdata(pdata, rdata);
1206                 }
1207         }
1208
1209         DBGPR("<--xgbe_free_tx_data\n");
1210 }
1211
1212 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
1213 {
1214         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1215         struct xgbe_ring *ring;
1216         struct xgbe_ring_data *rdata;
1217         unsigned int i, j;
1218
1219         DBGPR("-->xgbe_free_rx_data\n");
1220
1221         for (i = 0; i < pdata->channel_count; i++) {
1222                 ring = pdata->channel[i]->rx_ring;
1223                 if (!ring)
1224                         break;
1225
1226                 for (j = 0; j < ring->rdesc_count; j++) {
1227                         rdata = XGBE_GET_DESC_DATA(ring, j);
1228                         desc_if->unmap_rdata(pdata, rdata);
1229                 }
1230         }
1231
1232         DBGPR("<--xgbe_free_rx_data\n");
1233 }
1234
1235 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1236 {
1237         pdata->phy_link = -1;
1238         pdata->phy_speed = SPEED_UNKNOWN;
1239
1240         return pdata->phy_if.phy_reset(pdata);
1241 }
1242
1243 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
1244 {
1245         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1246         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1247         unsigned long flags;
1248
1249         DBGPR("-->xgbe_powerdown\n");
1250
1251         if (!netif_running(netdev) ||
1252             (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
1253                 netdev_alert(netdev, "Device is already powered down\n");
1254                 DBGPR("<--xgbe_powerdown\n");
1255                 return -EINVAL;
1256         }
1257
1258         spin_lock_irqsave(&pdata->lock, flags);
1259
1260         if (caller == XGMAC_DRIVER_CONTEXT)
1261                 netif_device_detach(netdev);
1262
1263         netif_tx_stop_all_queues(netdev);
1264
1265         xgbe_stop_timers(pdata);
1266         flush_workqueue(pdata->dev_workqueue);
1267
1268         hw_if->powerdown_tx(pdata);
1269         hw_if->powerdown_rx(pdata);
1270
1271         xgbe_napi_disable(pdata, 0);
1272
1273         pdata->power_down = 1;
1274
1275         spin_unlock_irqrestore(&pdata->lock, flags);
1276
1277         DBGPR("<--xgbe_powerdown\n");
1278
1279         return 0;
1280 }
1281
1282 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
1283 {
1284         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1285         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1286         unsigned long flags;
1287
1288         DBGPR("-->xgbe_powerup\n");
1289
1290         if (!netif_running(netdev) ||
1291             (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
1292                 netdev_alert(netdev, "Device is already powered up\n");
1293                 DBGPR("<--xgbe_powerup\n");
1294                 return -EINVAL;
1295         }
1296
1297         spin_lock_irqsave(&pdata->lock, flags);
1298
1299         pdata->power_down = 0;
1300
1301         xgbe_napi_enable(pdata, 0);
1302
1303         hw_if->powerup_tx(pdata);
1304         hw_if->powerup_rx(pdata);
1305
1306         if (caller == XGMAC_DRIVER_CONTEXT)
1307                 netif_device_attach(netdev);
1308
1309         netif_tx_start_all_queues(netdev);
1310
1311         xgbe_start_timers(pdata);
1312
1313         spin_unlock_irqrestore(&pdata->lock, flags);
1314
1315         DBGPR("<--xgbe_powerup\n");
1316
1317         return 0;
1318 }
1319
1320 static void xgbe_free_memory(struct xgbe_prv_data *pdata)
1321 {
1322         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1323
1324         /* Free the ring descriptors and buffers */
1325         desc_if->free_ring_resources(pdata);
1326
1327         /* Free the channel and ring structures */
1328         xgbe_free_channels(pdata);
1329 }
1330
1331 static int xgbe_alloc_memory(struct xgbe_prv_data *pdata)
1332 {
1333         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1334         struct net_device *netdev = pdata->netdev;
1335         int ret;
1336
1337         if (pdata->new_tx_ring_count) {
1338                 pdata->tx_ring_count = pdata->new_tx_ring_count;
1339                 pdata->tx_q_count = pdata->tx_ring_count;
1340                 pdata->new_tx_ring_count = 0;
1341         }
1342
1343         if (pdata->new_rx_ring_count) {
1344                 pdata->rx_ring_count = pdata->new_rx_ring_count;
1345                 pdata->new_rx_ring_count = 0;
1346         }
1347
1348         /* Calculate the Rx buffer size before allocating rings */
1349         pdata->rx_buf_size = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1350
1351         /* Allocate the channel and ring structures */
1352         ret = xgbe_alloc_channels(pdata);
1353         if (ret)
1354                 return ret;
1355
1356         /* Allocate the ring descriptors and buffers */
1357         ret = desc_if->alloc_ring_resources(pdata);
1358         if (ret)
1359                 goto err_channels;
1360
1361         /* Initialize the service and Tx timers */
1362         xgbe_init_timers(pdata);
1363
1364         return 0;
1365
1366 err_channels:
1367         xgbe_free_memory(pdata);
1368
1369         return ret;
1370 }
1371
1372 static int xgbe_start(struct xgbe_prv_data *pdata)
1373 {
1374         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1375         struct xgbe_phy_if *phy_if = &pdata->phy_if;
1376         struct net_device *netdev = pdata->netdev;
1377         unsigned int i;
1378         int ret;
1379
1380         /* Set the number of queues */
1381         ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
1382         if (ret) {
1383                 netdev_err(netdev, "error setting real tx queue count\n");
1384                 return ret;
1385         }
1386
1387         ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
1388         if (ret) {
1389                 netdev_err(netdev, "error setting real rx queue count\n");
1390                 return ret;
1391         }
1392
1393         /* Set RSS lookup table data for programming */
1394         for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1395                 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1396                                i % pdata->rx_ring_count);
1397
1398         ret = hw_if->init(pdata);
1399         if (ret)
1400                 return ret;
1401
1402         xgbe_napi_enable(pdata, 1);
1403
1404         ret = xgbe_request_irqs(pdata);
1405         if (ret)
1406                 goto err_napi;
1407
1408         ret = phy_if->phy_start(pdata);
1409         if (ret)
1410                 goto err_irqs;
1411
1412         hw_if->enable_tx(pdata);
1413         hw_if->enable_rx(pdata);
1414
1415         udp_tunnel_get_rx_info(netdev);
1416
1417         netif_tx_start_all_queues(netdev);
1418
1419         xgbe_start_timers(pdata);
1420         queue_work(pdata->dev_workqueue, &pdata->service_work);
1421
1422         clear_bit(XGBE_STOPPED, &pdata->dev_state);
1423
1424         return 0;
1425
1426 err_irqs:
1427         xgbe_free_irqs(pdata);
1428
1429 err_napi:
1430         xgbe_napi_disable(pdata, 1);
1431
1432         hw_if->exit(pdata);
1433
1434         return ret;
1435 }
1436
1437 static void xgbe_stop(struct xgbe_prv_data *pdata)
1438 {
1439         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1440         struct xgbe_phy_if *phy_if = &pdata->phy_if;
1441         struct xgbe_channel *channel;
1442         struct net_device *netdev = pdata->netdev;
1443         struct netdev_queue *txq;
1444         unsigned int i;
1445
1446         DBGPR("-->xgbe_stop\n");
1447
1448         if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1449                 return;
1450
1451         netif_tx_stop_all_queues(netdev);
1452         netif_carrier_off(pdata->netdev);
1453
1454         xgbe_stop_timers(pdata);
1455         flush_workqueue(pdata->dev_workqueue);
1456
1457         xgbe_reset_vxlan_accel(pdata);
1458
1459         hw_if->disable_tx(pdata);
1460         hw_if->disable_rx(pdata);
1461
1462         phy_if->phy_stop(pdata);
1463
1464         xgbe_free_irqs(pdata);
1465
1466         xgbe_napi_disable(pdata, 1);
1467
1468         hw_if->exit(pdata);
1469
1470         for (i = 0; i < pdata->channel_count; i++) {
1471                 channel = pdata->channel[i];
1472                 if (!channel->tx_ring)
1473                         continue;
1474
1475                 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1476                 netdev_tx_reset_queue(txq);
1477         }
1478
1479         set_bit(XGBE_STOPPED, &pdata->dev_state);
1480
1481         DBGPR("<--xgbe_stop\n");
1482 }
1483
1484 static void xgbe_stopdev(struct work_struct *work)
1485 {
1486         struct xgbe_prv_data *pdata = container_of(work,
1487                                                    struct xgbe_prv_data,
1488                                                    stopdev_work);
1489
1490         rtnl_lock();
1491
1492         xgbe_stop(pdata);
1493
1494         xgbe_free_tx_data(pdata);
1495         xgbe_free_rx_data(pdata);
1496
1497         rtnl_unlock();
1498
1499         netdev_alert(pdata->netdev, "device stopped\n");
1500 }
1501
1502 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata)
1503 {
1504         /* If not running, "restart" will happen on open */
1505         if (!netif_running(pdata->netdev))
1506                 return;
1507
1508         xgbe_stop(pdata);
1509
1510         xgbe_free_memory(pdata);
1511         xgbe_alloc_memory(pdata);
1512
1513         xgbe_start(pdata);
1514 }
1515
1516 void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1517 {
1518         /* If not running, "restart" will happen on open */
1519         if (!netif_running(pdata->netdev))
1520                 return;
1521
1522         xgbe_stop(pdata);
1523
1524         xgbe_free_tx_data(pdata);
1525         xgbe_free_rx_data(pdata);
1526
1527         xgbe_start(pdata);
1528 }
1529
1530 static void xgbe_restart(struct work_struct *work)
1531 {
1532         struct xgbe_prv_data *pdata = container_of(work,
1533                                                    struct xgbe_prv_data,
1534                                                    restart_work);
1535
1536         rtnl_lock();
1537
1538         xgbe_restart_dev(pdata);
1539
1540         rtnl_unlock();
1541 }
1542
1543 static void xgbe_tx_tstamp(struct work_struct *work)
1544 {
1545         struct xgbe_prv_data *pdata = container_of(work,
1546                                                    struct xgbe_prv_data,
1547                                                    tx_tstamp_work);
1548         struct skb_shared_hwtstamps hwtstamps;
1549         u64 nsec;
1550         unsigned long flags;
1551
1552         spin_lock_irqsave(&pdata->tstamp_lock, flags);
1553         if (!pdata->tx_tstamp_skb)
1554                 goto unlock;
1555
1556         if (pdata->tx_tstamp) {
1557                 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1558                                             pdata->tx_tstamp);
1559
1560                 memset(&hwtstamps, 0, sizeof(hwtstamps));
1561                 hwtstamps.hwtstamp = ns_to_ktime(nsec);
1562                 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1563         }
1564
1565         dev_kfree_skb_any(pdata->tx_tstamp_skb);
1566
1567         pdata->tx_tstamp_skb = NULL;
1568
1569 unlock:
1570         spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1571 }
1572
1573 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1574                                       struct ifreq *ifreq)
1575 {
1576         if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1577                          sizeof(pdata->tstamp_config)))
1578                 return -EFAULT;
1579
1580         return 0;
1581 }
1582
1583 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1584                                       struct ifreq *ifreq)
1585 {
1586         struct hwtstamp_config config;
1587         unsigned int mac_tscr;
1588
1589         if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1590                 return -EFAULT;
1591
1592         if (config.flags)
1593                 return -EINVAL;
1594
1595         mac_tscr = 0;
1596
1597         switch (config.tx_type) {
1598         case HWTSTAMP_TX_OFF:
1599                 break;
1600
1601         case HWTSTAMP_TX_ON:
1602                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1603                 break;
1604
1605         default:
1606                 return -ERANGE;
1607         }
1608
1609         switch (config.rx_filter) {
1610         case HWTSTAMP_FILTER_NONE:
1611                 break;
1612
1613         case HWTSTAMP_FILTER_NTP_ALL:
1614         case HWTSTAMP_FILTER_ALL:
1615                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1616                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1617                 break;
1618
1619         /* PTP v2, UDP, any kind of event packet */
1620         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1621                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1622         /* PTP v1, UDP, any kind of event packet */
1623         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1624                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1625                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1626                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1627                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1628                 break;
1629
1630         /* PTP v2, UDP, Sync packet */
1631         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1632                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1633         /* PTP v1, UDP, Sync packet */
1634         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1635                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1636                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1637                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1638                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1639                 break;
1640
1641         /* PTP v2, UDP, Delay_req packet */
1642         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1643                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1644         /* PTP v1, UDP, Delay_req packet */
1645         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1646                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1647                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1648                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1649                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1650                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1651                 break;
1652
1653         /* 802.AS1, Ethernet, any kind of event packet */
1654         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1655                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1656                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1657                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1658                 break;
1659
1660         /* 802.AS1, Ethernet, Sync packet */
1661         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1662                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1663                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1664                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1665                 break;
1666
1667         /* 802.AS1, Ethernet, Delay_req packet */
1668         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1669                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1670                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1671                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1672                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1673                 break;
1674
1675         /* PTP v2/802.AS1, any layer, any kind of event packet */
1676         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1677                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1678                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1679                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1680                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1681                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1682                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1683                 break;
1684
1685         /* PTP v2/802.AS1, any layer, Sync packet */
1686         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1687                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1688                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1689                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1690                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1691                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1692                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1693                 break;
1694
1695         /* PTP v2/802.AS1, any layer, Delay_req packet */
1696         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1697                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1698                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1699                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1700                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1701                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1702                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1703                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1704                 break;
1705
1706         default:
1707                 return -ERANGE;
1708         }
1709
1710         pdata->hw_if.config_tstamp(pdata, mac_tscr);
1711
1712         memcpy(&pdata->tstamp_config, &config, sizeof(config));
1713
1714         return 0;
1715 }
1716
1717 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1718                                 struct sk_buff *skb,
1719                                 struct xgbe_packet_data *packet)
1720 {
1721         unsigned long flags;
1722
1723         if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1724                 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1725                 if (pdata->tx_tstamp_skb) {
1726                         /* Another timestamp in progress, ignore this one */
1727                         XGMAC_SET_BITS(packet->attributes,
1728                                        TX_PACKET_ATTRIBUTES, PTP, 0);
1729                 } else {
1730                         pdata->tx_tstamp_skb = skb_get(skb);
1731                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1732                 }
1733                 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1734         }
1735
1736         skb_tx_timestamp(skb);
1737 }
1738
1739 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1740 {
1741         if (skb_vlan_tag_present(skb))
1742                 packet->vlan_ctag = skb_vlan_tag_get(skb);
1743 }
1744
1745 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1746 {
1747         int ret;
1748
1749         if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1750                             TSO_ENABLE))
1751                 return 0;
1752
1753         ret = skb_cow_head(skb, 0);
1754         if (ret)
1755                 return ret;
1756
1757         if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1758                 packet->header_len = skb_inner_transport_offset(skb) +
1759                                      inner_tcp_hdrlen(skb);
1760                 packet->tcp_header_len = inner_tcp_hdrlen(skb);
1761         } else {
1762                 packet->header_len = skb_transport_offset(skb) +
1763                                      tcp_hdrlen(skb);
1764                 packet->tcp_header_len = tcp_hdrlen(skb);
1765         }
1766         packet->tcp_payload_len = skb->len - packet->header_len;
1767         packet->mss = skb_shinfo(skb)->gso_size;
1768
1769         DBGPR("  packet->header_len=%u\n", packet->header_len);
1770         DBGPR("  packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1771               packet->tcp_header_len, packet->tcp_payload_len);
1772         DBGPR("  packet->mss=%u\n", packet->mss);
1773
1774         /* Update the number of packets that will ultimately be transmitted
1775          * along with the extra bytes for each extra packet
1776          */
1777         packet->tx_packets = skb_shinfo(skb)->gso_segs;
1778         packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1779
1780         return 0;
1781 }
1782
1783 static bool xgbe_is_vxlan(struct xgbe_prv_data *pdata, struct sk_buff *skb)
1784 {
1785         struct xgbe_vxlan_data *vdata;
1786
1787         if (pdata->vxlan_force_disable)
1788                 return false;
1789
1790         if (!skb->encapsulation)
1791                 return false;
1792
1793         if (skb->ip_summed != CHECKSUM_PARTIAL)
1794                 return false;
1795
1796         switch (skb->protocol) {
1797         case htons(ETH_P_IP):
1798                 if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1799                         return false;
1800                 break;
1801
1802         case htons(ETH_P_IPV6):
1803                 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1804                         return false;
1805                 break;
1806
1807         default:
1808                 return false;
1809         }
1810
1811         /* See if we have the UDP port in our list */
1812         list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
1813                 if ((skb->protocol == htons(ETH_P_IP)) &&
1814                     (vdata->sa_family == AF_INET) &&
1815                     (vdata->port == udp_hdr(skb)->dest))
1816                         return true;
1817                 else if ((skb->protocol == htons(ETH_P_IPV6)) &&
1818                          (vdata->sa_family == AF_INET6) &&
1819                          (vdata->port == udp_hdr(skb)->dest))
1820                         return true;
1821         }
1822
1823         return false;
1824 }
1825
1826 static int xgbe_is_tso(struct sk_buff *skb)
1827 {
1828         if (skb->ip_summed != CHECKSUM_PARTIAL)
1829                 return 0;
1830
1831         if (!skb_is_gso(skb))
1832                 return 0;
1833
1834         DBGPR("  TSO packet to be processed\n");
1835
1836         return 1;
1837 }
1838
1839 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1840                              struct xgbe_ring *ring, struct sk_buff *skb,
1841                              struct xgbe_packet_data *packet)
1842 {
1843         struct skb_frag_struct *frag;
1844         unsigned int context_desc;
1845         unsigned int len;
1846         unsigned int i;
1847
1848         packet->skb = skb;
1849
1850         context_desc = 0;
1851         packet->rdesc_count = 0;
1852
1853         packet->tx_packets = 1;
1854         packet->tx_bytes = skb->len;
1855
1856         if (xgbe_is_tso(skb)) {
1857                 /* TSO requires an extra descriptor if mss is different */
1858                 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1859                         context_desc = 1;
1860                         packet->rdesc_count++;
1861                 }
1862
1863                 /* TSO requires an extra descriptor for TSO header */
1864                 packet->rdesc_count++;
1865
1866                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1867                                TSO_ENABLE, 1);
1868                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1869                                CSUM_ENABLE, 1);
1870         } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1871                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1872                                CSUM_ENABLE, 1);
1873
1874         if (xgbe_is_vxlan(pdata, skb))
1875                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1876                                VXLAN, 1);
1877
1878         if (skb_vlan_tag_present(skb)) {
1879                 /* VLAN requires an extra descriptor if tag is different */
1880                 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1881                         /* We can share with the TSO context descriptor */
1882                         if (!context_desc) {
1883                                 context_desc = 1;
1884                                 packet->rdesc_count++;
1885                         }
1886
1887                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1888                                VLAN_CTAG, 1);
1889         }
1890
1891         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1892             (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1893                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1894                                PTP, 1);
1895
1896         for (len = skb_headlen(skb); len;) {
1897                 packet->rdesc_count++;
1898                 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1899         }
1900
1901         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1902                 frag = &skb_shinfo(skb)->frags[i];
1903                 for (len = skb_frag_size(frag); len; ) {
1904                         packet->rdesc_count++;
1905                         len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1906                 }
1907         }
1908 }
1909
1910 static int xgbe_open(struct net_device *netdev)
1911 {
1912         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1913         int ret;
1914
1915         /* Create the various names based on netdev name */
1916         snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1917                  netdev_name(netdev));
1918
1919         snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1920                  netdev_name(netdev));
1921
1922         snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1923                  netdev_name(netdev));
1924
1925         /* Create workqueues */
1926         pdata->dev_workqueue =
1927                 create_singlethread_workqueue(netdev_name(netdev));
1928         if (!pdata->dev_workqueue) {
1929                 netdev_err(netdev, "device workqueue creation failed\n");
1930                 return -ENOMEM;
1931         }
1932
1933         pdata->an_workqueue =
1934                 create_singlethread_workqueue(pdata->an_name);
1935         if (!pdata->an_workqueue) {
1936                 netdev_err(netdev, "phy workqueue creation failed\n");
1937                 ret = -ENOMEM;
1938                 goto err_dev_wq;
1939         }
1940
1941         /* Reset the phy settings */
1942         ret = xgbe_phy_reset(pdata);
1943         if (ret)
1944                 goto err_an_wq;
1945
1946         /* Enable the clocks */
1947         ret = clk_prepare_enable(pdata->sysclk);
1948         if (ret) {
1949                 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1950                 goto err_an_wq;
1951         }
1952
1953         ret = clk_prepare_enable(pdata->ptpclk);
1954         if (ret) {
1955                 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1956                 goto err_sysclk;
1957         }
1958
1959         INIT_WORK(&pdata->service_work, xgbe_service);
1960         INIT_WORK(&pdata->restart_work, xgbe_restart);
1961         INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1962         INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1963
1964         ret = xgbe_alloc_memory(pdata);
1965         if (ret)
1966                 goto err_ptpclk;
1967
1968         ret = xgbe_start(pdata);
1969         if (ret)
1970                 goto err_mem;
1971
1972         clear_bit(XGBE_DOWN, &pdata->dev_state);
1973
1974         return 0;
1975
1976 err_mem:
1977         xgbe_free_memory(pdata);
1978
1979 err_ptpclk:
1980         clk_disable_unprepare(pdata->ptpclk);
1981
1982 err_sysclk:
1983         clk_disable_unprepare(pdata->sysclk);
1984
1985 err_an_wq:
1986         destroy_workqueue(pdata->an_workqueue);
1987
1988 err_dev_wq:
1989         destroy_workqueue(pdata->dev_workqueue);
1990
1991         return ret;
1992 }
1993
1994 static int xgbe_close(struct net_device *netdev)
1995 {
1996         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1997
1998         /* Stop the device */
1999         xgbe_stop(pdata);
2000
2001         xgbe_free_memory(pdata);
2002
2003         /* Disable the clocks */
2004         clk_disable_unprepare(pdata->ptpclk);
2005         clk_disable_unprepare(pdata->sysclk);
2006
2007         flush_workqueue(pdata->an_workqueue);
2008         destroy_workqueue(pdata->an_workqueue);
2009
2010         flush_workqueue(pdata->dev_workqueue);
2011         destroy_workqueue(pdata->dev_workqueue);
2012
2013         set_bit(XGBE_DOWN, &pdata->dev_state);
2014
2015         return 0;
2016 }
2017
2018 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
2019 {
2020         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2021         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2022         struct xgbe_desc_if *desc_if = &pdata->desc_if;
2023         struct xgbe_channel *channel;
2024         struct xgbe_ring *ring;
2025         struct xgbe_packet_data *packet;
2026         struct netdev_queue *txq;
2027         netdev_tx_t ret;
2028
2029         DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
2030
2031         channel = pdata->channel[skb->queue_mapping];
2032         txq = netdev_get_tx_queue(netdev, channel->queue_index);
2033         ring = channel->tx_ring;
2034         packet = &ring->packet_data;
2035
2036         ret = NETDEV_TX_OK;
2037
2038         if (skb->len == 0) {
2039                 netif_err(pdata, tx_err, netdev,
2040                           "empty skb received from stack\n");
2041                 dev_kfree_skb_any(skb);
2042                 goto tx_netdev_return;
2043         }
2044
2045         /* Calculate preliminary packet info */
2046         memset(packet, 0, sizeof(*packet));
2047         xgbe_packet_info(pdata, ring, skb, packet);
2048
2049         /* Check that there are enough descriptors available */
2050         ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
2051         if (ret)
2052                 goto tx_netdev_return;
2053
2054         ret = xgbe_prep_tso(skb, packet);
2055         if (ret) {
2056                 netif_err(pdata, tx_err, netdev,
2057                           "error processing TSO packet\n");
2058                 dev_kfree_skb_any(skb);
2059                 goto tx_netdev_return;
2060         }
2061         xgbe_prep_vlan(skb, packet);
2062
2063         if (!desc_if->map_tx_skb(channel, skb)) {
2064                 dev_kfree_skb_any(skb);
2065                 goto tx_netdev_return;
2066         }
2067
2068         xgbe_prep_tx_tstamp(pdata, skb, packet);
2069
2070         /* Report on the actual number of bytes (to be) sent */
2071         netdev_tx_sent_queue(txq, packet->tx_bytes);
2072
2073         /* Configure required descriptor fields for transmission */
2074         hw_if->dev_xmit(channel);
2075
2076         if (netif_msg_pktdata(pdata))
2077                 xgbe_print_pkt(netdev, skb, true);
2078
2079         /* Stop the queue in advance if there may not be enough descriptors */
2080         xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
2081
2082         ret = NETDEV_TX_OK;
2083
2084 tx_netdev_return:
2085         return ret;
2086 }
2087
2088 static void xgbe_set_rx_mode(struct net_device *netdev)
2089 {
2090         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2091         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2092
2093         DBGPR("-->xgbe_set_rx_mode\n");
2094
2095         hw_if->config_rx_mode(pdata);
2096
2097         DBGPR("<--xgbe_set_rx_mode\n");
2098 }
2099
2100 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
2101 {
2102         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2103         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2104         struct sockaddr *saddr = addr;
2105
2106         DBGPR("-->xgbe_set_mac_address\n");
2107
2108         if (!is_valid_ether_addr(saddr->sa_data))
2109                 return -EADDRNOTAVAIL;
2110
2111         memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
2112
2113         hw_if->set_mac_address(pdata, netdev->dev_addr);
2114
2115         DBGPR("<--xgbe_set_mac_address\n");
2116
2117         return 0;
2118 }
2119
2120 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
2121 {
2122         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2123         int ret;
2124
2125         switch (cmd) {
2126         case SIOCGHWTSTAMP:
2127                 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
2128                 break;
2129
2130         case SIOCSHWTSTAMP:
2131                 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
2132                 break;
2133
2134         default:
2135                 ret = -EOPNOTSUPP;
2136         }
2137
2138         return ret;
2139 }
2140
2141 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
2142 {
2143         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2144         int ret;
2145
2146         DBGPR("-->xgbe_change_mtu\n");
2147
2148         ret = xgbe_calc_rx_buf_size(netdev, mtu);
2149         if (ret < 0)
2150                 return ret;
2151
2152         pdata->rx_buf_size = ret;
2153         netdev->mtu = mtu;
2154
2155         xgbe_restart_dev(pdata);
2156
2157         DBGPR("<--xgbe_change_mtu\n");
2158
2159         return 0;
2160 }
2161
2162 static void xgbe_tx_timeout(struct net_device *netdev)
2163 {
2164         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2165
2166         netdev_warn(netdev, "tx timeout, device restarting\n");
2167         schedule_work(&pdata->restart_work);
2168 }
2169
2170 static void xgbe_get_stats64(struct net_device *netdev,
2171                              struct rtnl_link_stats64 *s)
2172 {
2173         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2174         struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2175
2176         DBGPR("-->%s\n", __func__);
2177
2178         pdata->hw_if.read_mmc_stats(pdata);
2179
2180         s->rx_packets = pstats->rxframecount_gb;
2181         s->rx_bytes = pstats->rxoctetcount_gb;
2182         s->rx_errors = pstats->rxframecount_gb -
2183                        pstats->rxbroadcastframes_g -
2184                        pstats->rxmulticastframes_g -
2185                        pstats->rxunicastframes_g;
2186         s->multicast = pstats->rxmulticastframes_g;
2187         s->rx_length_errors = pstats->rxlengtherror;
2188         s->rx_crc_errors = pstats->rxcrcerror;
2189         s->rx_fifo_errors = pstats->rxfifooverflow;
2190
2191         s->tx_packets = pstats->txframecount_gb;
2192         s->tx_bytes = pstats->txoctetcount_gb;
2193         s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
2194         s->tx_dropped = netdev->stats.tx_dropped;
2195
2196         DBGPR("<--%s\n", __func__);
2197 }
2198
2199 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
2200                                 u16 vid)
2201 {
2202         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2203         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2204
2205         DBGPR("-->%s\n", __func__);
2206
2207         set_bit(vid, pdata->active_vlans);
2208         hw_if->update_vlan_hash_table(pdata);
2209
2210         DBGPR("<--%s\n", __func__);
2211
2212         return 0;
2213 }
2214
2215 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
2216                                  u16 vid)
2217 {
2218         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2219         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2220
2221         DBGPR("-->%s\n", __func__);
2222
2223         clear_bit(vid, pdata->active_vlans);
2224         hw_if->update_vlan_hash_table(pdata);
2225
2226         DBGPR("<--%s\n", __func__);
2227
2228         return 0;
2229 }
2230
2231 #ifdef CONFIG_NET_POLL_CONTROLLER
2232 static void xgbe_poll_controller(struct net_device *netdev)
2233 {
2234         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2235         struct xgbe_channel *channel;
2236         unsigned int i;
2237
2238         DBGPR("-->xgbe_poll_controller\n");
2239
2240         if (pdata->per_channel_irq) {
2241                 for (i = 0; i < pdata->channel_count; i++) {
2242                         channel = pdata->channel[i];
2243                         xgbe_dma_isr(channel->dma_irq, channel);
2244                 }
2245         } else {
2246                 disable_irq(pdata->dev_irq);
2247                 xgbe_isr(pdata->dev_irq, pdata);
2248                 enable_irq(pdata->dev_irq);
2249         }
2250
2251         DBGPR("<--xgbe_poll_controller\n");
2252 }
2253 #endif /* End CONFIG_NET_POLL_CONTROLLER */
2254
2255 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
2256                          void *type_data)
2257 {
2258         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2259         struct tc_mqprio_qopt *mqprio = type_data;
2260         u8 tc;
2261
2262         if (type != TC_SETUP_QDISC_MQPRIO)
2263                 return -EOPNOTSUPP;
2264
2265         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2266         tc = mqprio->num_tc;
2267
2268         if (tc > pdata->hw_feat.tc_cnt)
2269                 return -EINVAL;
2270
2271         pdata->num_tcs = tc;
2272         pdata->hw_if.config_tc(pdata);
2273
2274         return 0;
2275 }
2276
2277 static netdev_features_t xgbe_fix_features(struct net_device *netdev,
2278                                            netdev_features_t features)
2279 {
2280         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2281         netdev_features_t vxlan_base, vxlan_mask;
2282
2283         vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
2284         vxlan_mask = vxlan_base | NETIF_F_GSO_UDP_TUNNEL_CSUM;
2285
2286         pdata->vxlan_features = features & vxlan_mask;
2287
2288         /* Only fix VXLAN-related features */
2289         if (!pdata->vxlan_features)
2290                 return features;
2291
2292         /* If VXLAN isn't supported then clear any features:
2293          *   This is needed because NETIF_F_RX_UDP_TUNNEL_PORT gets
2294          *   automatically set if ndo_udp_tunnel_add is set.
2295          */
2296         if (!pdata->hw_feat.vxn)
2297                 return features & ~vxlan_mask;
2298
2299         /* VXLAN CSUM requires VXLAN base */
2300         if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
2301             !(features & NETIF_F_GSO_UDP_TUNNEL)) {
2302                 netdev_notice(netdev,
2303                               "forcing tx udp tunnel support\n");
2304                 features |= NETIF_F_GSO_UDP_TUNNEL;
2305         }
2306
2307         /* Can't do one without doing the other */
2308         if ((features & vxlan_base) != vxlan_base) {
2309                 netdev_notice(netdev,
2310                               "forcing both tx and rx udp tunnel support\n");
2311                 features |= vxlan_base;
2312         }
2313
2314         if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2315                 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
2316                         netdev_notice(netdev,
2317                                       "forcing tx udp tunnel checksumming on\n");
2318                         features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2319                 }
2320         } else {
2321                 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
2322                         netdev_notice(netdev,
2323                                       "forcing tx udp tunnel checksumming off\n");
2324                         features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
2325                 }
2326         }
2327
2328         pdata->vxlan_features = features & vxlan_mask;
2329
2330         /* Adjust UDP Tunnel based on current state */
2331         if (pdata->vxlan_force_disable) {
2332                 netdev_notice(netdev,
2333                               "VXLAN acceleration disabled, turning off udp tunnel features\n");
2334                 features &= ~vxlan_mask;
2335         }
2336
2337         return features;
2338 }
2339
2340 static int xgbe_set_features(struct net_device *netdev,
2341                              netdev_features_t features)
2342 {
2343         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2344         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2345         netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
2346         netdev_features_t udp_tunnel;
2347         int ret = 0;
2348
2349         rxhash = pdata->netdev_features & NETIF_F_RXHASH;
2350         rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
2351         rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
2352         rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
2353         udp_tunnel = pdata->netdev_features & NETIF_F_GSO_UDP_TUNNEL;
2354
2355         if ((features & NETIF_F_RXHASH) && !rxhash)
2356                 ret = hw_if->enable_rss(pdata);
2357         else if (!(features & NETIF_F_RXHASH) && rxhash)
2358                 ret = hw_if->disable_rss(pdata);
2359         if (ret)
2360                 return ret;
2361
2362         if ((features & NETIF_F_RXCSUM) && !rxcsum)
2363                 hw_if->enable_rx_csum(pdata);
2364         else if (!(features & NETIF_F_RXCSUM) && rxcsum)
2365                 hw_if->disable_rx_csum(pdata);
2366
2367         if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
2368                 hw_if->enable_rx_vlan_stripping(pdata);
2369         else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
2370                 hw_if->disable_rx_vlan_stripping(pdata);
2371
2372         if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
2373                 hw_if->enable_rx_vlan_filtering(pdata);
2374         else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
2375                 hw_if->disable_rx_vlan_filtering(pdata);
2376
2377         if ((features & NETIF_F_GSO_UDP_TUNNEL) && !udp_tunnel)
2378                 xgbe_enable_vxlan_accel(pdata);
2379         else if (!(features & NETIF_F_GSO_UDP_TUNNEL) && udp_tunnel)
2380                 xgbe_disable_vxlan_accel(pdata);
2381
2382         pdata->netdev_features = features;
2383
2384         DBGPR("<--xgbe_set_features\n");
2385
2386         return 0;
2387 }
2388
2389 static void xgbe_udp_tunnel_add(struct net_device *netdev,
2390                                 struct udp_tunnel_info *ti)
2391 {
2392         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2393         struct xgbe_vxlan_data *vdata;
2394
2395         if (!pdata->hw_feat.vxn)
2396                 return;
2397
2398         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2399                 return;
2400
2401         pdata->vxlan_port_count++;
2402
2403         netif_dbg(pdata, drv, netdev,
2404                   "adding VXLAN tunnel, family=%hx/port=%hx\n",
2405                   ti->sa_family, be16_to_cpu(ti->port));
2406
2407         if (pdata->vxlan_force_disable)
2408                 return;
2409
2410         vdata = kzalloc(sizeof(*vdata), GFP_ATOMIC);
2411         if (!vdata) {
2412                 /* Can no longer properly track VXLAN ports */
2413                 pdata->vxlan_force_disable = 1;
2414                 netif_dbg(pdata, drv, netdev,
2415                           "internal error, disabling VXLAN accelerations\n");
2416
2417                 xgbe_disable_vxlan_accel(pdata);
2418
2419                 return;
2420         }
2421         vdata->sa_family = ti->sa_family;
2422         vdata->port = ti->port;
2423
2424         list_add_tail(&vdata->list, &pdata->vxlan_ports);
2425
2426         /* First port added? */
2427         if (pdata->vxlan_port_count == 1) {
2428                 xgbe_enable_vxlan_accel(pdata);
2429
2430                 return;
2431         }
2432 }
2433
2434 static void xgbe_udp_tunnel_del(struct net_device *netdev,
2435                                 struct udp_tunnel_info *ti)
2436 {
2437         struct xgbe_prv_data *pdata = netdev_priv(netdev);
2438         struct xgbe_vxlan_data *vdata;
2439
2440         if (!pdata->hw_feat.vxn)
2441                 return;
2442
2443         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2444                 return;
2445
2446         netif_dbg(pdata, drv, netdev,
2447                   "deleting VXLAN tunnel, family=%hx/port=%hx\n",
2448                   ti->sa_family, be16_to_cpu(ti->port));
2449
2450         /* Don't need safe version since loop terminates with deletion */
2451         list_for_each_entry(vdata, &pdata->vxlan_ports, list) {
2452                 if (vdata->sa_family != ti->sa_family)
2453                         continue;
2454
2455                 if (vdata->port != ti->port)
2456                         continue;
2457
2458                 list_del(&vdata->list);
2459                 kfree(vdata);
2460
2461                 break;
2462         }
2463
2464         pdata->vxlan_port_count--;
2465         if (!pdata->vxlan_port_count) {
2466                 xgbe_reset_vxlan_accel(pdata);
2467
2468                 return;
2469         }
2470
2471         if (pdata->vxlan_force_disable)
2472                 return;
2473
2474         /* See if VXLAN tunnel id needs to be changed */
2475         vdata = list_first_entry(&pdata->vxlan_ports,
2476                                  struct xgbe_vxlan_data, list);
2477         if (pdata->vxlan_port == be16_to_cpu(vdata->port))
2478                 return;
2479
2480         pdata->vxlan_port = be16_to_cpu(vdata->port);
2481         pdata->hw_if.set_vxlan_id(pdata);
2482 }
2483
2484 static netdev_features_t xgbe_features_check(struct sk_buff *skb,
2485                                              struct net_device *netdev,
2486                                              netdev_features_t features)
2487 {
2488         features = vlan_features_check(skb, features);
2489         features = vxlan_features_check(skb, features);
2490
2491         return features;
2492 }
2493
2494 static const struct net_device_ops xgbe_netdev_ops = {
2495         .ndo_open               = xgbe_open,
2496         .ndo_stop               = xgbe_close,
2497         .ndo_start_xmit         = xgbe_xmit,
2498         .ndo_set_rx_mode        = xgbe_set_rx_mode,
2499         .ndo_set_mac_address    = xgbe_set_mac_address,
2500         .ndo_validate_addr      = eth_validate_addr,
2501         .ndo_do_ioctl           = xgbe_ioctl,
2502         .ndo_change_mtu         = xgbe_change_mtu,
2503         .ndo_tx_timeout         = xgbe_tx_timeout,
2504         .ndo_get_stats64        = xgbe_get_stats64,
2505         .ndo_vlan_rx_add_vid    = xgbe_vlan_rx_add_vid,
2506         .ndo_vlan_rx_kill_vid   = xgbe_vlan_rx_kill_vid,
2507 #ifdef CONFIG_NET_POLL_CONTROLLER
2508         .ndo_poll_controller    = xgbe_poll_controller,
2509 #endif
2510         .ndo_setup_tc           = xgbe_setup_tc,
2511         .ndo_fix_features       = xgbe_fix_features,
2512         .ndo_set_features       = xgbe_set_features,
2513         .ndo_udp_tunnel_add     = xgbe_udp_tunnel_add,
2514         .ndo_udp_tunnel_del     = xgbe_udp_tunnel_del,
2515         .ndo_features_check     = xgbe_features_check,
2516 };
2517
2518 const struct net_device_ops *xgbe_get_netdev_ops(void)
2519 {
2520         return &xgbe_netdev_ops;
2521 }
2522
2523 static void xgbe_rx_refresh(struct xgbe_channel *channel)
2524 {
2525         struct xgbe_prv_data *pdata = channel->pdata;
2526         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2527         struct xgbe_desc_if *desc_if = &pdata->desc_if;
2528         struct xgbe_ring *ring = channel->rx_ring;
2529         struct xgbe_ring_data *rdata;
2530
2531         while (ring->dirty != ring->cur) {
2532                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2533
2534                 /* Reset rdata values */
2535                 desc_if->unmap_rdata(pdata, rdata);
2536
2537                 if (desc_if->map_rx_buffer(pdata, ring, rdata))
2538                         break;
2539
2540                 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
2541
2542                 ring->dirty++;
2543         }
2544
2545         /* Make sure everything is written before the register write */
2546         wmb();
2547
2548         /* Update the Rx Tail Pointer Register with address of
2549          * the last cleaned entry */
2550         rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
2551         XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2552                           lower_32_bits(rdata->rdesc_dma));
2553 }
2554
2555 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2556                                        struct napi_struct *napi,
2557                                        struct xgbe_ring_data *rdata,
2558                                        unsigned int len)
2559 {
2560         struct sk_buff *skb;
2561         u8 *packet;
2562
2563         skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
2564         if (!skb)
2565                 return NULL;
2566
2567         /* Pull in the header buffer which may contain just the header
2568          * or the header plus data
2569          */
2570         dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2571                                       rdata->rx.hdr.dma_off,
2572                                       rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
2573
2574         packet = page_address(rdata->rx.hdr.pa.pages) +
2575                  rdata->rx.hdr.pa.pages_offset;
2576         skb_copy_to_linear_data(skb, packet, len);
2577         skb_put(skb, len);
2578
2579         return skb;
2580 }
2581
2582 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2583                                      struct xgbe_packet_data *packet)
2584 {
2585         /* Always zero if not the first descriptor */
2586         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2587                 return 0;
2588
2589         /* First descriptor with split header, return header length */
2590         if (rdata->rx.hdr_len)
2591                 return rdata->rx.hdr_len;
2592
2593         /* First descriptor but not the last descriptor and no split header,
2594          * so the full buffer was used
2595          */
2596         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2597                 return rdata->rx.hdr.dma_len;
2598
2599         /* First descriptor and last descriptor and no split header, so
2600          * calculate how much of the buffer was used
2601          */
2602         return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2603 }
2604
2605 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2606                                      struct xgbe_packet_data *packet,
2607                                      unsigned int len)
2608 {
2609         /* Always the full buffer if not the last descriptor */
2610         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2611                 return rdata->rx.buf.dma_len;
2612
2613         /* Last descriptor so calculate how much of the buffer was used
2614          * for the last bit of data
2615          */
2616         return rdata->rx.len - len;
2617 }
2618
2619 static int xgbe_tx_poll(struct xgbe_channel *channel)
2620 {
2621         struct xgbe_prv_data *pdata = channel->pdata;
2622         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2623         struct xgbe_desc_if *desc_if = &pdata->desc_if;
2624         struct xgbe_ring *ring = channel->tx_ring;
2625         struct xgbe_ring_data *rdata;
2626         struct xgbe_ring_desc *rdesc;
2627         struct net_device *netdev = pdata->netdev;
2628         struct netdev_queue *txq;
2629         int processed = 0;
2630         unsigned int tx_packets = 0, tx_bytes = 0;
2631         unsigned int cur;
2632
2633         DBGPR("-->xgbe_tx_poll\n");
2634
2635         /* Nothing to do if there isn't a Tx ring for this channel */
2636         if (!ring)
2637                 return 0;
2638
2639         cur = ring->cur;
2640
2641         /* Be sure we get ring->cur before accessing descriptor data */
2642         smp_rmb();
2643
2644         txq = netdev_get_tx_queue(netdev, channel->queue_index);
2645
2646         while ((processed < XGBE_TX_DESC_MAX_PROC) &&
2647                (ring->dirty != cur)) {
2648                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2649                 rdesc = rdata->rdesc;
2650
2651                 if (!hw_if->tx_complete(rdesc))
2652                         break;
2653
2654                 /* Make sure descriptor fields are read after reading the OWN
2655                  * bit */
2656                 dma_rmb();
2657
2658                 if (netif_msg_tx_done(pdata))
2659                         xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
2660
2661                 if (hw_if->is_last_desc(rdesc)) {
2662                         tx_packets += rdata->tx.packets;
2663                         tx_bytes += rdata->tx.bytes;
2664                 }
2665
2666                 /* Free the SKB and reset the descriptor for re-use */
2667                 desc_if->unmap_rdata(pdata, rdata);
2668                 hw_if->tx_desc_reset(rdata);
2669
2670                 processed++;
2671                 ring->dirty++;
2672         }
2673
2674         if (!processed)
2675                 return 0;
2676
2677         netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2678
2679         if ((ring->tx.queue_stopped == 1) &&
2680             (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
2681                 ring->tx.queue_stopped = 0;
2682                 netif_tx_wake_queue(txq);
2683         }
2684
2685         DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2686
2687         return processed;
2688 }
2689
2690 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2691 {
2692         struct xgbe_prv_data *pdata = channel->pdata;
2693         struct xgbe_hw_if *hw_if = &pdata->hw_if;
2694         struct xgbe_ring *ring = channel->rx_ring;
2695         struct xgbe_ring_data *rdata;
2696         struct xgbe_packet_data *packet;
2697         struct net_device *netdev = pdata->netdev;
2698         struct napi_struct *napi;
2699         struct sk_buff *skb;
2700         struct skb_shared_hwtstamps *hwtstamps;
2701         unsigned int last, error, context_next, context;
2702         unsigned int len, buf1_len, buf2_len, max_len;
2703         unsigned int received = 0;
2704         int packet_count = 0;
2705
2706         DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2707
2708         /* Nothing to do if there isn't a Rx ring for this channel */
2709         if (!ring)
2710                 return 0;
2711
2712         last = 0;
2713         context_next = 0;
2714
2715         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2716
2717         rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2718         packet = &ring->packet_data;
2719         while (packet_count < budget) {
2720                 DBGPR("  cur = %d\n", ring->cur);
2721
2722                 /* First time in loop see if we need to restore state */
2723                 if (!received && rdata->state_saved) {
2724                         skb = rdata->state.skb;
2725                         error = rdata->state.error;
2726                         len = rdata->state.len;
2727                 } else {
2728                         memset(packet, 0, sizeof(*packet));
2729                         skb = NULL;
2730                         error = 0;
2731                         len = 0;
2732                 }
2733
2734 read_again:
2735                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2736
2737                 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
2738                         xgbe_rx_refresh(channel);
2739
2740                 if (hw_if->dev_read(channel))
2741                         break;
2742
2743                 received++;
2744                 ring->cur++;
2745
2746                 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2747                                       LAST);
2748                 context_next = XGMAC_GET_BITS(packet->attributes,
2749                                               RX_PACKET_ATTRIBUTES,
2750                                               CONTEXT_NEXT);
2751                 context = XGMAC_GET_BITS(packet->attributes,
2752                                          RX_PACKET_ATTRIBUTES,
2753                                          CONTEXT);
2754
2755                 /* Earlier error, just drain the remaining data */
2756                 if ((!last || context_next) && error)
2757                         goto read_again;
2758
2759                 if (error || packet->errors) {
2760                         if (packet->errors)
2761                                 netif_err(pdata, rx_err, netdev,
2762                                           "error in received packet\n");
2763                         dev_kfree_skb(skb);
2764                         goto next_packet;
2765                 }
2766
2767                 if (!context) {
2768                         /* Get the data length in the descriptor buffers */
2769                         buf1_len = xgbe_rx_buf1_len(rdata, packet);
2770                         len += buf1_len;
2771                         buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2772                         len += buf2_len;
2773
2774                         if (buf2_len > rdata->rx.buf.dma_len) {
2775                                 /* Hardware inconsistency within the descriptors
2776                                  * that has resulted in a length underflow.
2777                                  */
2778                                 error = 1;
2779                                 goto skip_data;
2780                         }
2781
2782                         if (!skb) {
2783                                 skb = xgbe_create_skb(pdata, napi, rdata,
2784                                                       buf1_len);
2785                                 if (!skb) {
2786                                         error = 1;
2787                                         goto skip_data;
2788                                 }
2789                         }
2790
2791                         if (buf2_len) {
2792                                 dma_sync_single_range_for_cpu(pdata->dev,
2793                                                         rdata->rx.buf.dma_base,
2794                                                         rdata->rx.buf.dma_off,
2795                                                         rdata->rx.buf.dma_len,
2796                                                         DMA_FROM_DEVICE);
2797
2798                                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2799                                                 rdata->rx.buf.pa.pages,
2800                                                 rdata->rx.buf.pa.pages_offset,
2801                                                 buf2_len,
2802                                                 rdata->rx.buf.dma_len);
2803                                 rdata->rx.buf.pa.pages = NULL;
2804                         }
2805                 }
2806
2807 skip_data:
2808                 if (!last || context_next)
2809                         goto read_again;
2810
2811                 if (!skb || error) {
2812                         dev_kfree_skb(skb);
2813                         goto next_packet;
2814                 }
2815
2816                 /* Be sure we don't exceed the configured MTU */
2817                 max_len = netdev->mtu + ETH_HLEN;
2818                 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2819                     (skb->protocol == htons(ETH_P_8021Q)))
2820                         max_len += VLAN_HLEN;
2821
2822                 if (skb->len > max_len) {
2823                         netif_err(pdata, rx_err, netdev,
2824                                   "packet length exceeds configured MTU\n");
2825                         dev_kfree_skb(skb);
2826                         goto next_packet;
2827                 }
2828
2829                 if (netif_msg_pktdata(pdata))
2830                         xgbe_print_pkt(netdev, skb, false);
2831
2832                 skb_checksum_none_assert(skb);
2833                 if (XGMAC_GET_BITS(packet->attributes,
2834                                    RX_PACKET_ATTRIBUTES, CSUM_DONE))
2835                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2836
2837                 if (XGMAC_GET_BITS(packet->attributes,
2838                                    RX_PACKET_ATTRIBUTES, TNP)) {
2839                         skb->encapsulation = 1;
2840
2841                         if (XGMAC_GET_BITS(packet->attributes,
2842                                            RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2843                                 skb->csum_level = 1;
2844                 }
2845
2846                 if (XGMAC_GET_BITS(packet->attributes,
2847                                    RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2848                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2849                                                packet->vlan_ctag);
2850
2851                 if (XGMAC_GET_BITS(packet->attributes,
2852                                    RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2853                         u64 nsec;
2854
2855                         nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2856                                                     packet->rx_tstamp);
2857                         hwtstamps = skb_hwtstamps(skb);
2858                         hwtstamps->hwtstamp = ns_to_ktime(nsec);
2859                 }
2860
2861                 if (XGMAC_GET_BITS(packet->attributes,
2862                                    RX_PACKET_ATTRIBUTES, RSS_HASH))
2863                         skb_set_hash(skb, packet->rss_hash,
2864                                      packet->rss_hash_type);
2865
2866                 skb->dev = netdev;
2867                 skb->protocol = eth_type_trans(skb, netdev);
2868                 skb_record_rx_queue(skb, channel->queue_index);
2869
2870                 napi_gro_receive(napi, skb);
2871
2872 next_packet:
2873                 packet_count++;
2874         }
2875
2876         /* Check if we need to save state before leaving */
2877         if (received && (!last || context_next)) {
2878                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2879                 rdata->state_saved = 1;
2880                 rdata->state.skb = skb;
2881                 rdata->state.len = len;
2882                 rdata->state.error = error;
2883         }
2884
2885         DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2886
2887         return packet_count;
2888 }
2889
2890 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2891 {
2892         struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2893                                                     napi);
2894         struct xgbe_prv_data *pdata = channel->pdata;
2895         int processed = 0;
2896
2897         DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2898
2899         /* Cleanup Tx ring first */
2900         xgbe_tx_poll(channel);
2901
2902         /* Process Rx ring next */
2903         processed = xgbe_rx_poll(channel, budget);
2904
2905         /* If we processed everything, we are done */
2906         if ((processed < budget) && napi_complete_done(napi, processed)) {
2907                 /* Enable Tx and Rx interrupts */
2908                 if (pdata->channel_irq_mode)
2909                         xgbe_enable_rx_tx_int(pdata, channel);
2910                 else
2911                         enable_irq(channel->dma_irq);
2912         }
2913
2914         DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2915
2916         return processed;
2917 }
2918
2919 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2920 {
2921         struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2922                                                    napi);
2923         struct xgbe_channel *channel;
2924         int ring_budget;
2925         int processed, last_processed;
2926         unsigned int i;
2927
2928         DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2929
2930         processed = 0;
2931         ring_budget = budget / pdata->rx_ring_count;
2932         do {
2933                 last_processed = processed;
2934
2935                 for (i = 0; i < pdata->channel_count; i++) {
2936                         channel = pdata->channel[i];
2937
2938                         /* Cleanup Tx ring first */
2939                         xgbe_tx_poll(channel);
2940
2941                         /* Process Rx ring next */
2942                         if (ring_budget > (budget - processed))
2943                                 ring_budget = budget - processed;
2944                         processed += xgbe_rx_poll(channel, ring_budget);
2945                 }
2946         } while ((processed < budget) && (processed != last_processed));
2947
2948         /* If we processed everything, we are done */
2949         if ((processed < budget) && napi_complete_done(napi, processed)) {
2950                 /* Enable Tx and Rx interrupts */
2951                 xgbe_enable_rx_tx_ints(pdata);
2952         }
2953
2954         DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2955
2956         return processed;
2957 }
2958
2959 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2960                        unsigned int idx, unsigned int count, unsigned int flag)
2961 {
2962         struct xgbe_ring_data *rdata;
2963         struct xgbe_ring_desc *rdesc;
2964
2965         while (count--) {
2966                 rdata = XGBE_GET_DESC_DATA(ring, idx);
2967                 rdesc = rdata->rdesc;
2968                 netdev_dbg(pdata->netdev,
2969                            "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2970                            (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2971                            le32_to_cpu(rdesc->desc0),
2972                            le32_to_cpu(rdesc->desc1),
2973                            le32_to_cpu(rdesc->desc2),
2974                            le32_to_cpu(rdesc->desc3));
2975                 idx++;
2976         }
2977 }
2978
2979 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2980                        unsigned int idx)
2981 {
2982         struct xgbe_ring_data *rdata;
2983         struct xgbe_ring_desc *rdesc;
2984
2985         rdata = XGBE_GET_DESC_DATA(ring, idx);
2986         rdesc = rdata->rdesc;
2987         netdev_dbg(pdata->netdev,
2988                    "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2989                    idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2990                    le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2991 }
2992
2993 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2994 {
2995         struct ethhdr *eth = (struct ethhdr *)skb->data;
2996         unsigned char buffer[128];
2997         unsigned int i;
2998
2999         netdev_dbg(netdev, "\n************** SKB dump ****************\n");
3000
3001         netdev_dbg(netdev, "%s packet of %d bytes\n",
3002                    (tx_rx ? "TX" : "RX"), skb->len);
3003
3004         netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
3005         netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
3006         netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
3007
3008         for (i = 0; i < skb->len; i += 32) {
3009                 unsigned int len = min(skb->len - i, 32U);
3010
3011                 hex_dump_to_buffer(&skb->data[i], len, 32, 1,
3012                                    buffer, sizeof(buffer), false);
3013                 netdev_dbg(netdev, "  %#06x: %s\n", i, buffer);
3014         }
3015
3016         netdev_dbg(netdev, "\n************** SKB dump ****************\n");
3017 }