drivers/net/ethernet/amd/xgbe/xgbe-drv.c

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #include <linux/platform_device.h>
 118 #include <linux/spinlock.h>
 119 #include <linux/tcp.h>
 120 #include <linux/if_vlan.h>
 121 #include <net/busy_poll.h>
 122 #include <linux/clk.h>
 123 #include <linux/if_ether.h>
 124 #include <linux/net_tstamp.h>
 125 #include <linux/phy.h>
 126
 127 #include "xgbe.h"
 128 #include "xgbe-common.h"
 129
 130 static int xgbe_one_poll(struct napi_struct *, int);
 131 static int xgbe_all_poll(struct napi_struct *, int);
 132
 133 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
 134 {
 135         struct xgbe_channel *channel_mem, *channel;
 136         struct xgbe_ring *tx_ring, *rx_ring;
 137         unsigned int count, i;
 138         int ret = -ENOMEM;
 139
 140         count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
 141
 142         channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL);
 143         if (!channel_mem)
 144                 goto err_channel;
 145
 146         tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring),
 147                           GFP_KERNEL);
 148         if (!tx_ring)
 149                 goto err_tx_ring;
 150
 151         rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring),
 152                           GFP_KERNEL);
 153         if (!rx_ring)
 154                 goto err_rx_ring;
 155
 156         for (i = 0, channel = channel_mem; i < count; i++, channel++) {
 157                 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
 158                 channel->pdata = pdata;
 159                 channel->queue_index = i;
 160                 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
 161                                     (DMA_CH_INC * i);
 162
 163                 if (pdata->per_channel_irq) {
 164                         /* Get the DMA interrupt (offset 1) */
 165                         ret = platform_get_irq(pdata->pdev, i + 1);
 166                         if (ret < 0) {
 167                                 netdev_err(pdata->netdev,
 168                                            "platform_get_irq %u failed\n",
 169                                            i + 1);
 170                                 goto err_irq;
 171                         }
 172
 173                         channel->dma_irq = ret;
 174                 }
 175
 176                 if (i < pdata->tx_ring_count) {
 177                         spin_lock_init(&tx_ring->lock);
 178                         channel->tx_ring = tx_ring++;
 179                 }
 180
 181                 if (i < pdata->rx_ring_count) {
 182                         spin_lock_init(&rx_ring->lock);
 183                         channel->rx_ring = rx_ring++;
 184                 }
 185
 186                 netif_dbg(pdata, drv, pdata->netdev,
 187                           "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
 188                           channel->name, channel->dma_regs, channel->dma_irq,
 189                           channel->tx_ring, channel->rx_ring);
 190         }
 191
 192         pdata->channel = channel_mem;
 193         pdata->channel_count = count;
 194
 195         return 0;
 196
 197 err_irq:
 198         kfree(rx_ring);
 199
 200 err_rx_ring:
 201         kfree(tx_ring);
 202
 203 err_tx_ring:
 204         kfree(channel_mem);
 205
 206 err_channel:
 207         return ret;
 208 }
 209
 210 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
 211 {
 212         if (!pdata->channel)
 213                 return;
 214
 215         kfree(pdata->channel->rx_ring);
 216         kfree(pdata->channel->tx_ring);
 217         kfree(pdata->channel);
 218
 219         pdata->channel = NULL;
 220         pdata->channel_count = 0;
 221 }
 222
 223 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
 224 {
 225         return (ring->rdesc_count - (ring->cur - ring->dirty));
 226 }
 227
 228 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
 229 {
 230         return (ring->cur - ring->dirty);
 231 }
 232
 233 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
 234                                     struct xgbe_ring *ring, unsigned int count)
 235 {
 236         struct xgbe_prv_data *pdata = channel->pdata;
 237
 238         if (count > xgbe_tx_avail_desc(ring)) {
 239                 netif_info(pdata, drv, pdata->netdev,
 240                            "Tx queue stopped, not enough descriptors available\n");
 241                 netif_stop_subqueue(pdata->netdev, channel->queue_index);
 242                 ring->tx.queue_stopped = 1;
 243
 244                 /* If we haven't notified the hardware because of xmit_more
 245                  * support, tell it now
 246                  */
 247                 if (ring->tx.xmit_more)
 248                         pdata->hw_if.tx_start_xmit(channel, ring);
 249
 250                 return NETDEV_TX_BUSY;
 251         }
 252
 253         return 0;
 254 }
 255
 256 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
 257 {
 258         unsigned int rx_buf_size;
 259
 260         if (mtu > XGMAC_JUMBO_PACKET_MTU) {
 261                 netdev_alert(netdev, "MTU exceeds maximum supported value\n");
 262                 return -EINVAL;
 263         }
 264
 265         rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
 266         rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
 267
 268         rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
 269                       ~(XGBE_RX_BUF_ALIGN - 1);
 270
 271         return rx_buf_size;
 272 }
 273
 274 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
 275 {
 276         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 277         struct xgbe_channel *channel;
 278         enum xgbe_int int_id;
 279         unsigned int i;
 280
 281         channel = pdata->channel;
 282         for (i = 0; i < pdata->channel_count; i++, channel++) {
 283                 if (channel->tx_ring && channel->rx_ring)
 284                         int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 285                 else if (channel->tx_ring)
 286                         int_id = XGMAC_INT_DMA_CH_SR_TI;
 287                 else if (channel->rx_ring)
 288                         int_id = XGMAC_INT_DMA_CH_SR_RI;
 289                 else
 290                         continue;
 291
 292                 hw_if->enable_int(channel, int_id);
 293         }
 294 }
 295
 296 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
 297 {
 298         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 299         struct xgbe_channel *channel;
 300         enum xgbe_int int_id;
 301         unsigned int i;
 302
 303         channel = pdata->channel;
 304         for (i = 0; i < pdata->channel_count; i++, channel++) {
 305                 if (channel->tx_ring && channel->rx_ring)
 306                         int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 307                 else if (channel->tx_ring)
 308                         int_id = XGMAC_INT_DMA_CH_SR_TI;
 309                 else if (channel->rx_ring)
 310                         int_id = XGMAC_INT_DMA_CH_SR_RI;
 311                 else
 312                         continue;
 313
 314                 hw_if->disable_int(channel, int_id);
 315         }
 316 }
 317
 318 static irqreturn_t xgbe_isr(int irq, void *data)
 319 {
 320         struct xgbe_prv_data *pdata = data;
 321         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 322         struct xgbe_channel *channel;
 323         unsigned int dma_isr, dma_ch_isr;
 324         unsigned int mac_isr, mac_tssr;
 325         unsigned int i;
 326
 327         /* The DMA interrupt status register also reports MAC and MTL
 328          * interrupts. So for polling mode, we just need to check for
 329          * this register to be non-zero
 330          */
 331         dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
 332         if (!dma_isr)
 333                 goto isr_done;
 334
 335         netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
 336
 337         for (i = 0; i < pdata->channel_count; i++) {
 338                 if (!(dma_isr & (1 << i)))
 339                         continue;
 340
 341                 channel = pdata->channel + i;
 342
 343                 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
 344                 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
 345                           i, dma_ch_isr);
 346
 347                 /* The TI or RI interrupt bits may still be set even if using
 348                  * per channel DMA interrupts. Check to be sure those are not
 349                  * enabled before using the private data napi structure.
 350                  */
 351                 if (!pdata->per_channel_irq &&
 352                     (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
 353                      XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
 354                         if (napi_schedule_prep(&pdata->napi)) {
 355                                 /* Disable Tx and Rx interrupts */
 356                                 xgbe_disable_rx_tx_ints(pdata);
 357
 358                                 /* Turn on polling */
 359                                 __napi_schedule_irqoff(&pdata->napi);
 360                         }
 361                 }
 362
 363                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
 364                         pdata->ext_stats.rx_buffer_unavailable++;
 365
 366                 /* Restart the device on a Fatal Bus Error */
 367                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
 368                         schedule_work(&pdata->restart_work);
 369
 370                 /* Clear all interrupt signals */
 371                 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
 372         }
 373
 374         if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
 375                 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
 376
 377                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
 378                         hw_if->tx_mmc_int(pdata);
 379
 380                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
 381                         hw_if->rx_mmc_int(pdata);
 382
 383                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
 384                         mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
 385
 386                         if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
 387                                 /* Read Tx Timestamp to clear interrupt */
 388                                 pdata->tx_tstamp =
 389                                         hw_if->get_tx_tstamp(pdata);
 390                                 queue_work(pdata->dev_workqueue,
 391                                            &pdata->tx_tstamp_work);
 392                         }
 393                 }
 394         }
 395
 396 isr_done:
 397         return IRQ_HANDLED;
 398 }
 399
 400 static irqreturn_t xgbe_dma_isr(int irq, void *data)
 401 {
 402         struct xgbe_channel *channel = data;
 403
 404         /* Per channel DMA interrupts are enabled, so we use the per
 405          * channel napi structure and not the private data napi structure
 406          */
 407         if (napi_schedule_prep(&channel->napi)) {
 408                 /* Disable Tx and Rx interrupts */
 409                 disable_irq_nosync(channel->dma_irq);
 410
 411                 /* Turn on polling */
 412                 __napi_schedule_irqoff(&channel->napi);
 413         }
 414
 415         return IRQ_HANDLED;
 416 }
 417
 418 static void xgbe_tx_timer(unsigned long data)
 419 {
 420         struct xgbe_channel *channel = (struct xgbe_channel *)data;
 421         struct xgbe_prv_data *pdata = channel->pdata;
 422         struct napi_struct *napi;
 423
 424         DBGPR("-->xgbe_tx_timer\n");
 425
 426         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
 427
 428         if (napi_schedule_prep(napi)) {
 429                 /* Disable Tx and Rx interrupts */
 430                 if (pdata->per_channel_irq)
 431                         disable_irq_nosync(channel->dma_irq);
 432                 else
 433                         xgbe_disable_rx_tx_ints(pdata);
 434
 435                 /* Turn on polling */
 436                 __napi_schedule(napi);
 437         }
 438
 439         channel->tx_timer_active = 0;
 440
 441         DBGPR("<--xgbe_tx_timer\n");
 442 }
 443
 444 static void xgbe_service(struct work_struct *work)
 445 {
 446         struct xgbe_prv_data *pdata = container_of(work,
 447                                                    struct xgbe_prv_data,
 448                                                    service_work);
 449
 450         pdata->phy_if.phy_status(pdata);
 451 }
 452
 453 static void xgbe_service_timer(unsigned long data)
 454 {
 455         struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
 456
 457         queue_work(pdata->dev_workqueue, &pdata->service_work);
 458
 459         mod_timer(&pdata->service_timer, jiffies + HZ);
 460 }
 461
 462 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
 463 {
 464         struct xgbe_channel *channel;
 465         unsigned int i;
 466
 467         setup_timer(&pdata->service_timer, xgbe_service_timer,
 468                     (unsigned long)pdata);
 469
 470         channel = pdata->channel;
 471         for (i = 0; i < pdata->channel_count; i++, channel++) {
 472                 if (!channel->tx_ring)
 473                         break;
 474
 475                 setup_timer(&channel->tx_timer, xgbe_tx_timer,
 476                             (unsigned long)channel);
 477         }
 478 }
 479
 480 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
 481 {
 482         mod_timer(&pdata->service_timer, jiffies + HZ);
 483 }
 484
 485 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
 486 {
 487         struct xgbe_channel *channel;
 488         unsigned int i;
 489
 490         del_timer_sync(&pdata->service_timer);
 491
 492         channel = pdata->channel;
 493         for (i = 0; i < pdata->channel_count; i++, channel++) {
 494                 if (!channel->tx_ring)
 495                         break;
 496
 497                 /* Deactivate the Tx timer */
 498                 del_timer_sync(&channel->tx_timer);
 499                 channel->tx_timer_active = 0;
 500         }
 501 }
 502
 503 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
 504 {
 505         unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
 506         struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
 507
 508         DBGPR("-->xgbe_get_all_hw_features\n");
 509
 510         mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
 511         mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
 512         mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
 513
 514         memset(hw_feat, 0, sizeof(*hw_feat));
 515
 516         hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
 517
 518         /* Hardware feature register 0 */
 519         hw_feat->gmii        = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
 520         hw_feat->vlhash      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
 521         hw_feat->sma         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
 522         hw_feat->rwk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
 523         hw_feat->mgk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
 524         hw_feat->mmc         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
 525         hw_feat->aoe         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
 526         hw_feat->ts          = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
 527         hw_feat->eee         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
 528         hw_feat->tx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
 529         hw_feat->rx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
 530         hw_feat->addn_mac    = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
 531                                               ADDMACADRSEL);
 532         hw_feat->ts_src      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
 533         hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
 534
 535         /* Hardware feature register 1 */
 536         hw_feat->rx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 537                                                 RXFIFOSIZE);
 538         hw_feat->tx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 539                                                 TXFIFOSIZE);
 540         hw_feat->adv_ts_hi     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
 541         hw_feat->dma_width     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
 542         hw_feat->dcb           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
 543         hw_feat->sph           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
 544         hw_feat->tso           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
 545         hw_feat->dma_debug     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
 546         hw_feat->rss           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
 547         hw_feat->tc_cnt        = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
 548         hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 549                                                   HASHTBLSZ);
 550         hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 551                                                   L3L4FNUM);
 552
 553         /* Hardware feature register 2 */
 554         hw_feat->rx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
 555         hw_feat->tx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
 556         hw_feat->rx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
 557         hw_feat->tx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
 558         hw_feat->pps_out_num  = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
 559         hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
 560
 561         /* Translate the Hash Table size into actual number */
 562         switch (hw_feat->hash_table_size) {
 563         case 0:
 564                 break;
 565         case 1:
 566                 hw_feat->hash_table_size = 64;
 567                 break;
 568         case 2:
 569                 hw_feat->hash_table_size = 128;
 570                 break;
 571         case 3:
 572                 hw_feat->hash_table_size = 256;
 573                 break;
 574         }
 575
 576         /* Translate the address width setting into actual number */
 577         switch (hw_feat->dma_width) {
 578         case 0:
 579                 hw_feat->dma_width = 32;
 580                 break;
 581         case 1:
 582                 hw_feat->dma_width = 40;
 583                 break;
 584         case 2:
 585                 hw_feat->dma_width = 48;
 586                 break;
 587         default:
 588                 hw_feat->dma_width = 32;
 589         }
 590
 591         /* The Queue, Channel and TC counts are zero based so increment them
 592          * to get the actual number
 593          */
 594         hw_feat->rx_q_cnt++;
 595         hw_feat->tx_q_cnt++;
 596         hw_feat->rx_ch_cnt++;
 597         hw_feat->tx_ch_cnt++;
 598         hw_feat->tc_cnt++;
 599
 600         DBGPR("<--xgbe_get_all_hw_features\n");
 601 }
 602
 603 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
 604 {
 605         struct xgbe_channel *channel;
 606         unsigned int i;
 607
 608         if (pdata->per_channel_irq) {
 609                 channel = pdata->channel;
 610                 for (i = 0; i < pdata->channel_count; i++, channel++) {
 611                         if (add)
 612                                 netif_napi_add(pdata->netdev, &channel->napi,
 613                                                xgbe_one_poll, NAPI_POLL_WEIGHT);
 614
 615                         napi_enable(&channel->napi);
 616                 }
 617         } else {
 618                 if (add)
 619                         netif_napi_add(pdata->netdev, &pdata->napi,
 620                                        xgbe_all_poll, NAPI_POLL_WEIGHT);
 621
 622                 napi_enable(&pdata->napi);
 623         }
 624 }
 625
 626 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
 627 {
 628         struct xgbe_channel *channel;
 629         unsigned int i;
 630
 631         if (pdata->per_channel_irq) {
 632                 channel = pdata->channel;
 633                 for (i = 0; i < pdata->channel_count; i++, channel++) {
 634                         napi_disable(&channel->napi);
 635
 636                         if (del)
 637                                 netif_napi_del(&channel->napi);
 638                 }
 639         } else {
 640                 napi_disable(&pdata->napi);
 641
 642                 if (del)
 643                         netif_napi_del(&pdata->napi);
 644         }
 645 }
 646
 647 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
 648 {
 649         struct xgbe_channel *channel;
 650         struct net_device *netdev = pdata->netdev;
 651         unsigned int i;
 652         int ret;
 653
 654         ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
 655                                netdev->name, pdata);
 656         if (ret) {
 657                 netdev_alert(netdev, "error requesting irq %d\n",
 658                              pdata->dev_irq);
 659                 return ret;
 660         }
 661
 662         if (!pdata->per_channel_irq)
 663                 return 0;
 664
 665         channel = pdata->channel;
 666         for (i = 0; i < pdata->channel_count; i++, channel++) {
 667                 snprintf(channel->dma_irq_name,
 668                          sizeof(channel->dma_irq_name) - 1,
 669                          "%s-TxRx-%u", netdev_name(netdev),
 670                          channel->queue_index);
 671
 672                 ret = devm_request_irq(pdata->dev, channel->dma_irq,
 673                                        xgbe_dma_isr, 0,
 674                                        channel->dma_irq_name, channel);
 675                 if (ret) {
 676                         netdev_alert(netdev, "error requesting irq %d\n",
 677                                      channel->dma_irq);
 678                         goto err_irq;
 679                 }
 680         }
 681
 682         return 0;
 683
 684 err_irq:
 685         /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
 686         for (i--, channel--; i < pdata->channel_count; i--, channel--)
 687                 devm_free_irq(pdata->dev, channel->dma_irq, channel);
 688
 689         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
 690
 691         return ret;
 692 }
 693
 694 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
 695 {
 696         struct xgbe_channel *channel;
 697         unsigned int i;
 698
 699         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
 700
 701         if (!pdata->per_channel_irq)
 702                 return;
 703
 704         channel = pdata->channel;
 705         for (i = 0; i < pdata->channel_count; i++, channel++)
 706                 devm_free_irq(pdata->dev, channel->dma_irq, channel);
 707 }
 708
 709 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
 710 {
 711         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 712
 713         DBGPR("-->xgbe_init_tx_coalesce\n");
 714
 715         pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
 716         pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
 717
 718         hw_if->config_tx_coalesce(pdata);
 719
 720         DBGPR("<--xgbe_init_tx_coalesce\n");
 721 }
 722
 723 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
 724 {
 725         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 726
 727         DBGPR("-->xgbe_init_rx_coalesce\n");
 728
 729         pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
 730         pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
 731         pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
 732
 733         hw_if->config_rx_coalesce(pdata);
 734
 735         DBGPR("<--xgbe_init_rx_coalesce\n");
 736 }
 737
 738 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
 739 {
 740         struct xgbe_desc_if *desc_if = &pdata->desc_if;
 741         struct xgbe_channel *channel;
 742         struct xgbe_ring *ring;
 743         struct xgbe_ring_data *rdata;
 744         unsigned int i, j;
 745
 746         DBGPR("-->xgbe_free_tx_data\n");
 747
 748         channel = pdata->channel;
 749         for (i = 0; i < pdata->channel_count; i++, channel++) {
 750                 ring = channel->tx_ring;
 751                 if (!ring)
 752                         break;
 753
 754                 for (j = 0; j < ring->rdesc_count; j++) {
 755                         rdata = XGBE_GET_DESC_DATA(ring, j);
 756                         desc_if->unmap_rdata(pdata, rdata);
 757                 }
 758         }
 759
 760         DBGPR("<--xgbe_free_tx_data\n");
 761 }
 762
 763 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
 764 {
 765         struct xgbe_desc_if *desc_if = &pdata->desc_if;
 766         struct xgbe_channel *channel;
 767         struct xgbe_ring *ring;
 768         struct xgbe_ring_data *rdata;
 769         unsigned int i, j;
 770
 771         DBGPR("-->xgbe_free_rx_data\n");
 772
 773         channel = pdata->channel;
 774         for (i = 0; i < pdata->channel_count; i++, channel++) {
 775                 ring = channel->rx_ring;
 776                 if (!ring)
 777                         break;
 778
 779                 for (j = 0; j < ring->rdesc_count; j++) {
 780                         rdata = XGBE_GET_DESC_DATA(ring, j);
 781                         desc_if->unmap_rdata(pdata, rdata);
 782                 }
 783         }
 784
 785         DBGPR("<--xgbe_free_rx_data\n");
 786 }
 787
 788 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
 789 {
 790         pdata->phy_link = -1;
 791         pdata->phy_speed = SPEED_UNKNOWN;
 792
 793         return pdata->phy_if.phy_reset(pdata);
 794 }
 795
 796 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
 797 {
 798         struct xgbe_prv_data *pdata = netdev_priv(netdev);
 799         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 800         unsigned long flags;
 801
 802         DBGPR("-->xgbe_powerdown\n");
 803
 804         if (!netif_running(netdev) ||
 805             (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
 806                 netdev_alert(netdev, "Device is already powered down\n");
 807                 DBGPR("<--xgbe_powerdown\n");
 808                 return -EINVAL;
 809         }
 810
 811         spin_lock_irqsave(&pdata->lock, flags);
 812
 813         if (caller == XGMAC_DRIVER_CONTEXT)
 814                 netif_device_detach(netdev);
 815
 816         netif_tx_stop_all_queues(netdev);
 817
 818         xgbe_stop_timers(pdata);
 819         flush_workqueue(pdata->dev_workqueue);
 820
 821         hw_if->powerdown_tx(pdata);
 822         hw_if->powerdown_rx(pdata);
 823
 824         xgbe_napi_disable(pdata, 0);
 825
 826         pdata->power_down = 1;
 827
 828         spin_unlock_irqrestore(&pdata->lock, flags);
 829
 830         DBGPR("<--xgbe_powerdown\n");
 831
 832         return 0;
 833 }
 834
 835 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
 836 {
 837         struct xgbe_prv_data *pdata = netdev_priv(netdev);
 838         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 839         unsigned long flags;
 840
 841         DBGPR("-->xgbe_powerup\n");
 842
 843         if (!netif_running(netdev) ||
 844             (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
 845                 netdev_alert(netdev, "Device is already powered up\n");
 846                 DBGPR("<--xgbe_powerup\n");
 847                 return -EINVAL;
 848         }
 849
 850         spin_lock_irqsave(&pdata->lock, flags);
 851
 852         pdata->power_down = 0;
 853
 854         xgbe_napi_enable(pdata, 0);
 855
 856         hw_if->powerup_tx(pdata);
 857         hw_if->powerup_rx(pdata);
 858
 859         if (caller == XGMAC_DRIVER_CONTEXT)
 860                 netif_device_attach(netdev);
 861
 862         netif_tx_start_all_queues(netdev);
 863
 864         xgbe_start_timers(pdata);
 865
 866         spin_unlock_irqrestore(&pdata->lock, flags);
 867
 868         DBGPR("<--xgbe_powerup\n");
 869
 870         return 0;
 871 }
 872
 873 static int xgbe_start(struct xgbe_prv_data *pdata)
 874 {
 875         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 876         struct xgbe_phy_if *phy_if = &pdata->phy_if;
 877         struct net_device *netdev = pdata->netdev;
 878         int ret;
 879
 880         DBGPR("-->xgbe_start\n");
 881
 882         ret = hw_if->init(pdata);
 883         if (ret)
 884                 return ret;
 885
 886         ret = phy_if->phy_start(pdata);
 887         if (ret)
 888                 goto err_phy;
 889
 890         xgbe_napi_enable(pdata, 1);
 891
 892         ret = xgbe_request_irqs(pdata);
 893         if (ret)
 894                 goto err_napi;
 895
 896         hw_if->enable_tx(pdata);
 897         hw_if->enable_rx(pdata);
 898
 899         netif_tx_start_all_queues(netdev);
 900
 901         xgbe_start_timers(pdata);
 902         queue_work(pdata->dev_workqueue, &pdata->service_work);
 903
 904         DBGPR("<--xgbe_start\n");
 905
 906         return 0;
 907
 908 err_napi:
 909         xgbe_napi_disable(pdata, 1);
 910
 911         phy_if->phy_stop(pdata);
 912
 913 err_phy:
 914         hw_if->exit(pdata);
 915
 916         return ret;
 917 }
 918
 919 static void xgbe_stop(struct xgbe_prv_data *pdata)
 920 {
 921         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 922         struct xgbe_phy_if *phy_if = &pdata->phy_if;
 923         struct xgbe_channel *channel;
 924         struct net_device *netdev = pdata->netdev;
 925         struct netdev_queue *txq;
 926         unsigned int i;
 927
 928         DBGPR("-->xgbe_stop\n");
 929
 930         netif_tx_stop_all_queues(netdev);
 931
 932         xgbe_stop_timers(pdata);
 933         flush_workqueue(pdata->dev_workqueue);
 934
 935         hw_if->disable_tx(pdata);
 936         hw_if->disable_rx(pdata);
 937
 938         xgbe_free_irqs(pdata);
 939
 940         xgbe_napi_disable(pdata, 1);
 941
 942         phy_if->phy_stop(pdata);
 943
 944         hw_if->exit(pdata);
 945
 946         channel = pdata->channel;
 947         for (i = 0; i < pdata->channel_count; i++, channel++) {
 948                 if (!channel->tx_ring)
 949                         continue;
 950
 951                 txq = netdev_get_tx_queue(netdev, channel->queue_index);
 952                 netdev_tx_reset_queue(txq);
 953         }
 954
 955         DBGPR("<--xgbe_stop\n");
 956 }
 957
 958 static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
 959 {
 960         DBGPR("-->xgbe_restart_dev\n");
 961
 962         /* If not running, "restart" will happen on open */
 963         if (!netif_running(pdata->netdev))
 964                 return;
 965
 966         xgbe_stop(pdata);
 967
 968         xgbe_free_tx_data(pdata);
 969         xgbe_free_rx_data(pdata);
 970
 971         xgbe_start(pdata);
 972
 973         DBGPR("<--xgbe_restart_dev\n");
 974 }
 975
 976 static void xgbe_restart(struct work_struct *work)
 977 {
 978         struct xgbe_prv_data *pdata = container_of(work,
 979                                                    struct xgbe_prv_data,
 980                                                    restart_work);
 981
 982         rtnl_lock();
 983
 984         xgbe_restart_dev(pdata);
 985
 986         rtnl_unlock();
 987 }
 988
 989 static void xgbe_tx_tstamp(struct work_struct *work)
 990 {
 991         struct xgbe_prv_data *pdata = container_of(work,
 992                                                    struct xgbe_prv_data,
 993                                                    tx_tstamp_work);
 994         struct skb_shared_hwtstamps hwtstamps;
 995         u64 nsec;
 996         unsigned long flags;
 997
 998         if (pdata->tx_tstamp) {
 999                 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1000                                             pdata->tx_tstamp);
1001
1002                 memset(&hwtstamps, 0, sizeof(hwtstamps));
1003                 hwtstamps.hwtstamp = ns_to_ktime(nsec);
1004                 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1005         }
1006
1007         dev_kfree_skb_any(pdata->tx_tstamp_skb);
1008
1009         spin_lock_irqsave(&pdata->tstamp_lock, flags);
1010         pdata->tx_tstamp_skb = NULL;
1011         spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1012 }
1013
1014 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1015                                       struct ifreq *ifreq)
1016 {
1017         if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1018                          sizeof(pdata->tstamp_config)))
1019                 return -EFAULT;
1020
1021         return 0;
1022 }
1023
1024 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1025                                       struct ifreq *ifreq)
1026 {
1027         struct hwtstamp_config config;
1028         unsigned int mac_tscr;
1029
1030         if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1031                 return -EFAULT;
1032
1033         if (config.flags)
1034                 return -EINVAL;
1035
1036         mac_tscr = 0;
1037
1038         switch (config.tx_type) {
1039         case HWTSTAMP_TX_OFF:
1040                 break;
1041
1042         case HWTSTAMP_TX_ON:
1043                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1044                 break;
1045
1046         default:
1047                 return -ERANGE;
1048         }
1049
1050         switch (config.rx_filter) {
1051         case HWTSTAMP_FILTER_NONE:
1052                 break;
1053
1054         case HWTSTAMP_FILTER_ALL:
1055                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1056                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1057                 break;
1058
1059         /* PTP v2, UDP, any kind of event packet */
1060         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1061                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1062         /* PTP v1, UDP, any kind of event packet */
1063         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1064                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1065                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1066                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1067                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1068                 break;
1069
1070         /* PTP v2, UDP, Sync packet */
1071         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1072                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1073         /* PTP v1, UDP, Sync packet */
1074         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1075                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1076                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1077                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1078                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1079                 break;
1080
1081         /* PTP v2, UDP, Delay_req packet */
1082         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1083                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1084         /* PTP v1, UDP, Delay_req packet */
1085         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1086                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1087                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1088                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1089                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1090                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1091                 break;
1092
1093         /* 802.AS1, Ethernet, any kind of event packet */
1094         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1095                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1096                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1097                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1098                 break;
1099
1100         /* 802.AS1, Ethernet, Sync packet */
1101         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1102                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1103                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1104                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1105                 break;
1106
1107         /* 802.AS1, Ethernet, Delay_req packet */
1108         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1109                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1110                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1111                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1112                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1113                 break;
1114
1115         /* PTP v2/802.AS1, any layer, any kind of event packet */
1116         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1117                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1118                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1119                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1120                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1121                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1122                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1123                 break;
1124
1125         /* PTP v2/802.AS1, any layer, Sync packet */
1126         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1127                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1128                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1129                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1130                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1131                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1132                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1133                 break;
1134
1135         /* PTP v2/802.AS1, any layer, Delay_req packet */
1136         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1137                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1138                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1139                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1140                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1141                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1142                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1143                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1144                 break;
1145
1146         default:
1147                 return -ERANGE;
1148         }
1149
1150         pdata->hw_if.config_tstamp(pdata, mac_tscr);
1151
1152         memcpy(&pdata->tstamp_config, &config, sizeof(config));
1153
1154         return 0;
1155 }
1156
1157 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1158                                 struct sk_buff *skb,
1159                                 struct xgbe_packet_data *packet)
1160 {
1161         unsigned long flags;
1162
1163         if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1164                 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1165                 if (pdata->tx_tstamp_skb) {
1166                         /* Another timestamp in progress, ignore this one */
1167                         XGMAC_SET_BITS(packet->attributes,
1168                                        TX_PACKET_ATTRIBUTES, PTP, 0);
1169                 } else {
1170                         pdata->tx_tstamp_skb = skb_get(skb);
1171                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1172                 }
1173                 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1174         }
1175
1176         if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1177                 skb_tx_timestamp(skb);
1178 }
1179
1180 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1181 {
1182         if (skb_vlan_tag_present(skb))
1183                 packet->vlan_ctag = skb_vlan_tag_get(skb);
1184 }
1185
1186 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1187 {
1188         int ret;
1189
1190         if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1191                             TSO_ENABLE))
1192                 return 0;
1193
1194         ret = skb_cow_head(skb, 0);
1195         if (ret)
1196                 return ret;
1197
1198         packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1199         packet->tcp_header_len = tcp_hdrlen(skb);
1200         packet->tcp_payload_len = skb->len - packet->header_len;
1201         packet->mss = skb_shinfo(skb)->gso_size;
1202         DBGPR("  packet->header_len=%u\n", packet->header_len);
1203         DBGPR("  packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1204               packet->tcp_header_len, packet->tcp_payload_len);
1205         DBGPR("  packet->mss=%u\n", packet->mss);
1206
1207         /* Update the number of packets that will ultimately be transmitted
1208          * along with the extra bytes for each extra packet
1209          */
1210         packet->tx_packets = skb_shinfo(skb)->gso_segs;
1211         packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1212
1213         return 0;
1214 }
1215
1216 static int xgbe_is_tso(struct sk_buff *skb)
1217 {
1218         if (skb->ip_summed != CHECKSUM_PARTIAL)
1219                 return 0;
1220
1221         if (!skb_is_gso(skb))
1222                 return 0;
1223
1224         DBGPR("  TSO packet to be processed\n");
1225
1226         return 1;
1227 }
1228
1229 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1230                              struct xgbe_ring *ring, struct sk_buff *skb,
1231                              struct xgbe_packet_data *packet)
1232 {
1233         struct skb_frag_struct *frag;
1234         unsigned int context_desc;
1235         unsigned int len;
1236         unsigned int i;
1237
1238         packet->skb = skb;
1239
1240         context_desc = 0;
1241         packet->rdesc_count = 0;
1242
1243         packet->tx_packets = 1;
1244         packet->tx_bytes = skb->len;
1245
1246         if (xgbe_is_tso(skb)) {
1247                 /* TSO requires an extra descriptor if mss is different */
1248                 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1249                         context_desc = 1;
1250                         packet->rdesc_count++;
1251                 }
1252
1253                 /* TSO requires an extra descriptor for TSO header */
1254                 packet->rdesc_count++;
1255
1256                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1257                                TSO_ENABLE, 1);
1258                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1259                                CSUM_ENABLE, 1);
1260         } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1261                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1262                                CSUM_ENABLE, 1);
1263
1264         if (skb_vlan_tag_present(skb)) {
1265                 /* VLAN requires an extra descriptor if tag is different */
1266                 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1267                         /* We can share with the TSO context descriptor */
1268                         if (!context_desc) {
1269                                 context_desc = 1;
1270                                 packet->rdesc_count++;
1271                         }
1272
1273                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1274                                VLAN_CTAG, 1);
1275         }
1276
1277         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1278             (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1279                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1280                                PTP, 1);
1281
1282         for (len = skb_headlen(skb); len;) {
1283                 packet->rdesc_count++;
1284                 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1285         }
1286
1287         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1288                 frag = &skb_shinfo(skb)->frags[i];
1289                 for (len = skb_frag_size(frag); len; ) {
1290                         packet->rdesc_count++;
1291                         len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1292                 }
1293         }
1294 }
1295
1296 static int xgbe_open(struct net_device *netdev)
1297 {
1298         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1299         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1300         int ret;
1301
1302         DBGPR("-->xgbe_open\n");
1303
1304         /* Initialize the phy */
1305         ret = xgbe_phy_init(pdata);
1306         if (ret)
1307                 return ret;
1308
1309         /* Enable the clocks */
1310         ret = clk_prepare_enable(pdata->sysclk);
1311         if (ret) {
1312                 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1313                 return ret;
1314         }
1315
1316         ret = clk_prepare_enable(pdata->ptpclk);
1317         if (ret) {
1318                 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1319                 goto err_sysclk;
1320         }
1321
1322         /* Calculate the Rx buffer size before allocating rings */
1323         ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1324         if (ret < 0)
1325                 goto err_ptpclk;
1326         pdata->rx_buf_size = ret;
1327
1328         /* Allocate the channel and ring structures */
1329         ret = xgbe_alloc_channels(pdata);
1330         if (ret)
1331                 goto err_ptpclk;
1332
1333         /* Allocate the ring descriptors and buffers */
1334         ret = desc_if->alloc_ring_resources(pdata);
1335         if (ret)
1336                 goto err_channels;
1337
1338         INIT_WORK(&pdata->service_work, xgbe_service);
1339         INIT_WORK(&pdata->restart_work, xgbe_restart);
1340         INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1341         xgbe_init_timers(pdata);
1342
1343         ret = xgbe_start(pdata);
1344         if (ret)
1345                 goto err_rings;
1346
1347         clear_bit(XGBE_DOWN, &pdata->dev_state);
1348
1349         DBGPR("<--xgbe_open\n");
1350
1351         return 0;
1352
1353 err_rings:
1354         desc_if->free_ring_resources(pdata);
1355
1356 err_channels:
1357         xgbe_free_channels(pdata);
1358
1359 err_ptpclk:
1360         clk_disable_unprepare(pdata->ptpclk);
1361
1362 err_sysclk:
1363         clk_disable_unprepare(pdata->sysclk);
1364
1365         return ret;
1366 }
1367
1368 static int xgbe_close(struct net_device *netdev)
1369 {
1370         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1371         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1372
1373         DBGPR("-->xgbe_close\n");
1374
1375         /* Stop the device */
1376         xgbe_stop(pdata);
1377
1378         /* Free the ring descriptors and buffers */
1379         desc_if->free_ring_resources(pdata);
1380
1381         /* Free the channel and ring structures */
1382         xgbe_free_channels(pdata);
1383
1384         /* Disable the clocks */
1385         clk_disable_unprepare(pdata->ptpclk);
1386         clk_disable_unprepare(pdata->sysclk);
1387
1388         set_bit(XGBE_DOWN, &pdata->dev_state);
1389
1390         DBGPR("<--xgbe_close\n");
1391
1392         return 0;
1393 }
1394
1395 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1396 {
1397         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1398         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1399         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1400         struct xgbe_channel *channel;
1401         struct xgbe_ring *ring;
1402         struct xgbe_packet_data *packet;
1403         struct netdev_queue *txq;
1404         netdev_tx_t ret;
1405
1406         DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1407
1408         channel = pdata->channel + skb->queue_mapping;
1409         txq = netdev_get_tx_queue(netdev, channel->queue_index);
1410         ring = channel->tx_ring;
1411         packet = &ring->packet_data;
1412
1413         ret = NETDEV_TX_OK;
1414
1415         if (skb->len == 0) {
1416                 netif_err(pdata, tx_err, netdev,
1417                           "empty skb received from stack\n");
1418                 dev_kfree_skb_any(skb);
1419                 goto tx_netdev_return;
1420         }
1421
1422         /* Calculate preliminary packet info */
1423         memset(packet, 0, sizeof(*packet));
1424         xgbe_packet_info(pdata, ring, skb, packet);
1425
1426         /* Check that there are enough descriptors available */
1427         ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1428         if (ret)
1429                 goto tx_netdev_return;
1430
1431         ret = xgbe_prep_tso(skb, packet);
1432         if (ret) {
1433                 netif_err(pdata, tx_err, netdev,
1434                           "error processing TSO packet\n");
1435                 dev_kfree_skb_any(skb);
1436                 goto tx_netdev_return;
1437         }
1438         xgbe_prep_vlan(skb, packet);
1439
1440         if (!desc_if->map_tx_skb(channel, skb)) {
1441                 dev_kfree_skb_any(skb);
1442                 goto tx_netdev_return;
1443         }
1444
1445         xgbe_prep_tx_tstamp(pdata, skb, packet);
1446
1447         /* Report on the actual number of bytes (to be) sent */
1448         netdev_tx_sent_queue(txq, packet->tx_bytes);
1449
1450         /* Configure required descriptor fields for transmission */
1451         hw_if->dev_xmit(channel);
1452
1453         if (netif_msg_pktdata(pdata))
1454                 xgbe_print_pkt(netdev, skb, true);
1455
1456         /* Stop the queue in advance if there may not be enough descriptors */
1457         xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1458
1459         ret = NETDEV_TX_OK;
1460
1461 tx_netdev_return:
1462         return ret;
1463 }
1464
1465 static void xgbe_set_rx_mode(struct net_device *netdev)
1466 {
1467         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1468         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1469
1470         DBGPR("-->xgbe_set_rx_mode\n");
1471
1472         hw_if->config_rx_mode(pdata);
1473
1474         DBGPR("<--xgbe_set_rx_mode\n");
1475 }
1476
1477 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
1478 {
1479         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1480         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1481         struct sockaddr *saddr = addr;
1482
1483         DBGPR("-->xgbe_set_mac_address\n");
1484
1485         if (!is_valid_ether_addr(saddr->sa_data))
1486                 return -EADDRNOTAVAIL;
1487
1488         memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
1489
1490         hw_if->set_mac_address(pdata, netdev->dev_addr);
1491
1492         DBGPR("<--xgbe_set_mac_address\n");
1493
1494         return 0;
1495 }
1496
1497 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
1498 {
1499         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1500         int ret;
1501
1502         switch (cmd) {
1503         case SIOCGHWTSTAMP:
1504                 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
1505                 break;
1506
1507         case SIOCSHWTSTAMP:
1508                 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
1509                 break;
1510
1511         default:
1512                 ret = -EOPNOTSUPP;
1513         }
1514
1515         return ret;
1516 }
1517
1518 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
1519 {
1520         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1521         int ret;
1522
1523         DBGPR("-->xgbe_change_mtu\n");
1524
1525         ret = xgbe_calc_rx_buf_size(netdev, mtu);
1526         if (ret < 0)
1527                 return ret;
1528
1529         pdata->rx_buf_size = ret;
1530         netdev->mtu = mtu;
1531
1532         xgbe_restart_dev(pdata);
1533
1534         DBGPR("<--xgbe_change_mtu\n");
1535
1536         return 0;
1537 }
1538
1539 static void xgbe_tx_timeout(struct net_device *netdev)
1540 {
1541         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1542
1543         netdev_warn(netdev, "tx timeout, device restarting\n");
1544         schedule_work(&pdata->restart_work);
1545 }
1546
1547 static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev,
1548                                                   struct rtnl_link_stats64 *s)
1549 {
1550         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1551         struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
1552
1553         DBGPR("-->%s\n", __func__);
1554
1555         pdata->hw_if.read_mmc_stats(pdata);
1556
1557         s->rx_packets = pstats->rxframecount_gb;
1558         s->rx_bytes = pstats->rxoctetcount_gb;
1559         s->rx_errors = pstats->rxframecount_gb -
1560                        pstats->rxbroadcastframes_g -
1561                        pstats->rxmulticastframes_g -
1562                        pstats->rxunicastframes_g;
1563         s->multicast = pstats->rxmulticastframes_g;
1564         s->rx_length_errors = pstats->rxlengtherror;
1565         s->rx_crc_errors = pstats->rxcrcerror;
1566         s->rx_fifo_errors = pstats->rxfifooverflow;
1567
1568         s->tx_packets = pstats->txframecount_gb;
1569         s->tx_bytes = pstats->txoctetcount_gb;
1570         s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
1571         s->tx_dropped = netdev->stats.tx_dropped;
1572
1573         DBGPR("<--%s\n", __func__);
1574
1575         return s;
1576 }
1577
1578 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1579                                 u16 vid)
1580 {
1581         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1582         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1583
1584         DBGPR("-->%s\n", __func__);
1585
1586         set_bit(vid, pdata->active_vlans);
1587         hw_if->update_vlan_hash_table(pdata);
1588
1589         DBGPR("<--%s\n", __func__);
1590
1591         return 0;
1592 }
1593
1594 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1595                                  u16 vid)
1596 {
1597         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1598         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1599
1600         DBGPR("-->%s\n", __func__);
1601
1602         clear_bit(vid, pdata->active_vlans);
1603         hw_if->update_vlan_hash_table(pdata);
1604
1605         DBGPR("<--%s\n", __func__);
1606
1607         return 0;
1608 }
1609
1610 #ifdef CONFIG_NET_POLL_CONTROLLER
1611 static void xgbe_poll_controller(struct net_device *netdev)
1612 {
1613         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1614         struct xgbe_channel *channel;
1615         unsigned int i;
1616
1617         DBGPR("-->xgbe_poll_controller\n");
1618
1619         if (pdata->per_channel_irq) {
1620                 channel = pdata->channel;
1621                 for (i = 0; i < pdata->channel_count; i++, channel++)
1622                         xgbe_dma_isr(channel->dma_irq, channel);
1623         } else {
1624                 disable_irq(pdata->dev_irq);
1625                 xgbe_isr(pdata->dev_irq, pdata);
1626                 enable_irq(pdata->dev_irq);
1627         }
1628
1629         DBGPR("<--xgbe_poll_controller\n");
1630 }
1631 #endif /* End CONFIG_NET_POLL_CONTROLLER */
1632
1633 static int xgbe_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
1634                          struct tc_to_netdev *tc_to_netdev)
1635 {
1636         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1637         u8 tc;
1638
1639         if (tc_to_netdev->type != TC_SETUP_MQPRIO)
1640                 return -EINVAL;
1641
1642         tc = tc_to_netdev->tc;
1643
1644         if (tc > pdata->hw_feat.tc_cnt)
1645                 return -EINVAL;
1646
1647         pdata->num_tcs = tc;
1648         pdata->hw_if.config_tc(pdata);
1649
1650         return 0;
1651 }
1652
1653 static int xgbe_set_features(struct net_device *netdev,
1654                              netdev_features_t features)
1655 {
1656         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1657         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1658         netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
1659         int ret = 0;
1660
1661         rxhash = pdata->netdev_features & NETIF_F_RXHASH;
1662         rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
1663         rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
1664         rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
1665
1666         if ((features & NETIF_F_RXHASH) && !rxhash)
1667                 ret = hw_if->enable_rss(pdata);
1668         else if (!(features & NETIF_F_RXHASH) && rxhash)
1669                 ret = hw_if->disable_rss(pdata);
1670         if (ret)
1671                 return ret;
1672
1673         if ((features & NETIF_F_RXCSUM) && !rxcsum)
1674                 hw_if->enable_rx_csum(pdata);
1675         else if (!(features & NETIF_F_RXCSUM) && rxcsum)
1676                 hw_if->disable_rx_csum(pdata);
1677
1678         if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
1679                 hw_if->enable_rx_vlan_stripping(pdata);
1680         else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
1681                 hw_if->disable_rx_vlan_stripping(pdata);
1682
1683         if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
1684                 hw_if->enable_rx_vlan_filtering(pdata);
1685         else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
1686                 hw_if->disable_rx_vlan_filtering(pdata);
1687
1688         pdata->netdev_features = features;
1689
1690         DBGPR("<--xgbe_set_features\n");
1691
1692         return 0;
1693 }
1694
1695 static const struct net_device_ops xgbe_netdev_ops = {
1696         .ndo_open               = xgbe_open,
1697         .ndo_stop               = xgbe_close,
1698         .ndo_start_xmit         = xgbe_xmit,
1699         .ndo_set_rx_mode        = xgbe_set_rx_mode,
1700         .ndo_set_mac_address    = xgbe_set_mac_address,
1701         .ndo_validate_addr      = eth_validate_addr,
1702         .ndo_do_ioctl           = xgbe_ioctl,
1703         .ndo_change_mtu         = xgbe_change_mtu,
1704         .ndo_tx_timeout         = xgbe_tx_timeout,
1705         .ndo_get_stats64        = xgbe_get_stats64,
1706         .ndo_vlan_rx_add_vid    = xgbe_vlan_rx_add_vid,
1707         .ndo_vlan_rx_kill_vid   = xgbe_vlan_rx_kill_vid,
1708 #ifdef CONFIG_NET_POLL_CONTROLLER
1709         .ndo_poll_controller    = xgbe_poll_controller,
1710 #endif
1711         .ndo_setup_tc           = xgbe_setup_tc,
1712         .ndo_set_features       = xgbe_set_features,
1713 };
1714
1715 const struct net_device_ops *xgbe_get_netdev_ops(void)
1716 {
1717         return &xgbe_netdev_ops;
1718 }
1719
1720 static void xgbe_rx_refresh(struct xgbe_channel *channel)
1721 {
1722         struct xgbe_prv_data *pdata = channel->pdata;
1723         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1724         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1725         struct xgbe_ring *ring = channel->rx_ring;
1726         struct xgbe_ring_data *rdata;
1727
1728         while (ring->dirty != ring->cur) {
1729                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1730
1731                 /* Reset rdata values */
1732                 desc_if->unmap_rdata(pdata, rdata);
1733
1734                 if (desc_if->map_rx_buffer(pdata, ring, rdata))
1735                         break;
1736
1737                 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
1738
1739                 ring->dirty++;
1740         }
1741
1742         /* Make sure everything is written before the register write */
1743         wmb();
1744
1745         /* Update the Rx Tail Pointer Register with address of
1746          * the last cleaned entry */
1747         rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
1748         XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1749                           lower_32_bits(rdata->rdesc_dma));
1750 }
1751
1752 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
1753                                        struct napi_struct *napi,
1754                                        struct xgbe_ring_data *rdata,
1755                                        unsigned int len)
1756 {
1757         struct sk_buff *skb;
1758         u8 *packet;
1759
1760         skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
1761         if (!skb)
1762                 return NULL;
1763
1764         /* Pull in the header buffer which may contain just the header
1765          * or the header plus data
1766          */
1767         dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
1768                                       rdata->rx.hdr.dma_off,
1769                                       rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
1770
1771         packet = page_address(rdata->rx.hdr.pa.pages) +
1772                  rdata->rx.hdr.pa.pages_offset;
1773         skb_copy_to_linear_data(skb, packet, len);
1774         skb_put(skb, len);
1775
1776         return skb;
1777 }
1778
1779 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
1780                                      struct xgbe_packet_data *packet)
1781 {
1782         /* Always zero if not the first descriptor */
1783         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
1784                 return 0;
1785
1786         /* First descriptor with split header, return header length */
1787         if (rdata->rx.hdr_len)
1788                 return rdata->rx.hdr_len;
1789
1790         /* First descriptor but not the last descriptor and no split header,
1791          * so the full buffer was used
1792          */
1793         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
1794                 return rdata->rx.hdr.dma_len;
1795
1796         /* First descriptor and last descriptor and no split header, so
1797          * calculate how much of the buffer was used
1798          */
1799         return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
1800 }
1801
1802 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
1803                                      struct xgbe_packet_data *packet,
1804                                      unsigned int len)
1805 {
1806         /* Always the full buffer if not the last descriptor */
1807         if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
1808                 return rdata->rx.buf.dma_len;
1809
1810         /* Last descriptor so calculate how much of the buffer was used
1811          * for the last bit of data
1812          */
1813         return rdata->rx.len - len;
1814 }
1815
1816 static int xgbe_tx_poll(struct xgbe_channel *channel)
1817 {
1818         struct xgbe_prv_data *pdata = channel->pdata;
1819         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1820         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1821         struct xgbe_ring *ring = channel->tx_ring;
1822         struct xgbe_ring_data *rdata;
1823         struct xgbe_ring_desc *rdesc;
1824         struct net_device *netdev = pdata->netdev;
1825         struct netdev_queue *txq;
1826         int processed = 0;
1827         unsigned int tx_packets = 0, tx_bytes = 0;
1828         unsigned int cur;
1829
1830         DBGPR("-->xgbe_tx_poll\n");
1831
1832         /* Nothing to do if there isn't a Tx ring for this channel */
1833         if (!ring)
1834                 return 0;
1835
1836         cur = ring->cur;
1837
1838         /* Be sure we get ring->cur before accessing descriptor data */
1839         smp_rmb();
1840
1841         txq = netdev_get_tx_queue(netdev, channel->queue_index);
1842
1843         while ((processed < XGBE_TX_DESC_MAX_PROC) &&
1844                (ring->dirty != cur)) {
1845                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1846                 rdesc = rdata->rdesc;
1847
1848                 if (!hw_if->tx_complete(rdesc))
1849                         break;
1850
1851                 /* Make sure descriptor fields are read after reading the OWN
1852                  * bit */
1853                 dma_rmb();
1854
1855                 if (netif_msg_tx_done(pdata))
1856                         xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
1857
1858                 if (hw_if->is_last_desc(rdesc)) {
1859                         tx_packets += rdata->tx.packets;
1860                         tx_bytes += rdata->tx.bytes;
1861                 }
1862
1863                 /* Free the SKB and reset the descriptor for re-use */
1864                 desc_if->unmap_rdata(pdata, rdata);
1865                 hw_if->tx_desc_reset(rdata);
1866
1867                 processed++;
1868                 ring->dirty++;
1869         }
1870
1871         if (!processed)
1872                 return 0;
1873
1874         netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
1875
1876         if ((ring->tx.queue_stopped == 1) &&
1877             (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
1878                 ring->tx.queue_stopped = 0;
1879                 netif_tx_wake_queue(txq);
1880         }
1881
1882         DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
1883
1884         return processed;
1885 }
1886
1887 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
1888 {
1889         struct xgbe_prv_data *pdata = channel->pdata;
1890         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1891         struct xgbe_ring *ring = channel->rx_ring;
1892         struct xgbe_ring_data *rdata;
1893         struct xgbe_packet_data *packet;
1894         struct net_device *netdev = pdata->netdev;
1895         struct napi_struct *napi;
1896         struct sk_buff *skb;
1897         struct skb_shared_hwtstamps *hwtstamps;
1898         unsigned int last, error, context_next, context;
1899         unsigned int len, buf1_len, buf2_len, max_len;
1900         unsigned int received = 0;
1901         int packet_count = 0;
1902
1903         DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
1904
1905         /* Nothing to do if there isn't a Rx ring for this channel */
1906         if (!ring)
1907                 return 0;
1908
1909         last = 0;
1910         context_next = 0;
1911
1912         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
1913
1914         rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1915         packet = &ring->packet_data;
1916         while (packet_count < budget) {
1917                 DBGPR("  cur = %d\n", ring->cur);
1918
1919                 /* First time in loop see if we need to restore state */
1920                 if (!received && rdata->state_saved) {
1921                         skb = rdata->state.skb;
1922                         error = rdata->state.error;
1923                         len = rdata->state.len;
1924                 } else {
1925                         memset(packet, 0, sizeof(*packet));
1926                         skb = NULL;
1927                         error = 0;
1928                         len = 0;
1929                 }
1930
1931 read_again:
1932                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1933
1934                 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
1935                         xgbe_rx_refresh(channel);
1936
1937                 if (hw_if->dev_read(channel))
1938                         break;
1939
1940                 received++;
1941                 ring->cur++;
1942
1943                 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1944                                       LAST);
1945                 context_next = XGMAC_GET_BITS(packet->attributes,
1946                                               RX_PACKET_ATTRIBUTES,
1947                                               CONTEXT_NEXT);
1948                 context = XGMAC_GET_BITS(packet->attributes,
1949                                          RX_PACKET_ATTRIBUTES,
1950                                          CONTEXT);
1951
1952                 /* Earlier error, just drain the remaining data */
1953                 if ((!last || context_next) && error)
1954                         goto read_again;
1955
1956                 if (error || packet->errors) {
1957                         if (packet->errors)
1958                                 netif_err(pdata, rx_err, netdev,
1959                                           "error in received packet\n");
1960                         dev_kfree_skb(skb);
1961                         goto next_packet;
1962                 }
1963
1964                 if (!context) {
1965                         /* Get the data length in the descriptor buffers */
1966                         buf1_len = xgbe_rx_buf1_len(rdata, packet);
1967                         len += buf1_len;
1968                         buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
1969                         len += buf2_len;
1970
1971                         if (buf2_len > rdata->rx.buf.dma_len) {
1972                                 /* Hardware inconsistency within the descriptors
1973                                  * that has resulted in a length underflow.
1974                                  */
1975                                 error = 1;
1976                                 goto skip_data;
1977                         }
1978
1979                         if (!skb) {
1980                                 skb = xgbe_create_skb(pdata, napi, rdata,
1981                                                       buf1_len);
1982                                 if (!skb) {
1983                                         error = 1;
1984                                         goto skip_data;
1985                                 }
1986                         }
1987
1988                         if (buf2_len) {
1989                                 dma_sync_single_range_for_cpu(pdata->dev,
1990                                                         rdata->rx.buf.dma_base,
1991                                                         rdata->rx.buf.dma_off,
1992                                                         rdata->rx.buf.dma_len,
1993                                                         DMA_FROM_DEVICE);
1994
1995                                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1996                                                 rdata->rx.buf.pa.pages,
1997                                                 rdata->rx.buf.pa.pages_offset,
1998                                                 buf2_len,
1999                                                 rdata->rx.buf.dma_len);
2000                                 rdata->rx.buf.pa.pages = NULL;
2001                         }
2002                 }
2003
2004 skip_data:
2005                 if (!last || context_next)
2006                         goto read_again;
2007
2008                 if (!skb || error) {
2009                         dev_kfree_skb(skb);
2010                         goto next_packet;
2011                 }
2012
2013                 /* Be sure we don't exceed the configured MTU */
2014                 max_len = netdev->mtu + ETH_HLEN;
2015                 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2016                     (skb->protocol == htons(ETH_P_8021Q)))
2017                         max_len += VLAN_HLEN;
2018
2019                 if (skb->len > max_len) {
2020                         netif_err(pdata, rx_err, netdev,
2021                                   "packet length exceeds configured MTU\n");
2022                         dev_kfree_skb(skb);
2023                         goto next_packet;
2024                 }
2025
2026                 if (netif_msg_pktdata(pdata))
2027                         xgbe_print_pkt(netdev, skb, false);
2028
2029                 skb_checksum_none_assert(skb);
2030                 if (XGMAC_GET_BITS(packet->attributes,
2031                                    RX_PACKET_ATTRIBUTES, CSUM_DONE))
2032                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2033
2034                 if (XGMAC_GET_BITS(packet->attributes,
2035                                    RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2036                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2037                                                packet->vlan_ctag);
2038
2039                 if (XGMAC_GET_BITS(packet->attributes,
2040                                    RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2041                         u64 nsec;
2042
2043                         nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2044                                                     packet->rx_tstamp);
2045                         hwtstamps = skb_hwtstamps(skb);
2046                         hwtstamps->hwtstamp = ns_to_ktime(nsec);
2047                 }
2048
2049                 if (XGMAC_GET_BITS(packet->attributes,
2050                                    RX_PACKET_ATTRIBUTES, RSS_HASH))
2051                         skb_set_hash(skb, packet->rss_hash,
2052                                      packet->rss_hash_type);
2053
2054                 skb->dev = netdev;
2055                 skb->protocol = eth_type_trans(skb, netdev);
2056                 skb_record_rx_queue(skb, channel->queue_index);
2057
2058                 napi_gro_receive(napi, skb);
2059
2060 next_packet:
2061                 packet_count++;
2062         }
2063
2064         /* Check if we need to save state before leaving */
2065         if (received && (!last || context_next)) {
2066                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2067                 rdata->state_saved = 1;
2068                 rdata->state.skb = skb;
2069                 rdata->state.len = len;
2070                 rdata->state.error = error;
2071         }
2072
2073         DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2074
2075         return packet_count;
2076 }
2077
2078 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2079 {
2080         struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2081                                                     napi);
2082         int processed = 0;
2083
2084         DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2085
2086         /* Cleanup Tx ring first */
2087         xgbe_tx_poll(channel);
2088
2089         /* Process Rx ring next */
2090         processed = xgbe_rx_poll(channel, budget);
2091
2092         /* If we processed everything, we are done */
2093         if (processed < budget) {
2094                 /* Turn off polling */
2095                 napi_complete_done(napi, processed);
2096
2097                 /* Enable Tx and Rx interrupts */
2098                 enable_irq(channel->dma_irq);
2099         }
2100
2101         DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2102
2103         return processed;
2104 }
2105
2106 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2107 {
2108         struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2109                                                    napi);
2110         struct xgbe_channel *channel;
2111         int ring_budget;
2112         int processed, last_processed;
2113         unsigned int i;
2114
2115         DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2116
2117         processed = 0;
2118         ring_budget = budget / pdata->rx_ring_count;
2119         do {
2120                 last_processed = processed;
2121
2122                 channel = pdata->channel;
2123                 for (i = 0; i < pdata->channel_count; i++, channel++) {
2124                         /* Cleanup Tx ring first */
2125                         xgbe_tx_poll(channel);
2126
2127                         /* Process Rx ring next */
2128                         if (ring_budget > (budget - processed))
2129                                 ring_budget = budget - processed;
2130                         processed += xgbe_rx_poll(channel, ring_budget);
2131                 }
2132         } while ((processed < budget) && (processed != last_processed));
2133
2134         /* If we processed everything, we are done */
2135         if (processed < budget) {
2136                 /* Turn off polling */
2137                 napi_complete_done(napi, processed);
2138
2139                 /* Enable Tx and Rx interrupts */
2140                 xgbe_enable_rx_tx_ints(pdata);
2141         }
2142
2143         DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2144
2145         return processed;
2146 }
2147
2148 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2149                        unsigned int idx, unsigned int count, unsigned int flag)
2150 {
2151         struct xgbe_ring_data *rdata;
2152         struct xgbe_ring_desc *rdesc;
2153
2154         while (count--) {
2155                 rdata = XGBE_GET_DESC_DATA(ring, idx);
2156                 rdesc = rdata->rdesc;
2157                 netdev_dbg(pdata->netdev,
2158                            "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2159                            (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2160                            le32_to_cpu(rdesc->desc0),
2161                            le32_to_cpu(rdesc->desc1),
2162                            le32_to_cpu(rdesc->desc2),
2163                            le32_to_cpu(rdesc->desc3));
2164                 idx++;
2165         }
2166 }
2167
2168 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2169                        unsigned int idx)
2170 {
2171         struct xgbe_ring_data *rdata;
2172         struct xgbe_ring_desc *rdesc;
2173
2174         rdata = XGBE_GET_DESC_DATA(ring, idx);
2175         rdesc = rdata->rdesc;
2176         netdev_dbg(pdata->netdev,
2177                    "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2178                    idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2179                    le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2180 }
2181
2182 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2183 {
2184         struct ethhdr *eth = (struct ethhdr *)skb->data;
2185         unsigned char *buf = skb->data;
2186         unsigned char buffer[128];
2187         unsigned int i, j;
2188
2189         netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2190
2191         netdev_dbg(netdev, "%s packet of %d bytes\n",
2192                    (tx_rx ? "TX" : "RX"), skb->len);
2193
2194         netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2195         netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2196         netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
2197
2198         for (i = 0, j = 0; i < skb->len;) {
2199                 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
2200                               buf[i++]);
2201
2202                 if ((i % 32) == 0) {
2203                         netdev_dbg(netdev, "  %#06x: %s\n", i - 32, buffer);
2204                         j = 0;
2205                 } else if ((i % 16) == 0) {
2206                         buffer[j++] = ' ';
2207                         buffer[j++] = ' ';
2208                 } else if ((i % 4) == 0) {
2209                         buffer[j++] = ' ';
2210                 }
2211         }
2212         if (i % 32)
2213                 netdev_dbg(netdev, "  %#06x: %s\n", i - (i % 32), buffer);
2214
2215         netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2216 }