2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/module.h>
118 #include <linux/device.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
124 #include "xgbe-common.h"
126 #define XGBE_PHY_PORT_SPEED_100 BIT(0)
127 #define XGBE_PHY_PORT_SPEED_1000 BIT(1)
128 #define XGBE_PHY_PORT_SPEED_2500 BIT(2)
129 #define XGBE_PHY_PORT_SPEED_10000 BIT(3)
131 #define XGBE_MUTEX_RELEASE 0x80000000
133 #define XGBE_SFP_DIRECT 7
135 /* I2C target addresses */
136 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
137 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
138 #define XGBE_SFP_PHY_ADDRESS 0x56
139 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
141 /* SFP sideband signal indicators */
142 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
143 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
144 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
145 #define XGBE_GPIO_NO_RX_LOS BIT(3)
147 /* Rate-change complete wait/retry count */
148 #define XGBE_RATECHANGE_COUNT 500
150 /* CDR delay values for KR support (in usec) */
151 #define XGBE_CDR_DELAY_INIT 10000
152 #define XGBE_CDR_DELAY_INC 10000
153 #define XGBE_CDR_DELAY_MAX 100000
155 /* RRC frequency during link status check */
156 #define XGBE_RRC_FREQUENCY 10
158 enum xgbe_port_mode {
159 XGBE_PORT_MODE_RSVD = 0,
160 XGBE_PORT_MODE_BACKPLANE,
161 XGBE_PORT_MODE_BACKPLANE_2500,
162 XGBE_PORT_MODE_1000BASE_T,
163 XGBE_PORT_MODE_1000BASE_X,
164 XGBE_PORT_MODE_NBASE_T,
165 XGBE_PORT_MODE_10GBASE_T,
166 XGBE_PORT_MODE_10GBASE_R,
171 enum xgbe_conn_type {
172 XGBE_CONN_TYPE_NONE = 0,
175 XGBE_CONN_TYPE_RSVD1,
176 XGBE_CONN_TYPE_BACKPLANE,
180 /* SFP/SFP+ related definitions */
182 XGBE_SFP_COMM_DIRECT = 0,
183 XGBE_SFP_COMM_PCA9545,
186 enum xgbe_sfp_cable {
187 XGBE_SFP_CABLE_UNKNOWN = 0,
188 XGBE_SFP_CABLE_ACTIVE,
189 XGBE_SFP_CABLE_PASSIVE,
193 XGBE_SFP_BASE_UNKNOWN = 0,
194 XGBE_SFP_BASE_1000_T,
195 XGBE_SFP_BASE_1000_SX,
196 XGBE_SFP_BASE_1000_LX,
197 XGBE_SFP_BASE_1000_CX,
198 XGBE_SFP_BASE_10000_SR,
199 XGBE_SFP_BASE_10000_LR,
200 XGBE_SFP_BASE_10000_LRM,
201 XGBE_SFP_BASE_10000_ER,
202 XGBE_SFP_BASE_10000_CR,
205 enum xgbe_sfp_speed {
206 XGBE_SFP_SPEED_UNKNOWN = 0,
207 XGBE_SFP_SPEED_100_1000,
209 XGBE_SFP_SPEED_10000,
212 /* SFP Serial ID Base ID values relative to an offset of 0 */
213 #define XGBE_SFP_BASE_ID 0
214 #define XGBE_SFP_ID_SFP 0x03
216 #define XGBE_SFP_BASE_EXT_ID 1
217 #define XGBE_SFP_EXT_ID_SFP 0x04
219 #define XGBE_SFP_BASE_10GBE_CC 3
220 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
221 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
222 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
223 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
225 #define XGBE_SFP_BASE_1GBE_CC 6
226 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
227 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
228 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
229 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
231 #define XGBE_SFP_BASE_CABLE 8
232 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
233 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
235 #define XGBE_SFP_BASE_BR 12
236 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
237 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
238 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
239 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
241 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
243 #define XGBE_SFP_BASE_VENDOR_NAME 20
244 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
245 #define XGBE_SFP_BASE_VENDOR_PN 40
246 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
247 #define XGBE_SFP_BASE_VENDOR_REV 56
248 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
250 #define XGBE_SFP_BASE_CC 63
252 /* SFP Serial ID Extended ID values relative to an offset of 64 */
253 #define XGBE_SFP_BASE_VENDOR_SN 4
254 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
256 #define XGBE_SFP_EXTD_OPT1 1
257 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
258 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
260 #define XGBE_SFP_EXTD_DIAG 28
261 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
263 #define XGBE_SFP_EXTD_SFF_8472 30
265 #define XGBE_SFP_EXTD_CC 31
267 struct xgbe_sfp_eeprom {
273 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
274 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
276 struct xgbe_sfp_ascii {
278 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
279 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
280 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
281 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
285 /* MDIO PHY reset types */
286 enum xgbe_mdio_reset {
287 XGBE_MDIO_RESET_NONE = 0,
288 XGBE_MDIO_RESET_I2C_GPIO,
289 XGBE_MDIO_RESET_INT_GPIO,
293 /* Re-driver related definitions */
294 enum xgbe_phy_redrv_if {
295 XGBE_PHY_REDRV_IF_MDIO = 0,
296 XGBE_PHY_REDRV_IF_I2C,
297 XGBE_PHY_REDRV_IF_MAX,
300 enum xgbe_phy_redrv_model {
301 XGBE_PHY_REDRV_MODEL_4223 = 0,
302 XGBE_PHY_REDRV_MODEL_4227,
303 XGBE_PHY_REDRV_MODEL_MAX,
306 enum xgbe_phy_redrv_mode {
307 XGBE_PHY_REDRV_MODE_CX = 5,
308 XGBE_PHY_REDRV_MODE_SR = 9,
311 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
313 /* PHY related configuration information */
314 struct xgbe_phy_data {
315 enum xgbe_port_mode port_mode;
317 unsigned int port_id;
319 unsigned int port_speeds;
321 enum xgbe_conn_type conn_type;
323 enum xgbe_mode cur_mode;
324 enum xgbe_mode start_mode;
326 unsigned int rrc_count;
328 unsigned int mdio_addr;
330 unsigned int comm_owned;
333 enum xgbe_sfp_comm sfp_comm;
334 unsigned int sfp_mux_address;
335 unsigned int sfp_mux_channel;
337 unsigned int sfp_gpio_address;
338 unsigned int sfp_gpio_mask;
339 unsigned int sfp_gpio_inputs;
340 unsigned int sfp_gpio_rx_los;
341 unsigned int sfp_gpio_tx_fault;
342 unsigned int sfp_gpio_mod_absent;
343 unsigned int sfp_gpio_rate_select;
345 unsigned int sfp_rx_los;
346 unsigned int sfp_tx_fault;
347 unsigned int sfp_mod_absent;
348 unsigned int sfp_diags;
349 unsigned int sfp_changed;
350 unsigned int sfp_phy_avail;
351 unsigned int sfp_cable_len;
352 enum xgbe_sfp_base sfp_base;
353 enum xgbe_sfp_cable sfp_cable;
354 enum xgbe_sfp_speed sfp_speed;
355 struct xgbe_sfp_eeprom sfp_eeprom;
357 /* External PHY support */
358 enum xgbe_mdio_mode phydev_mode;
360 struct phy_device *phydev;
361 enum xgbe_mdio_reset mdio_reset;
362 unsigned int mdio_reset_addr;
363 unsigned int mdio_reset_gpio;
365 /* Re-driver support */
367 unsigned int redrv_if;
368 unsigned int redrv_addr;
369 unsigned int redrv_lane;
370 unsigned int redrv_model;
373 unsigned int phy_cdr_notrack;
374 unsigned int phy_cdr_delay;
377 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
378 static DEFINE_MUTEX(xgbe_phy_comm_lock);
380 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
382 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
383 struct xgbe_i2c_op *i2c_op)
385 struct xgbe_phy_data *phy_data = pdata->phy_data;
387 /* Be sure we own the bus */
388 if (WARN_ON(!phy_data->comm_owned))
391 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
394 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
397 struct xgbe_phy_data *phy_data = pdata->phy_data;
398 struct xgbe_i2c_op i2c_op;
400 u8 redrv_data[5], csum;
401 unsigned int i, retry;
404 /* High byte of register contains read/write indicator */
405 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
406 redrv_data[1] = reg & 0xff;
407 redrv_val = (__be16 *)&redrv_data[2];
408 *redrv_val = cpu_to_be16(val);
410 /* Calculate 1 byte checksum */
412 for (i = 0; i < 4; i++) {
413 csum += redrv_data[i];
414 if (redrv_data[i] > csum)
417 redrv_data[4] = ~csum;
421 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
422 i2c_op.target = phy_data->redrv_addr;
423 i2c_op.len = sizeof(redrv_data);
424 i2c_op.buf = redrv_data;
425 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
427 if ((ret == -EAGAIN) && retry--)
435 i2c_op.cmd = XGBE_I2C_CMD_READ;
436 i2c_op.target = phy_data->redrv_addr;
438 i2c_op.buf = redrv_data;
439 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
441 if ((ret == -EAGAIN) && retry--)
447 if (redrv_data[0] != 0xff) {
448 netif_dbg(pdata, drv, pdata->netdev,
449 "Redriver write checksum error\n");
456 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
457 void *val, unsigned int val_len)
459 struct xgbe_i2c_op i2c_op;
464 /* Write the specfied register */
465 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
466 i2c_op.target = target;
467 i2c_op.len = val_len;
469 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
470 if ((ret == -EAGAIN) && retry--)
476 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
477 void *reg, unsigned int reg_len,
478 void *val, unsigned int val_len)
480 struct xgbe_i2c_op i2c_op;
485 /* Set the specified register to read */
486 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
487 i2c_op.target = target;
488 i2c_op.len = reg_len;
490 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
492 if ((ret == -EAGAIN) && retry--)
500 /* Read the specfied register */
501 i2c_op.cmd = XGBE_I2C_CMD_READ;
502 i2c_op.target = target;
503 i2c_op.len = val_len;
505 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
506 if ((ret == -EAGAIN) && retry--)
512 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
514 struct xgbe_phy_data *phy_data = pdata->phy_data;
515 struct xgbe_i2c_op i2c_op;
518 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
521 /* Select no mux channels */
523 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
524 i2c_op.target = phy_data->sfp_mux_address;
525 i2c_op.len = sizeof(mux_channel);
526 i2c_op.buf = &mux_channel;
528 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
531 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
533 struct xgbe_phy_data *phy_data = pdata->phy_data;
534 struct xgbe_i2c_op i2c_op;
537 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
540 /* Select desired mux channel */
541 mux_channel = 1 << phy_data->sfp_mux_channel;
542 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
543 i2c_op.target = phy_data->sfp_mux_address;
544 i2c_op.len = sizeof(mux_channel);
545 i2c_op.buf = &mux_channel;
547 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
550 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
552 struct xgbe_phy_data *phy_data = pdata->phy_data;
554 phy_data->comm_owned = 0;
556 mutex_unlock(&xgbe_phy_comm_lock);
559 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
561 struct xgbe_phy_data *phy_data = pdata->phy_data;
562 unsigned long timeout;
563 unsigned int mutex_id;
565 if (phy_data->comm_owned)
568 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
569 * the driver needs to take the software mutex and then the hardware
570 * mutexes before being able to use the busses.
572 mutex_lock(&xgbe_phy_comm_lock);
574 /* Clear the mutexes */
575 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
576 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
578 /* Mutex formats are the same for I2C and MDIO/GPIO */
580 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
581 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
583 timeout = jiffies + (5 * HZ);
584 while (time_before(jiffies, timeout)) {
585 /* Must be all zeroes in order to obtain the mutex */
586 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
587 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
588 usleep_range(100, 200);
592 /* Obtain the mutex */
593 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
594 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
596 phy_data->comm_owned = 1;
600 mutex_unlock(&xgbe_phy_comm_lock);
602 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
607 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
610 struct xgbe_phy_data *phy_data = pdata->phy_data;
612 if (reg & MII_ADDR_C45) {
613 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
616 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
620 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
623 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
629 ret = xgbe_phy_sfp_get_mux(pdata);
633 mii_data[0] = reg & 0xff;
634 mii_val = (__be16 *)&mii_data[1];
635 *mii_val = cpu_to_be16(val);
637 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
638 mii_data, sizeof(mii_data));
640 xgbe_phy_sfp_put_mux(pdata);
645 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
647 struct xgbe_prv_data *pdata = mii->priv;
648 struct xgbe_phy_data *phy_data = pdata->phy_data;
651 ret = xgbe_phy_get_comm_ownership(pdata);
655 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
656 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
657 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
658 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
662 xgbe_phy_put_comm_ownership(pdata);
667 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
670 struct xgbe_phy_data *phy_data = pdata->phy_data;
672 if (reg & MII_ADDR_C45) {
673 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
676 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
680 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
683 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
689 ret = xgbe_phy_sfp_get_mux(pdata);
694 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
695 &mii_reg, sizeof(mii_reg),
696 &mii_val, sizeof(mii_val));
698 ret = be16_to_cpu(mii_val);
700 xgbe_phy_sfp_put_mux(pdata);
705 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
707 struct xgbe_prv_data *pdata = mii->priv;
708 struct xgbe_phy_data *phy_data = pdata->phy_data;
711 ret = xgbe_phy_get_comm_ownership(pdata);
715 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
716 ret = xgbe_phy_i2c_mii_read(pdata, reg);
717 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
718 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
722 xgbe_phy_put_comm_ownership(pdata);
727 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
729 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
730 struct xgbe_phy_data *phy_data = pdata->phy_data;
732 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
737 if (phy_data->sfp_mod_absent) {
738 pdata->phy.speed = SPEED_UNKNOWN;
739 pdata->phy.duplex = DUPLEX_UNKNOWN;
740 pdata->phy.autoneg = AUTONEG_ENABLE;
741 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
743 XGBE_SET_SUP(lks, Autoneg);
744 XGBE_SET_SUP(lks, Pause);
745 XGBE_SET_SUP(lks, Asym_Pause);
746 XGBE_SET_SUP(lks, TP);
747 XGBE_SET_SUP(lks, FIBRE);
749 XGBE_LM_COPY(lks, advertising, lks, supported);
754 switch (phy_data->sfp_base) {
755 case XGBE_SFP_BASE_1000_T:
756 case XGBE_SFP_BASE_1000_SX:
757 case XGBE_SFP_BASE_1000_LX:
758 case XGBE_SFP_BASE_1000_CX:
759 pdata->phy.speed = SPEED_UNKNOWN;
760 pdata->phy.duplex = DUPLEX_UNKNOWN;
761 pdata->phy.autoneg = AUTONEG_ENABLE;
762 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
763 XGBE_SET_SUP(lks, Autoneg);
764 XGBE_SET_SUP(lks, Pause);
765 XGBE_SET_SUP(lks, Asym_Pause);
766 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
767 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
768 XGBE_SET_SUP(lks, 100baseT_Full);
769 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
770 XGBE_SET_SUP(lks, 1000baseT_Full);
772 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
773 XGBE_SET_SUP(lks, 1000baseX_Full);
776 case XGBE_SFP_BASE_10000_SR:
777 case XGBE_SFP_BASE_10000_LR:
778 case XGBE_SFP_BASE_10000_LRM:
779 case XGBE_SFP_BASE_10000_ER:
780 case XGBE_SFP_BASE_10000_CR:
781 pdata->phy.speed = SPEED_10000;
782 pdata->phy.duplex = DUPLEX_FULL;
783 pdata->phy.autoneg = AUTONEG_DISABLE;
784 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
785 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
786 switch (phy_data->sfp_base) {
787 case XGBE_SFP_BASE_10000_SR:
788 XGBE_SET_SUP(lks, 10000baseSR_Full);
790 case XGBE_SFP_BASE_10000_LR:
791 XGBE_SET_SUP(lks, 10000baseLR_Full);
793 case XGBE_SFP_BASE_10000_LRM:
794 XGBE_SET_SUP(lks, 10000baseLRM_Full);
796 case XGBE_SFP_BASE_10000_ER:
797 XGBE_SET_SUP(lks, 10000baseER_Full);
799 case XGBE_SFP_BASE_10000_CR:
800 XGBE_SET_SUP(lks, 10000baseCR_Full);
808 pdata->phy.speed = SPEED_UNKNOWN;
809 pdata->phy.duplex = DUPLEX_UNKNOWN;
810 pdata->phy.autoneg = AUTONEG_DISABLE;
811 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
815 switch (phy_data->sfp_base) {
816 case XGBE_SFP_BASE_1000_T:
817 case XGBE_SFP_BASE_1000_CX:
818 case XGBE_SFP_BASE_10000_CR:
819 XGBE_SET_SUP(lks, TP);
822 XGBE_SET_SUP(lks, FIBRE);
826 XGBE_LM_COPY(lks, advertising, lks, supported);
829 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
830 enum xgbe_sfp_speed sfp_speed)
832 u8 *sfp_base, min, max;
834 sfp_base = sfp_eeprom->base;
837 case XGBE_SFP_SPEED_1000:
838 min = XGBE_SFP_BASE_BR_1GBE_MIN;
839 max = XGBE_SFP_BASE_BR_1GBE_MAX;
841 case XGBE_SFP_SPEED_10000:
842 min = XGBE_SFP_BASE_BR_10GBE_MIN;
843 max = XGBE_SFP_BASE_BR_10GBE_MAX;
849 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
850 (sfp_base[XGBE_SFP_BASE_BR] <= max));
853 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
855 struct xgbe_phy_data *phy_data = pdata->phy_data;
857 if (phy_data->phydev) {
858 phy_detach(phy_data->phydev);
859 phy_device_remove(phy_data->phydev);
860 phy_device_free(phy_data->phydev);
861 phy_data->phydev = NULL;
865 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
867 struct xgbe_phy_data *phy_data = pdata->phy_data;
868 unsigned int phy_id = phy_data->phydev->phy_id;
870 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
873 /* Enable Base-T AN */
874 phy_write(phy_data->phydev, 0x16, 0x0001);
875 phy_write(phy_data->phydev, 0x00, 0x9140);
876 phy_write(phy_data->phydev, 0x16, 0x0000);
878 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
879 phy_write(phy_data->phydev, 0x1b, 0x9084);
880 phy_write(phy_data->phydev, 0x09, 0x0e00);
881 phy_write(phy_data->phydev, 0x00, 0x8140);
882 phy_write(phy_data->phydev, 0x04, 0x0d01);
883 phy_write(phy_data->phydev, 0x00, 0x9140);
885 phy_data->phydev->supported = PHY_GBIT_FEATURES;
886 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
887 phy_data->phydev->advertising = phy_data->phydev->supported;
889 netif_dbg(pdata, drv, pdata->netdev,
890 "Finisar PHY quirk in place\n");
895 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
897 if (xgbe_phy_finisar_phy_quirks(pdata))
901 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
903 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
904 struct xgbe_phy_data *phy_data = pdata->phy_data;
905 struct phy_device *phydev;
909 /* If we already have a PHY, just return */
910 if (phy_data->phydev)
913 /* Check for the use of an external PHY */
914 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
917 /* For SFP, only use an external PHY if available */
918 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
919 !phy_data->sfp_phy_avail)
922 /* Set the proper MDIO mode for the PHY */
923 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
924 phy_data->phydev_mode);
926 netdev_err(pdata->netdev,
927 "mdio port/clause not compatible (%u/%u)\n",
928 phy_data->mdio_addr, phy_data->phydev_mode);
932 /* Create and connect to the PHY device */
933 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
934 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
935 if (IS_ERR(phydev)) {
936 netdev_err(pdata->netdev, "get_phy_device failed\n");
939 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
942 /*TODO: If c45, add request_module based on one of the MMD ids? */
944 ret = phy_device_register(phydev);
946 netdev_err(pdata->netdev, "phy_device_register failed\n");
947 phy_device_free(phydev);
951 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
952 PHY_INTERFACE_MODE_SGMII);
954 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
955 phy_device_remove(phydev);
956 phy_device_free(phydev);
959 phy_data->phydev = phydev;
961 xgbe_phy_external_phy_quirks(pdata);
963 ethtool_convert_link_mode_to_legacy_u32(&advertising,
964 lks->link_modes.advertising);
965 phydev->advertising &= advertising;
967 phy_start_aneg(phy_data->phydev);
972 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
974 struct xgbe_phy_data *phy_data = pdata->phy_data;
977 if (!phy_data->sfp_changed)
980 phy_data->sfp_phy_avail = 0;
982 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
985 /* Check access to the PHY by reading CTRL1 */
986 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
990 /* Successfully accessed the PHY */
991 phy_data->sfp_phy_avail = 1;
994 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
996 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
998 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1001 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1004 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1010 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1012 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1014 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1017 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1020 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1026 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1028 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1031 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1037 static bool xgbe_phy_belfuse_parse_quirks(struct xgbe_prv_data *pdata)
1039 struct xgbe_phy_data *phy_data = pdata->phy_data;
1040 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1042 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1043 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
1046 if (!memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1047 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) {
1048 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1049 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1050 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1051 if (phy_data->sfp_changed)
1052 netif_dbg(pdata, drv, pdata->netdev,
1053 "Bel-Fuse SFP quirk in place\n");
1060 static bool xgbe_phy_sfp_parse_quirks(struct xgbe_prv_data *pdata)
1062 if (xgbe_phy_belfuse_parse_quirks(pdata))
1068 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1070 struct xgbe_phy_data *phy_data = pdata->phy_data;
1071 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1074 sfp_base = sfp_eeprom->base;
1076 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1079 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1082 /* Update transceiver signals (eeprom extd/options) */
1083 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1084 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1086 if (xgbe_phy_sfp_parse_quirks(pdata))
1089 /* Assume ACTIVE cable unless told it is PASSIVE */
1090 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1091 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1092 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1094 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1097 /* Determine the type of SFP */
1098 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1099 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1100 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1101 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1102 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1103 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1104 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1105 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1106 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1107 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1108 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1109 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1110 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1111 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1112 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1113 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1114 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
1115 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1116 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1118 switch (phy_data->sfp_base) {
1119 case XGBE_SFP_BASE_1000_T:
1120 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1122 case XGBE_SFP_BASE_1000_SX:
1123 case XGBE_SFP_BASE_1000_LX:
1124 case XGBE_SFP_BASE_1000_CX:
1125 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1127 case XGBE_SFP_BASE_10000_SR:
1128 case XGBE_SFP_BASE_10000_LR:
1129 case XGBE_SFP_BASE_10000_LRM:
1130 case XGBE_SFP_BASE_10000_ER:
1131 case XGBE_SFP_BASE_10000_CR:
1132 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1139 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1140 struct xgbe_sfp_eeprom *sfp_eeprom)
1142 struct xgbe_sfp_ascii sfp_ascii;
1143 char *sfp_data = (char *)&sfp_ascii;
1145 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1146 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1147 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1148 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1149 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1152 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1153 XGBE_SFP_BASE_VENDOR_PN_LEN);
1154 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1155 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1158 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1159 XGBE_SFP_BASE_VENDOR_REV_LEN);
1160 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1161 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1164 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1165 XGBE_SFP_BASE_VENDOR_SN_LEN);
1166 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1167 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1171 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1175 for (cc = 0; len; buf++, len--)
1178 return (cc == cc_in) ? true : false;
1181 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1183 struct xgbe_phy_data *phy_data = pdata->phy_data;
1184 struct xgbe_sfp_eeprom sfp_eeprom;
1188 ret = xgbe_phy_sfp_get_mux(pdata);
1190 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1191 netdev_name(pdata->netdev));
1195 /* Read the SFP serial ID eeprom */
1197 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1198 &eeprom_addr, sizeof(eeprom_addr),
1199 &sfp_eeprom, sizeof(sfp_eeprom));
1201 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1202 netdev_name(pdata->netdev));
1206 /* Validate the contents read */
1207 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1209 sizeof(sfp_eeprom.base) - 1)) {
1214 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1216 sizeof(sfp_eeprom.extd) - 1)) {
1221 /* Check for an added or changed SFP */
1222 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1223 phy_data->sfp_changed = 1;
1225 if (netif_msg_drv(pdata))
1226 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1228 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1230 if (sfp_eeprom.extd[XGBE_SFP_EXTD_SFF_8472]) {
1231 u8 diag_type = sfp_eeprom.extd[XGBE_SFP_EXTD_DIAG];
1233 if (!(diag_type & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
1234 phy_data->sfp_diags = 1;
1237 xgbe_phy_free_phy_device(pdata);
1239 phy_data->sfp_changed = 0;
1243 xgbe_phy_sfp_put_mux(pdata);
1248 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1250 struct xgbe_phy_data *phy_data = pdata->phy_data;
1251 u8 gpio_reg, gpio_ports[2];
1254 /* Read the input port registers */
1256 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1257 &gpio_reg, sizeof(gpio_reg),
1258 gpio_ports, sizeof(gpio_ports));
1260 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1261 netdev_name(pdata->netdev));
1265 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1267 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1270 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1272 struct xgbe_phy_data *phy_data = pdata->phy_data;
1274 xgbe_phy_free_phy_device(pdata);
1276 phy_data->sfp_mod_absent = 1;
1277 phy_data->sfp_phy_avail = 0;
1278 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1281 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1283 phy_data->sfp_rx_los = 0;
1284 phy_data->sfp_tx_fault = 0;
1285 phy_data->sfp_mod_absent = 1;
1286 phy_data->sfp_diags = 0;
1287 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1288 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1289 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1292 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1294 struct xgbe_phy_data *phy_data = pdata->phy_data;
1297 /* Reset the SFP signals and info */
1298 xgbe_phy_sfp_reset(phy_data);
1300 ret = xgbe_phy_get_comm_ownership(pdata);
1304 /* Read the SFP signals and check for module presence */
1305 xgbe_phy_sfp_signals(pdata);
1306 if (phy_data->sfp_mod_absent) {
1307 xgbe_phy_sfp_mod_absent(pdata);
1311 ret = xgbe_phy_sfp_read_eeprom(pdata);
1313 /* Treat any error as if there isn't an SFP plugged in */
1314 xgbe_phy_sfp_reset(phy_data);
1315 xgbe_phy_sfp_mod_absent(pdata);
1319 xgbe_phy_sfp_parse_eeprom(pdata);
1321 xgbe_phy_sfp_external_phy(pdata);
1324 xgbe_phy_sfp_phy_settings(pdata);
1326 xgbe_phy_put_comm_ownership(pdata);
1329 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1331 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1332 struct xgbe_phy_data *phy_data = pdata->phy_data;
1333 u16 lcl_adv = 0, rmt_adv = 0;
1336 pdata->phy.tx_pause = 0;
1337 pdata->phy.rx_pause = 0;
1339 if (!phy_data->phydev)
1342 if (phy_data->phydev->advertising & ADVERTISED_Pause)
1343 lcl_adv |= ADVERTISE_PAUSE_CAP;
1344 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause)
1345 lcl_adv |= ADVERTISE_PAUSE_ASYM;
1347 if (phy_data->phydev->pause) {
1348 XGBE_SET_LP_ADV(lks, Pause);
1349 rmt_adv |= LPA_PAUSE_CAP;
1351 if (phy_data->phydev->asym_pause) {
1352 XGBE_SET_LP_ADV(lks, Asym_Pause);
1353 rmt_adv |= LPA_PAUSE_ASYM;
1356 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1357 if (fc & FLOW_CTRL_TX)
1358 pdata->phy.tx_pause = 1;
1359 if (fc & FLOW_CTRL_RX)
1360 pdata->phy.rx_pause = 1;
1363 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1365 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1366 enum xgbe_mode mode;
1368 XGBE_SET_LP_ADV(lks, Autoneg);
1369 XGBE_SET_LP_ADV(lks, TP);
1371 /* Use external PHY to determine flow control */
1372 if (pdata->phy.pause_autoneg)
1373 xgbe_phy_phydev_flowctrl(pdata);
1375 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1376 case XGBE_SGMII_AN_LINK_SPEED_100:
1377 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1378 XGBE_SET_LP_ADV(lks, 100baseT_Full);
1379 mode = XGBE_MODE_SGMII_100;
1381 /* Half-duplex not supported */
1382 XGBE_SET_LP_ADV(lks, 100baseT_Half);
1383 mode = XGBE_MODE_UNKNOWN;
1386 case XGBE_SGMII_AN_LINK_SPEED_1000:
1387 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1388 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1389 mode = XGBE_MODE_SGMII_1000;
1391 /* Half-duplex not supported */
1392 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1393 mode = XGBE_MODE_UNKNOWN;
1397 mode = XGBE_MODE_UNKNOWN;
1403 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1405 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1406 enum xgbe_mode mode;
1407 unsigned int ad_reg, lp_reg;
1409 XGBE_SET_LP_ADV(lks, Autoneg);
1410 XGBE_SET_LP_ADV(lks, FIBRE);
1412 /* Compare Advertisement and Link Partner register */
1413 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1414 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1416 XGBE_SET_LP_ADV(lks, Pause);
1418 XGBE_SET_LP_ADV(lks, Asym_Pause);
1420 if (pdata->phy.pause_autoneg) {
1421 /* Set flow control based on auto-negotiation result */
1422 pdata->phy.tx_pause = 0;
1423 pdata->phy.rx_pause = 0;
1425 if (ad_reg & lp_reg & 0x100) {
1426 pdata->phy.tx_pause = 1;
1427 pdata->phy.rx_pause = 1;
1428 } else if (ad_reg & lp_reg & 0x80) {
1430 pdata->phy.rx_pause = 1;
1431 else if (lp_reg & 0x100)
1432 pdata->phy.tx_pause = 1;
1437 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1439 /* Half duplex is not supported */
1441 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1446 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1448 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1449 struct xgbe_phy_data *phy_data = pdata->phy_data;
1450 enum xgbe_mode mode;
1451 unsigned int ad_reg, lp_reg;
1453 XGBE_SET_LP_ADV(lks, Autoneg);
1454 XGBE_SET_LP_ADV(lks, Backplane);
1456 /* Use external PHY to determine flow control */
1457 if (pdata->phy.pause_autoneg)
1458 xgbe_phy_phydev_flowctrl(pdata);
1460 /* Compare Advertisement and Link Partner register 2 */
1461 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1462 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1464 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1466 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1469 if (ad_reg & 0x80) {
1470 switch (phy_data->port_mode) {
1471 case XGBE_PORT_MODE_BACKPLANE:
1472 mode = XGBE_MODE_KR;
1475 mode = XGBE_MODE_SFI;
1478 } else if (ad_reg & 0x20) {
1479 switch (phy_data->port_mode) {
1480 case XGBE_PORT_MODE_BACKPLANE:
1481 mode = XGBE_MODE_KX_1000;
1483 case XGBE_PORT_MODE_1000BASE_X:
1486 case XGBE_PORT_MODE_SFP:
1487 switch (phy_data->sfp_base) {
1488 case XGBE_SFP_BASE_1000_T:
1489 if (phy_data->phydev &&
1490 (phy_data->phydev->speed == SPEED_100))
1491 mode = XGBE_MODE_SGMII_100;
1493 mode = XGBE_MODE_SGMII_1000;
1495 case XGBE_SFP_BASE_1000_SX:
1496 case XGBE_SFP_BASE_1000_LX:
1497 case XGBE_SFP_BASE_1000_CX:
1504 if (phy_data->phydev &&
1505 (phy_data->phydev->speed == SPEED_100))
1506 mode = XGBE_MODE_SGMII_100;
1508 mode = XGBE_MODE_SGMII_1000;
1512 mode = XGBE_MODE_UNKNOWN;
1515 /* Compare Advertisement and Link Partner register 3 */
1516 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1517 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1518 if (lp_reg & 0xc000)
1519 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1524 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1526 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1527 enum xgbe_mode mode;
1528 unsigned int ad_reg, lp_reg;
1530 XGBE_SET_LP_ADV(lks, Autoneg);
1531 XGBE_SET_LP_ADV(lks, Backplane);
1533 /* Compare Advertisement and Link Partner register 1 */
1534 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1535 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1537 XGBE_SET_LP_ADV(lks, Pause);
1539 XGBE_SET_LP_ADV(lks, Asym_Pause);
1541 if (pdata->phy.pause_autoneg) {
1542 /* Set flow control based on auto-negotiation result */
1543 pdata->phy.tx_pause = 0;
1544 pdata->phy.rx_pause = 0;
1546 if (ad_reg & lp_reg & 0x400) {
1547 pdata->phy.tx_pause = 1;
1548 pdata->phy.rx_pause = 1;
1549 } else if (ad_reg & lp_reg & 0x800) {
1551 pdata->phy.rx_pause = 1;
1552 else if (lp_reg & 0x400)
1553 pdata->phy.tx_pause = 1;
1557 /* Compare Advertisement and Link Partner register 2 */
1558 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1559 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1561 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1563 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1567 mode = XGBE_MODE_KR;
1568 else if (ad_reg & 0x20)
1569 mode = XGBE_MODE_KX_1000;
1571 mode = XGBE_MODE_UNKNOWN;
1573 /* Compare Advertisement and Link Partner register 3 */
1574 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1575 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1576 if (lp_reg & 0xc000)
1577 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1582 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1584 switch (pdata->an_mode) {
1585 case XGBE_AN_MODE_CL73:
1586 return xgbe_phy_an73_outcome(pdata);
1587 case XGBE_AN_MODE_CL73_REDRV:
1588 return xgbe_phy_an73_redrv_outcome(pdata);
1589 case XGBE_AN_MODE_CL37:
1590 return xgbe_phy_an37_outcome(pdata);
1591 case XGBE_AN_MODE_CL37_SGMII:
1592 return xgbe_phy_an37_sgmii_outcome(pdata);
1594 return XGBE_MODE_UNKNOWN;
1598 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1599 struct ethtool_link_ksettings *dlks)
1601 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1602 struct xgbe_phy_data *phy_data = pdata->phy_data;
1604 XGBE_LM_COPY(dlks, advertising, slks, advertising);
1606 /* Without a re-driver, just return current advertising */
1607 if (!phy_data->redrv)
1610 /* With the KR re-driver we need to advertise a single speed */
1611 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1612 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1614 switch (phy_data->port_mode) {
1615 case XGBE_PORT_MODE_BACKPLANE:
1616 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1618 case XGBE_PORT_MODE_BACKPLANE_2500:
1619 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1621 case XGBE_PORT_MODE_1000BASE_T:
1622 case XGBE_PORT_MODE_1000BASE_X:
1623 case XGBE_PORT_MODE_NBASE_T:
1624 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1626 case XGBE_PORT_MODE_10GBASE_T:
1627 if (phy_data->phydev &&
1628 (phy_data->phydev->speed == SPEED_10000))
1629 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1631 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1633 case XGBE_PORT_MODE_10GBASE_R:
1634 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1636 case XGBE_PORT_MODE_SFP:
1637 switch (phy_data->sfp_base) {
1638 case XGBE_SFP_BASE_1000_T:
1639 case XGBE_SFP_BASE_1000_SX:
1640 case XGBE_SFP_BASE_1000_LX:
1641 case XGBE_SFP_BASE_1000_CX:
1642 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1645 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1650 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1655 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1657 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1658 struct xgbe_phy_data *phy_data = pdata->phy_data;
1662 ret = xgbe_phy_find_phy_device(pdata);
1666 if (!phy_data->phydev)
1669 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1670 lks->link_modes.advertising);
1672 phy_data->phydev->autoneg = pdata->phy.autoneg;
1673 phy_data->phydev->advertising = phy_data->phydev->supported &
1676 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1677 phy_data->phydev->speed = pdata->phy.speed;
1678 phy_data->phydev->duplex = pdata->phy.duplex;
1681 ret = phy_start_aneg(phy_data->phydev);
1686 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1688 switch (phy_data->sfp_base) {
1689 case XGBE_SFP_BASE_1000_T:
1690 return XGBE_AN_MODE_CL37_SGMII;
1691 case XGBE_SFP_BASE_1000_SX:
1692 case XGBE_SFP_BASE_1000_LX:
1693 case XGBE_SFP_BASE_1000_CX:
1694 return XGBE_AN_MODE_CL37;
1696 return XGBE_AN_MODE_NONE;
1700 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1702 struct xgbe_phy_data *phy_data = pdata->phy_data;
1704 /* A KR re-driver will always require CL73 AN */
1705 if (phy_data->redrv)
1706 return XGBE_AN_MODE_CL73_REDRV;
1708 switch (phy_data->port_mode) {
1709 case XGBE_PORT_MODE_BACKPLANE:
1710 return XGBE_AN_MODE_CL73;
1711 case XGBE_PORT_MODE_BACKPLANE_2500:
1712 return XGBE_AN_MODE_NONE;
1713 case XGBE_PORT_MODE_1000BASE_T:
1714 return XGBE_AN_MODE_CL37_SGMII;
1715 case XGBE_PORT_MODE_1000BASE_X:
1716 return XGBE_AN_MODE_CL37;
1717 case XGBE_PORT_MODE_NBASE_T:
1718 return XGBE_AN_MODE_CL37_SGMII;
1719 case XGBE_PORT_MODE_10GBASE_T:
1720 return XGBE_AN_MODE_CL73;
1721 case XGBE_PORT_MODE_10GBASE_R:
1722 return XGBE_AN_MODE_NONE;
1723 case XGBE_PORT_MODE_SFP:
1724 return xgbe_phy_an_sfp_mode(phy_data);
1726 return XGBE_AN_MODE_NONE;
1730 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1731 enum xgbe_phy_redrv_mode mode)
1733 struct xgbe_phy_data *phy_data = pdata->phy_data;
1734 u16 redrv_reg, redrv_val;
1736 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1737 redrv_val = (u16)mode;
1739 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1740 redrv_reg, redrv_val);
1743 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1744 enum xgbe_phy_redrv_mode mode)
1746 struct xgbe_phy_data *phy_data = pdata->phy_data;
1747 unsigned int redrv_reg;
1750 /* Calculate the register to write */
1751 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1753 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1758 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1760 struct xgbe_phy_data *phy_data = pdata->phy_data;
1761 enum xgbe_phy_redrv_mode mode;
1764 if (!phy_data->redrv)
1767 mode = XGBE_PHY_REDRV_MODE_CX;
1768 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1769 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1770 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1771 mode = XGBE_PHY_REDRV_MODE_SR;
1773 ret = xgbe_phy_get_comm_ownership(pdata);
1777 if (phy_data->redrv_if)
1778 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1780 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1782 xgbe_phy_put_comm_ownership(pdata);
1785 static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
1789 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
1790 XGBE_PCS_PSEQ_STATE_MASK);
1791 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
1792 /* Mailbox command timed out, reset of RX block is required.
1793 * This can be done by asseting the reset bit and wait for
1796 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1797 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
1799 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1800 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
1801 usleep_range(40, 50);
1802 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n");
1806 static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
1808 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
1809 XGBE_PMA_PLL_CTRL_MASK,
1810 enable ? XGBE_PMA_PLL_CTRL_ENABLE
1811 : XGBE_PMA_PLL_CTRL_DISABLE);
1813 /* Wait for command to complete */
1814 usleep_range(100, 200);
1817 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
1818 unsigned int cmd, unsigned int sub_cmd)
1820 unsigned int s0 = 0;
1823 /* Disable PLL re-initialization during FW command processing */
1824 xgbe_phy_pll_ctrl(pdata, false);
1826 /* Log if a previous command did not complete */
1827 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
1828 netif_dbg(pdata, link, pdata->netdev,
1829 "firmware mailbox not ready for command\n");
1830 xgbe_phy_rx_reset(pdata);
1833 /* Construct the command */
1834 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
1835 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
1837 /* Issue the command */
1838 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1839 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1840 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1842 /* Wait for command to complete */
1843 wait = XGBE_RATECHANGE_COUNT;
1845 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1848 usleep_range(1000, 2000);
1851 netif_dbg(pdata, link, pdata->netdev,
1852 "firmware mailbox command did not complete\n");
1854 /* Reset on error */
1855 xgbe_phy_rx_reset(pdata);
1858 /* Enable PLL re-initialization */
1859 xgbe_phy_pll_ctrl(pdata, true);
1862 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
1864 /* Receiver Reset Cycle */
1865 xgbe_phy_perform_ratechange(pdata, 5, 0);
1867 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
1870 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
1872 struct xgbe_phy_data *phy_data = pdata->phy_data;
1875 xgbe_phy_perform_ratechange(pdata, 0, 0);
1877 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
1879 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
1882 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
1884 struct xgbe_phy_data *phy_data = pdata->phy_data;
1886 xgbe_phy_set_redrv_mode(pdata);
1889 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
1890 xgbe_phy_perform_ratechange(pdata, 3, 0);
1892 if (phy_data->sfp_cable_len <= 1)
1893 xgbe_phy_perform_ratechange(pdata, 3, 1);
1894 else if (phy_data->sfp_cable_len <= 3)
1895 xgbe_phy_perform_ratechange(pdata, 3, 2);
1897 xgbe_phy_perform_ratechange(pdata, 3, 3);
1900 phy_data->cur_mode = XGBE_MODE_SFI;
1902 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
1905 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
1907 struct xgbe_phy_data *phy_data = pdata->phy_data;
1909 xgbe_phy_set_redrv_mode(pdata);
1912 xgbe_phy_perform_ratechange(pdata, 1, 3);
1914 phy_data->cur_mode = XGBE_MODE_X;
1916 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
1919 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
1921 struct xgbe_phy_data *phy_data = pdata->phy_data;
1923 xgbe_phy_set_redrv_mode(pdata);
1926 xgbe_phy_perform_ratechange(pdata, 1, 2);
1928 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
1930 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
1933 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
1935 struct xgbe_phy_data *phy_data = pdata->phy_data;
1937 xgbe_phy_set_redrv_mode(pdata);
1940 xgbe_phy_perform_ratechange(pdata, 1, 1);
1942 phy_data->cur_mode = XGBE_MODE_SGMII_100;
1944 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
1947 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
1949 struct xgbe_phy_data *phy_data = pdata->phy_data;
1951 xgbe_phy_set_redrv_mode(pdata);
1954 xgbe_phy_perform_ratechange(pdata, 4, 0);
1956 phy_data->cur_mode = XGBE_MODE_KR;
1958 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
1961 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
1963 struct xgbe_phy_data *phy_data = pdata->phy_data;
1965 xgbe_phy_set_redrv_mode(pdata);
1968 xgbe_phy_perform_ratechange(pdata, 2, 0);
1970 phy_data->cur_mode = XGBE_MODE_KX_2500;
1972 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
1975 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
1977 struct xgbe_phy_data *phy_data = pdata->phy_data;
1979 xgbe_phy_set_redrv_mode(pdata);
1982 xgbe_phy_perform_ratechange(pdata, 1, 3);
1984 phy_data->cur_mode = XGBE_MODE_KX_1000;
1986 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
1989 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
1991 struct xgbe_phy_data *phy_data = pdata->phy_data;
1993 return phy_data->cur_mode;
1996 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
1998 struct xgbe_phy_data *phy_data = pdata->phy_data;
2000 /* No switching if not 10GBase-T */
2001 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2002 return xgbe_phy_cur_mode(pdata);
2004 switch (xgbe_phy_cur_mode(pdata)) {
2005 case XGBE_MODE_SGMII_100:
2006 case XGBE_MODE_SGMII_1000:
2007 return XGBE_MODE_KR;
2010 return XGBE_MODE_SGMII_1000;
2014 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2016 return XGBE_MODE_KX_2500;
2019 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2021 /* If we are in KR switch to KX, and vice-versa */
2022 switch (xgbe_phy_cur_mode(pdata)) {
2023 case XGBE_MODE_KX_1000:
2024 return XGBE_MODE_KR;
2027 return XGBE_MODE_KX_1000;
2031 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2033 struct xgbe_phy_data *phy_data = pdata->phy_data;
2035 switch (phy_data->port_mode) {
2036 case XGBE_PORT_MODE_BACKPLANE:
2037 return xgbe_phy_switch_bp_mode(pdata);
2038 case XGBE_PORT_MODE_BACKPLANE_2500:
2039 return xgbe_phy_switch_bp_2500_mode(pdata);
2040 case XGBE_PORT_MODE_1000BASE_T:
2041 case XGBE_PORT_MODE_NBASE_T:
2042 case XGBE_PORT_MODE_10GBASE_T:
2043 return xgbe_phy_switch_baset_mode(pdata);
2044 case XGBE_PORT_MODE_1000BASE_X:
2045 case XGBE_PORT_MODE_10GBASE_R:
2046 case XGBE_PORT_MODE_SFP:
2047 /* No switching, so just return current mode */
2048 return xgbe_phy_cur_mode(pdata);
2050 return XGBE_MODE_UNKNOWN;
2054 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2061 return XGBE_MODE_KR;
2063 return XGBE_MODE_UNKNOWN;
2067 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2072 return XGBE_MODE_SGMII_100;
2074 return XGBE_MODE_SGMII_1000;
2076 return XGBE_MODE_KX_2500;
2078 return XGBE_MODE_KR;
2080 return XGBE_MODE_UNKNOWN;
2084 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2089 return XGBE_MODE_SGMII_100;
2091 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2092 return XGBE_MODE_SGMII_1000;
2097 return XGBE_MODE_SFI;
2099 return XGBE_MODE_UNKNOWN;
2103 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2107 return XGBE_MODE_KX_2500;
2109 return XGBE_MODE_UNKNOWN;
2113 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2117 return XGBE_MODE_KX_1000;
2119 return XGBE_MODE_KR;
2121 return XGBE_MODE_UNKNOWN;
2125 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2128 struct xgbe_phy_data *phy_data = pdata->phy_data;
2130 switch (phy_data->port_mode) {
2131 case XGBE_PORT_MODE_BACKPLANE:
2132 return xgbe_phy_get_bp_mode(speed);
2133 case XGBE_PORT_MODE_BACKPLANE_2500:
2134 return xgbe_phy_get_bp_2500_mode(speed);
2135 case XGBE_PORT_MODE_1000BASE_T:
2136 case XGBE_PORT_MODE_NBASE_T:
2137 case XGBE_PORT_MODE_10GBASE_T:
2138 return xgbe_phy_get_baset_mode(phy_data, speed);
2139 case XGBE_PORT_MODE_1000BASE_X:
2140 case XGBE_PORT_MODE_10GBASE_R:
2141 return xgbe_phy_get_basex_mode(phy_data, speed);
2142 case XGBE_PORT_MODE_SFP:
2143 return xgbe_phy_get_sfp_mode(phy_data, speed);
2145 return XGBE_MODE_UNKNOWN;
2149 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2152 case XGBE_MODE_KX_1000:
2153 xgbe_phy_kx_1000_mode(pdata);
2155 case XGBE_MODE_KX_2500:
2156 xgbe_phy_kx_2500_mode(pdata);
2159 xgbe_phy_kr_mode(pdata);
2161 case XGBE_MODE_SGMII_100:
2162 xgbe_phy_sgmii_100_mode(pdata);
2164 case XGBE_MODE_SGMII_1000:
2165 xgbe_phy_sgmii_1000_mode(pdata);
2168 xgbe_phy_x_mode(pdata);
2171 xgbe_phy_sfi_mode(pdata);
2178 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2179 enum xgbe_mode mode, bool advert)
2181 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2184 enum xgbe_mode cur_mode;
2186 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2187 if (cur_mode == mode)
2194 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2195 enum xgbe_mode mode)
2197 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2201 return xgbe_phy_check_mode(pdata, mode,
2202 XGBE_ADV(lks, 1000baseX_Full));
2204 return xgbe_phy_check_mode(pdata, mode,
2205 XGBE_ADV(lks, 10000baseKR_Full));
2211 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2212 enum xgbe_mode mode)
2214 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2217 case XGBE_MODE_SGMII_100:
2218 return xgbe_phy_check_mode(pdata, mode,
2219 XGBE_ADV(lks, 100baseT_Full));
2220 case XGBE_MODE_SGMII_1000:
2221 return xgbe_phy_check_mode(pdata, mode,
2222 XGBE_ADV(lks, 1000baseT_Full));
2223 case XGBE_MODE_KX_2500:
2224 return xgbe_phy_check_mode(pdata, mode,
2225 XGBE_ADV(lks, 2500baseT_Full));
2227 return xgbe_phy_check_mode(pdata, mode,
2228 XGBE_ADV(lks, 10000baseT_Full));
2234 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2235 enum xgbe_mode mode)
2237 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2238 struct xgbe_phy_data *phy_data = pdata->phy_data;
2242 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2244 return xgbe_phy_check_mode(pdata, mode,
2245 XGBE_ADV(lks, 1000baseX_Full));
2246 case XGBE_MODE_SGMII_100:
2247 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2249 return xgbe_phy_check_mode(pdata, mode,
2250 XGBE_ADV(lks, 100baseT_Full));
2251 case XGBE_MODE_SGMII_1000:
2252 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2254 return xgbe_phy_check_mode(pdata, mode,
2255 XGBE_ADV(lks, 1000baseT_Full));
2257 if (phy_data->sfp_mod_absent)
2259 return xgbe_phy_check_mode(pdata, mode,
2260 XGBE_ADV(lks, 10000baseSR_Full) ||
2261 XGBE_ADV(lks, 10000baseLR_Full) ||
2262 XGBE_ADV(lks, 10000baseLRM_Full) ||
2263 XGBE_ADV(lks, 10000baseER_Full) ||
2264 XGBE_ADV(lks, 10000baseCR_Full));
2270 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2271 enum xgbe_mode mode)
2273 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2276 case XGBE_MODE_KX_2500:
2277 return xgbe_phy_check_mode(pdata, mode,
2278 XGBE_ADV(lks, 2500baseX_Full));
2284 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2285 enum xgbe_mode mode)
2287 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2290 case XGBE_MODE_KX_1000:
2291 return xgbe_phy_check_mode(pdata, mode,
2292 XGBE_ADV(lks, 1000baseKX_Full));
2294 return xgbe_phy_check_mode(pdata, mode,
2295 XGBE_ADV(lks, 10000baseKR_Full));
2301 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2303 struct xgbe_phy_data *phy_data = pdata->phy_data;
2305 switch (phy_data->port_mode) {
2306 case XGBE_PORT_MODE_BACKPLANE:
2307 return xgbe_phy_use_bp_mode(pdata, mode);
2308 case XGBE_PORT_MODE_BACKPLANE_2500:
2309 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2310 case XGBE_PORT_MODE_1000BASE_T:
2311 case XGBE_PORT_MODE_NBASE_T:
2312 case XGBE_PORT_MODE_10GBASE_T:
2313 return xgbe_phy_use_baset_mode(pdata, mode);
2314 case XGBE_PORT_MODE_1000BASE_X:
2315 case XGBE_PORT_MODE_10GBASE_R:
2316 return xgbe_phy_use_basex_mode(pdata, mode);
2317 case XGBE_PORT_MODE_SFP:
2318 return xgbe_phy_use_sfp_mode(pdata, mode);
2324 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2329 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2331 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2337 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2345 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2347 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2353 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2358 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2360 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2361 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2363 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2369 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2379 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2390 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2392 struct xgbe_phy_data *phy_data = pdata->phy_data;
2394 switch (phy_data->port_mode) {
2395 case XGBE_PORT_MODE_BACKPLANE:
2396 return xgbe_phy_valid_speed_bp_mode(speed);
2397 case XGBE_PORT_MODE_BACKPLANE_2500:
2398 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2399 case XGBE_PORT_MODE_1000BASE_T:
2400 case XGBE_PORT_MODE_NBASE_T:
2401 case XGBE_PORT_MODE_10GBASE_T:
2402 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2403 case XGBE_PORT_MODE_1000BASE_X:
2404 case XGBE_PORT_MODE_10GBASE_R:
2405 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2406 case XGBE_PORT_MODE_SFP:
2407 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
2413 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2415 struct xgbe_phy_data *phy_data = pdata->phy_data;
2421 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2422 /* Check SFP signals */
2423 xgbe_phy_sfp_detect(pdata);
2425 if (phy_data->sfp_changed) {
2430 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2434 if (phy_data->phydev) {
2435 /* Check external PHY */
2436 ret = phy_read_status(phy_data->phydev);
2440 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2441 !phy_aneg_done(phy_data->phydev))
2444 if (!phy_data->phydev->link)
2448 /* Link status is latched low, so read once to clear
2449 * and then read again to get current state
2451 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2452 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2453 if (reg & MDIO_STAT1_LSTATUS)
2456 if (pdata->phy.autoneg == AUTONEG_ENABLE &&
2457 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) {
2458 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
2459 netif_carrier_off(pdata->netdev);
2464 /* No link, attempt a receiver reset cycle */
2465 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2466 phy_data->rrc_count = 0;
2467 xgbe_phy_rrc(pdata);
2473 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2475 struct xgbe_phy_data *phy_data = pdata->phy_data;
2478 reg = XP_IOREAD(pdata, XP_PROP_3);
2480 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2481 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
2483 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
2485 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
2487 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
2489 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
2491 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
2494 if (netif_msg_probe(pdata)) {
2495 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2496 phy_data->sfp_gpio_address);
2497 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2498 phy_data->sfp_gpio_mask);
2499 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2500 phy_data->sfp_gpio_rx_los);
2501 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2502 phy_data->sfp_gpio_tx_fault);
2503 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2504 phy_data->sfp_gpio_mod_absent);
2505 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2506 phy_data->sfp_gpio_rate_select);
2510 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2512 struct xgbe_phy_data *phy_data = pdata->phy_data;
2513 unsigned int reg, mux_addr_hi, mux_addr_lo;
2515 reg = XP_IOREAD(pdata, XP_PROP_4);
2517 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
2518 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
2519 if (mux_addr_lo == XGBE_SFP_DIRECT)
2522 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2523 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2524 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
2526 if (netif_msg_probe(pdata)) {
2527 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2528 phy_data->sfp_mux_address);
2529 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2530 phy_data->sfp_mux_channel);
2534 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2536 xgbe_phy_sfp_comm_setup(pdata);
2537 xgbe_phy_sfp_gpio_setup(pdata);
2540 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2542 struct xgbe_phy_data *phy_data = pdata->phy_data;
2545 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2549 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2554 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2556 struct xgbe_phy_data *phy_data = pdata->phy_data;
2557 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2560 /* Read the output port registers */
2562 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2563 &gpio_reg, sizeof(gpio_reg),
2564 gpio_ports, sizeof(gpio_ports));
2568 /* Prepare to write the GPIO data */
2570 gpio_data[1] = gpio_ports[0];
2571 gpio_data[2] = gpio_ports[1];
2573 /* Set the GPIO pin */
2574 if (phy_data->mdio_reset_gpio < 8)
2575 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2577 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2579 /* Write the output port registers */
2580 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2581 gpio_data, sizeof(gpio_data));
2585 /* Clear the GPIO pin */
2586 if (phy_data->mdio_reset_gpio < 8)
2587 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2589 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2591 /* Write the output port registers */
2592 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2593 gpio_data, sizeof(gpio_data));
2598 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2600 struct xgbe_phy_data *phy_data = pdata->phy_data;
2603 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2606 ret = xgbe_phy_get_comm_ownership(pdata);
2610 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2611 ret = xgbe_phy_i2c_mdio_reset(pdata);
2612 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2613 ret = xgbe_phy_int_mdio_reset(pdata);
2615 xgbe_phy_put_comm_ownership(pdata);
2620 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2622 if (!phy_data->redrv)
2625 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2628 switch (phy_data->redrv_model) {
2629 case XGBE_PHY_REDRV_MODEL_4223:
2630 if (phy_data->redrv_lane > 3)
2633 case XGBE_PHY_REDRV_MODEL_4227:
2634 if (phy_data->redrv_lane > 1)
2644 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2646 struct xgbe_phy_data *phy_data = pdata->phy_data;
2649 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2652 reg = XP_IOREAD(pdata, XP_PROP_3);
2653 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
2654 switch (phy_data->mdio_reset) {
2655 case XGBE_MDIO_RESET_NONE:
2656 case XGBE_MDIO_RESET_I2C_GPIO:
2657 case XGBE_MDIO_RESET_INT_GPIO:
2660 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2661 phy_data->mdio_reset);
2665 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2666 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
2667 XP_GET_BITS(reg, XP_PROP_3,
2668 MDIO_RESET_I2C_ADDR);
2669 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
2670 MDIO_RESET_I2C_GPIO);
2671 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
2672 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
2673 MDIO_RESET_INT_GPIO);
2679 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2681 struct xgbe_phy_data *phy_data = pdata->phy_data;
2683 switch (phy_data->port_mode) {
2684 case XGBE_PORT_MODE_BACKPLANE:
2685 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2686 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2689 case XGBE_PORT_MODE_BACKPLANE_2500:
2690 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2693 case XGBE_PORT_MODE_1000BASE_T:
2694 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2695 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2698 case XGBE_PORT_MODE_1000BASE_X:
2699 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2702 case XGBE_PORT_MODE_NBASE_T:
2703 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2704 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2705 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2708 case XGBE_PORT_MODE_10GBASE_T:
2709 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2710 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2711 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2714 case XGBE_PORT_MODE_10GBASE_R:
2715 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2718 case XGBE_PORT_MODE_SFP:
2719 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2720 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2721 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2731 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2733 struct xgbe_phy_data *phy_data = pdata->phy_data;
2735 switch (phy_data->port_mode) {
2736 case XGBE_PORT_MODE_BACKPLANE:
2737 case XGBE_PORT_MODE_BACKPLANE_2500:
2738 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2741 case XGBE_PORT_MODE_1000BASE_T:
2742 case XGBE_PORT_MODE_1000BASE_X:
2743 case XGBE_PORT_MODE_NBASE_T:
2744 case XGBE_PORT_MODE_10GBASE_T:
2745 case XGBE_PORT_MODE_10GBASE_R:
2746 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2749 case XGBE_PORT_MODE_SFP:
2750 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2760 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2764 reg = XP_IOREAD(pdata, XP_PROP_0);
2765 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
2767 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
2773 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
2775 struct xgbe_phy_data *phy_data = pdata->phy_data;
2777 if (!pdata->debugfs_an_cdr_workaround)
2780 if (!phy_data->phy_cdr_notrack)
2783 usleep_range(phy_data->phy_cdr_delay,
2784 phy_data->phy_cdr_delay + 500);
2786 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2787 XGBE_PMA_CDR_TRACK_EN_MASK,
2788 XGBE_PMA_CDR_TRACK_EN_ON);
2790 phy_data->phy_cdr_notrack = 0;
2793 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
2795 struct xgbe_phy_data *phy_data = pdata->phy_data;
2797 if (!pdata->debugfs_an_cdr_workaround)
2800 if (phy_data->phy_cdr_notrack)
2803 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2804 XGBE_PMA_CDR_TRACK_EN_MASK,
2805 XGBE_PMA_CDR_TRACK_EN_OFF);
2807 xgbe_phy_rrc(pdata);
2809 phy_data->phy_cdr_notrack = 1;
2812 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
2814 if (!pdata->debugfs_an_cdr_track_early)
2815 xgbe_phy_cdr_track(pdata);
2818 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
2820 if (pdata->debugfs_an_cdr_track_early)
2821 xgbe_phy_cdr_track(pdata);
2824 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
2826 struct xgbe_phy_data *phy_data = pdata->phy_data;
2828 switch (pdata->an_mode) {
2829 case XGBE_AN_MODE_CL73:
2830 case XGBE_AN_MODE_CL73_REDRV:
2831 if (phy_data->cur_mode != XGBE_MODE_KR)
2834 xgbe_phy_cdr_track(pdata);
2836 switch (pdata->an_result) {
2838 case XGBE_AN_COMPLETE:
2841 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
2842 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
2844 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
2853 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
2855 struct xgbe_phy_data *phy_data = pdata->phy_data;
2857 switch (pdata->an_mode) {
2858 case XGBE_AN_MODE_CL73:
2859 case XGBE_AN_MODE_CL73_REDRV:
2860 if (phy_data->cur_mode != XGBE_MODE_KR)
2863 xgbe_phy_cdr_notrack(pdata);
2870 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
2872 struct xgbe_phy_data *phy_data = pdata->phy_data;
2874 /* If we have an external PHY, free it */
2875 xgbe_phy_free_phy_device(pdata);
2877 /* Reset SFP data */
2878 xgbe_phy_sfp_reset(phy_data);
2879 xgbe_phy_sfp_mod_absent(pdata);
2881 /* Reset CDR support */
2882 xgbe_phy_cdr_track(pdata);
2884 /* Power off the PHY */
2885 xgbe_phy_power_off(pdata);
2887 /* Stop the I2C controller */
2888 pdata->i2c_if.i2c_stop(pdata);
2891 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
2893 struct xgbe_phy_data *phy_data = pdata->phy_data;
2896 /* Start the I2C controller */
2897 ret = pdata->i2c_if.i2c_start(pdata);
2901 /* Set the proper MDIO mode for the re-driver */
2902 if (phy_data->redrv && !phy_data->redrv_if) {
2903 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
2904 XGBE_MDIO_MODE_CL22);
2906 netdev_err(pdata->netdev,
2907 "redriver mdio port not compatible (%u)\n",
2908 phy_data->redrv_addr);
2913 /* Start in highest supported mode */
2914 xgbe_phy_set_mode(pdata, phy_data->start_mode);
2916 /* Reset CDR support */
2917 xgbe_phy_cdr_track(pdata);
2919 /* After starting the I2C controller, we can check for an SFP */
2920 switch (phy_data->port_mode) {
2921 case XGBE_PORT_MODE_SFP:
2922 xgbe_phy_sfp_detect(pdata);
2928 /* If we have an external PHY, start it */
2929 ret = xgbe_phy_find_phy_device(pdata);
2936 pdata->i2c_if.i2c_stop(pdata);
2941 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
2943 struct xgbe_phy_data *phy_data = pdata->phy_data;
2944 enum xgbe_mode cur_mode;
2947 /* Reset by power cycling the PHY */
2948 cur_mode = phy_data->cur_mode;
2949 xgbe_phy_power_off(pdata);
2950 xgbe_phy_set_mode(pdata, cur_mode);
2952 if (!phy_data->phydev)
2955 /* Reset the external PHY */
2956 ret = xgbe_phy_mdio_reset(pdata);
2960 return phy_init_hw(phy_data->phydev);
2963 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
2965 struct xgbe_phy_data *phy_data = pdata->phy_data;
2967 /* Unregister for driving external PHYs */
2968 mdiobus_unregister(phy_data->mii);
2971 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
2973 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2974 struct xgbe_phy_data *phy_data;
2975 struct mii_bus *mii;
2979 /* Check if enabled */
2980 if (!xgbe_phy_port_enabled(pdata)) {
2981 dev_info(pdata->dev, "device is not enabled\n");
2985 /* Initialize the I2C controller */
2986 ret = pdata->i2c_if.i2c_init(pdata);
2990 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
2993 pdata->phy_data = phy_data;
2995 reg = XP_IOREAD(pdata, XP_PROP_0);
2996 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
2997 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
2998 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
2999 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
3000 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
3001 if (netif_msg_probe(pdata)) {
3002 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3003 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3004 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3005 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3006 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3009 reg = XP_IOREAD(pdata, XP_PROP_4);
3010 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);
3011 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);
3012 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);
3013 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);
3014 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);
3015 if (phy_data->redrv && netif_msg_probe(pdata)) {
3016 dev_dbg(pdata->dev, "redrv present\n");
3017 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3018 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3019 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3020 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3023 /* Validate the connection requested */
3024 if (xgbe_phy_conn_type_mismatch(pdata)) {
3025 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3026 phy_data->port_mode, phy_data->conn_type);
3030 /* Validate the mode requested */
3031 if (xgbe_phy_port_mode_mismatch(pdata)) {
3032 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3033 phy_data->port_mode, phy_data->port_speeds);
3037 /* Check for and validate MDIO reset support */
3038 ret = xgbe_phy_mdio_reset_setup(pdata);
3042 /* Validate the re-driver information */
3043 if (xgbe_phy_redrv_error(phy_data)) {
3044 dev_err(pdata->dev, "phy re-driver settings error\n");
3047 pdata->kr_redrv = phy_data->redrv;
3049 /* Indicate current mode is unknown */
3050 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3052 /* Initialize supported features */
3055 switch (phy_data->port_mode) {
3056 /* Backplane support */
3057 case XGBE_PORT_MODE_BACKPLANE:
3058 XGBE_SET_SUP(lks, Autoneg);
3059 XGBE_SET_SUP(lks, Pause);
3060 XGBE_SET_SUP(lks, Asym_Pause);
3061 XGBE_SET_SUP(lks, Backplane);
3062 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3063 XGBE_SET_SUP(lks, 1000baseKX_Full);
3064 phy_data->start_mode = XGBE_MODE_KX_1000;
3066 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3067 XGBE_SET_SUP(lks, 10000baseKR_Full);
3068 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3069 XGBE_SET_SUP(lks, 10000baseR_FEC);
3070 phy_data->start_mode = XGBE_MODE_KR;
3073 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3075 case XGBE_PORT_MODE_BACKPLANE_2500:
3076 XGBE_SET_SUP(lks, Pause);
3077 XGBE_SET_SUP(lks, Asym_Pause);
3078 XGBE_SET_SUP(lks, Backplane);
3079 XGBE_SET_SUP(lks, 2500baseX_Full);
3080 phy_data->start_mode = XGBE_MODE_KX_2500;
3082 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3085 /* MDIO 1GBase-T support */
3086 case XGBE_PORT_MODE_1000BASE_T:
3087 XGBE_SET_SUP(lks, Autoneg);
3088 XGBE_SET_SUP(lks, Pause);
3089 XGBE_SET_SUP(lks, Asym_Pause);
3090 XGBE_SET_SUP(lks, TP);
3091 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3092 XGBE_SET_SUP(lks, 100baseT_Full);
3093 phy_data->start_mode = XGBE_MODE_SGMII_100;
3095 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3096 XGBE_SET_SUP(lks, 1000baseT_Full);
3097 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3100 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3103 /* MDIO Base-X support */
3104 case XGBE_PORT_MODE_1000BASE_X:
3105 XGBE_SET_SUP(lks, Autoneg);
3106 XGBE_SET_SUP(lks, Pause);
3107 XGBE_SET_SUP(lks, Asym_Pause);
3108 XGBE_SET_SUP(lks, FIBRE);
3109 XGBE_SET_SUP(lks, 1000baseX_Full);
3110 phy_data->start_mode = XGBE_MODE_X;
3112 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3115 /* MDIO NBase-T support */
3116 case XGBE_PORT_MODE_NBASE_T:
3117 XGBE_SET_SUP(lks, Autoneg);
3118 XGBE_SET_SUP(lks, Pause);
3119 XGBE_SET_SUP(lks, Asym_Pause);
3120 XGBE_SET_SUP(lks, TP);
3121 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3122 XGBE_SET_SUP(lks, 100baseT_Full);
3123 phy_data->start_mode = XGBE_MODE_SGMII_100;
3125 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3126 XGBE_SET_SUP(lks, 1000baseT_Full);
3127 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3129 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3130 XGBE_SET_SUP(lks, 2500baseT_Full);
3131 phy_data->start_mode = XGBE_MODE_KX_2500;
3134 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3137 /* 10GBase-T support */
3138 case XGBE_PORT_MODE_10GBASE_T:
3139 XGBE_SET_SUP(lks, Autoneg);
3140 XGBE_SET_SUP(lks, Pause);
3141 XGBE_SET_SUP(lks, Asym_Pause);
3142 XGBE_SET_SUP(lks, TP);
3143 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3144 XGBE_SET_SUP(lks, 100baseT_Full);
3145 phy_data->start_mode = XGBE_MODE_SGMII_100;
3147 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3148 XGBE_SET_SUP(lks, 1000baseT_Full);
3149 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3151 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3152 XGBE_SET_SUP(lks, 10000baseT_Full);
3153 phy_data->start_mode = XGBE_MODE_KR;
3156 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3159 /* 10GBase-R support */
3160 case XGBE_PORT_MODE_10GBASE_R:
3161 XGBE_SET_SUP(lks, Autoneg);
3162 XGBE_SET_SUP(lks, Pause);
3163 XGBE_SET_SUP(lks, Asym_Pause);
3164 XGBE_SET_SUP(lks, FIBRE);
3165 XGBE_SET_SUP(lks, 10000baseSR_Full);
3166 XGBE_SET_SUP(lks, 10000baseLR_Full);
3167 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3168 XGBE_SET_SUP(lks, 10000baseER_Full);
3169 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3170 XGBE_SET_SUP(lks, 10000baseR_FEC);
3171 phy_data->start_mode = XGBE_MODE_SFI;
3173 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3177 case XGBE_PORT_MODE_SFP:
3178 XGBE_SET_SUP(lks, Autoneg);
3179 XGBE_SET_SUP(lks, Pause);
3180 XGBE_SET_SUP(lks, Asym_Pause);
3181 XGBE_SET_SUP(lks, TP);
3182 XGBE_SET_SUP(lks, FIBRE);
3183 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3184 phy_data->start_mode = XGBE_MODE_SGMII_100;
3185 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3186 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3187 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3188 phy_data->start_mode = XGBE_MODE_SFI;
3190 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3192 xgbe_phy_sfp_setup(pdata);
3198 if (netif_msg_probe(pdata))
3199 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3200 __ETHTOOL_LINK_MODE_MASK_NBITS,
3201 lks->link_modes.supported);
3203 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3204 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3205 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3206 phy_data->phydev_mode);
3209 "mdio port/clause not compatible (%d/%u)\n",
3210 phy_data->mdio_addr, phy_data->phydev_mode);
3215 if (phy_data->redrv && !phy_data->redrv_if) {
3216 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3217 XGBE_MDIO_MODE_CL22);
3220 "redriver mdio port not compatible (%u)\n",
3221 phy_data->redrv_addr);
3226 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3228 /* Register for driving external PHYs */
3229 mii = devm_mdiobus_alloc(pdata->dev);
3231 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3236 mii->name = "amd-xgbe-mii";
3237 mii->read = xgbe_phy_mii_read;
3238 mii->write = xgbe_phy_mii_write;
3239 mii->parent = pdata->dev;
3241 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3242 ret = mdiobus_register(mii);
3244 dev_err(pdata->dev, "mdiobus_register failed\n");
3247 phy_data->mii = mii;
3252 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3254 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3256 phy_impl->init = xgbe_phy_init;
3257 phy_impl->exit = xgbe_phy_exit;
3259 phy_impl->reset = xgbe_phy_reset;
3260 phy_impl->start = xgbe_phy_start;
3261 phy_impl->stop = xgbe_phy_stop;
3263 phy_impl->link_status = xgbe_phy_link_status;
3265 phy_impl->valid_speed = xgbe_phy_valid_speed;
3267 phy_impl->use_mode = xgbe_phy_use_mode;
3268 phy_impl->set_mode = xgbe_phy_set_mode;
3269 phy_impl->get_mode = xgbe_phy_get_mode;
3270 phy_impl->switch_mode = xgbe_phy_switch_mode;
3271 phy_impl->cur_mode = xgbe_phy_cur_mode;
3273 phy_impl->an_mode = xgbe_phy_an_mode;
3275 phy_impl->an_config = xgbe_phy_an_config;
3277 phy_impl->an_advertising = xgbe_phy_an_advertising;
3279 phy_impl->an_outcome = xgbe_phy_an_outcome;
3281 phy_impl->an_pre = xgbe_phy_an_pre;
3282 phy_impl->an_post = xgbe_phy_an_post;
3284 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3285 phy_impl->kr_training_post = xgbe_phy_kr_training_post;