2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/module.h>
118 #include <linux/device.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/ethtool.h>
125 #include "xgbe-common.h"
127 #define XGBE_PHY_PORT_SPEED_100 BIT(0)
128 #define XGBE_PHY_PORT_SPEED_1000 BIT(1)
129 #define XGBE_PHY_PORT_SPEED_2500 BIT(2)
130 #define XGBE_PHY_PORT_SPEED_10000 BIT(3)
132 #define XGBE_MUTEX_RELEASE 0x80000000
134 #define XGBE_SFP_DIRECT 7
136 /* I2C target addresses */
137 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
138 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
139 #define XGBE_SFP_PHY_ADDRESS 0x56
140 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
142 /* SFP sideband signal indicators */
143 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
144 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
145 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
146 #define XGBE_GPIO_NO_RX_LOS BIT(3)
148 /* Rate-change complete wait/retry count */
149 #define XGBE_RATECHANGE_COUNT 500
151 /* CDR delay values for KR support (in usec) */
152 #define XGBE_CDR_DELAY_INIT 10000
153 #define XGBE_CDR_DELAY_INC 10000
154 #define XGBE_CDR_DELAY_MAX 100000
156 /* RRC frequency during link status check */
157 #define XGBE_RRC_FREQUENCY 10
159 enum xgbe_port_mode {
160 XGBE_PORT_MODE_RSVD = 0,
161 XGBE_PORT_MODE_BACKPLANE,
162 XGBE_PORT_MODE_BACKPLANE_2500,
163 XGBE_PORT_MODE_1000BASE_T,
164 XGBE_PORT_MODE_1000BASE_X,
165 XGBE_PORT_MODE_NBASE_T,
166 XGBE_PORT_MODE_10GBASE_T,
167 XGBE_PORT_MODE_10GBASE_R,
172 enum xgbe_conn_type {
173 XGBE_CONN_TYPE_NONE = 0,
176 XGBE_CONN_TYPE_RSVD1,
177 XGBE_CONN_TYPE_BACKPLANE,
181 /* SFP/SFP+ related definitions */
183 XGBE_SFP_COMM_DIRECT = 0,
184 XGBE_SFP_COMM_PCA9545,
187 enum xgbe_sfp_cable {
188 XGBE_SFP_CABLE_UNKNOWN = 0,
189 XGBE_SFP_CABLE_ACTIVE,
190 XGBE_SFP_CABLE_PASSIVE,
194 XGBE_SFP_BASE_UNKNOWN = 0,
195 XGBE_SFP_BASE_1000_T,
196 XGBE_SFP_BASE_1000_SX,
197 XGBE_SFP_BASE_1000_LX,
198 XGBE_SFP_BASE_1000_CX,
199 XGBE_SFP_BASE_10000_SR,
200 XGBE_SFP_BASE_10000_LR,
201 XGBE_SFP_BASE_10000_LRM,
202 XGBE_SFP_BASE_10000_ER,
203 XGBE_SFP_BASE_10000_CR,
206 enum xgbe_sfp_speed {
207 XGBE_SFP_SPEED_UNKNOWN = 0,
208 XGBE_SFP_SPEED_100_1000,
210 XGBE_SFP_SPEED_10000,
213 /* SFP Serial ID Base ID values relative to an offset of 0 */
214 #define XGBE_SFP_BASE_ID 0
215 #define XGBE_SFP_ID_SFP 0x03
217 #define XGBE_SFP_BASE_EXT_ID 1
218 #define XGBE_SFP_EXT_ID_SFP 0x04
220 #define XGBE_SFP_BASE_10GBE_CC 3
221 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
222 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
223 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
224 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
226 #define XGBE_SFP_BASE_1GBE_CC 6
227 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
228 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
229 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
230 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
232 #define XGBE_SFP_BASE_CABLE 8
233 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
234 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
236 #define XGBE_SFP_BASE_BR 12
237 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
238 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
239 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
240 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
241 #define XGBE_MOLEX_SFP_BASE_BR_10GBE_MAX 0x78
243 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
245 #define XGBE_SFP_BASE_VENDOR_NAME 20
246 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
247 #define XGBE_SFP_BASE_VENDOR_PN 40
248 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
249 #define XGBE_SFP_BASE_VENDOR_REV 56
250 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
252 #define XGBE_SFP_BASE_CC 63
254 /* SFP Serial ID Extended ID values relative to an offset of 64 */
255 #define XGBE_SFP_BASE_VENDOR_SN 4
256 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
258 #define XGBE_SFP_EXTD_OPT1 1
259 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
260 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
262 #define XGBE_SFP_EXTD_DIAG 28
263 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
265 #define XGBE_SFP_EXTD_SFF_8472 30
267 #define XGBE_SFP_EXTD_CC 31
269 struct xgbe_sfp_eeprom {
275 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
279 #define XGBE_SFP_EEPROM_BASE_LEN 256
280 #define XGBE_SFP_EEPROM_DIAG_LEN 256
281 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
282 XGBE_SFP_EEPROM_DIAG_LEN)
284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
287 #define XGBE_MOLEX_VENDOR "Molex Inc. "
289 struct xgbe_sfp_ascii {
291 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
292 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
293 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
294 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
298 /* MDIO PHY reset types */
299 enum xgbe_mdio_reset {
300 XGBE_MDIO_RESET_NONE = 0,
301 XGBE_MDIO_RESET_I2C_GPIO,
302 XGBE_MDIO_RESET_INT_GPIO,
306 /* Re-driver related definitions */
307 enum xgbe_phy_redrv_if {
308 XGBE_PHY_REDRV_IF_MDIO = 0,
309 XGBE_PHY_REDRV_IF_I2C,
310 XGBE_PHY_REDRV_IF_MAX,
313 enum xgbe_phy_redrv_model {
314 XGBE_PHY_REDRV_MODEL_4223 = 0,
315 XGBE_PHY_REDRV_MODEL_4227,
316 XGBE_PHY_REDRV_MODEL_MAX,
319 enum xgbe_phy_redrv_mode {
320 XGBE_PHY_REDRV_MODE_CX = 5,
321 XGBE_PHY_REDRV_MODE_SR = 9,
324 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
326 /* PHY related configuration information */
327 struct xgbe_phy_data {
328 enum xgbe_port_mode port_mode;
330 unsigned int port_id;
332 unsigned int port_speeds;
334 enum xgbe_conn_type conn_type;
336 enum xgbe_mode cur_mode;
337 enum xgbe_mode start_mode;
339 unsigned int rrc_count;
341 unsigned int mdio_addr;
344 enum xgbe_sfp_comm sfp_comm;
345 unsigned int sfp_mux_address;
346 unsigned int sfp_mux_channel;
348 unsigned int sfp_gpio_address;
349 unsigned int sfp_gpio_mask;
350 unsigned int sfp_gpio_inputs;
351 unsigned int sfp_gpio_rx_los;
352 unsigned int sfp_gpio_tx_fault;
353 unsigned int sfp_gpio_mod_absent;
354 unsigned int sfp_gpio_rate_select;
356 unsigned int sfp_rx_los;
357 unsigned int sfp_tx_fault;
358 unsigned int sfp_mod_absent;
359 unsigned int sfp_changed;
360 unsigned int sfp_phy_avail;
361 unsigned int sfp_cable_len;
362 enum xgbe_sfp_base sfp_base;
363 enum xgbe_sfp_cable sfp_cable;
364 enum xgbe_sfp_speed sfp_speed;
365 struct xgbe_sfp_eeprom sfp_eeprom;
367 /* External PHY support */
368 enum xgbe_mdio_mode phydev_mode;
370 struct phy_device *phydev;
371 enum xgbe_mdio_reset mdio_reset;
372 unsigned int mdio_reset_addr;
373 unsigned int mdio_reset_gpio;
375 /* Re-driver support */
377 unsigned int redrv_if;
378 unsigned int redrv_addr;
379 unsigned int redrv_lane;
380 unsigned int redrv_model;
383 unsigned int phy_cdr_notrack;
384 unsigned int phy_cdr_delay;
387 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
388 static DEFINE_MUTEX(xgbe_phy_comm_lock);
390 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
392 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
393 struct xgbe_i2c_op *i2c_op)
395 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
398 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
401 struct xgbe_phy_data *phy_data = pdata->phy_data;
402 struct xgbe_i2c_op i2c_op;
404 u8 redrv_data[5], csum;
405 unsigned int i, retry;
408 /* High byte of register contains read/write indicator */
409 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
410 redrv_data[1] = reg & 0xff;
411 redrv_val = (__be16 *)&redrv_data[2];
412 *redrv_val = cpu_to_be16(val);
414 /* Calculate 1 byte checksum */
416 for (i = 0; i < 4; i++) {
417 csum += redrv_data[i];
418 if (redrv_data[i] > csum)
421 redrv_data[4] = ~csum;
425 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
426 i2c_op.target = phy_data->redrv_addr;
427 i2c_op.len = sizeof(redrv_data);
428 i2c_op.buf = redrv_data;
429 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
431 if ((ret == -EAGAIN) && retry--)
439 i2c_op.cmd = XGBE_I2C_CMD_READ;
440 i2c_op.target = phy_data->redrv_addr;
442 i2c_op.buf = redrv_data;
443 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
445 if ((ret == -EAGAIN) && retry--)
451 if (redrv_data[0] != 0xff) {
452 netif_dbg(pdata, drv, pdata->netdev,
453 "Redriver write checksum error\n");
460 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
461 void *val, unsigned int val_len)
463 struct xgbe_i2c_op i2c_op;
468 /* Write the specfied register */
469 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
470 i2c_op.target = target;
471 i2c_op.len = val_len;
473 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
474 if ((ret == -EAGAIN) && retry--)
480 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
481 void *reg, unsigned int reg_len,
482 void *val, unsigned int val_len)
484 struct xgbe_i2c_op i2c_op;
489 /* Set the specified register to read */
490 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
491 i2c_op.target = target;
492 i2c_op.len = reg_len;
494 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
496 if ((ret == -EAGAIN) && retry--)
504 /* Read the specfied register */
505 i2c_op.cmd = XGBE_I2C_CMD_READ;
506 i2c_op.target = target;
507 i2c_op.len = val_len;
509 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
510 if ((ret == -EAGAIN) && retry--)
516 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
518 struct xgbe_phy_data *phy_data = pdata->phy_data;
519 struct xgbe_i2c_op i2c_op;
522 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
525 /* Select no mux channels */
527 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
528 i2c_op.target = phy_data->sfp_mux_address;
529 i2c_op.len = sizeof(mux_channel);
530 i2c_op.buf = &mux_channel;
532 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
535 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
537 struct xgbe_phy_data *phy_data = pdata->phy_data;
538 struct xgbe_i2c_op i2c_op;
541 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
544 /* Select desired mux channel */
545 mux_channel = 1 << phy_data->sfp_mux_channel;
546 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
547 i2c_op.target = phy_data->sfp_mux_address;
548 i2c_op.len = sizeof(mux_channel);
549 i2c_op.buf = &mux_channel;
551 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
554 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
556 mutex_unlock(&xgbe_phy_comm_lock);
559 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
561 struct xgbe_phy_data *phy_data = pdata->phy_data;
562 unsigned long timeout;
563 unsigned int mutex_id;
565 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
566 * the driver needs to take the software mutex and then the hardware
567 * mutexes before being able to use the busses.
569 mutex_lock(&xgbe_phy_comm_lock);
571 /* Clear the mutexes */
572 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
573 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
575 /* Mutex formats are the same for I2C and MDIO/GPIO */
577 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
578 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
580 timeout = jiffies + (5 * HZ);
581 while (time_before(jiffies, timeout)) {
582 /* Must be all zeroes in order to obtain the mutex */
583 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
584 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
585 usleep_range(100, 200);
589 /* Obtain the mutex */
590 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
591 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
596 mutex_unlock(&xgbe_phy_comm_lock);
598 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
603 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
606 struct xgbe_phy_data *phy_data = pdata->phy_data;
608 if (reg & MII_ADDR_C45) {
609 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
612 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
616 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
619 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
625 ret = xgbe_phy_sfp_get_mux(pdata);
629 mii_data[0] = reg & 0xff;
630 mii_val = (__be16 *)&mii_data[1];
631 *mii_val = cpu_to_be16(val);
633 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
634 mii_data, sizeof(mii_data));
636 xgbe_phy_sfp_put_mux(pdata);
641 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
643 struct xgbe_prv_data *pdata = mii->priv;
644 struct xgbe_phy_data *phy_data = pdata->phy_data;
647 ret = xgbe_phy_get_comm_ownership(pdata);
651 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
652 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
653 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
654 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
658 xgbe_phy_put_comm_ownership(pdata);
663 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
666 struct xgbe_phy_data *phy_data = pdata->phy_data;
668 if (reg & MII_ADDR_C45) {
669 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
672 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
676 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
679 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
685 ret = xgbe_phy_sfp_get_mux(pdata);
690 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
691 &mii_reg, sizeof(mii_reg),
692 &mii_val, sizeof(mii_val));
694 ret = be16_to_cpu(mii_val);
696 xgbe_phy_sfp_put_mux(pdata);
701 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
703 struct xgbe_prv_data *pdata = mii->priv;
704 struct xgbe_phy_data *phy_data = pdata->phy_data;
707 ret = xgbe_phy_get_comm_ownership(pdata);
711 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
712 ret = xgbe_phy_i2c_mii_read(pdata, reg);
713 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
714 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
718 xgbe_phy_put_comm_ownership(pdata);
723 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
725 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
726 struct xgbe_phy_data *phy_data = pdata->phy_data;
728 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
733 if (phy_data->sfp_mod_absent) {
734 pdata->phy.speed = SPEED_UNKNOWN;
735 pdata->phy.duplex = DUPLEX_UNKNOWN;
736 pdata->phy.autoneg = AUTONEG_ENABLE;
737 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
739 XGBE_SET_SUP(lks, Autoneg);
740 XGBE_SET_SUP(lks, Pause);
741 XGBE_SET_SUP(lks, Asym_Pause);
742 XGBE_SET_SUP(lks, TP);
743 XGBE_SET_SUP(lks, FIBRE);
745 XGBE_LM_COPY(lks, advertising, lks, supported);
750 switch (phy_data->sfp_base) {
751 case XGBE_SFP_BASE_1000_T:
752 case XGBE_SFP_BASE_1000_SX:
753 case XGBE_SFP_BASE_1000_LX:
754 case XGBE_SFP_BASE_1000_CX:
755 pdata->phy.speed = SPEED_UNKNOWN;
756 pdata->phy.duplex = DUPLEX_UNKNOWN;
757 pdata->phy.autoneg = AUTONEG_ENABLE;
758 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
759 XGBE_SET_SUP(lks, Autoneg);
760 XGBE_SET_SUP(lks, Pause);
761 XGBE_SET_SUP(lks, Asym_Pause);
762 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
763 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
764 XGBE_SET_SUP(lks, 100baseT_Full);
765 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
766 XGBE_SET_SUP(lks, 1000baseT_Full);
768 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
769 XGBE_SET_SUP(lks, 1000baseX_Full);
772 case XGBE_SFP_BASE_10000_SR:
773 case XGBE_SFP_BASE_10000_LR:
774 case XGBE_SFP_BASE_10000_LRM:
775 case XGBE_SFP_BASE_10000_ER:
776 case XGBE_SFP_BASE_10000_CR:
777 pdata->phy.speed = SPEED_10000;
778 pdata->phy.duplex = DUPLEX_FULL;
779 pdata->phy.autoneg = AUTONEG_DISABLE;
780 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
781 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
782 switch (phy_data->sfp_base) {
783 case XGBE_SFP_BASE_10000_SR:
784 XGBE_SET_SUP(lks, 10000baseSR_Full);
786 case XGBE_SFP_BASE_10000_LR:
787 XGBE_SET_SUP(lks, 10000baseLR_Full);
789 case XGBE_SFP_BASE_10000_LRM:
790 XGBE_SET_SUP(lks, 10000baseLRM_Full);
792 case XGBE_SFP_BASE_10000_ER:
793 XGBE_SET_SUP(lks, 10000baseER_Full);
795 case XGBE_SFP_BASE_10000_CR:
796 XGBE_SET_SUP(lks, 10000baseCR_Full);
804 pdata->phy.speed = SPEED_UNKNOWN;
805 pdata->phy.duplex = DUPLEX_UNKNOWN;
806 pdata->phy.autoneg = AUTONEG_DISABLE;
807 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
811 switch (phy_data->sfp_base) {
812 case XGBE_SFP_BASE_1000_T:
813 case XGBE_SFP_BASE_1000_CX:
814 case XGBE_SFP_BASE_10000_CR:
815 XGBE_SET_SUP(lks, TP);
818 XGBE_SET_SUP(lks, FIBRE);
822 XGBE_LM_COPY(lks, advertising, lks, supported);
825 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
826 enum xgbe_sfp_speed sfp_speed)
828 u8 *sfp_base, min, max;
830 sfp_base = sfp_eeprom->base;
833 case XGBE_SFP_SPEED_1000:
834 min = XGBE_SFP_BASE_BR_1GBE_MIN;
835 max = XGBE_SFP_BASE_BR_1GBE_MAX;
837 case XGBE_SFP_SPEED_10000:
838 min = XGBE_SFP_BASE_BR_10GBE_MIN;
839 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
840 XGBE_MOLEX_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN) == 0)
841 max = XGBE_MOLEX_SFP_BASE_BR_10GBE_MAX;
843 max = XGBE_SFP_BASE_BR_10GBE_MAX;
849 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
850 (sfp_base[XGBE_SFP_BASE_BR] <= max));
853 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
855 struct xgbe_phy_data *phy_data = pdata->phy_data;
857 if (phy_data->phydev) {
858 phy_detach(phy_data->phydev);
859 phy_device_remove(phy_data->phydev);
860 phy_device_free(phy_data->phydev);
861 phy_data->phydev = NULL;
865 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
867 struct xgbe_phy_data *phy_data = pdata->phy_data;
868 unsigned int phy_id = phy_data->phydev->phy_id;
870 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
873 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
876 /* Enable Base-T AN */
877 phy_write(phy_data->phydev, 0x16, 0x0001);
878 phy_write(phy_data->phydev, 0x00, 0x9140);
879 phy_write(phy_data->phydev, 0x16, 0x0000);
881 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
882 phy_write(phy_data->phydev, 0x1b, 0x9084);
883 phy_write(phy_data->phydev, 0x09, 0x0e00);
884 phy_write(phy_data->phydev, 0x00, 0x8140);
885 phy_write(phy_data->phydev, 0x04, 0x0d01);
886 phy_write(phy_data->phydev, 0x00, 0x9140);
888 phy_data->phydev->supported = PHY_GBIT_FEATURES;
889 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
890 phy_data->phydev->advertising = phy_data->phydev->supported;
892 netif_dbg(pdata, drv, pdata->netdev,
893 "Finisar PHY quirk in place\n");
898 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
900 struct xgbe_phy_data *phy_data = pdata->phy_data;
901 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
902 unsigned int phy_id = phy_data->phydev->phy_id;
905 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
908 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
909 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
912 /* For Bel-Fuse, use the extra AN flag */
915 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
916 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
919 if ((phy_id & 0xfffffff0) != 0x03625d10)
922 /* Reset PHY - wait for self-clearing reset bit to clear */
923 genphy_soft_reset(phy_data->phydev);
925 /* Disable RGMII mode */
926 phy_write(phy_data->phydev, 0x18, 0x7007);
927 reg = phy_read(phy_data->phydev, 0x18);
928 phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
930 /* Enable fiber register bank */
931 phy_write(phy_data->phydev, 0x1c, 0x7c00);
932 reg = phy_read(phy_data->phydev, 0x1c);
935 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
937 /* Power down SerDes */
938 reg = phy_read(phy_data->phydev, 0x00);
939 phy_write(phy_data->phydev, 0x00, reg | 0x00800);
941 /* Configure SGMII-to-Copper mode */
942 phy_write(phy_data->phydev, 0x1c, 0x7c00);
943 reg = phy_read(phy_data->phydev, 0x1c);
946 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
948 /* Power up SerDes */
949 reg = phy_read(phy_data->phydev, 0x00);
950 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
952 /* Enable copper register bank */
953 phy_write(phy_data->phydev, 0x1c, 0x7c00);
954 reg = phy_read(phy_data->phydev, 0x1c);
957 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
959 /* Power up SerDes */
960 reg = phy_read(phy_data->phydev, 0x00);
961 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
963 phy_data->phydev->supported = PHY_GBIT_FEATURES;
964 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
965 phy_data->phydev->advertising = phy_data->phydev->supported;
967 netif_dbg(pdata, drv, pdata->netdev,
968 "BelFuse PHY quirk in place\n");
973 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
975 if (xgbe_phy_belfuse_phy_quirks(pdata))
978 if (xgbe_phy_finisar_phy_quirks(pdata))
982 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
984 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
985 struct xgbe_phy_data *phy_data = pdata->phy_data;
986 struct phy_device *phydev;
990 /* If we already have a PHY, just return */
991 if (phy_data->phydev)
994 /* Clear the extra AN flag */
997 /* Check for the use of an external PHY */
998 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
1001 /* For SFP, only use an external PHY if available */
1002 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1003 !phy_data->sfp_phy_avail)
1006 /* Set the proper MDIO mode for the PHY */
1007 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1008 phy_data->phydev_mode);
1010 netdev_err(pdata->netdev,
1011 "mdio port/clause not compatible (%u/%u)\n",
1012 phy_data->mdio_addr, phy_data->phydev_mode);
1016 /* Create and connect to the PHY device */
1017 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
1018 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
1019 if (IS_ERR(phydev)) {
1020 netdev_err(pdata->netdev, "get_phy_device failed\n");
1023 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
1026 /*TODO: If c45, add request_module based on one of the MMD ids? */
1028 ret = phy_device_register(phydev);
1030 netdev_err(pdata->netdev, "phy_device_register failed\n");
1031 phy_device_free(phydev);
1035 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
1036 PHY_INTERFACE_MODE_SGMII);
1038 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
1039 phy_device_remove(phydev);
1040 phy_device_free(phydev);
1043 phy_data->phydev = phydev;
1045 xgbe_phy_external_phy_quirks(pdata);
1047 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1048 lks->link_modes.advertising);
1049 phydev->advertising &= advertising;
1051 phy_start_aneg(phy_data->phydev);
1056 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1058 struct xgbe_phy_data *phy_data = pdata->phy_data;
1061 if (!phy_data->sfp_changed)
1064 phy_data->sfp_phy_avail = 0;
1066 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1069 /* Check access to the PHY by reading CTRL1 */
1070 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1074 /* Successfully accessed the PHY */
1075 phy_data->sfp_phy_avail = 1;
1078 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1080 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1082 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1085 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1088 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1094 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1096 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1098 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1101 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1104 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1110 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1112 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1115 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1121 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1123 struct xgbe_phy_data *phy_data = pdata->phy_data;
1124 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1127 sfp_base = sfp_eeprom->base;
1129 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1132 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1135 /* Update transceiver signals (eeprom extd/options) */
1136 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1137 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1139 /* Assume ACTIVE cable unless told it is PASSIVE */
1140 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1141 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1142 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1144 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1147 /* Determine the type of SFP */
1148 if (phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE &&
1149 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1150 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1151 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1152 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1153 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1154 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1155 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1156 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1157 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1158 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1159 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1160 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1161 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1162 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1163 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1164 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1165 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1166 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1168 switch (phy_data->sfp_base) {
1169 case XGBE_SFP_BASE_1000_T:
1170 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1172 case XGBE_SFP_BASE_1000_SX:
1173 case XGBE_SFP_BASE_1000_LX:
1174 case XGBE_SFP_BASE_1000_CX:
1175 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1177 case XGBE_SFP_BASE_10000_SR:
1178 case XGBE_SFP_BASE_10000_LR:
1179 case XGBE_SFP_BASE_10000_LRM:
1180 case XGBE_SFP_BASE_10000_ER:
1181 case XGBE_SFP_BASE_10000_CR:
1182 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1189 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1190 struct xgbe_sfp_eeprom *sfp_eeprom)
1192 struct xgbe_sfp_ascii sfp_ascii;
1193 char *sfp_data = (char *)&sfp_ascii;
1195 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1196 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1197 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1198 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1199 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1202 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1203 XGBE_SFP_BASE_VENDOR_PN_LEN);
1204 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1205 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1208 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1209 XGBE_SFP_BASE_VENDOR_REV_LEN);
1210 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1211 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1214 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1215 XGBE_SFP_BASE_VENDOR_SN_LEN);
1216 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1217 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1221 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1225 for (cc = 0; len; buf++, len--)
1228 return (cc == cc_in) ? true : false;
1231 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1233 struct xgbe_phy_data *phy_data = pdata->phy_data;
1234 struct xgbe_sfp_eeprom sfp_eeprom;
1238 ret = xgbe_phy_sfp_get_mux(pdata);
1240 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1241 netdev_name(pdata->netdev));
1245 /* Read the SFP serial ID eeprom */
1247 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1248 &eeprom_addr, sizeof(eeprom_addr),
1249 &sfp_eeprom, sizeof(sfp_eeprom));
1251 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1252 netdev_name(pdata->netdev));
1256 /* Validate the contents read */
1257 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1259 sizeof(sfp_eeprom.base) - 1)) {
1264 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1266 sizeof(sfp_eeprom.extd) - 1)) {
1271 /* Check for an added or changed SFP */
1272 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1273 phy_data->sfp_changed = 1;
1275 if (netif_msg_drv(pdata))
1276 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1278 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1280 xgbe_phy_free_phy_device(pdata);
1282 phy_data->sfp_changed = 0;
1286 xgbe_phy_sfp_put_mux(pdata);
1291 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1293 struct xgbe_phy_data *phy_data = pdata->phy_data;
1294 u8 gpio_reg, gpio_ports[2];
1297 /* Read the input port registers */
1299 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1300 &gpio_reg, sizeof(gpio_reg),
1301 gpio_ports, sizeof(gpio_ports));
1303 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1304 netdev_name(pdata->netdev));
1308 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1310 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1313 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1315 struct xgbe_phy_data *phy_data = pdata->phy_data;
1317 xgbe_phy_free_phy_device(pdata);
1319 phy_data->sfp_mod_absent = 1;
1320 phy_data->sfp_phy_avail = 0;
1321 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1324 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1326 phy_data->sfp_rx_los = 0;
1327 phy_data->sfp_tx_fault = 0;
1328 phy_data->sfp_mod_absent = 1;
1329 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1330 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1331 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1334 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1336 struct xgbe_phy_data *phy_data = pdata->phy_data;
1339 /* Reset the SFP signals and info */
1340 xgbe_phy_sfp_reset(phy_data);
1342 ret = xgbe_phy_get_comm_ownership(pdata);
1346 /* Read the SFP signals and check for module presence */
1347 xgbe_phy_sfp_signals(pdata);
1348 if (phy_data->sfp_mod_absent) {
1349 xgbe_phy_sfp_mod_absent(pdata);
1353 ret = xgbe_phy_sfp_read_eeprom(pdata);
1355 /* Treat any error as if there isn't an SFP plugged in */
1356 xgbe_phy_sfp_reset(phy_data);
1357 xgbe_phy_sfp_mod_absent(pdata);
1361 xgbe_phy_sfp_parse_eeprom(pdata);
1363 xgbe_phy_sfp_external_phy(pdata);
1366 xgbe_phy_sfp_phy_settings(pdata);
1368 xgbe_phy_put_comm_ownership(pdata);
1371 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1372 struct ethtool_eeprom *eeprom, u8 *data)
1374 struct xgbe_phy_data *phy_data = pdata->phy_data;
1375 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1376 struct xgbe_sfp_eeprom *sfp_eeprom;
1377 unsigned int i, j, rem;
1387 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1392 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1397 if (!netif_running(pdata->netdev)) {
1402 if (phy_data->sfp_mod_absent) {
1407 ret = xgbe_phy_get_comm_ownership(pdata);
1413 ret = xgbe_phy_sfp_get_mux(pdata);
1415 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1420 /* Read the SFP serial ID eeprom */
1422 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1423 &eeprom_addr, sizeof(eeprom_addr),
1424 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1426 netdev_err(pdata->netdev,
1427 "I2C error reading SFP EEPROM\n");
1432 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1434 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1435 /* Read the SFP diagnostic eeprom */
1437 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1438 &eeprom_addr, sizeof(eeprom_addr),
1439 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1440 XGBE_SFP_EEPROM_DIAG_LEN);
1442 netdev_err(pdata->netdev,
1443 "I2C error reading SFP DIAGS\n");
1449 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1450 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1451 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1454 data[i] = eeprom_data[j];
1459 xgbe_phy_sfp_put_mux(pdata);
1462 xgbe_phy_put_comm_ownership(pdata);
1470 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1471 struct ethtool_modinfo *modinfo)
1473 struct xgbe_phy_data *phy_data = pdata->phy_data;
1475 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1478 if (!netif_running(pdata->netdev))
1481 if (phy_data->sfp_mod_absent)
1484 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1485 modinfo->type = ETH_MODULE_SFF_8472;
1486 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1488 modinfo->type = ETH_MODULE_SFF_8079;
1489 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1495 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1497 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1498 struct xgbe_phy_data *phy_data = pdata->phy_data;
1499 u16 lcl_adv = 0, rmt_adv = 0;
1502 pdata->phy.tx_pause = 0;
1503 pdata->phy.rx_pause = 0;
1505 if (!phy_data->phydev)
1508 if (phy_data->phydev->advertising & ADVERTISED_Pause)
1509 lcl_adv |= ADVERTISE_PAUSE_CAP;
1510 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause)
1511 lcl_adv |= ADVERTISE_PAUSE_ASYM;
1513 if (phy_data->phydev->pause) {
1514 XGBE_SET_LP_ADV(lks, Pause);
1515 rmt_adv |= LPA_PAUSE_CAP;
1517 if (phy_data->phydev->asym_pause) {
1518 XGBE_SET_LP_ADV(lks, Asym_Pause);
1519 rmt_adv |= LPA_PAUSE_ASYM;
1522 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1523 if (fc & FLOW_CTRL_TX)
1524 pdata->phy.tx_pause = 1;
1525 if (fc & FLOW_CTRL_RX)
1526 pdata->phy.rx_pause = 1;
1529 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1531 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1532 enum xgbe_mode mode;
1534 XGBE_SET_LP_ADV(lks, Autoneg);
1535 XGBE_SET_LP_ADV(lks, TP);
1537 /* Use external PHY to determine flow control */
1538 if (pdata->phy.pause_autoneg)
1539 xgbe_phy_phydev_flowctrl(pdata);
1541 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1542 case XGBE_SGMII_AN_LINK_SPEED_100:
1543 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1544 XGBE_SET_LP_ADV(lks, 100baseT_Full);
1545 mode = XGBE_MODE_SGMII_100;
1547 /* Half-duplex not supported */
1548 XGBE_SET_LP_ADV(lks, 100baseT_Half);
1549 mode = XGBE_MODE_UNKNOWN;
1552 case XGBE_SGMII_AN_LINK_SPEED_1000:
1553 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1554 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1555 mode = XGBE_MODE_SGMII_1000;
1557 /* Half-duplex not supported */
1558 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1559 mode = XGBE_MODE_UNKNOWN;
1563 mode = XGBE_MODE_UNKNOWN;
1569 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1571 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1572 enum xgbe_mode mode;
1573 unsigned int ad_reg, lp_reg;
1575 XGBE_SET_LP_ADV(lks, Autoneg);
1576 XGBE_SET_LP_ADV(lks, FIBRE);
1578 /* Compare Advertisement and Link Partner register */
1579 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1580 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1582 XGBE_SET_LP_ADV(lks, Pause);
1584 XGBE_SET_LP_ADV(lks, Asym_Pause);
1586 if (pdata->phy.pause_autoneg) {
1587 /* Set flow control based on auto-negotiation result */
1588 pdata->phy.tx_pause = 0;
1589 pdata->phy.rx_pause = 0;
1591 if (ad_reg & lp_reg & 0x100) {
1592 pdata->phy.tx_pause = 1;
1593 pdata->phy.rx_pause = 1;
1594 } else if (ad_reg & lp_reg & 0x80) {
1596 pdata->phy.rx_pause = 1;
1597 else if (lp_reg & 0x100)
1598 pdata->phy.tx_pause = 1;
1603 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1605 /* Half duplex is not supported */
1607 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1612 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1614 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1615 struct xgbe_phy_data *phy_data = pdata->phy_data;
1616 enum xgbe_mode mode;
1617 unsigned int ad_reg, lp_reg;
1619 XGBE_SET_LP_ADV(lks, Autoneg);
1620 XGBE_SET_LP_ADV(lks, Backplane);
1622 /* Use external PHY to determine flow control */
1623 if (pdata->phy.pause_autoneg)
1624 xgbe_phy_phydev_flowctrl(pdata);
1626 /* Compare Advertisement and Link Partner register 2 */
1627 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1628 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1630 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1632 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1635 if (ad_reg & 0x80) {
1636 switch (phy_data->port_mode) {
1637 case XGBE_PORT_MODE_BACKPLANE:
1638 mode = XGBE_MODE_KR;
1641 mode = XGBE_MODE_SFI;
1644 } else if (ad_reg & 0x20) {
1645 switch (phy_data->port_mode) {
1646 case XGBE_PORT_MODE_BACKPLANE:
1647 mode = XGBE_MODE_KX_1000;
1649 case XGBE_PORT_MODE_1000BASE_X:
1652 case XGBE_PORT_MODE_SFP:
1653 switch (phy_data->sfp_base) {
1654 case XGBE_SFP_BASE_1000_T:
1655 if (phy_data->phydev &&
1656 (phy_data->phydev->speed == SPEED_100))
1657 mode = XGBE_MODE_SGMII_100;
1659 mode = XGBE_MODE_SGMII_1000;
1661 case XGBE_SFP_BASE_1000_SX:
1662 case XGBE_SFP_BASE_1000_LX:
1663 case XGBE_SFP_BASE_1000_CX:
1670 if (phy_data->phydev &&
1671 (phy_data->phydev->speed == SPEED_100))
1672 mode = XGBE_MODE_SGMII_100;
1674 mode = XGBE_MODE_SGMII_1000;
1678 mode = XGBE_MODE_UNKNOWN;
1681 /* Compare Advertisement and Link Partner register 3 */
1682 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1683 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1684 if (lp_reg & 0xc000)
1685 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1690 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1692 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1693 enum xgbe_mode mode;
1694 unsigned int ad_reg, lp_reg;
1696 XGBE_SET_LP_ADV(lks, Autoneg);
1697 XGBE_SET_LP_ADV(lks, Backplane);
1699 /* Compare Advertisement and Link Partner register 1 */
1700 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1701 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1703 XGBE_SET_LP_ADV(lks, Pause);
1705 XGBE_SET_LP_ADV(lks, Asym_Pause);
1707 if (pdata->phy.pause_autoneg) {
1708 /* Set flow control based on auto-negotiation result */
1709 pdata->phy.tx_pause = 0;
1710 pdata->phy.rx_pause = 0;
1712 if (ad_reg & lp_reg & 0x400) {
1713 pdata->phy.tx_pause = 1;
1714 pdata->phy.rx_pause = 1;
1715 } else if (ad_reg & lp_reg & 0x800) {
1717 pdata->phy.rx_pause = 1;
1718 else if (lp_reg & 0x400)
1719 pdata->phy.tx_pause = 1;
1723 /* Compare Advertisement and Link Partner register 2 */
1724 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1725 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1727 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1729 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1733 mode = XGBE_MODE_KR;
1734 else if (ad_reg & 0x20)
1735 mode = XGBE_MODE_KX_1000;
1737 mode = XGBE_MODE_UNKNOWN;
1739 /* Compare Advertisement and Link Partner register 3 */
1740 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1741 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1742 if (lp_reg & 0xc000)
1743 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1748 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1750 switch (pdata->an_mode) {
1751 case XGBE_AN_MODE_CL73:
1752 return xgbe_phy_an73_outcome(pdata);
1753 case XGBE_AN_MODE_CL73_REDRV:
1754 return xgbe_phy_an73_redrv_outcome(pdata);
1755 case XGBE_AN_MODE_CL37:
1756 return xgbe_phy_an37_outcome(pdata);
1757 case XGBE_AN_MODE_CL37_SGMII:
1758 return xgbe_phy_an37_sgmii_outcome(pdata);
1760 return XGBE_MODE_UNKNOWN;
1764 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1765 struct ethtool_link_ksettings *dlks)
1767 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1768 struct xgbe_phy_data *phy_data = pdata->phy_data;
1770 XGBE_LM_COPY(dlks, advertising, slks, advertising);
1772 /* Without a re-driver, just return current advertising */
1773 if (!phy_data->redrv)
1776 /* With the KR re-driver we need to advertise a single speed */
1777 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1778 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1780 /* Advertise FEC support is present */
1781 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1782 XGBE_SET_ADV(dlks, 10000baseR_FEC);
1784 switch (phy_data->port_mode) {
1785 case XGBE_PORT_MODE_BACKPLANE:
1786 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1788 case XGBE_PORT_MODE_BACKPLANE_2500:
1789 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1791 case XGBE_PORT_MODE_1000BASE_T:
1792 case XGBE_PORT_MODE_1000BASE_X:
1793 case XGBE_PORT_MODE_NBASE_T:
1794 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1796 case XGBE_PORT_MODE_10GBASE_T:
1797 if (phy_data->phydev &&
1798 (phy_data->phydev->speed == SPEED_10000))
1799 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1801 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1803 case XGBE_PORT_MODE_10GBASE_R:
1804 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1806 case XGBE_PORT_MODE_SFP:
1807 switch (phy_data->sfp_base) {
1808 case XGBE_SFP_BASE_1000_T:
1809 case XGBE_SFP_BASE_1000_SX:
1810 case XGBE_SFP_BASE_1000_LX:
1811 case XGBE_SFP_BASE_1000_CX:
1812 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1815 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1820 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1825 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1827 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1828 struct xgbe_phy_data *phy_data = pdata->phy_data;
1832 ret = xgbe_phy_find_phy_device(pdata);
1836 if (!phy_data->phydev)
1839 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1840 lks->link_modes.advertising);
1842 phy_data->phydev->autoneg = pdata->phy.autoneg;
1843 phy_data->phydev->advertising = phy_data->phydev->supported &
1846 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1847 phy_data->phydev->speed = pdata->phy.speed;
1848 phy_data->phydev->duplex = pdata->phy.duplex;
1851 ret = phy_start_aneg(phy_data->phydev);
1856 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1858 switch (phy_data->sfp_base) {
1859 case XGBE_SFP_BASE_1000_T:
1860 return XGBE_AN_MODE_CL37_SGMII;
1861 case XGBE_SFP_BASE_1000_SX:
1862 case XGBE_SFP_BASE_1000_LX:
1863 case XGBE_SFP_BASE_1000_CX:
1864 return XGBE_AN_MODE_CL37;
1866 return XGBE_AN_MODE_NONE;
1870 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1872 struct xgbe_phy_data *phy_data = pdata->phy_data;
1874 /* A KR re-driver will always require CL73 AN */
1875 if (phy_data->redrv)
1876 return XGBE_AN_MODE_CL73_REDRV;
1878 switch (phy_data->port_mode) {
1879 case XGBE_PORT_MODE_BACKPLANE:
1880 return XGBE_AN_MODE_CL73;
1881 case XGBE_PORT_MODE_BACKPLANE_2500:
1882 return XGBE_AN_MODE_NONE;
1883 case XGBE_PORT_MODE_1000BASE_T:
1884 return XGBE_AN_MODE_CL37_SGMII;
1885 case XGBE_PORT_MODE_1000BASE_X:
1886 return XGBE_AN_MODE_CL37;
1887 case XGBE_PORT_MODE_NBASE_T:
1888 return XGBE_AN_MODE_CL37_SGMII;
1889 case XGBE_PORT_MODE_10GBASE_T:
1890 return XGBE_AN_MODE_CL73;
1891 case XGBE_PORT_MODE_10GBASE_R:
1892 return XGBE_AN_MODE_NONE;
1893 case XGBE_PORT_MODE_SFP:
1894 return xgbe_phy_an_sfp_mode(phy_data);
1896 return XGBE_AN_MODE_NONE;
1900 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1901 enum xgbe_phy_redrv_mode mode)
1903 struct xgbe_phy_data *phy_data = pdata->phy_data;
1904 u16 redrv_reg, redrv_val;
1906 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1907 redrv_val = (u16)mode;
1909 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1910 redrv_reg, redrv_val);
1913 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1914 enum xgbe_phy_redrv_mode mode)
1916 struct xgbe_phy_data *phy_data = pdata->phy_data;
1917 unsigned int redrv_reg;
1920 /* Calculate the register to write */
1921 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1923 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1928 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1930 struct xgbe_phy_data *phy_data = pdata->phy_data;
1931 enum xgbe_phy_redrv_mode mode;
1934 if (!phy_data->redrv)
1937 mode = XGBE_PHY_REDRV_MODE_CX;
1938 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1939 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1940 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1941 mode = XGBE_PHY_REDRV_MODE_SR;
1943 ret = xgbe_phy_get_comm_ownership(pdata);
1947 if (phy_data->redrv_if)
1948 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1950 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1952 xgbe_phy_put_comm_ownership(pdata);
1955 static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
1959 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
1960 XGBE_PCS_PSEQ_STATE_MASK);
1961 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
1962 /* Mailbox command timed out, reset of RX block is required.
1963 * This can be done by asseting the reset bit and wait for
1966 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1967 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
1969 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1970 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
1971 usleep_range(40, 50);
1972 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n");
1976 static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
1978 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
1979 XGBE_PMA_PLL_CTRL_MASK,
1980 enable ? XGBE_PMA_PLL_CTRL_ENABLE
1981 : XGBE_PMA_PLL_CTRL_DISABLE);
1983 /* Wait for command to complete */
1984 usleep_range(100, 200);
1987 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
1988 unsigned int cmd, unsigned int sub_cmd)
1990 unsigned int s0 = 0;
1993 /* Disable PLL re-initialization during FW command processing */
1994 xgbe_phy_pll_ctrl(pdata, false);
1996 /* Log if a previous command did not complete */
1997 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
1998 netif_dbg(pdata, link, pdata->netdev,
1999 "firmware mailbox not ready for command\n");
2000 xgbe_phy_rx_reset(pdata);
2003 /* Construct the command */
2004 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
2005 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
2007 /* Issue the command */
2008 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
2009 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2010 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2012 /* Wait for command to complete */
2013 wait = XGBE_RATECHANGE_COUNT;
2015 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
2018 usleep_range(1000, 2000);
2021 netif_dbg(pdata, link, pdata->netdev,
2022 "firmware mailbox command did not complete\n");
2024 /* Reset on error */
2025 xgbe_phy_rx_reset(pdata);
2028 /* Enable PLL re-initialization */
2029 xgbe_phy_pll_ctrl(pdata, true);
2032 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2034 /* Receiver Reset Cycle */
2035 xgbe_phy_perform_ratechange(pdata, 5, 0);
2037 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
2040 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2042 struct xgbe_phy_data *phy_data = pdata->phy_data;
2045 xgbe_phy_perform_ratechange(pdata, 0, 0);
2047 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2049 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
2052 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2054 struct xgbe_phy_data *phy_data = pdata->phy_data;
2056 xgbe_phy_set_redrv_mode(pdata);
2059 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
2060 xgbe_phy_perform_ratechange(pdata, 3, 0);
2062 if (phy_data->sfp_cable_len <= 1)
2063 xgbe_phy_perform_ratechange(pdata, 3, 1);
2064 else if (phy_data->sfp_cable_len <= 3)
2065 xgbe_phy_perform_ratechange(pdata, 3, 2);
2067 xgbe_phy_perform_ratechange(pdata, 3, 3);
2070 phy_data->cur_mode = XGBE_MODE_SFI;
2072 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2075 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2077 struct xgbe_phy_data *phy_data = pdata->phy_data;
2079 xgbe_phy_set_redrv_mode(pdata);
2082 xgbe_phy_perform_ratechange(pdata, 1, 3);
2084 phy_data->cur_mode = XGBE_MODE_X;
2086 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2089 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2091 struct xgbe_phy_data *phy_data = pdata->phy_data;
2093 xgbe_phy_set_redrv_mode(pdata);
2096 xgbe_phy_perform_ratechange(pdata, 1, 2);
2098 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2100 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2103 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2105 struct xgbe_phy_data *phy_data = pdata->phy_data;
2107 xgbe_phy_set_redrv_mode(pdata);
2110 xgbe_phy_perform_ratechange(pdata, 1, 1);
2112 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2114 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2117 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2119 struct xgbe_phy_data *phy_data = pdata->phy_data;
2121 xgbe_phy_set_redrv_mode(pdata);
2124 xgbe_phy_perform_ratechange(pdata, 4, 0);
2126 phy_data->cur_mode = XGBE_MODE_KR;
2128 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2131 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2133 struct xgbe_phy_data *phy_data = pdata->phy_data;
2135 xgbe_phy_set_redrv_mode(pdata);
2138 xgbe_phy_perform_ratechange(pdata, 2, 0);
2140 phy_data->cur_mode = XGBE_MODE_KX_2500;
2142 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2145 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2147 struct xgbe_phy_data *phy_data = pdata->phy_data;
2149 xgbe_phy_set_redrv_mode(pdata);
2152 xgbe_phy_perform_ratechange(pdata, 1, 3);
2154 phy_data->cur_mode = XGBE_MODE_KX_1000;
2156 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2159 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2161 struct xgbe_phy_data *phy_data = pdata->phy_data;
2163 return phy_data->cur_mode;
2166 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2168 struct xgbe_phy_data *phy_data = pdata->phy_data;
2170 /* No switching if not 10GBase-T */
2171 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2172 return xgbe_phy_cur_mode(pdata);
2174 switch (xgbe_phy_cur_mode(pdata)) {
2175 case XGBE_MODE_SGMII_100:
2176 case XGBE_MODE_SGMII_1000:
2177 return XGBE_MODE_KR;
2180 return XGBE_MODE_SGMII_1000;
2184 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2186 return XGBE_MODE_KX_2500;
2189 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2191 /* If we are in KR switch to KX, and vice-versa */
2192 switch (xgbe_phy_cur_mode(pdata)) {
2193 case XGBE_MODE_KX_1000:
2194 return XGBE_MODE_KR;
2197 return XGBE_MODE_KX_1000;
2201 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2203 struct xgbe_phy_data *phy_data = pdata->phy_data;
2205 switch (phy_data->port_mode) {
2206 case XGBE_PORT_MODE_BACKPLANE:
2207 return xgbe_phy_switch_bp_mode(pdata);
2208 case XGBE_PORT_MODE_BACKPLANE_2500:
2209 return xgbe_phy_switch_bp_2500_mode(pdata);
2210 case XGBE_PORT_MODE_1000BASE_T:
2211 case XGBE_PORT_MODE_NBASE_T:
2212 case XGBE_PORT_MODE_10GBASE_T:
2213 return xgbe_phy_switch_baset_mode(pdata);
2214 case XGBE_PORT_MODE_1000BASE_X:
2215 case XGBE_PORT_MODE_10GBASE_R:
2216 case XGBE_PORT_MODE_SFP:
2217 /* No switching, so just return current mode */
2218 return xgbe_phy_cur_mode(pdata);
2220 return XGBE_MODE_UNKNOWN;
2224 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2231 return XGBE_MODE_KR;
2233 return XGBE_MODE_UNKNOWN;
2237 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2242 return XGBE_MODE_SGMII_100;
2244 return XGBE_MODE_SGMII_1000;
2246 return XGBE_MODE_KX_2500;
2248 return XGBE_MODE_KR;
2250 return XGBE_MODE_UNKNOWN;
2254 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2259 return XGBE_MODE_SGMII_100;
2261 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2262 return XGBE_MODE_SGMII_1000;
2267 return XGBE_MODE_SFI;
2269 return XGBE_MODE_UNKNOWN;
2273 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2277 return XGBE_MODE_KX_2500;
2279 return XGBE_MODE_UNKNOWN;
2283 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2287 return XGBE_MODE_KX_1000;
2289 return XGBE_MODE_KR;
2291 return XGBE_MODE_UNKNOWN;
2295 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2298 struct xgbe_phy_data *phy_data = pdata->phy_data;
2300 switch (phy_data->port_mode) {
2301 case XGBE_PORT_MODE_BACKPLANE:
2302 return xgbe_phy_get_bp_mode(speed);
2303 case XGBE_PORT_MODE_BACKPLANE_2500:
2304 return xgbe_phy_get_bp_2500_mode(speed);
2305 case XGBE_PORT_MODE_1000BASE_T:
2306 case XGBE_PORT_MODE_NBASE_T:
2307 case XGBE_PORT_MODE_10GBASE_T:
2308 return xgbe_phy_get_baset_mode(phy_data, speed);
2309 case XGBE_PORT_MODE_1000BASE_X:
2310 case XGBE_PORT_MODE_10GBASE_R:
2311 return xgbe_phy_get_basex_mode(phy_data, speed);
2312 case XGBE_PORT_MODE_SFP:
2313 return xgbe_phy_get_sfp_mode(phy_data, speed);
2315 return XGBE_MODE_UNKNOWN;
2319 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2322 case XGBE_MODE_KX_1000:
2323 xgbe_phy_kx_1000_mode(pdata);
2325 case XGBE_MODE_KX_2500:
2326 xgbe_phy_kx_2500_mode(pdata);
2329 xgbe_phy_kr_mode(pdata);
2331 case XGBE_MODE_SGMII_100:
2332 xgbe_phy_sgmii_100_mode(pdata);
2334 case XGBE_MODE_SGMII_1000:
2335 xgbe_phy_sgmii_1000_mode(pdata);
2338 xgbe_phy_x_mode(pdata);
2341 xgbe_phy_sfi_mode(pdata);
2348 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2349 enum xgbe_mode mode, bool advert)
2351 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2354 enum xgbe_mode cur_mode;
2356 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2357 if (cur_mode == mode)
2364 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2365 enum xgbe_mode mode)
2367 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2371 return xgbe_phy_check_mode(pdata, mode,
2372 XGBE_ADV(lks, 1000baseX_Full));
2374 return xgbe_phy_check_mode(pdata, mode,
2375 XGBE_ADV(lks, 10000baseKR_Full));
2381 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2382 enum xgbe_mode mode)
2384 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2387 case XGBE_MODE_SGMII_100:
2388 return xgbe_phy_check_mode(pdata, mode,
2389 XGBE_ADV(lks, 100baseT_Full));
2390 case XGBE_MODE_SGMII_1000:
2391 return xgbe_phy_check_mode(pdata, mode,
2392 XGBE_ADV(lks, 1000baseT_Full));
2393 case XGBE_MODE_KX_2500:
2394 return xgbe_phy_check_mode(pdata, mode,
2395 XGBE_ADV(lks, 2500baseT_Full));
2397 return xgbe_phy_check_mode(pdata, mode,
2398 XGBE_ADV(lks, 10000baseT_Full));
2404 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2405 enum xgbe_mode mode)
2407 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2408 struct xgbe_phy_data *phy_data = pdata->phy_data;
2412 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2414 return xgbe_phy_check_mode(pdata, mode,
2415 XGBE_ADV(lks, 1000baseX_Full));
2416 case XGBE_MODE_SGMII_100:
2417 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2419 return xgbe_phy_check_mode(pdata, mode,
2420 XGBE_ADV(lks, 100baseT_Full));
2421 case XGBE_MODE_SGMII_1000:
2422 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2424 return xgbe_phy_check_mode(pdata, mode,
2425 XGBE_ADV(lks, 1000baseT_Full));
2427 if (phy_data->sfp_mod_absent)
2429 return xgbe_phy_check_mode(pdata, mode,
2430 XGBE_ADV(lks, 10000baseSR_Full) ||
2431 XGBE_ADV(lks, 10000baseLR_Full) ||
2432 XGBE_ADV(lks, 10000baseLRM_Full) ||
2433 XGBE_ADV(lks, 10000baseER_Full) ||
2434 XGBE_ADV(lks, 10000baseCR_Full));
2440 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2441 enum xgbe_mode mode)
2443 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2446 case XGBE_MODE_KX_2500:
2447 return xgbe_phy_check_mode(pdata, mode,
2448 XGBE_ADV(lks, 2500baseX_Full));
2454 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2455 enum xgbe_mode mode)
2457 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2460 case XGBE_MODE_KX_1000:
2461 return xgbe_phy_check_mode(pdata, mode,
2462 XGBE_ADV(lks, 1000baseKX_Full));
2464 return xgbe_phy_check_mode(pdata, mode,
2465 XGBE_ADV(lks, 10000baseKR_Full));
2471 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2473 struct xgbe_phy_data *phy_data = pdata->phy_data;
2475 switch (phy_data->port_mode) {
2476 case XGBE_PORT_MODE_BACKPLANE:
2477 return xgbe_phy_use_bp_mode(pdata, mode);
2478 case XGBE_PORT_MODE_BACKPLANE_2500:
2479 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2480 case XGBE_PORT_MODE_1000BASE_T:
2481 case XGBE_PORT_MODE_NBASE_T:
2482 case XGBE_PORT_MODE_10GBASE_T:
2483 return xgbe_phy_use_baset_mode(pdata, mode);
2484 case XGBE_PORT_MODE_1000BASE_X:
2485 case XGBE_PORT_MODE_10GBASE_R:
2486 return xgbe_phy_use_basex_mode(pdata, mode);
2487 case XGBE_PORT_MODE_SFP:
2488 return xgbe_phy_use_sfp_mode(pdata, mode);
2494 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2499 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2501 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2507 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2515 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2517 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2523 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2528 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2530 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2531 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2533 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2539 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2549 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2560 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2562 struct xgbe_phy_data *phy_data = pdata->phy_data;
2564 switch (phy_data->port_mode) {
2565 case XGBE_PORT_MODE_BACKPLANE:
2566 return xgbe_phy_valid_speed_bp_mode(speed);
2567 case XGBE_PORT_MODE_BACKPLANE_2500:
2568 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2569 case XGBE_PORT_MODE_1000BASE_T:
2570 case XGBE_PORT_MODE_NBASE_T:
2571 case XGBE_PORT_MODE_10GBASE_T:
2572 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2573 case XGBE_PORT_MODE_1000BASE_X:
2574 case XGBE_PORT_MODE_10GBASE_R:
2575 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2576 case XGBE_PORT_MODE_SFP:
2577 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
2583 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2585 struct xgbe_phy_data *phy_data = pdata->phy_data;
2591 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2592 /* Check SFP signals */
2593 xgbe_phy_sfp_detect(pdata);
2595 if (phy_data->sfp_changed) {
2600 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2604 if (phy_data->phydev) {
2605 /* Check external PHY */
2606 ret = phy_read_status(phy_data->phydev);
2610 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2611 !phy_aneg_done(phy_data->phydev))
2614 if (!phy_data->phydev->link)
2618 /* Link status is latched low, so read once to clear
2619 * and then read again to get current state
2621 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2622 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2623 if (reg & MDIO_STAT1_LSTATUS)
2626 if (pdata->phy.autoneg == AUTONEG_ENABLE &&
2627 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) {
2628 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
2629 netif_carrier_off(pdata->netdev);
2634 /* No link, attempt a receiver reset cycle */
2635 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2636 phy_data->rrc_count = 0;
2637 xgbe_phy_rrc(pdata);
2643 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2645 struct xgbe_phy_data *phy_data = pdata->phy_data;
2647 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2648 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2651 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2654 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2656 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2658 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2660 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2663 if (netif_msg_probe(pdata)) {
2664 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2665 phy_data->sfp_gpio_address);
2666 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2667 phy_data->sfp_gpio_mask);
2668 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2669 phy_data->sfp_gpio_rx_los);
2670 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2671 phy_data->sfp_gpio_tx_fault);
2672 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2673 phy_data->sfp_gpio_mod_absent);
2674 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2675 phy_data->sfp_gpio_rate_select);
2679 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2681 struct xgbe_phy_data *phy_data = pdata->phy_data;
2682 unsigned int mux_addr_hi, mux_addr_lo;
2684 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2685 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2686 if (mux_addr_lo == XGBE_SFP_DIRECT)
2689 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2690 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2691 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2694 if (netif_msg_probe(pdata)) {
2695 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2696 phy_data->sfp_mux_address);
2697 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2698 phy_data->sfp_mux_channel);
2702 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2704 xgbe_phy_sfp_comm_setup(pdata);
2705 xgbe_phy_sfp_gpio_setup(pdata);
2708 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2710 struct xgbe_phy_data *phy_data = pdata->phy_data;
2713 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2717 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2722 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2724 struct xgbe_phy_data *phy_data = pdata->phy_data;
2725 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2728 /* Read the output port registers */
2730 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2731 &gpio_reg, sizeof(gpio_reg),
2732 gpio_ports, sizeof(gpio_ports));
2736 /* Prepare to write the GPIO data */
2738 gpio_data[1] = gpio_ports[0];
2739 gpio_data[2] = gpio_ports[1];
2741 /* Set the GPIO pin */
2742 if (phy_data->mdio_reset_gpio < 8)
2743 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2745 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2747 /* Write the output port registers */
2748 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2749 gpio_data, sizeof(gpio_data));
2753 /* Clear the GPIO pin */
2754 if (phy_data->mdio_reset_gpio < 8)
2755 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2757 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2759 /* Write the output port registers */
2760 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2761 gpio_data, sizeof(gpio_data));
2766 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2768 struct xgbe_phy_data *phy_data = pdata->phy_data;
2771 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2774 ret = xgbe_phy_get_comm_ownership(pdata);
2778 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2779 ret = xgbe_phy_i2c_mdio_reset(pdata);
2780 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2781 ret = xgbe_phy_int_mdio_reset(pdata);
2783 xgbe_phy_put_comm_ownership(pdata);
2788 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2790 if (!phy_data->redrv)
2793 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2796 switch (phy_data->redrv_model) {
2797 case XGBE_PHY_REDRV_MODEL_4223:
2798 if (phy_data->redrv_lane > 3)
2801 case XGBE_PHY_REDRV_MODEL_4227:
2802 if (phy_data->redrv_lane > 1)
2812 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2814 struct xgbe_phy_data *phy_data = pdata->phy_data;
2816 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2819 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
2820 switch (phy_data->mdio_reset) {
2821 case XGBE_MDIO_RESET_NONE:
2822 case XGBE_MDIO_RESET_I2C_GPIO:
2823 case XGBE_MDIO_RESET_INT_GPIO:
2826 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2827 phy_data->mdio_reset);
2831 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2832 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
2833 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2834 MDIO_RESET_I2C_ADDR);
2835 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2836 MDIO_RESET_I2C_GPIO);
2837 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
2838 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2839 MDIO_RESET_INT_GPIO);
2845 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2847 struct xgbe_phy_data *phy_data = pdata->phy_data;
2849 switch (phy_data->port_mode) {
2850 case XGBE_PORT_MODE_BACKPLANE:
2851 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2852 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2855 case XGBE_PORT_MODE_BACKPLANE_2500:
2856 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2859 case XGBE_PORT_MODE_1000BASE_T:
2860 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2861 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2864 case XGBE_PORT_MODE_1000BASE_X:
2865 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2868 case XGBE_PORT_MODE_NBASE_T:
2869 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2870 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2871 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2874 case XGBE_PORT_MODE_10GBASE_T:
2875 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2876 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2877 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2880 case XGBE_PORT_MODE_10GBASE_R:
2881 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2884 case XGBE_PORT_MODE_SFP:
2885 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2886 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2887 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2897 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2899 struct xgbe_phy_data *phy_data = pdata->phy_data;
2901 switch (phy_data->port_mode) {
2902 case XGBE_PORT_MODE_BACKPLANE:
2903 case XGBE_PORT_MODE_BACKPLANE_2500:
2904 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2907 case XGBE_PORT_MODE_1000BASE_T:
2908 case XGBE_PORT_MODE_1000BASE_X:
2909 case XGBE_PORT_MODE_NBASE_T:
2910 case XGBE_PORT_MODE_10GBASE_T:
2911 case XGBE_PORT_MODE_10GBASE_R:
2912 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2915 case XGBE_PORT_MODE_SFP:
2916 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2926 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2928 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
2930 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
2936 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
2938 struct xgbe_phy_data *phy_data = pdata->phy_data;
2940 if (!pdata->debugfs_an_cdr_workaround)
2943 if (!phy_data->phy_cdr_notrack)
2946 usleep_range(phy_data->phy_cdr_delay,
2947 phy_data->phy_cdr_delay + 500);
2949 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2950 XGBE_PMA_CDR_TRACK_EN_MASK,
2951 XGBE_PMA_CDR_TRACK_EN_ON);
2953 phy_data->phy_cdr_notrack = 0;
2956 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
2958 struct xgbe_phy_data *phy_data = pdata->phy_data;
2960 if (!pdata->debugfs_an_cdr_workaround)
2963 if (phy_data->phy_cdr_notrack)
2966 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2967 XGBE_PMA_CDR_TRACK_EN_MASK,
2968 XGBE_PMA_CDR_TRACK_EN_OFF);
2970 xgbe_phy_rrc(pdata);
2972 phy_data->phy_cdr_notrack = 1;
2975 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
2977 if (!pdata->debugfs_an_cdr_track_early)
2978 xgbe_phy_cdr_track(pdata);
2981 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
2983 if (pdata->debugfs_an_cdr_track_early)
2984 xgbe_phy_cdr_track(pdata);
2987 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
2989 struct xgbe_phy_data *phy_data = pdata->phy_data;
2991 switch (pdata->an_mode) {
2992 case XGBE_AN_MODE_CL73:
2993 case XGBE_AN_MODE_CL73_REDRV:
2994 if (phy_data->cur_mode != XGBE_MODE_KR)
2997 xgbe_phy_cdr_track(pdata);
2999 switch (pdata->an_result) {
3001 case XGBE_AN_COMPLETE:
3004 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
3005 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3007 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3016 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3018 struct xgbe_phy_data *phy_data = pdata->phy_data;
3020 switch (pdata->an_mode) {
3021 case XGBE_AN_MODE_CL73:
3022 case XGBE_AN_MODE_CL73_REDRV:
3023 if (phy_data->cur_mode != XGBE_MODE_KR)
3026 xgbe_phy_cdr_notrack(pdata);
3033 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
3035 struct xgbe_phy_data *phy_data = pdata->phy_data;
3037 /* If we have an external PHY, free it */
3038 xgbe_phy_free_phy_device(pdata);
3040 /* Reset SFP data */
3041 xgbe_phy_sfp_reset(phy_data);
3042 xgbe_phy_sfp_mod_absent(pdata);
3044 /* Reset CDR support */
3045 xgbe_phy_cdr_track(pdata);
3047 /* Power off the PHY */
3048 xgbe_phy_power_off(pdata);
3050 /* Stop the I2C controller */
3051 pdata->i2c_if.i2c_stop(pdata);
3054 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
3056 struct xgbe_phy_data *phy_data = pdata->phy_data;
3059 /* Start the I2C controller */
3060 ret = pdata->i2c_if.i2c_start(pdata);
3064 /* Set the proper MDIO mode for the re-driver */
3065 if (phy_data->redrv && !phy_data->redrv_if) {
3066 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3067 XGBE_MDIO_MODE_CL22);
3069 netdev_err(pdata->netdev,
3070 "redriver mdio port not compatible (%u)\n",
3071 phy_data->redrv_addr);
3076 /* Start in highest supported mode */
3077 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3079 /* Reset CDR support */
3080 xgbe_phy_cdr_track(pdata);
3082 /* After starting the I2C controller, we can check for an SFP */
3083 switch (phy_data->port_mode) {
3084 case XGBE_PORT_MODE_SFP:
3085 xgbe_phy_sfp_detect(pdata);
3091 /* If we have an external PHY, start it */
3092 ret = xgbe_phy_find_phy_device(pdata);
3099 pdata->i2c_if.i2c_stop(pdata);
3104 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3106 struct xgbe_phy_data *phy_data = pdata->phy_data;
3107 enum xgbe_mode cur_mode;
3110 /* Reset by power cycling the PHY */
3111 cur_mode = phy_data->cur_mode;
3112 xgbe_phy_power_off(pdata);
3113 xgbe_phy_set_mode(pdata, cur_mode);
3115 if (!phy_data->phydev)
3118 /* Reset the external PHY */
3119 ret = xgbe_phy_mdio_reset(pdata);
3123 return phy_init_hw(phy_data->phydev);
3126 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3128 struct xgbe_phy_data *phy_data = pdata->phy_data;
3130 /* Unregister for driving external PHYs */
3131 mdiobus_unregister(phy_data->mii);
3134 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3136 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
3137 struct xgbe_phy_data *phy_data;
3138 struct mii_bus *mii;
3141 /* Check if enabled */
3142 if (!xgbe_phy_port_enabled(pdata)) {
3143 dev_info(pdata->dev, "device is not enabled\n");
3147 /* Initialize the I2C controller */
3148 ret = pdata->i2c_if.i2c_init(pdata);
3152 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3155 pdata->phy_data = phy_data;
3157 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3158 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3159 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3160 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3161 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3162 if (netif_msg_probe(pdata)) {
3163 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3164 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3165 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3166 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3167 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3170 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3171 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3172 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3173 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3174 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3175 if (phy_data->redrv && netif_msg_probe(pdata)) {
3176 dev_dbg(pdata->dev, "redrv present\n");
3177 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3178 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3179 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3180 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3183 /* Validate the connection requested */
3184 if (xgbe_phy_conn_type_mismatch(pdata)) {
3185 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3186 phy_data->port_mode, phy_data->conn_type);
3190 /* Validate the mode requested */
3191 if (xgbe_phy_port_mode_mismatch(pdata)) {
3192 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3193 phy_data->port_mode, phy_data->port_speeds);
3197 /* Check for and validate MDIO reset support */
3198 ret = xgbe_phy_mdio_reset_setup(pdata);
3202 /* Validate the re-driver information */
3203 if (xgbe_phy_redrv_error(phy_data)) {
3204 dev_err(pdata->dev, "phy re-driver settings error\n");
3207 pdata->kr_redrv = phy_data->redrv;
3209 /* Indicate current mode is unknown */
3210 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3212 /* Initialize supported features */
3215 switch (phy_data->port_mode) {
3216 /* Backplane support */
3217 case XGBE_PORT_MODE_BACKPLANE:
3218 XGBE_SET_SUP(lks, Autoneg);
3219 XGBE_SET_SUP(lks, Pause);
3220 XGBE_SET_SUP(lks, Asym_Pause);
3221 XGBE_SET_SUP(lks, Backplane);
3222 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3223 XGBE_SET_SUP(lks, 1000baseKX_Full);
3224 phy_data->start_mode = XGBE_MODE_KX_1000;
3226 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3227 XGBE_SET_SUP(lks, 10000baseKR_Full);
3228 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3229 XGBE_SET_SUP(lks, 10000baseR_FEC);
3230 phy_data->start_mode = XGBE_MODE_KR;
3233 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3235 case XGBE_PORT_MODE_BACKPLANE_2500:
3236 XGBE_SET_SUP(lks, Pause);
3237 XGBE_SET_SUP(lks, Asym_Pause);
3238 XGBE_SET_SUP(lks, Backplane);
3239 XGBE_SET_SUP(lks, 2500baseX_Full);
3240 phy_data->start_mode = XGBE_MODE_KX_2500;
3242 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3245 /* MDIO 1GBase-T support */
3246 case XGBE_PORT_MODE_1000BASE_T:
3247 XGBE_SET_SUP(lks, Autoneg);
3248 XGBE_SET_SUP(lks, Pause);
3249 XGBE_SET_SUP(lks, Asym_Pause);
3250 XGBE_SET_SUP(lks, TP);
3251 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3252 XGBE_SET_SUP(lks, 100baseT_Full);
3253 phy_data->start_mode = XGBE_MODE_SGMII_100;
3255 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3256 XGBE_SET_SUP(lks, 1000baseT_Full);
3257 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3260 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3263 /* MDIO Base-X support */
3264 case XGBE_PORT_MODE_1000BASE_X:
3265 XGBE_SET_SUP(lks, Autoneg);
3266 XGBE_SET_SUP(lks, Pause);
3267 XGBE_SET_SUP(lks, Asym_Pause);
3268 XGBE_SET_SUP(lks, FIBRE);
3269 XGBE_SET_SUP(lks, 1000baseX_Full);
3270 phy_data->start_mode = XGBE_MODE_X;
3272 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3275 /* MDIO NBase-T support */
3276 case XGBE_PORT_MODE_NBASE_T:
3277 XGBE_SET_SUP(lks, Autoneg);
3278 XGBE_SET_SUP(lks, Pause);
3279 XGBE_SET_SUP(lks, Asym_Pause);
3280 XGBE_SET_SUP(lks, TP);
3281 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3282 XGBE_SET_SUP(lks, 100baseT_Full);
3283 phy_data->start_mode = XGBE_MODE_SGMII_100;
3285 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3286 XGBE_SET_SUP(lks, 1000baseT_Full);
3287 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3289 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3290 XGBE_SET_SUP(lks, 2500baseT_Full);
3291 phy_data->start_mode = XGBE_MODE_KX_2500;
3294 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3297 /* 10GBase-T support */
3298 case XGBE_PORT_MODE_10GBASE_T:
3299 XGBE_SET_SUP(lks, Autoneg);
3300 XGBE_SET_SUP(lks, Pause);
3301 XGBE_SET_SUP(lks, Asym_Pause);
3302 XGBE_SET_SUP(lks, TP);
3303 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3304 XGBE_SET_SUP(lks, 100baseT_Full);
3305 phy_data->start_mode = XGBE_MODE_SGMII_100;
3307 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3308 XGBE_SET_SUP(lks, 1000baseT_Full);
3309 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3311 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3312 XGBE_SET_SUP(lks, 10000baseT_Full);
3313 phy_data->start_mode = XGBE_MODE_KR;
3316 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3319 /* 10GBase-R support */
3320 case XGBE_PORT_MODE_10GBASE_R:
3321 XGBE_SET_SUP(lks, Autoneg);
3322 XGBE_SET_SUP(lks, Pause);
3323 XGBE_SET_SUP(lks, Asym_Pause);
3324 XGBE_SET_SUP(lks, FIBRE);
3325 XGBE_SET_SUP(lks, 10000baseSR_Full);
3326 XGBE_SET_SUP(lks, 10000baseLR_Full);
3327 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3328 XGBE_SET_SUP(lks, 10000baseER_Full);
3329 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3330 XGBE_SET_SUP(lks, 10000baseR_FEC);
3331 phy_data->start_mode = XGBE_MODE_SFI;
3333 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3337 case XGBE_PORT_MODE_SFP:
3338 XGBE_SET_SUP(lks, Autoneg);
3339 XGBE_SET_SUP(lks, Pause);
3340 XGBE_SET_SUP(lks, Asym_Pause);
3341 XGBE_SET_SUP(lks, TP);
3342 XGBE_SET_SUP(lks, FIBRE);
3343 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3344 phy_data->start_mode = XGBE_MODE_SGMII_100;
3345 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3346 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3347 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3348 phy_data->start_mode = XGBE_MODE_SFI;
3350 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3352 xgbe_phy_sfp_setup(pdata);
3358 if (netif_msg_probe(pdata))
3359 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3360 __ETHTOOL_LINK_MODE_MASK_NBITS,
3361 lks->link_modes.supported);
3363 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3364 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3365 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3366 phy_data->phydev_mode);
3369 "mdio port/clause not compatible (%d/%u)\n",
3370 phy_data->mdio_addr, phy_data->phydev_mode);
3375 if (phy_data->redrv && !phy_data->redrv_if) {
3376 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3377 XGBE_MDIO_MODE_CL22);
3380 "redriver mdio port not compatible (%u)\n",
3381 phy_data->redrv_addr);
3386 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3388 /* Register for driving external PHYs */
3389 mii = devm_mdiobus_alloc(pdata->dev);
3391 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3396 mii->name = "amd-xgbe-mii";
3397 mii->read = xgbe_phy_mii_read;
3398 mii->write = xgbe_phy_mii_write;
3399 mii->parent = pdata->dev;
3401 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3402 ret = mdiobus_register(mii);
3404 dev_err(pdata->dev, "mdiobus_register failed\n");
3407 phy_data->mii = mii;
3412 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3414 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3416 phy_impl->init = xgbe_phy_init;
3417 phy_impl->exit = xgbe_phy_exit;
3419 phy_impl->reset = xgbe_phy_reset;
3420 phy_impl->start = xgbe_phy_start;
3421 phy_impl->stop = xgbe_phy_stop;
3423 phy_impl->link_status = xgbe_phy_link_status;
3425 phy_impl->valid_speed = xgbe_phy_valid_speed;
3427 phy_impl->use_mode = xgbe_phy_use_mode;
3428 phy_impl->set_mode = xgbe_phy_set_mode;
3429 phy_impl->get_mode = xgbe_phy_get_mode;
3430 phy_impl->switch_mode = xgbe_phy_switch_mode;
3431 phy_impl->cur_mode = xgbe_phy_cur_mode;
3433 phy_impl->an_mode = xgbe_phy_an_mode;
3435 phy_impl->an_config = xgbe_phy_an_config;
3437 phy_impl->an_advertising = xgbe_phy_an_advertising;
3439 phy_impl->an_outcome = xgbe_phy_an_outcome;
3441 phy_impl->an_pre = xgbe_phy_an_pre;
3442 phy_impl->an_post = xgbe_phy_an_post;
3444 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3445 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
3447 phy_impl->module_info = xgbe_phy_module_info;
3448 phy_impl->module_eeprom = xgbe_phy_module_eeprom;