drivers/net/ethernet/apm/xgene/xgene_enet_main.c

   1 /* Applied Micro X-Gene SoC Ethernet Driver
   2  *
   3  * Copyright (c) 2014, Applied Micro Circuits Corporation
   4  * Authors: Iyappan Subramanian <isubramanian@apm.com>
   5  *          Ravi Patel <rapatel@apm.com>
   6  *          Keyur Chudgar <kchudgar@apm.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/gpio.h>
  23 #include "xgene_enet_main.h"
  24 #include "xgene_enet_hw.h"
  25 #include "xgene_enet_sgmac.h"
  26 #include "xgene_enet_xgmac.h"
  27
  28 #define RES_ENET_CSR    0
  29 #define RES_RING_CSR    1
  30 #define RES_RING_CMD    2
  31
  32 static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
  33 {
  34         struct xgene_enet_raw_desc16 *raw_desc;
  35         int i;
  36
  37         if (!buf_pool)
  38                 return;
  39
  40         for (i = 0; i < buf_pool->slots; i++) {
  41                 raw_desc = &buf_pool->raw_desc16[i];
  42
  43                 /* Hardware expects descriptor in little endian format */
  44                 raw_desc->m0 = cpu_to_le64(i |
  45                                 SET_VAL(FPQNUM, buf_pool->dst_ring_num) |
  46                                 SET_VAL(STASH, 3));
  47         }
  48 }
  49
  50 static u16 xgene_enet_get_data_len(u64 bufdatalen)
  51 {
  52         u16 hw_len, mask;
  53
  54         hw_len = GET_VAL(BUFDATALEN, bufdatalen);
  55
  56         if (unlikely(hw_len == 0x7800)) {
  57                 return 0;
  58         } else if (!(hw_len & BIT(14))) {
  59                 mask = GENMASK(13, 0);
  60                 return (hw_len & mask) ? (hw_len & mask) : SIZE_16K;
  61         } else if (!(hw_len & GENMASK(13, 12))) {
  62                 mask = GENMASK(11, 0);
  63                 return (hw_len & mask) ? (hw_len & mask) : SIZE_4K;
  64         } else {
  65                 mask = GENMASK(11, 0);
  66                 return (hw_len & mask) ? (hw_len & mask) : SIZE_2K;
  67         }
  68 }
  69
  70 static u16 xgene_enet_set_data_len(u32 size)
  71 {
  72         u16 hw_len;
  73
  74         hw_len =  (size == SIZE_4K) ? BIT(14) : 0;
  75
  76         return hw_len;
  77 }
  78
  79 static int xgene_enet_refill_pagepool(struct xgene_enet_desc_ring *buf_pool,
  80                                       u32 nbuf)
  81 {
  82         struct xgene_enet_raw_desc16 *raw_desc;
  83         struct xgene_enet_pdata *pdata;
  84         struct net_device *ndev;
  85         dma_addr_t dma_addr;
  86         struct device *dev;
  87         struct page *page;
  88         u32 slots, tail;
  89         u16 hw_len;
  90         int i;
  91
  92         if (unlikely(!buf_pool))
  93                 return 0;
  94
  95         ndev = buf_pool->ndev;
  96         pdata = netdev_priv(ndev);
  97         dev = ndev_to_dev(ndev);
  98         slots = buf_pool->slots - 1;
  99         tail = buf_pool->tail;
 100
 101         for (i = 0; i < nbuf; i++) {
 102                 raw_desc = &buf_pool->raw_desc16[tail];
 103
 104                 page = dev_alloc_page();
 105                 if (unlikely(!page))
 106                         return -ENOMEM;
 107
 108                 dma_addr = dma_map_page(dev, page, 0,
 109                                         PAGE_SIZE, DMA_FROM_DEVICE);
 110                 if (unlikely(dma_mapping_error(dev, dma_addr))) {
 111                         put_page(page);
 112                         return -ENOMEM;
 113                 }
 114
 115                 hw_len = xgene_enet_set_data_len(PAGE_SIZE);
 116                 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
 117                                            SET_VAL(BUFDATALEN, hw_len) |
 118                                            SET_BIT(COHERENT));
 119
 120                 buf_pool->frag_page[tail] = page;
 121                 tail = (tail + 1) & slots;
 122         }
 123
 124         pdata->ring_ops->wr_cmd(buf_pool, nbuf);
 125         buf_pool->tail = tail;
 126
 127         return 0;
 128 }
 129
 130 static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool,
 131                                      u32 nbuf)
 132 {
 133         struct sk_buff *skb;
 134         struct xgene_enet_raw_desc16 *raw_desc;
 135         struct xgene_enet_pdata *pdata;
 136         struct net_device *ndev;
 137         struct device *dev;
 138         dma_addr_t dma_addr;
 139         u32 tail = buf_pool->tail;
 140         u32 slots = buf_pool->slots - 1;
 141         u16 bufdatalen, len;
 142         int i;
 143
 144         ndev = buf_pool->ndev;
 145         dev = ndev_to_dev(buf_pool->ndev);
 146         pdata = netdev_priv(ndev);
 147
 148         bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0));
 149         len = XGENE_ENET_STD_MTU;
 150
 151         for (i = 0; i < nbuf; i++) {
 152                 raw_desc = &buf_pool->raw_desc16[tail];
 153
 154                 skb = netdev_alloc_skb_ip_align(ndev, len);
 155                 if (unlikely(!skb))
 156                         return -ENOMEM;
 157
 158                 dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
 159                 if (dma_mapping_error(dev, dma_addr)) {
 160                         netdev_err(ndev, "DMA mapping error\n");
 161                         dev_kfree_skb_any(skb);
 162                         return -EINVAL;
 163                 }
 164
 165                 buf_pool->rx_skb[tail] = skb;
 166
 167                 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
 168                                            SET_VAL(BUFDATALEN, bufdatalen) |
 169                                            SET_BIT(COHERENT));
 170                 tail = (tail + 1) & slots;
 171         }
 172
 173         pdata->ring_ops->wr_cmd(buf_pool, nbuf);
 174         buf_pool->tail = tail;
 175
 176         return 0;
 177 }
 178
 179 static u8 xgene_enet_hdr_len(const void *data)
 180 {
 181         const struct ethhdr *eth = data;
 182
 183         return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN;
 184 }
 185
 186 static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool)
 187 {
 188         struct device *dev = ndev_to_dev(buf_pool->ndev);
 189         struct xgene_enet_raw_desc16 *raw_desc;
 190         dma_addr_t dma_addr;
 191         int i;
 192
 193         /* Free up the buffers held by hardware */
 194         for (i = 0; i < buf_pool->slots; i++) {
 195                 if (buf_pool->rx_skb[i]) {
 196                         dev_kfree_skb_any(buf_pool->rx_skb[i]);
 197
 198                         raw_desc = &buf_pool->raw_desc16[i];
 199                         dma_addr = GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1));
 200                         dma_unmap_single(dev, dma_addr, XGENE_ENET_MAX_MTU,
 201                                          DMA_FROM_DEVICE);
 202                 }
 203         }
 204 }
 205
 206 static void xgene_enet_delete_pagepool(struct xgene_enet_desc_ring *buf_pool)
 207 {
 208         struct device *dev = ndev_to_dev(buf_pool->ndev);
 209         dma_addr_t dma_addr;
 210         struct page *page;
 211         int i;
 212
 213         /* Free up the buffers held by hardware */
 214         for (i = 0; i < buf_pool->slots; i++) {
 215                 page = buf_pool->frag_page[i];
 216                 if (page) {
 217                         dma_addr = buf_pool->frag_dma_addr[i];
 218                         dma_unmap_page(dev, dma_addr, PAGE_SIZE,
 219                                        DMA_FROM_DEVICE);
 220                         put_page(page);
 221                 }
 222         }
 223 }
 224
 225 static irqreturn_t xgene_enet_rx_irq(const int irq, void *data)
 226 {
 227         struct xgene_enet_desc_ring *rx_ring = data;
 228
 229         if (napi_schedule_prep(&rx_ring->napi)) {
 230                 disable_irq_nosync(irq);
 231                 __napi_schedule(&rx_ring->napi);
 232         }
 233
 234         return IRQ_HANDLED;
 235 }
 236
 237 static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
 238                                     struct xgene_enet_raw_desc *raw_desc)
 239 {
 240         struct xgene_enet_pdata *pdata = netdev_priv(cp_ring->ndev);
 241         struct sk_buff *skb;
 242         struct device *dev;
 243         skb_frag_t *frag;
 244         dma_addr_t *frag_dma_addr;
 245         u16 skb_index;
 246         u8 mss_index;
 247         u8 status;
 248         int i;
 249
 250         skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
 251         skb = cp_ring->cp_skb[skb_index];
 252         frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS];
 253
 254         dev = ndev_to_dev(cp_ring->ndev);
 255         dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
 256                          skb_headlen(skb),
 257                          DMA_TO_DEVICE);
 258
 259         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 260                 frag = &skb_shinfo(skb)->frags[i];
 261                 dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag),
 262                                DMA_TO_DEVICE);
 263         }
 264
 265         if (GET_BIT(ET, le64_to_cpu(raw_desc->m3))) {
 266                 mss_index = GET_VAL(MSS, le64_to_cpu(raw_desc->m3));
 267                 spin_lock(&pdata->mss_lock);
 268                 pdata->mss_refcnt[mss_index]--;
 269                 spin_unlock(&pdata->mss_lock);
 270         }
 271
 272         /* Checking for error */
 273         status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
 274         if (unlikely(status > 2)) {
 275                 cp_ring->tx_dropped++;
 276                 cp_ring->tx_errors++;
 277         }
 278
 279         if (likely(skb)) {
 280                 dev_kfree_skb_any(skb);
 281         } else {
 282                 netdev_err(cp_ring->ndev, "completion skb is NULL\n");
 283         }
 284
 285         return 0;
 286 }
 287
 288 static int xgene_enet_setup_mss(struct net_device *ndev, u32 mss)
 289 {
 290         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
 291         int mss_index = -EBUSY;
 292         int i;
 293
 294         spin_lock(&pdata->mss_lock);
 295
 296         /* Reuse the slot if MSS matches */
 297         for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) {
 298                 if (pdata->mss[i] == mss) {
 299                         pdata->mss_refcnt[i]++;
 300                         mss_index = i;
 301                 }
 302         }
 303
 304         /* Overwrite the slot with ref_count = 0 */
 305         for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) {
 306                 if (!pdata->mss_refcnt[i]) {
 307                         pdata->mss_refcnt[i]++;
 308                         pdata->mac_ops->set_mss(pdata, mss, i);
 309                         pdata->mss[i] = mss;
 310                         mss_index = i;
 311                 }
 312         }
 313
 314         spin_unlock(&pdata->mss_lock);
 315
 316         return mss_index;
 317 }
 318
 319 static int xgene_enet_work_msg(struct sk_buff *skb, u64 *hopinfo)
 320 {
 321         struct net_device *ndev = skb->dev;
 322         struct iphdr *iph;
 323         u8 l3hlen = 0, l4hlen = 0;
 324         u8 ethhdr, proto = 0, csum_enable = 0;
 325         u32 hdr_len, mss = 0;
 326         u32 i, len, nr_frags;
 327         int mss_index;
 328
 329         ethhdr = xgene_enet_hdr_len(skb->data);
 330
 331         if (unlikely(skb->protocol != htons(ETH_P_IP)) &&
 332             unlikely(skb->protocol != htons(ETH_P_8021Q)))
 333                 goto out;
 334
 335         if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM)))
 336                 goto out;
 337
 338         iph = ip_hdr(skb);
 339         if (unlikely(ip_is_fragment(iph)))
 340                 goto out;
 341
 342         if (likely(iph->protocol == IPPROTO_TCP)) {
 343                 l4hlen = tcp_hdrlen(skb) >> 2;
 344                 csum_enable = 1;
 345                 proto = TSO_IPPROTO_TCP;
 346                 if (ndev->features & NETIF_F_TSO) {
 347                         hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb);
 348                         mss = skb_shinfo(skb)->gso_size;
 349
 350                         if (skb_is_nonlinear(skb)) {
 351                                 len = skb_headlen(skb);
 352                                 nr_frags = skb_shinfo(skb)->nr_frags;
 353
 354                                 for (i = 0; i < 2 && i < nr_frags; i++)
 355                                         len += skb_shinfo(skb)->frags[i].size;
 356
 357                                 /* HW requires header must reside in 3 buffer */
 358                                 if (unlikely(hdr_len > len)) {
 359                                         if (skb_linearize(skb))
 360                                                 return 0;
 361                                 }
 362                         }
 363
 364                         if (!mss || ((skb->len - hdr_len) <= mss))
 365                                 goto out;
 366
 367                         mss_index = xgene_enet_setup_mss(ndev, mss);
 368                         if (unlikely(mss_index < 0))
 369                                 return -EBUSY;
 370
 371                         *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index);
 372                 }
 373         } else if (iph->protocol == IPPROTO_UDP) {
 374                 l4hlen = UDP_HDR_SIZE;
 375                 csum_enable = 1;
 376         }
 377 out:
 378         l3hlen = ip_hdrlen(skb) >> 2;
 379         *hopinfo |= SET_VAL(TCPHDR, l4hlen) |
 380                     SET_VAL(IPHDR, l3hlen) |
 381                     SET_VAL(ETHHDR, ethhdr) |
 382                     SET_VAL(EC, csum_enable) |
 383                     SET_VAL(IS, proto) |
 384                     SET_BIT(IC) |
 385                     SET_BIT(TYPE_ETH_WORK_MESSAGE);
 386
 387         return 0;
 388 }
 389
 390 static u16 xgene_enet_encode_len(u16 len)
 391 {
 392         return (len == BUFLEN_16K) ? 0 : len;
 393 }
 394
 395 static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len)
 396 {
 397         desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) |
 398                                     SET_VAL(BUFDATALEN, len));
 399 }
 400
 401 static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring)
 402 {
 403         __le64 *exp_bufs;
 404
 405         exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS];
 406         memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS);
 407         ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1);
 408
 409         return exp_bufs;
 410 }
 411
 412 static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring)
 413 {
 414         return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS];
 415 }
 416
 417 static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
 418                                     struct sk_buff *skb)
 419 {
 420         struct device *dev = ndev_to_dev(tx_ring->ndev);
 421         struct xgene_enet_pdata *pdata = netdev_priv(tx_ring->ndev);
 422         struct xgene_enet_raw_desc *raw_desc;
 423         __le64 *exp_desc = NULL, *exp_bufs = NULL;
 424         dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr;
 425         skb_frag_t *frag;
 426         u16 tail = tx_ring->tail;
 427         u64 hopinfo = 0;
 428         u32 len, hw_len;
 429         u8 ll = 0, nv = 0, idx = 0;
 430         bool split = false;
 431         u32 size, offset, ell_bytes = 0;
 432         u32 i, fidx, nr_frags, count = 1;
 433         int ret;
 434
 435         raw_desc = &tx_ring->raw_desc[tail];
 436         tail = (tail + 1) & (tx_ring->slots - 1);
 437         memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc));
 438
 439         ret = xgene_enet_work_msg(skb, &hopinfo);
 440         if (ret)
 441                 return ret;
 442
 443         raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
 444                                    hopinfo);
 445
 446         len = skb_headlen(skb);
 447         hw_len = xgene_enet_encode_len(len);
 448
 449         dma_addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
 450         if (dma_mapping_error(dev, dma_addr)) {
 451                 netdev_err(tx_ring->ndev, "DMA mapping error\n");
 452                 return -EINVAL;
 453         }
 454
 455         /* Hardware expects descriptor in little endian format */
 456         raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
 457                                    SET_VAL(BUFDATALEN, hw_len) |
 458                                    SET_BIT(COHERENT));
 459
 460         if (!skb_is_nonlinear(skb))
 461                 goto out;
 462
 463         /* scatter gather */
 464         nv = 1;
 465         exp_desc = (void *)&tx_ring->raw_desc[tail];
 466         tail = (tail + 1) & (tx_ring->slots - 1);
 467         memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc));
 468
 469         nr_frags = skb_shinfo(skb)->nr_frags;
 470         for (i = nr_frags; i < 4 ; i++)
 471                 exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER);
 472
 473         frag_dma_addr = xgene_get_frag_dma_array(tx_ring);
 474
 475         for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) {
 476                 if (!split) {
 477                         frag = &skb_shinfo(skb)->frags[fidx];
 478                         size = skb_frag_size(frag);
 479                         offset = 0;
 480
 481                         pbuf_addr = skb_frag_dma_map(dev, frag, 0, size,
 482                                                      DMA_TO_DEVICE);
 483                         if (dma_mapping_error(dev, pbuf_addr))
 484                                 return -EINVAL;
 485
 486                         frag_dma_addr[fidx] = pbuf_addr;
 487                         fidx++;
 488
 489                         if (size > BUFLEN_16K)
 490                                 split = true;
 491                 }
 492
 493                 if (size > BUFLEN_16K) {
 494                         len = BUFLEN_16K;
 495                         size -= BUFLEN_16K;
 496                 } else {
 497                         len = size;
 498                         split = false;
 499                 }
 500
 501                 dma_addr = pbuf_addr + offset;
 502                 hw_len = xgene_enet_encode_len(len);
 503
 504                 switch (i) {
 505                 case 0:
 506                 case 1:
 507                 case 2:
 508                         xgene_set_addr_len(exp_desc, i, dma_addr, hw_len);
 509                         break;
 510                 case 3:
 511                         if (split || (fidx != nr_frags)) {
 512                                 exp_bufs = xgene_enet_get_exp_bufs(tx_ring);
 513                                 xgene_set_addr_len(exp_bufs, idx, dma_addr,
 514                                                    hw_len);
 515                                 idx++;
 516                                 ell_bytes += len;
 517                         } else {
 518                                 xgene_set_addr_len(exp_desc, i, dma_addr,
 519                                                    hw_len);
 520                         }
 521                         break;
 522                 default:
 523                         xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len);
 524                         idx++;
 525                         ell_bytes += len;
 526                         break;
 527                 }
 528
 529                 if (split)
 530                         offset += BUFLEN_16K;
 531         }
 532         count++;
 533
 534         if (idx) {
 535                 ll = 1;
 536                 dma_addr = dma_map_single(dev, exp_bufs,
 537                                           sizeof(u64) * MAX_EXP_BUFFS,
 538                                           DMA_TO_DEVICE);
 539                 if (dma_mapping_error(dev, dma_addr)) {
 540                         dev_kfree_skb_any(skb);
 541                         return -EINVAL;
 542                 }
 543                 i = ell_bytes >> LL_BYTES_LSB_LEN;
 544                 exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
 545                                           SET_VAL(LL_BYTES_MSB, i) |
 546                                           SET_VAL(LL_LEN, idx));
 547                 raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes));
 548         }
 549
 550 out:
 551         raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) |
 552                                    SET_VAL(USERINFO, tx_ring->tail));
 553         tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb;
 554         pdata->tx_level[tx_ring->cp_ring->index] += count;
 555         tx_ring->tail = tail;
 556
 557         return count;
 558 }
 559
 560 static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb,
 561                                          struct net_device *ndev)
 562 {
 563         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
 564         struct xgene_enet_desc_ring *tx_ring;
 565         int index = skb->queue_mapping;
 566         u32 tx_level = pdata->tx_level[index];
 567         int count;
 568
 569         tx_ring = pdata->tx_ring[index];
 570         if (tx_level < pdata->txc_level[index])
 571                 tx_level += ((typeof(pdata->tx_level[index]))~0U);
 572
 573         if ((tx_level - pdata->txc_level[index]) > pdata->tx_qcnt_hi) {
 574                 netif_stop_subqueue(ndev, index);
 575                 return NETDEV_TX_BUSY;
 576         }
 577
 578         if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE))
 579                 return NETDEV_TX_OK;
 580
 581         count = xgene_enet_setup_tx_desc(tx_ring, skb);
 582         if (count == -EBUSY)
 583                 return NETDEV_TX_BUSY;
 584
 585         if (count <= 0) {
 586                 dev_kfree_skb_any(skb);
 587                 return NETDEV_TX_OK;
 588         }
 589
 590         skb_tx_timestamp(skb);
 591
 592         tx_ring->tx_packets++;
 593         tx_ring->tx_bytes += skb->len;
 594
 595         pdata->ring_ops->wr_cmd(tx_ring, count);
 596         return NETDEV_TX_OK;
 597 }
 598
 599 static void xgene_enet_rx_csum(struct sk_buff *skb)
 600 {
 601         struct net_device *ndev = skb->dev;
 602         struct iphdr *iph = ip_hdr(skb);
 603
 604         if (!(ndev->features & NETIF_F_RXCSUM))
 605                 return;
 606
 607         if (skb->protocol != htons(ETH_P_IP))
 608                 return;
 609
 610         if (ip_is_fragment(iph))
 611                 return;
 612
 613         if (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)
 614                 return;
 615
 616         skb->ip_summed = CHECKSUM_UNNECESSARY;
 617 }
 618
 619 static void xgene_enet_free_pagepool(struct xgene_enet_desc_ring *buf_pool,
 620                                      struct xgene_enet_raw_desc *raw_desc,
 621                                      struct xgene_enet_raw_desc *exp_desc)
 622 {
 623         __le64 *desc = (void *)exp_desc;
 624         dma_addr_t dma_addr;
 625         struct device *dev;
 626         struct page *page;
 627         u16 slots, head;
 628         u32 frag_size;
 629         int i;
 630
 631         if (!buf_pool || !raw_desc || !exp_desc ||
 632             (!GET_VAL(NV, le64_to_cpu(raw_desc->m0))))
 633                 return;
 634
 635         dev = ndev_to_dev(buf_pool->ndev);
 636         slots = buf_pool->slots - 1;
 637         head = buf_pool->head;
 638
 639         for (i = 0; i < 4; i++) {
 640                 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1]));
 641                 if (!frag_size)
 642                         break;
 643
 644                 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1]));
 645                 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
 646
 647                 page = buf_pool->frag_page[head];
 648                 put_page(page);
 649
 650                 buf_pool->frag_page[head] = NULL;
 651                 head = (head + 1) & slots;
 652         }
 653         buf_pool->head = head;
 654 }
 655
 656 /* Errata 10GE_10 and ENET_15 - Fix duplicated HW statistic counters */
 657 static bool xgene_enet_errata_10GE_10(struct sk_buff *skb, u32 len, u8 status)
 658 {
 659         if (status == INGRESS_CRC &&
 660             len >= (ETHER_STD_PACKET + 1) &&
 661             len <= (ETHER_STD_PACKET + 4) &&
 662             skb->protocol == htons(ETH_P_8021Q))
 663                 return true;
 664
 665         return false;
 666 }
 667
 668 /* Errata 10GE_8 and ENET_11 - allow packet with length <=64B */
 669 static bool xgene_enet_errata_10GE_8(struct sk_buff *skb, u32 len, u8 status)
 670 {
 671         if (status == INGRESS_PKT_LEN && len == ETHER_MIN_PACKET) {
 672                 if (ntohs(eth_hdr(skb)->h_proto) < 46)
 673                         return true;
 674         }
 675
 676         return false;
 677 }
 678
 679 static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring,
 680                                struct xgene_enet_raw_desc *raw_desc,
 681                                struct xgene_enet_raw_desc *exp_desc)
 682 {
 683         struct xgene_enet_desc_ring *buf_pool, *page_pool;
 684         u32 datalen, frag_size, skb_index;
 685         struct xgene_enet_pdata *pdata;
 686         struct net_device *ndev;
 687         dma_addr_t dma_addr;
 688         struct sk_buff *skb;
 689         struct device *dev;
 690         struct page *page;
 691         u16 slots, head;
 692         int i, ret = 0;
 693         __le64 *desc;
 694         u8 status;
 695         bool nv;
 696
 697         ndev = rx_ring->ndev;
 698         pdata = netdev_priv(ndev);
 699         dev = ndev_to_dev(rx_ring->ndev);
 700         buf_pool = rx_ring->buf_pool;
 701         page_pool = rx_ring->page_pool;
 702
 703         dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
 704                          XGENE_ENET_STD_MTU, DMA_FROM_DEVICE);
 705         skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
 706         skb = buf_pool->rx_skb[skb_index];
 707         buf_pool->rx_skb[skb_index] = NULL;
 708
 709         datalen = xgene_enet_get_data_len(le64_to_cpu(raw_desc->m1));
 710
 711         /* strip off CRC as HW isn't doing this */
 712         nv = GET_VAL(NV, le64_to_cpu(raw_desc->m0));
 713         if (!nv)
 714                 datalen -= 4;
 715
 716         skb_put(skb, datalen);
 717         prefetch(skb->data - NET_IP_ALIGN);
 718         skb->protocol = eth_type_trans(skb, ndev);
 719
 720         /* checking for error */
 721         status = (GET_VAL(ELERR, le64_to_cpu(raw_desc->m0)) << LERR_LEN) |
 722                   GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
 723         if (unlikely(status)) {
 724                 if (xgene_enet_errata_10GE_8(skb, datalen, status)) {
 725                         pdata->false_rflr++;
 726                 } else if (xgene_enet_errata_10GE_10(skb, datalen, status)) {
 727                         pdata->vlan_rjbr++;
 728                 } else {
 729                         dev_kfree_skb_any(skb);
 730                         xgene_enet_free_pagepool(page_pool, raw_desc, exp_desc);
 731                         xgene_enet_parse_error(rx_ring, status);
 732                         rx_ring->rx_dropped++;
 733                         goto out;
 734                 }
 735         }
 736
 737         if (!nv)
 738                 goto skip_jumbo;
 739
 740         slots = page_pool->slots - 1;
 741         head = page_pool->head;
 742         desc = (void *)exp_desc;
 743
 744         for (i = 0; i < 4; i++) {
 745                 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1]));
 746                 if (!frag_size)
 747                         break;
 748
 749                 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1]));
 750                 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
 751
 752                 page = page_pool->frag_page[head];
 753                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0,
 754                                 frag_size, PAGE_SIZE);
 755
 756                 datalen += frag_size;
 757
 758                 page_pool->frag_page[head] = NULL;
 759                 head = (head + 1) & slots;
 760         }
 761
 762         page_pool->head = head;
 763         rx_ring->npagepool -= skb_shinfo(skb)->nr_frags;
 764
 765 skip_jumbo:
 766         skb_checksum_none_assert(skb);
 767         xgene_enet_rx_csum(skb);
 768
 769         rx_ring->rx_packets++;
 770         rx_ring->rx_bytes += datalen;
 771         napi_gro_receive(&rx_ring->napi, skb);
 772
 773 out:
 774         if (rx_ring->npagepool <= 0) {
 775                 ret = xgene_enet_refill_pagepool(page_pool, NUM_NXTBUFPOOL);
 776                 rx_ring->npagepool = NUM_NXTBUFPOOL;
 777                 if (ret)
 778                         return ret;
 779         }
 780
 781         if (--rx_ring->nbufpool == 0) {
 782                 ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL);
 783                 rx_ring->nbufpool = NUM_BUFPOOL;
 784         }
 785
 786         return ret;
 787 }
 788
 789 static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc)
 790 {
 791         return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false;
 792 }
 793
 794 static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
 795                                    int budget)
 796 {
 797         struct net_device *ndev = ring->ndev;
 798         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
 799         struct xgene_enet_raw_desc *raw_desc, *exp_desc;
 800         u16 head = ring->head;
 801         u16 slots = ring->slots - 1;
 802         int ret, desc_count, count = 0, processed = 0;
 803         bool is_completion;
 804
 805         do {
 806                 raw_desc = &ring->raw_desc[head];
 807                 desc_count = 0;
 808                 is_completion = false;
 809                 exp_desc = NULL;
 810                 if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc)))
 811                         break;
 812
 813                 /* read fpqnum field after dataaddr field */
 814                 dma_rmb();
 815                 if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) {
 816                         head = (head + 1) & slots;
 817                         exp_desc = &ring->raw_desc[head];
 818
 819                         if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) {
 820                                 head = (head - 1) & slots;
 821                                 break;
 822                         }
 823                         dma_rmb();
 824                         count++;
 825                         desc_count++;
 826                 }
 827                 if (is_rx_desc(raw_desc)) {
 828                         ret = xgene_enet_rx_frame(ring, raw_desc, exp_desc);
 829                 } else {
 830                         ret = xgene_enet_tx_completion(ring, raw_desc);
 831                         is_completion = true;
 832                 }
 833                 xgene_enet_mark_desc_slot_empty(raw_desc);
 834                 if (exp_desc)
 835                         xgene_enet_mark_desc_slot_empty(exp_desc);
 836
 837                 head = (head + 1) & slots;
 838                 count++;
 839                 desc_count++;
 840                 processed++;
 841                 if (is_completion)
 842                         pdata->txc_level[ring->index] += desc_count;
 843
 844                 if (ret)
 845                         break;
 846         } while (--budget);
 847
 848         if (likely(count)) {
 849                 pdata->ring_ops->wr_cmd(ring, -count);
 850                 ring->head = head;
 851
 852                 if (__netif_subqueue_stopped(ndev, ring->index))
 853                         netif_start_subqueue(ndev, ring->index);
 854         }
 855
 856         return processed;
 857 }
 858
 859 static int xgene_enet_napi(struct napi_struct *napi, const int budget)
 860 {
 861         struct xgene_enet_desc_ring *ring;
 862         int processed;
 863
 864         ring = container_of(napi, struct xgene_enet_desc_ring, napi);
 865         processed = xgene_enet_process_ring(ring, budget);
 866
 867         if (processed != budget) {
 868                 napi_complete_done(napi, processed);
 869                 enable_irq(ring->irq);
 870         }
 871
 872         return processed;
 873 }
 874
 875 static void xgene_enet_timeout(struct net_device *ndev)
 876 {
 877         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
 878         struct netdev_queue *txq;
 879         int i;
 880
 881         pdata->mac_ops->reset(pdata);
 882
 883         for (i = 0; i < pdata->txq_cnt; i++) {
 884                 txq = netdev_get_tx_queue(ndev, i);
 885                 txq->trans_start = jiffies;
 886                 netif_tx_start_queue(txq);
 887         }
 888 }
 889
 890 static void xgene_enet_set_irq_name(struct net_device *ndev)
 891 {
 892         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
 893         struct xgene_enet_desc_ring *ring;
 894         int i;
 895
 896         for (i = 0; i < pdata->rxq_cnt; i++) {
 897                 ring = pdata->rx_ring[i];
 898                 if (!pdata->cq_cnt) {
 899                         snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc",
 900                                  ndev->name);
 901                 } else {
 902                         snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-%d",
 903                                  ndev->name, i);
 904                 }
 905         }
 906
 907         for (i = 0; i < pdata->cq_cnt; i++) {
 908                 ring = pdata->tx_ring[i]->cp_ring;
 909                 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-txc-%d",
 910                          ndev->name, i);
 911         }
 912 }
 913
 914 static int xgene_enet_register_irq(struct net_device *ndev)
 915 {
 916         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
 917         struct device *dev = ndev_to_dev(ndev);
 918         struct xgene_enet_desc_ring *ring;
 919         int ret = 0, i;
 920
 921         xgene_enet_set_irq_name(ndev);
 922         for (i = 0; i < pdata->rxq_cnt; i++) {
 923                 ring = pdata->rx_ring[i];
 924                 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
 925                 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
 926                                        0, ring->irq_name, ring);
 927                 if (ret) {
 928                         netdev_err(ndev, "Failed to request irq %s\n",
 929                                    ring->irq_name);
 930                 }
 931         }
 932
 933         for (i = 0; i < pdata->cq_cnt; i++) {
 934                 ring = pdata->tx_ring[i]->cp_ring;
 935                 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
 936                 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
 937                                        0, ring->irq_name, ring);
 938                 if (ret) {
 939                         netdev_err(ndev, "Failed to request irq %s\n",
 940                                    ring->irq_name);
 941                 }
 942         }
 943
 944         return ret;
 945 }
 946
 947 static void xgene_enet_free_irq(struct net_device *ndev)
 948 {
 949         struct xgene_enet_pdata *pdata;
 950         struct xgene_enet_desc_ring *ring;
 951         struct device *dev;
 952         int i;
 953
 954         pdata = netdev_priv(ndev);
 955         dev = ndev_to_dev(ndev);
 956
 957         for (i = 0; i < pdata->rxq_cnt; i++) {
 958                 ring = pdata->rx_ring[i];
 959                 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
 960                 devm_free_irq(dev, ring->irq, ring);
 961         }
 962
 963         for (i = 0; i < pdata->cq_cnt; i++) {
 964                 ring = pdata->tx_ring[i]->cp_ring;
 965                 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
 966                 devm_free_irq(dev, ring->irq, ring);
 967         }
 968 }
 969
 970 static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata)
 971 {
 972         struct napi_struct *napi;
 973         int i;
 974
 975         for (i = 0; i < pdata->rxq_cnt; i++) {
 976                 napi = &pdata->rx_ring[i]->napi;
 977                 napi_enable(napi);
 978         }
 979
 980         for (i = 0; i < pdata->cq_cnt; i++) {
 981                 napi = &pdata->tx_ring[i]->cp_ring->napi;
 982                 napi_enable(napi);
 983         }
 984 }
 985
 986 static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata)
 987 {
 988         struct napi_struct *napi;
 989         int i;
 990
 991         for (i = 0; i < pdata->rxq_cnt; i++) {
 992                 napi = &pdata->rx_ring[i]->napi;
 993                 napi_disable(napi);
 994         }
 995
 996         for (i = 0; i < pdata->cq_cnt; i++) {
 997                 napi = &pdata->tx_ring[i]->cp_ring->napi;
 998                 napi_disable(napi);
 999         }
1000 }
1001
1002 static int xgene_enet_open(struct net_device *ndev)
1003 {
1004         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1005         const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
1006         int ret;
1007
1008         ret = netif_set_real_num_tx_queues(ndev, pdata->txq_cnt);
1009         if (ret)
1010                 return ret;
1011
1012         ret = netif_set_real_num_rx_queues(ndev, pdata->rxq_cnt);
1013         if (ret)
1014                 return ret;
1015
1016         xgene_enet_napi_enable(pdata);
1017         ret = xgene_enet_register_irq(ndev);
1018         if (ret)
1019                 return ret;
1020
1021         if (ndev->phydev) {
1022                 phy_start(ndev->phydev);
1023         } else {
1024                 schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF);
1025                 netif_carrier_off(ndev);
1026         }
1027
1028         mac_ops->tx_enable(pdata);
1029         mac_ops->rx_enable(pdata);
1030         netif_tx_start_all_queues(ndev);
1031
1032         return ret;
1033 }
1034
1035 static int xgene_enet_close(struct net_device *ndev)
1036 {
1037         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1038         const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
1039         int i;
1040
1041         netif_tx_stop_all_queues(ndev);
1042         mac_ops->tx_disable(pdata);
1043         mac_ops->rx_disable(pdata);
1044
1045         if (ndev->phydev)
1046                 phy_stop(ndev->phydev);
1047         else
1048                 cancel_delayed_work_sync(&pdata->link_work);
1049
1050         xgene_enet_free_irq(ndev);
1051         xgene_enet_napi_disable(pdata);
1052         for (i = 0; i < pdata->rxq_cnt; i++)
1053                 xgene_enet_process_ring(pdata->rx_ring[i], -1);
1054
1055         return 0;
1056 }
1057 static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring)
1058 {
1059         struct xgene_enet_pdata *pdata;
1060         struct device *dev;
1061
1062         pdata = netdev_priv(ring->ndev);
1063         dev = ndev_to_dev(ring->ndev);
1064
1065         pdata->ring_ops->clear(ring);
1066         dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
1067 }
1068
1069 static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata)
1070 {
1071         struct xgene_enet_desc_ring *buf_pool, *page_pool;
1072         struct xgene_enet_desc_ring *ring;
1073         int i;
1074
1075         for (i = 0; i < pdata->txq_cnt; i++) {
1076                 ring = pdata->tx_ring[i];
1077                 if (ring) {
1078                         xgene_enet_delete_ring(ring);
1079                         pdata->port_ops->clear(pdata, ring);
1080                         if (pdata->cq_cnt)
1081                                 xgene_enet_delete_ring(ring->cp_ring);
1082                         pdata->tx_ring[i] = NULL;
1083                 }
1084
1085         }
1086
1087         for (i = 0; i < pdata->rxq_cnt; i++) {
1088                 ring = pdata->rx_ring[i];
1089                 if (ring) {
1090                         page_pool = ring->page_pool;
1091                         if (page_pool) {
1092                                 xgene_enet_delete_pagepool(page_pool);
1093                                 xgene_enet_delete_ring(page_pool);
1094                                 pdata->port_ops->clear(pdata, page_pool);
1095                         }
1096
1097                         buf_pool = ring->buf_pool;
1098                         xgene_enet_delete_bufpool(buf_pool);
1099                         xgene_enet_delete_ring(buf_pool);
1100                         pdata->port_ops->clear(pdata, buf_pool);
1101
1102                         xgene_enet_delete_ring(ring);
1103                         pdata->rx_ring[i] = NULL;
1104                 }
1105
1106         }
1107 }
1108
1109 static int xgene_enet_get_ring_size(struct device *dev,
1110                                     enum xgene_enet_ring_cfgsize cfgsize)
1111 {
1112         int size = -EINVAL;
1113
1114         switch (cfgsize) {
1115         case RING_CFGSIZE_512B:
1116                 size = 0x200;
1117                 break;
1118         case RING_CFGSIZE_2KB:
1119                 size = 0x800;
1120                 break;
1121         case RING_CFGSIZE_16KB:
1122                 size = 0x4000;
1123                 break;
1124         case RING_CFGSIZE_64KB:
1125                 size = 0x10000;
1126                 break;
1127         case RING_CFGSIZE_512KB:
1128                 size = 0x80000;
1129                 break;
1130         default:
1131                 dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize);
1132                 break;
1133         }
1134
1135         return size;
1136 }
1137
1138 static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring)
1139 {
1140         struct xgene_enet_pdata *pdata;
1141         struct device *dev;
1142
1143         if (!ring)
1144                 return;
1145
1146         dev = ndev_to_dev(ring->ndev);
1147         pdata = netdev_priv(ring->ndev);
1148
1149         if (ring->desc_addr) {
1150                 pdata->ring_ops->clear(ring);
1151                 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
1152         }
1153         devm_kfree(dev, ring);
1154 }
1155
1156 static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata)
1157 {
1158         struct xgene_enet_desc_ring *page_pool;
1159         struct device *dev = &pdata->pdev->dev;
1160         struct xgene_enet_desc_ring *ring;
1161         void *p;
1162         int i;
1163
1164         for (i = 0; i < pdata->txq_cnt; i++) {
1165                 ring = pdata->tx_ring[i];
1166                 if (ring) {
1167                         if (ring->cp_ring && ring->cp_ring->cp_skb)
1168                                 devm_kfree(dev, ring->cp_ring->cp_skb);
1169
1170                         if (ring->cp_ring && pdata->cq_cnt)
1171                                 xgene_enet_free_desc_ring(ring->cp_ring);
1172
1173                         xgene_enet_free_desc_ring(ring);
1174                 }
1175
1176         }
1177
1178         for (i = 0; i < pdata->rxq_cnt; i++) {
1179                 ring = pdata->rx_ring[i];
1180                 if (ring) {
1181                         if (ring->buf_pool) {
1182                                 if (ring->buf_pool->rx_skb)
1183                                         devm_kfree(dev, ring->buf_pool->rx_skb);
1184
1185                                 xgene_enet_free_desc_ring(ring->buf_pool);
1186                         }
1187
1188                         page_pool = ring->page_pool;
1189                         if (page_pool) {
1190                                 p = page_pool->frag_page;
1191                                 if (p)
1192                                         devm_kfree(dev, p);
1193
1194                                 p = page_pool->frag_dma_addr;
1195                                 if (p)
1196                                         devm_kfree(dev, p);
1197                         }
1198
1199                         xgene_enet_free_desc_ring(ring);
1200                 }
1201         }
1202 }
1203
1204 static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata,
1205                                  struct xgene_enet_desc_ring *ring)
1206 {
1207         if ((pdata->enet_id == XGENE_ENET2) &&
1208             (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) {
1209                 return true;
1210         }
1211
1212         return false;
1213 }
1214
1215 static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata,
1216                                               struct xgene_enet_desc_ring *ring)
1217 {
1218         u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift;
1219
1220         return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift);
1221 }
1222
1223 static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
1224                         struct net_device *ndev, u32 ring_num,
1225                         enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id)
1226 {
1227         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1228         struct device *dev = ndev_to_dev(ndev);
1229         struct xgene_enet_desc_ring *ring;
1230         void *irq_mbox_addr;
1231         int size;
1232
1233         size = xgene_enet_get_ring_size(dev, cfgsize);
1234         if (size < 0)
1235                 return NULL;
1236
1237         ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring),
1238                             GFP_KERNEL);
1239         if (!ring)
1240                 return NULL;
1241
1242         ring->ndev = ndev;
1243         ring->num = ring_num;
1244         ring->cfgsize = cfgsize;
1245         ring->id = ring_id;
1246
1247         ring->desc_addr = dmam_alloc_coherent(dev, size, &ring->dma,
1248                                               GFP_KERNEL | __GFP_ZERO);
1249         if (!ring->desc_addr) {
1250                 devm_kfree(dev, ring);
1251                 return NULL;
1252         }
1253         ring->size = size;
1254
1255         if (is_irq_mbox_required(pdata, ring)) {
1256                 irq_mbox_addr = dmam_alloc_coherent(dev, INTR_MBOX_SIZE,
1257                                                     &ring->irq_mbox_dma,
1258                                                     GFP_KERNEL | __GFP_ZERO);
1259                 if (!irq_mbox_addr) {
1260                         dmam_free_coherent(dev, size, ring->desc_addr,
1261                                            ring->dma);
1262                         devm_kfree(dev, ring);
1263                         return NULL;
1264                 }
1265                 ring->irq_mbox_addr = irq_mbox_addr;
1266         }
1267
1268         ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring);
1269         ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
1270         ring = pdata->ring_ops->setup(ring);
1271         netdev_dbg(ndev, "ring info: num=%d  size=%d  id=%d  slots=%d\n",
1272                    ring->num, ring->size, ring->id, ring->slots);
1273
1274         return ring;
1275 }
1276
1277 static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum)
1278 {
1279         return (owner << 6) | (bufnum & GENMASK(5, 0));
1280 }
1281
1282 static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p)
1283 {
1284         enum xgene_ring_owner owner;
1285
1286         if (p->enet_id == XGENE_ENET1) {
1287                 switch (p->phy_mode) {
1288                 case PHY_INTERFACE_MODE_SGMII:
1289                         owner = RING_OWNER_ETH0;
1290                         break;
1291                 default:
1292                         owner = (!p->port_id) ? RING_OWNER_ETH0 :
1293                                                 RING_OWNER_ETH1;
1294                         break;
1295                 }
1296         } else {
1297                 owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1;
1298         }
1299
1300         return owner;
1301 }
1302
1303 static u8 xgene_start_cpu_bufnum(struct xgene_enet_pdata *pdata)
1304 {
1305         struct device *dev = &pdata->pdev->dev;
1306         u32 cpu_bufnum;
1307         int ret;
1308
1309         ret = device_property_read_u32(dev, "channel", &cpu_bufnum);
1310
1311         return (!ret) ? cpu_bufnum : pdata->cpu_bufnum;
1312 }
1313
1314 static int xgene_enet_create_desc_rings(struct net_device *ndev)
1315 {
1316         struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
1317         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1318         struct xgene_enet_desc_ring *page_pool = NULL;
1319         struct xgene_enet_desc_ring *buf_pool = NULL;
1320         struct device *dev = ndev_to_dev(ndev);
1321         u8 eth_bufnum = pdata->eth_bufnum;
1322         u8 bp_bufnum = pdata->bp_bufnum;
1323         u16 ring_num = pdata->ring_num;
1324         enum xgene_ring_owner owner;
1325         dma_addr_t dma_exp_bufs;
1326         u16 ring_id, slots;
1327         __le64 *exp_bufs;
1328         int i, ret, size;
1329         u8 cpu_bufnum;
1330
1331         cpu_bufnum = xgene_start_cpu_bufnum(pdata);
1332
1333         for (i = 0; i < pdata->rxq_cnt; i++) {
1334                 /* allocate rx descriptor ring */
1335                 owner = xgene_derive_ring_owner(pdata);
1336                 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
1337                 rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1338                                                       RING_CFGSIZE_16KB,
1339                                                       ring_id);
1340                 if (!rx_ring) {
1341                         ret = -ENOMEM;
1342                         goto err;
1343                 }
1344
1345                 /* allocate buffer pool for receiving packets */
1346                 owner = xgene_derive_ring_owner(pdata);
1347                 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
1348                 buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
1349                                                        RING_CFGSIZE_16KB,
1350                                                        ring_id);
1351                 if (!buf_pool) {
1352                         ret = -ENOMEM;
1353                         goto err;
1354                 }
1355
1356                 rx_ring->nbufpool = NUM_BUFPOOL;
1357                 rx_ring->npagepool = NUM_NXTBUFPOOL;
1358                 rx_ring->irq = pdata->irqs[i];
1359                 buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots,
1360                                                 sizeof(struct sk_buff *),
1361                                                 GFP_KERNEL);
1362                 if (!buf_pool->rx_skb) {
1363                         ret = -ENOMEM;
1364                         goto err;
1365                 }
1366
1367                 buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool);
1368                 rx_ring->buf_pool = buf_pool;
1369                 pdata->rx_ring[i] = rx_ring;
1370
1371                 if ((pdata->enet_id == XGENE_ENET1 &&  pdata->rxq_cnt > 4) ||
1372                     (pdata->enet_id == XGENE_ENET2 &&  pdata->rxq_cnt > 16)) {
1373                         break;
1374                 }
1375
1376                 /* allocate next buffer pool for jumbo packets */
1377                 owner = xgene_derive_ring_owner(pdata);
1378                 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
1379                 page_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
1380                                                         RING_CFGSIZE_16KB,
1381                                                         ring_id);
1382                 if (!page_pool) {
1383                         ret = -ENOMEM;
1384                         goto err;
1385                 }
1386
1387                 slots = page_pool->slots;
1388                 page_pool->frag_page = devm_kcalloc(dev, slots,
1389                                                     sizeof(struct page *),
1390                                                     GFP_KERNEL);
1391                 if (!page_pool->frag_page) {
1392                         ret = -ENOMEM;
1393                         goto err;
1394                 }
1395
1396                 page_pool->frag_dma_addr = devm_kcalloc(dev, slots,
1397                                                         sizeof(dma_addr_t),
1398                                                         GFP_KERNEL);
1399                 if (!page_pool->frag_dma_addr) {
1400                         ret = -ENOMEM;
1401                         goto err;
1402                 }
1403
1404                 page_pool->dst_ring_num = xgene_enet_dst_ring_num(page_pool);
1405                 rx_ring->page_pool = page_pool;
1406         }
1407
1408         for (i = 0; i < pdata->txq_cnt; i++) {
1409                 /* allocate tx descriptor ring */
1410                 owner = xgene_derive_ring_owner(pdata);
1411                 ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++);
1412                 tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1413                                                       RING_CFGSIZE_16KB,
1414                                                       ring_id);
1415                 if (!tx_ring) {
1416                         ret = -ENOMEM;
1417                         goto err;
1418                 }
1419
1420                 size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS;
1421                 exp_bufs = dmam_alloc_coherent(dev, size, &dma_exp_bufs,
1422                                                GFP_KERNEL | __GFP_ZERO);
1423                 if (!exp_bufs) {
1424                         ret = -ENOMEM;
1425                         goto err;
1426                 }
1427                 tx_ring->exp_bufs = exp_bufs;
1428
1429                 pdata->tx_ring[i] = tx_ring;
1430
1431                 if (!pdata->cq_cnt) {
1432                         cp_ring = pdata->rx_ring[i];
1433                 } else {
1434                         /* allocate tx completion descriptor ring */
1435                         ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU,
1436                                                          cpu_bufnum++);
1437                         cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1438                                                               RING_CFGSIZE_16KB,
1439                                                               ring_id);
1440                         if (!cp_ring) {
1441                                 ret = -ENOMEM;
1442                                 goto err;
1443                         }
1444
1445                         cp_ring->irq = pdata->irqs[pdata->rxq_cnt + i];
1446                         cp_ring->index = i;
1447                 }
1448
1449                 cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots,
1450                                                sizeof(struct sk_buff *),
1451                                                GFP_KERNEL);
1452                 if (!cp_ring->cp_skb) {
1453                         ret = -ENOMEM;
1454                         goto err;
1455                 }
1456
1457                 size = sizeof(dma_addr_t) * MAX_SKB_FRAGS;
1458                 cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots,
1459                                                       size, GFP_KERNEL);
1460                 if (!cp_ring->frag_dma_addr) {
1461                         devm_kfree(dev, cp_ring->cp_skb);
1462                         ret = -ENOMEM;
1463                         goto err;
1464                 }
1465
1466                 tx_ring->cp_ring = cp_ring;
1467                 tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring);
1468         }
1469
1470         if (pdata->ring_ops->coalesce)
1471                 pdata->ring_ops->coalesce(pdata->tx_ring[0]);
1472         pdata->tx_qcnt_hi = pdata->tx_ring[0]->slots - 128;
1473
1474         return 0;
1475
1476 err:
1477         xgene_enet_free_desc_rings(pdata);
1478         return ret;
1479 }
1480
1481 static void xgene_enet_get_stats64(
1482                         struct net_device *ndev,
1483                         struct rtnl_link_stats64 *stats)
1484 {
1485         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1486         struct xgene_enet_desc_ring *ring;
1487         int i;
1488
1489         for (i = 0; i < pdata->txq_cnt; i++) {
1490                 ring = pdata->tx_ring[i];
1491                 if (ring) {
1492                         stats->tx_packets += ring->tx_packets;
1493                         stats->tx_bytes += ring->tx_bytes;
1494                         stats->tx_dropped += ring->tx_dropped;
1495                         stats->tx_errors += ring->tx_errors;
1496                 }
1497         }
1498
1499         for (i = 0; i < pdata->rxq_cnt; i++) {
1500                 ring = pdata->rx_ring[i];
1501                 if (ring) {
1502                         stats->rx_packets += ring->rx_packets;
1503                         stats->rx_bytes += ring->rx_bytes;
1504                         stats->rx_dropped += ring->rx_dropped;
1505                         stats->rx_errors += ring->rx_errors +
1506                                 ring->rx_length_errors +
1507                                 ring->rx_crc_errors +
1508                                 ring->rx_frame_errors +
1509                                 ring->rx_fifo_errors;
1510                         stats->rx_length_errors += ring->rx_length_errors;
1511                         stats->rx_crc_errors += ring->rx_crc_errors;
1512                         stats->rx_frame_errors += ring->rx_frame_errors;
1513                         stats->rx_fifo_errors += ring->rx_fifo_errors;
1514                 }
1515         }
1516 }
1517
1518 static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr)
1519 {
1520         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1521         int ret;
1522
1523         ret = eth_mac_addr(ndev, addr);
1524         if (ret)
1525                 return ret;
1526         pdata->mac_ops->set_mac_addr(pdata);
1527
1528         return ret;
1529 }
1530
1531 static int xgene_change_mtu(struct net_device *ndev, int new_mtu)
1532 {
1533         struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1534         int frame_size;
1535
1536         if (!netif_running(ndev))
1537                 return 0;
1538
1539         frame_size = (new_mtu > ETH_DATA_LEN) ? (new_mtu + 18) : 0x600;
1540
1541         xgene_enet_close(ndev);
1542         ndev->mtu = new_mtu;
1543         pdata->mac_ops->set_framesize(pdata, frame_size);
1544         xgene_enet_open(ndev);
1545
1546         return 0;
1547 }
1548
1549 static const struct net_device_ops xgene_ndev_ops = {
1550         .ndo_open = xgene_enet_open,
1551         .ndo_stop = xgene_enet_close,
1552         .ndo_start_xmit = xgene_enet_start_xmit,
1553         .ndo_tx_timeout = xgene_enet_timeout,
1554         .ndo_get_stats64 = xgene_enet_get_stats64,
1555         .ndo_change_mtu = xgene_change_mtu,
1556         .ndo_set_mac_address = xgene_enet_set_mac_address,
1557 };
1558
1559 #ifdef CONFIG_ACPI
1560 static void xgene_get_port_id_acpi(struct device *dev,
1561                                   struct xgene_enet_pdata *pdata)
1562 {
1563         acpi_status status;
1564         u64 temp;
1565
1566         status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp);
1567         if (ACPI_FAILURE(status)) {
1568                 pdata->port_id = 0;
1569         } else {
1570                 pdata->port_id = temp;
1571         }
1572
1573         return;
1574 }
1575 #endif
1576
1577 static void xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata)
1578 {
1579         u32 id = 0;
1580
1581         of_property_read_u32(dev->of_node, "port-id", &id);
1582
1583         pdata->port_id = id & BIT(0);
1584
1585         return;
1586 }
1587
1588 static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata)
1589 {
1590         struct device *dev = &pdata->pdev->dev;
1591         int delay, ret;
1592
1593         ret = device_property_read_u32(dev, "tx-delay", &delay);
1594         if (ret) {
1595                 pdata->tx_delay = 4;
1596                 return 0;
1597         }
1598
1599         if (delay < 0 || delay > 7) {
1600                 dev_err(dev, "Invalid tx-delay specified\n");
1601                 return -EINVAL;
1602         }
1603
1604         pdata->tx_delay = delay;
1605
1606         return 0;
1607 }
1608
1609 static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata)
1610 {
1611         struct device *dev = &pdata->pdev->dev;
1612         int delay, ret;
1613
1614         ret = device_property_read_u32(dev, "rx-delay", &delay);
1615         if (ret) {
1616                 pdata->rx_delay = 2;
1617                 return 0;
1618         }
1619
1620         if (delay < 0 || delay > 7) {
1621                 dev_err(dev, "Invalid rx-delay specified\n");
1622                 return -EINVAL;
1623         }
1624
1625         pdata->rx_delay = delay;
1626
1627         return 0;
1628 }
1629
1630 static int xgene_enet_get_irqs(struct xgene_enet_pdata *pdata)
1631 {
1632         struct platform_device *pdev = pdata->pdev;
1633         struct device *dev = &pdev->dev;
1634         int i, ret, max_irqs;
1635
1636         if (phy_interface_mode_is_rgmii(pdata->phy_mode))
1637                 max_irqs = 1;
1638         else if (pdata->phy_mode == PHY_INTERFACE_MODE_SGMII)
1639                 max_irqs = 2;
1640         else
1641                 max_irqs = XGENE_MAX_ENET_IRQ;
1642
1643         for (i = 0; i < max_irqs; i++) {
1644                 ret = platform_get_irq(pdev, i);
1645                 if (ret <= 0) {
1646                         if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1647                                 max_irqs = i;
1648                                 pdata->rxq_cnt = max_irqs / 2;
1649                                 pdata->txq_cnt = max_irqs / 2;
1650                                 pdata->cq_cnt = max_irqs / 2;
1651                                 break;
1652                         }
1653                         dev_err(dev, "Unable to get ENET IRQ\n");
1654                         ret = ret ? : -ENXIO;
1655                         return ret;
1656                 }
1657                 pdata->irqs[i] = ret;
1658         }
1659
1660         return 0;
1661 }
1662
1663 static void xgene_enet_check_phy_handle(struct xgene_enet_pdata *pdata)
1664 {
1665         int ret;
1666
1667         if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII)
1668                 return;
1669
1670         if (!IS_ENABLED(CONFIG_MDIO_XGENE))
1671                 return;
1672
1673         ret = xgene_enet_phy_connect(pdata->ndev);
1674         if (!ret)
1675                 pdata->mdio_driver = true;
1676 }
1677
1678 static void xgene_enet_gpiod_get(struct xgene_enet_pdata *pdata)
1679 {
1680         struct device *dev = &pdata->pdev->dev;
1681
1682         pdata->sfp_gpio_en = false;
1683         if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII ||
1684             (!device_property_present(dev, "sfp-gpios") &&
1685              !device_property_present(dev, "rxlos-gpios")))
1686                 return;
1687
1688         pdata->sfp_gpio_en = true;
1689         pdata->sfp_rdy = gpiod_get(dev, "rxlos", GPIOD_IN);
1690         if (IS_ERR(pdata->sfp_rdy))
1691                 pdata->sfp_rdy = gpiod_get(dev, "sfp", GPIOD_IN);
1692 }
1693
1694 static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
1695 {
1696         struct platform_device *pdev;
1697         struct net_device *ndev;
1698         struct device *dev;
1699         struct resource *res;
1700         void __iomem *base_addr;
1701         u32 offset;
1702         int ret = 0;
1703
1704         pdev = pdata->pdev;
1705         dev = &pdev->dev;
1706         ndev = pdata->ndev;
1707
1708         res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR);
1709         if (!res) {
1710                 dev_err(dev, "Resource enet_csr not defined\n");
1711                 return -ENODEV;
1712         }
1713         pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res));
1714         if (!pdata->base_addr) {
1715                 dev_err(dev, "Unable to retrieve ENET Port CSR region\n");
1716                 return -ENOMEM;
1717         }
1718
1719         res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR);
1720         if (!res) {
1721                 dev_err(dev, "Resource ring_csr not defined\n");
1722                 return -ENODEV;
1723         }
1724         pdata->ring_csr_addr = devm_ioremap(dev, res->start,
1725                                                         resource_size(res));
1726         if (!pdata->ring_csr_addr) {
1727                 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n");
1728                 return -ENOMEM;
1729         }
1730
1731         res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD);
1732         if (!res) {
1733                 dev_err(dev, "Resource ring_cmd not defined\n");
1734                 return -ENODEV;
1735         }
1736         pdata->ring_cmd_addr = devm_ioremap(dev, res->start,
1737                                                         resource_size(res));
1738         if (!pdata->ring_cmd_addr) {
1739                 dev_err(dev, "Unable to retrieve ENET Ring command region\n");
1740                 return -ENOMEM;
1741         }
1742
1743         if (dev->of_node)
1744                 xgene_get_port_id_dt(dev, pdata);
1745 #ifdef CONFIG_ACPI
1746         else
1747                 xgene_get_port_id_acpi(dev, pdata);
1748 #endif
1749
1750         if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN))
1751                 eth_hw_addr_random(ndev);
1752
1753         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
1754
1755         pdata->phy_mode = device_get_phy_mode(dev);
1756         if (pdata->phy_mode < 0) {
1757                 dev_err(dev, "Unable to get phy-connection-type\n");
1758                 return pdata->phy_mode;
1759         }
1760         if (!phy_interface_mode_is_rgmii(pdata->phy_mode) &&
1761             pdata->phy_mode != PHY_INTERFACE_MODE_SGMII &&
1762             pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
1763                 dev_err(dev, "Incorrect phy-connection-type specified\n");
1764                 return -ENODEV;
1765         }
1766
1767         ret = xgene_get_tx_delay(pdata);
1768         if (ret)
1769                 return ret;
1770
1771         ret = xgene_get_rx_delay(pdata);
1772         if (ret)
1773                 return ret;
1774
1775         ret = xgene_enet_get_irqs(pdata);
1776         if (ret)
1777                 return ret;
1778
1779         xgene_enet_gpiod_get(pdata);
1780
1781         pdata->clk = devm_clk_get(&pdev->dev, NULL);
1782         if (IS_ERR(pdata->clk)) {
1783                 if (pdata->phy_mode != PHY_INTERFACE_MODE_SGMII) {
1784                         /* Abort if the clock is defined but couldn't be
1785                          * retrived. Always abort if the clock is missing on
1786                          * DT system as the driver can't cope with this case.
1787                          */
1788                         if (PTR_ERR(pdata->clk) != -ENOENT || dev->of_node)
1789                                 return PTR_ERR(pdata->clk);
1790                         /* Firmware may have set up the clock already. */
1791                         dev_info(dev, "clocks have been setup already\n");
1792                 }
1793         }
1794
1795         if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII)
1796                 base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET);
1797         else
1798                 base_addr = pdata->base_addr;
1799         pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
1800         pdata->cle.base = base_addr + BLOCK_ETH_CLE_CSR_OFFSET;
1801         pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
1802         pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
1803         if (phy_interface_mode_is_rgmii(pdata->phy_mode) ||
1804             pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) {
1805                 pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET;
1806                 pdata->mcx_stats_addr =
1807                         pdata->base_addr + BLOCK_ETH_STATS_OFFSET;
1808                 offset = (pdata->enet_id == XGENE_ENET1) ?
1809                           BLOCK_ETH_MAC_CSR_OFFSET :
1810                           X2_BLOCK_ETH_MAC_CSR_OFFSET;
1811                 pdata->mcx_mac_csr_addr = base_addr + offset;
1812         } else {
1813                 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
1814                 pdata->mcx_stats_addr = base_addr + BLOCK_AXG_STATS_OFFSET;
1815                 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
1816                 pdata->pcs_addr = base_addr + BLOCK_PCS_OFFSET;
1817         }
1818         pdata->rx_buff_cnt = NUM_PKT_BUF;
1819
1820         return 0;
1821 }
1822
1823 static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
1824 {
1825         struct xgene_enet_cle *enet_cle = &pdata->cle;
1826         struct xgene_enet_desc_ring *page_pool;
1827         struct net_device *ndev = pdata->ndev;
1828         struct xgene_enet_desc_ring *buf_pool;
1829         u16 dst_ring_num, ring_id;
1830         int i, ret;
1831         u32 count;
1832
1833         ret = pdata->port_ops->reset(pdata);
1834         if (ret)
1835                 return ret;
1836
1837         ret = xgene_enet_create_desc_rings(ndev);
1838         if (ret) {
1839                 netdev_err(ndev, "Error in ring configuration\n");
1840                 return ret;
1841         }
1842
1843         /* setup buffer pool */
1844         for (i = 0; i < pdata->rxq_cnt; i++) {
1845                 buf_pool = pdata->rx_ring[i]->buf_pool;
1846                 xgene_enet_init_bufpool(buf_pool);
1847                 page_pool = pdata->rx_ring[i]->page_pool;
1848                 xgene_enet_init_bufpool(page_pool);
1849
1850                 count = pdata->rx_buff_cnt;
1851                 ret = xgene_enet_refill_bufpool(buf_pool, count);
1852                 if (ret)
1853                         goto err;
1854
1855                 ret = xgene_enet_refill_pagepool(page_pool, count);
1856                 if (ret)
1857                         goto err;
1858
1859         }
1860
1861         dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
1862         buf_pool = pdata->rx_ring[0]->buf_pool;
1863         if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1864                 /* Initialize and Enable  PreClassifier Tree */
1865                 enet_cle->max_nodes = 512;
1866                 enet_cle->max_dbptrs = 1024;
1867                 enet_cle->parsers = 3;
1868                 enet_cle->active_parser = PARSER_ALL;
1869                 enet_cle->ptree.start_node = 0;
1870                 enet_cle->ptree.start_dbptr = 0;
1871                 enet_cle->jump_bytes = 8;
1872                 ret = pdata->cle_ops->cle_init(pdata);
1873                 if (ret) {
1874                         netdev_err(ndev, "Preclass Tree init error\n");
1875                         goto err;
1876                 }
1877
1878         } else {
1879                 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
1880                 buf_pool = pdata->rx_ring[0]->buf_pool;
1881                 page_pool = pdata->rx_ring[0]->page_pool;
1882                 ring_id = (page_pool) ? page_pool->id : 0;
1883                 pdata->port_ops->cle_bypass(pdata, dst_ring_num,
1884                                             buf_pool->id, ring_id);
1885         }
1886
1887         ndev->max_mtu = XGENE_ENET_MAX_MTU;
1888         pdata->phy_speed = SPEED_UNKNOWN;
1889         pdata->mac_ops->init(pdata);
1890
1891         return ret;
1892
1893 err:
1894         xgene_enet_delete_desc_rings(pdata);
1895         return ret;
1896 }
1897
1898 static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
1899 {
1900         switch (pdata->phy_mode) {
1901         case PHY_INTERFACE_MODE_RGMII:
1902         case PHY_INTERFACE_MODE_RGMII_ID:
1903         case PHY_INTERFACE_MODE_RGMII_RXID:
1904         case PHY_INTERFACE_MODE_RGMII_TXID:
1905                 pdata->mac_ops = &xgene_gmac_ops;
1906                 pdata->port_ops = &xgene_gport_ops;
1907                 pdata->rm = RM3;
1908                 pdata->rxq_cnt = 1;
1909                 pdata->txq_cnt = 1;
1910                 pdata->cq_cnt = 0;
1911                 break;
1912         case PHY_INTERFACE_MODE_SGMII:
1913                 pdata->mac_ops = &xgene_sgmac_ops;
1914                 pdata->port_ops = &xgene_sgport_ops;
1915                 pdata->rm = RM1;
1916                 pdata->rxq_cnt = 1;
1917                 pdata->txq_cnt = 1;
1918                 pdata->cq_cnt = 1;
1919                 break;
1920         default:
1921                 pdata->mac_ops = &xgene_xgmac_ops;
1922                 pdata->port_ops = &xgene_xgport_ops;
1923                 pdata->cle_ops = &xgene_cle3in_ops;
1924                 pdata->rm = RM0;
1925                 if (!pdata->rxq_cnt) {
1926                         pdata->rxq_cnt = XGENE_NUM_RX_RING;
1927                         pdata->txq_cnt = XGENE_NUM_TX_RING;
1928                         pdata->cq_cnt = XGENE_NUM_TXC_RING;
1929                 }
1930                 break;
1931         }
1932
1933         if (pdata->enet_id == XGENE_ENET1) {
1934                 switch (pdata->port_id) {
1935                 case 0:
1936                         if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1937                                 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1938                                 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1939                                 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1940                                 pdata->ring_num = START_RING_NUM_0;
1941                         } else {
1942                                 pdata->cpu_bufnum = START_CPU_BUFNUM_0;
1943                                 pdata->eth_bufnum = START_ETH_BUFNUM_0;
1944                                 pdata->bp_bufnum = START_BP_BUFNUM_0;
1945                                 pdata->ring_num = START_RING_NUM_0;
1946                         }
1947                         break;
1948                 case 1:
1949                         if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1950                                 pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1;
1951                                 pdata->eth_bufnum = XG_START_ETH_BUFNUM_1;
1952                                 pdata->bp_bufnum = XG_START_BP_BUFNUM_1;
1953                                 pdata->ring_num = XG_START_RING_NUM_1;
1954                         } else {
1955                                 pdata->cpu_bufnum = START_CPU_BUFNUM_1;
1956                                 pdata->eth_bufnum = START_ETH_BUFNUM_1;
1957                                 pdata->bp_bufnum = START_BP_BUFNUM_1;
1958                                 pdata->ring_num = START_RING_NUM_1;
1959                         }
1960                         break;
1961                 default:
1962                         break;
1963                 }
1964                 pdata->ring_ops = &xgene_ring1_ops;
1965         } else {
1966                 switch (pdata->port_id) {
1967                 case 0:
1968                         pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1969                         pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1970                         pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1971                         pdata->ring_num = X2_START_RING_NUM_0;
1972                         break;
1973                 case 1:
1974                         pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1;
1975                         pdata->eth_bufnum = X2_START_ETH_BUFNUM_1;
1976                         pdata->bp_bufnum = X2_START_BP_BUFNUM_1;
1977                         pdata->ring_num = X2_START_RING_NUM_1;
1978                         break;
1979                 default:
1980                         break;
1981                 }
1982                 pdata->rm = RM0;
1983                 pdata->ring_ops = &xgene_ring2_ops;
1984         }
1985 }
1986
1987 static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata)
1988 {
1989         struct napi_struct *napi;
1990         int i;
1991
1992         for (i = 0; i < pdata->rxq_cnt; i++) {
1993                 napi = &pdata->rx_ring[i]->napi;
1994                 netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
1995                                NAPI_POLL_WEIGHT);
1996         }
1997
1998         for (i = 0; i < pdata->cq_cnt; i++) {
1999                 napi = &pdata->tx_ring[i]->cp_ring->napi;
2000                 netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
2001                                NAPI_POLL_WEIGHT);
2002         }
2003 }
2004
2005 #ifdef CONFIG_ACPI
2006 static const struct acpi_device_id xgene_enet_acpi_match[] = {
2007         { "APMC0D05", XGENE_ENET1},
2008         { "APMC0D30", XGENE_ENET1},
2009         { "APMC0D31", XGENE_ENET1},
2010         { "APMC0D3F", XGENE_ENET1},
2011         { "APMC0D26", XGENE_ENET2},
2012         { "APMC0D25", XGENE_ENET2},
2013         { }
2014 };
2015 MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match);
2016 #endif
2017
2018 static const struct of_device_id xgene_enet_of_match[] = {
2019         {.compatible = "apm,xgene-enet",    .data = (void *)XGENE_ENET1},
2020         {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1},
2021         {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1},
2022         {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2},
2023         {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2},
2024         {},
2025 };
2026
2027 MODULE_DEVICE_TABLE(of, xgene_enet_of_match);
2028
2029 static int xgene_enet_probe(struct platform_device *pdev)
2030 {
2031         struct net_device *ndev;
2032         struct xgene_enet_pdata *pdata;
2033         struct device *dev = &pdev->dev;
2034         void (*link_state)(struct work_struct *);
2035         const struct of_device_id *of_id;
2036         int ret;
2037
2038         ndev = alloc_etherdev_mqs(sizeof(struct xgene_enet_pdata),
2039                                   XGENE_NUM_TX_RING, XGENE_NUM_RX_RING);
2040         if (!ndev)
2041                 return -ENOMEM;
2042
2043         pdata = netdev_priv(ndev);
2044
2045         pdata->pdev = pdev;
2046         pdata->ndev = ndev;
2047         SET_NETDEV_DEV(ndev, dev);
2048         platform_set_drvdata(pdev, pdata);
2049         ndev->netdev_ops = &xgene_ndev_ops;
2050         xgene_enet_set_ethtool_ops(ndev);
2051         ndev->features |= NETIF_F_IP_CSUM |
2052                           NETIF_F_GSO |
2053                           NETIF_F_GRO |
2054                           NETIF_F_SG;
2055
2056         of_id = of_match_device(xgene_enet_of_match, &pdev->dev);
2057         if (of_id) {
2058                 pdata->enet_id = (enum xgene_enet_id)of_id->data;
2059         }
2060 #ifdef CONFIG_ACPI
2061         else {
2062                 const struct acpi_device_id *acpi_id;
2063
2064                 acpi_id = acpi_match_device(xgene_enet_acpi_match, &pdev->dev);
2065                 if (acpi_id)
2066                         pdata->enet_id = (enum xgene_enet_id) acpi_id->driver_data;
2067         }
2068 #endif
2069         if (!pdata->enet_id) {
2070                 ret = -ENODEV;
2071                 goto err;
2072         }
2073
2074         ret = xgene_enet_get_resources(pdata);
2075         if (ret)
2076                 goto err;
2077
2078         xgene_enet_setup_ops(pdata);
2079         spin_lock_init(&pdata->mac_lock);
2080
2081         if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
2082                 ndev->features |= NETIF_F_TSO | NETIF_F_RXCSUM;
2083                 spin_lock_init(&pdata->mss_lock);
2084         }
2085         ndev->hw_features = ndev->features;
2086
2087         ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
2088         if (ret) {
2089                 netdev_err(ndev, "No usable DMA configuration\n");
2090                 goto err;
2091         }
2092
2093         xgene_enet_check_phy_handle(pdata);
2094
2095         ret = xgene_enet_init_hw(pdata);
2096         if (ret)
2097                 goto err2;
2098
2099         link_state = pdata->mac_ops->link_state;
2100         if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
2101                 INIT_DELAYED_WORK(&pdata->link_work, link_state);
2102         } else if (!pdata->mdio_driver) {
2103                 if (phy_interface_mode_is_rgmii(pdata->phy_mode))
2104                         ret = xgene_enet_mdio_config(pdata);
2105                 else
2106                         INIT_DELAYED_WORK(&pdata->link_work, link_state);
2107
2108                 if (ret)
2109                         goto err1;
2110         }
2111
2112         spin_lock_init(&pdata->stats_lock);
2113         ret = xgene_extd_stats_init(pdata);
2114         if (ret)
2115                 goto err1;
2116
2117         xgene_enet_napi_add(pdata);
2118         ret = register_netdev(ndev);
2119         if (ret) {
2120                 netdev_err(ndev, "Failed to register netdev\n");
2121                 goto err1;
2122         }
2123
2124         return 0;
2125
2126 err1:
2127         /*
2128          * If necessary, free_netdev() will call netif_napi_del() and undo
2129          * the effects of xgene_enet_napi_add()'s calls to netif_napi_add().
2130          */
2131
2132         xgene_enet_delete_desc_rings(pdata);
2133
2134 err2:
2135         if (pdata->mdio_driver)
2136                 xgene_enet_phy_disconnect(pdata);
2137         else if (phy_interface_mode_is_rgmii(pdata->phy_mode))
2138                 xgene_enet_mdio_remove(pdata);
2139 err:
2140         free_netdev(ndev);
2141         return ret;
2142 }
2143
2144 static int xgene_enet_remove(struct platform_device *pdev)
2145 {
2146         struct xgene_enet_pdata *pdata;
2147         struct net_device *ndev;
2148
2149         pdata = platform_get_drvdata(pdev);
2150         ndev = pdata->ndev;
2151
2152         rtnl_lock();
2153         if (netif_running(ndev))
2154                 dev_close(ndev);
2155         rtnl_unlock();
2156
2157         if (pdata->mdio_driver)
2158                 xgene_enet_phy_disconnect(pdata);
2159         else if (phy_interface_mode_is_rgmii(pdata->phy_mode))
2160                 xgene_enet_mdio_remove(pdata);
2161
2162         unregister_netdev(ndev);
2163         xgene_enet_delete_desc_rings(pdata);
2164         pdata->port_ops->shutdown(pdata);
2165         free_netdev(ndev);
2166
2167         return 0;
2168 }
2169
2170 static void xgene_enet_shutdown(struct platform_device *pdev)
2171 {
2172         struct xgene_enet_pdata *pdata;
2173
2174         pdata = platform_get_drvdata(pdev);
2175         if (!pdata)
2176                 return;
2177
2178         if (!pdata->ndev)
2179                 return;
2180
2181         xgene_enet_remove(pdev);
2182 }
2183
2184 static struct platform_driver xgene_enet_driver = {
2185         .driver = {
2186                    .name = "xgene-enet",
2187                    .of_match_table = of_match_ptr(xgene_enet_of_match),
2188                    .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match),
2189         },
2190         .probe = xgene_enet_probe,
2191         .remove = xgene_enet_remove,
2192         .shutdown = xgene_enet_shutdown,
2193 };
2194
2195 module_platform_driver(xgene_enet_driver);
2196
2197 MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver");
2198 MODULE_VERSION(XGENE_DRV_VERSION);
2199 MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
2200 MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>");
2201 MODULE_LICENSE("GPL");