drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c

   1 /*
   2  * aQuantia Corporation Network Driver
   3  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  */
   9
  10 /* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
  11
  12 #include "../aq_hw.h"
  13 #include "../aq_hw_utils.h"
  14 #include "../aq_ring.h"
  15 #include "hw_atl_b0.h"
  16 #include "hw_atl_utils.h"
  17 #include "hw_atl_llh.h"
  18 #include "hw_atl_b0_internal.h"
  19 #include "hw_atl_llh_internal.h"
  20
  21 static int hw_atl_b0_get_hw_caps(struct aq_hw_s *self,
  22                                  struct aq_hw_caps_s *aq_hw_caps,
  23                                  unsigned short device,
  24                                  unsigned short subsystem_device)
  25 {
  26         memcpy(aq_hw_caps, &hw_atl_b0_hw_caps_, sizeof(*aq_hw_caps));
  27
  28         if (device == HW_ATL_DEVICE_ID_D108 && subsystem_device == 0x0001)
  29                 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G;
  30
  31         if (device == HW_ATL_DEVICE_ID_D109 && subsystem_device == 0x0001) {
  32                 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G;
  33                 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_5G;
  34         }
  35
  36         return 0;
  37 }
  38
  39 static struct aq_hw_s *hw_atl_b0_create(struct aq_pci_func_s *aq_pci_func,
  40                                         unsigned int port,
  41                                         struct aq_hw_ops *ops)
  42 {
  43         struct hw_atl_s *self = NULL;
  44
  45         self = kzalloc(sizeof(*self), GFP_KERNEL);
  46         if (!self)
  47                 goto err_exit;
  48
  49         self->base.aq_pci_func = aq_pci_func;
  50
  51         self->base.not_ff_addr = 0x10U;
  52
  53 err_exit:
  54         return (struct aq_hw_s *)self;
  55 }
  56
  57 static void hw_atl_b0_destroy(struct aq_hw_s *self)
  58 {
  59         kfree(self);
  60 }
  61
  62 static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
  63 {
  64         int err = 0;
  65
  66         glb_glb_reg_res_dis_set(self, 1U);
  67         pci_pci_reg_res_dis_set(self, 0U);
  68         rx_rx_reg_res_dis_set(self, 0U);
  69         tx_tx_reg_res_dis_set(self, 0U);
  70
  71         HW_ATL_FLUSH();
  72         glb_soft_res_set(self, 1);
  73
  74         /* check 10 times by 1ms */
  75         AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U);
  76         if (err < 0)
  77                 goto err_exit;
  78
  79         itr_irq_reg_res_dis_set(self, 0U);
  80         itr_res_irq_set(self, 1U);
  81
  82         /* check 10 times by 1ms */
  83         AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U);
  84         if (err < 0)
  85                 goto err_exit;
  86
  87         hw_atl_utils_mpi_set(self, MPI_RESET, 0x0U);
  88
  89         err = aq_hw_err_from_flags(self);
  90
  91 err_exit:
  92         return err;
  93 }
  94
  95 static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
  96 {
  97         u32 tc = 0U;
  98         u32 buff_size = 0U;
  99         unsigned int i_priority = 0U;
 100         bool is_rx_flow_control = false;
 101
 102         /* TPS Descriptor rate init */
 103         tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
 104         tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
 105
 106         /* TPS VM init */
 107         tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
 108
 109         /* TPS TC credits init */
 110         tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
 111         tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
 112
 113         tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
 114         tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
 115         tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
 116         tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
 117
 118         /* Tx buf size */
 119         buff_size = HW_ATL_B0_TXBUF_MAX;
 120
 121         tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
 122         tpb_tx_buff_hi_threshold_per_tc_set(self,
 123                                             (buff_size * (1024 / 32U) * 66U) /
 124                                             100U, tc);
 125         tpb_tx_buff_lo_threshold_per_tc_set(self,
 126                                             (buff_size * (1024 / 32U) * 50U) /
 127                                             100U, tc);
 128
 129         /* QoS Rx buf size per TC */
 130         tc = 0;
 131         is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
 132         buff_size = HW_ATL_B0_RXBUF_MAX;
 133
 134         rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
 135         rpb_rx_buff_hi_threshold_per_tc_set(self,
 136                                             (buff_size *
 137                                             (1024U / 32U) * 66U) /
 138                                             100U, tc);
 139         rpb_rx_buff_lo_threshold_per_tc_set(self,
 140                                             (buff_size *
 141                                             (1024U / 32U) * 50U) /
 142                                             100U, tc);
 143         rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
 144
 145         /* QoS 802.1p priority -> TC mapping */
 146         for (i_priority = 8U; i_priority--;)
 147                 rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
 148
 149         return aq_hw_err_from_flags(self);
 150 }
 151
 152 static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
 153                                      struct aq_rss_parameters *rss_params)
 154 {
 155         struct aq_nic_cfg_s *cfg = NULL;
 156         int err = 0;
 157         unsigned int i = 0U;
 158         unsigned int addr = 0U;
 159
 160         cfg = self->aq_nic_cfg;
 161
 162         for (i = 10, addr = 0U; i--; ++addr) {
 163                 u32 key_data = cfg->is_rss ?
 164                         __swab32(rss_params->hash_secret_key[i]) : 0U;
 165                 rpf_rss_key_wr_data_set(self, key_data);
 166                 rpf_rss_key_addr_set(self, addr);
 167                 rpf_rss_key_wr_en_set(self, 1U);
 168                 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U);
 169                 if (err < 0)
 170                         goto err_exit;
 171         }
 172
 173         err = aq_hw_err_from_flags(self);
 174
 175 err_exit:
 176         return err;
 177 }
 178
 179 static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
 180                                 struct aq_rss_parameters *rss_params)
 181 {
 182         u8 *indirection_table = rss_params->indirection_table;
 183         u32 i = 0U;
 184         u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
 185         int err = 0;
 186         u16 bitary[1 + (HW_ATL_B0_RSS_REDIRECTION_MAX *
 187                    HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)];
 188
 189         memset(bitary, 0, sizeof(bitary));
 190
 191         for (i = HW_ATL_B0_RSS_REDIRECTION_MAX; i--;) {
 192                 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
 193                         ((indirection_table[i] % num_rss_queues) <<
 194                         ((i * 3U) & 0xFU));
 195         }
 196
 197         for (i = AQ_DIMOF(bitary); i--;) {
 198                 rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
 199                 rpf_rss_redir_tbl_addr_set(self, i);
 200                 rpf_rss_redir_wr_en_set(self, 1U);
 201                 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U);
 202                 if (err < 0)
 203                         goto err_exit;
 204         }
 205
 206         err = aq_hw_err_from_flags(self);
 207
 208 err_exit:
 209         return err;
 210 }
 211
 212 static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
 213                                     struct aq_nic_cfg_s *aq_nic_cfg)
 214 {
 215         unsigned int i;
 216
 217         /* TX checksums offloads*/
 218         tpo_ipv4header_crc_offload_en_set(self, 1);
 219         tpo_tcp_udp_crc_offload_en_set(self, 1);
 220
 221         /* RX checksums offloads*/
 222         rpo_ipv4header_crc_offload_en_set(self, 1);
 223         rpo_tcp_udp_crc_offload_en_set(self, 1);
 224
 225         /* LSO offloads*/
 226         tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
 227
 228 /* LRO offloads */
 229         {
 230                 unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :
 231                         ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :
 232                         ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));
 233
 234                 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)
 235                         rpo_lro_max_num_of_descriptors_set(self, val, i);
 236
 237                 rpo_lro_time_base_divider_set(self, 0x61AU);
 238                 rpo_lro_inactive_interval_set(self, 0);
 239                 rpo_lro_max_coalescing_interval_set(self, 2);
 240
 241                 rpo_lro_qsessions_lim_set(self, 1U);
 242
 243                 rpo_lro_total_desc_lim_set(self, 2U);
 244
 245                 rpo_lro_patch_optimization_en_set(self, 0U);
 246
 247                 rpo_lro_min_pay_of_first_pkt_set(self, 10U);
 248
 249                 rpo_lro_pkt_lim_set(self, 1U);
 250
 251                 rpo_lro_en_set(self, aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
 252         }
 253         return aq_hw_err_from_flags(self);
 254 }
 255
 256 static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
 257 {
 258         thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
 259         thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
 260         thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
 261
 262         /* Tx interrupts */
 263         tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
 264
 265         /* misc */
 266         aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
 267                         0x00010000U : 0x00000000U);
 268         tdm_tx_dca_en_set(self, 0U);
 269         tdm_tx_dca_mode_set(self, 0U);
 270
 271         tpb_tx_path_scp_ins_en_set(self, 1U);
 272
 273         return aq_hw_err_from_flags(self);
 274 }
 275
 276 static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
 277 {
 278         struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
 279         int i;
 280
 281         /* Rx TC/RSS number config */
 282         rpb_rpf_rx_traf_class_mode_set(self, 1U);
 283
 284         /* Rx flow control */
 285         rpb_rx_flow_ctl_mode_set(self, 1U);
 286
 287         /* RSS Ring selection */
 288         reg_rx_flr_rss_control1set(self, cfg->is_rss ?
 289                                         0xB3333333U : 0x00000000U);
 290
 291         /* Multicast filters */
 292         for (i = HW_ATL_B0_MAC_MAX; i--;) {
 293                 rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
 294                 rpfl2unicast_flr_act_set(self, 1U, i);
 295         }
 296
 297         reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
 298         reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
 299
 300         /* Vlan filters */
 301         rpf_vlan_outer_etht_set(self, 0x88A8U);
 302         rpf_vlan_inner_etht_set(self, 0x8100U);
 303
 304         if (cfg->vlan_id) {
 305                 rpf_vlan_flr_act_set(self, 1U, 0U);
 306                 rpf_vlan_id_flr_set(self, 0U, 0U);
 307                 rpf_vlan_flr_en_set(self, 0U, 0U);
 308
 309                 rpf_vlan_accept_untagged_packets_set(self, 1U);
 310                 rpf_vlan_untagged_act_set(self, 1U);
 311
 312                 rpf_vlan_flr_act_set(self, 1U, 1U);
 313                 rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U);
 314                 rpf_vlan_flr_en_set(self, 1U, 1U);
 315         } else {
 316                 rpf_vlan_prom_mode_en_set(self, 1);
 317         }
 318
 319         /* Rx Interrupts */
 320         rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
 321
 322         /* misc */
 323         aq_hw_write_reg(self, 0x00005040U,
 324                         IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U);
 325
 326         rpfl2broadcast_flr_act_set(self, 1U);
 327         rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
 328
 329         rdm_rx_dca_en_set(self, 0U);
 330         rdm_rx_dca_mode_set(self, 0U);
 331
 332         return aq_hw_err_from_flags(self);
 333 }
 334
 335 static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
 336 {
 337         int err = 0;
 338         unsigned int h = 0U;
 339         unsigned int l = 0U;
 340
 341         if (!mac_addr) {
 342                 err = -EINVAL;
 343                 goto err_exit;
 344         }
 345         h = (mac_addr[0] << 8) | (mac_addr[1]);
 346         l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
 347                 (mac_addr[4] << 8) | mac_addr[5];
 348
 349         rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
 350         rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
 351         rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
 352         rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
 353
 354         err = aq_hw_err_from_flags(self);
 355
 356 err_exit:
 357         return err;
 358 }
 359
 360 static int hw_atl_b0_hw_init(struct aq_hw_s *self,
 361                              struct aq_nic_cfg_s *aq_nic_cfg,
 362                              u8 *mac_addr)
 363 {
 364         static u32 aq_hw_atl_igcr_table_[4][2] = {
 365                 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
 366                 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
 367                 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
 368                 { 0x20000022U, 0x20000026U }  /* AQ_IRQ_MSIX */
 369         };
 370
 371         int err = 0;
 372         u32 val;
 373
 374         self->aq_nic_cfg = aq_nic_cfg;
 375
 376         hw_atl_utils_hw_chip_features_init(self,
 377                                            &PHAL_ATLANTIC_B0->chip_features);
 378
 379         hw_atl_b0_hw_init_tx_path(self);
 380         hw_atl_b0_hw_init_rx_path(self);
 381
 382         hw_atl_b0_hw_mac_addr_set(self, mac_addr);
 383
 384         hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk);
 385
 386         hw_atl_b0_hw_qos_set(self);
 387         hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
 388         hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
 389
 390         /* Force limit MRRS on RDM/TDM to 2K */
 391         val = aq_hw_read_reg(self, pci_reg_control6_adr);
 392         aq_hw_write_reg(self, pci_reg_control6_adr, (val & ~0x707) | 0x404);
 393
 394         /* TX DMA total request limit. B0 hardware is not capable to
 395          * handle more than (8K-MRRS) incoming DMA data.
 396          * Value 24 in 256byte units
 397          */
 398         aq_hw_write_reg(self, tx_dma_total_req_limit_adr, 24);
 399
 400         err = aq_hw_err_from_flags(self);
 401         if (err < 0)
 402                 goto err_exit;
 403
 404         /* Interrupts */
 405         reg_irq_glb_ctl_set(self,
 406                             aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
 407                                                  [(aq_nic_cfg->vecs > 1U) ?
 408                                                  1 : 0]);
 409
 410         itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
 411
 412         /* Interrupts */
 413         reg_gen_irq_map_set(self,
 414                             ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) |
 415                             ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U);
 416
 417         hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
 418
 419 err_exit:
 420         return err;
 421 }
 422
 423 static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self,
 424                                       struct aq_ring_s *ring)
 425 {
 426         tdm_tx_desc_en_set(self, 1, ring->idx);
 427         return aq_hw_err_from_flags(self);
 428 }
 429
 430 static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self,
 431                                       struct aq_ring_s *ring)
 432 {
 433         rdm_rx_desc_en_set(self, 1, ring->idx);
 434         return aq_hw_err_from_flags(self);
 435 }
 436
 437 static int hw_atl_b0_hw_start(struct aq_hw_s *self)
 438 {
 439         tpb_tx_buff_en_set(self, 1);
 440         rpb_rx_buff_en_set(self, 1);
 441         return aq_hw_err_from_flags(self);
 442 }
 443
 444 static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self,
 445                                             struct aq_ring_s *ring)
 446 {
 447         reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
 448         return 0;
 449 }
 450
 451 static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self,
 452                                      struct aq_ring_s *ring,
 453                                      unsigned int frags)
 454 {
 455         struct aq_ring_buff_s *buff = NULL;
 456         struct hw_atl_txd_s *txd = NULL;
 457         unsigned int buff_pa_len = 0U;
 458         unsigned int pkt_len = 0U;
 459         unsigned int frag_count = 0U;
 460         bool is_gso = false;
 461
 462         buff = &ring->buff_ring[ring->sw_tail];
 463         pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
 464
 465         for (frag_count = 0; frag_count < frags; frag_count++) {
 466                 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
 467                                                 HW_ATL_B0_TXD_SIZE];
 468                 txd->ctl = 0;
 469                 txd->ctl2 = 0;
 470                 txd->buf_addr = 0;
 471
 472                 buff = &ring->buff_ring[ring->sw_tail];
 473
 474                 if (buff->is_txc) {
 475                         txd->ctl |= (buff->len_l3 << 31) |
 476                                 (buff->len_l2 << 24) |
 477                                 HW_ATL_B0_TXD_CTL_CMD_TCP |
 478                                 HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC;
 479                         txd->ctl2 |= (buff->mss << 16) |
 480                                 (buff->len_l4 << 8) |
 481                                 (buff->len_l3 >> 1);
 482
 483                         pkt_len -= (buff->len_l4 +
 484                                     buff->len_l3 +
 485                                     buff->len_l2);
 486                         is_gso = true;
 487
 488                         if (buff->is_ipv6)
 489                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPV6;
 490                 } else {
 491                         buff_pa_len = buff->len;
 492
 493                         txd->buf_addr = buff->pa;
 494                         txd->ctl |= (HW_ATL_B0_TXD_CTL_BLEN &
 495                                                 ((u32)buff_pa_len << 4));
 496                         txd->ctl |= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD;
 497                         /* PAY_LEN */
 498                         txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14);
 499
 500                         if (is_gso) {
 501                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_LSO;
 502                                 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN;
 503                         }
 504
 505                         /* Tx checksum offloads */
 506                         if (buff->is_ip_cso)
 507                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPCSO;
 508
 509                         if (buff->is_udp_cso || buff->is_tcp_cso)
 510                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_TUCSO;
 511
 512                         if (unlikely(buff->is_eop)) {
 513                                 txd->ctl |= HW_ATL_B0_TXD_CTL_EOP;
 514                                 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_WB;
 515                                 is_gso = false;
 516                         }
 517                 }
 518
 519                 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
 520         }
 521
 522         hw_atl_b0_hw_tx_ring_tail_update(self, ring);
 523         return aq_hw_err_from_flags(self);
 524 }
 525
 526 static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self,
 527                                      struct aq_ring_s *aq_ring,
 528                                      struct aq_ring_param_s *aq_ring_param)
 529 {
 530         u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
 531         u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 532
 533         rdm_rx_desc_en_set(self, false, aq_ring->idx);
 534
 535         rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 536
 537         reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
 538                                            aq_ring->idx);
 539
 540         reg_rx_dma_desc_base_addressmswset(self,
 541                                            dma_desc_addr_msw, aq_ring->idx);
 542
 543         rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 544
 545         rdm_rx_desc_data_buff_size_set(self,
 546                                        AQ_CFG_RX_FRAME_MAX / 1024U,
 547                                        aq_ring->idx);
 548
 549         rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
 550         rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 551         rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
 552
 553         /* Rx ring set mode */
 554
 555         /* Mapping interrupt vector */
 556         itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
 557         itr_irq_map_en_rx_set(self, true, aq_ring->idx);
 558
 559         rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
 560         rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
 561         rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
 562         rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
 563
 564         return aq_hw_err_from_flags(self);
 565 }
 566
 567 static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self,
 568                                      struct aq_ring_s *aq_ring,
 569                                      struct aq_ring_param_s *aq_ring_param)
 570 {
 571         u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
 572         u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 573
 574         reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
 575                                            aq_ring->idx);
 576
 577         reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
 578                                            aq_ring->idx);
 579
 580         tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 581
 582         hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring);
 583
 584         /* Set Tx threshold */
 585         tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
 586
 587         /* Mapping interrupt vector */
 588         itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
 589         itr_irq_map_en_tx_set(self, true, aq_ring->idx);
 590
 591         tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
 592         tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
 593
 594         return aq_hw_err_from_flags(self);
 595 }
 596
 597 static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self,
 598                                      struct aq_ring_s *ring,
 599                                      unsigned int sw_tail_old)
 600 {
 601         for (; sw_tail_old != ring->sw_tail;
 602                 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
 603                 struct hw_atl_rxd_s *rxd =
 604                         (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
 605                                                         HW_ATL_B0_RXD_SIZE];
 606
 607                 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
 608
 609                 rxd->buf_addr = buff->pa;
 610                 rxd->hdr_addr = 0U;
 611         }
 612
 613         reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
 614
 615         return aq_hw_err_from_flags(self);
 616 }
 617
 618 static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
 619                                             struct aq_ring_s *ring)
 620 {
 621         int err = 0;
 622         unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx);
 623
 624         if (aq_utils_obj_test(&self->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) {
 625                 err = -ENXIO;
 626                 goto err_exit;
 627         }
 628
 629         /* Validate that the new hw_head_ is reasonable. */
 630         if (hw_head_ >= ring->size) {
 631                 err = -ENXIO;
 632                 goto err_exit;
 633         }
 634
 635         ring->hw_head = hw_head_;
 636         err = aq_hw_err_from_flags(self);
 637
 638 err_exit:
 639         return err;
 640 }
 641
 642 static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self,
 643                                         struct aq_ring_s *ring)
 644 {
 645         struct device *ndev = aq_nic_get_dev(ring->aq_nic);
 646
 647         for (; ring->hw_head != ring->sw_tail;
 648                 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
 649                 struct aq_ring_buff_s *buff = NULL;
 650                 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
 651                         &ring->dx_ring[ring->hw_head * HW_ATL_B0_RXD_SIZE];
 652
 653                 unsigned int is_err = 1U;
 654                 unsigned int is_rx_check_sum_enabled = 0U;
 655                 unsigned int pkt_type = 0U;
 656
 657                 if (!(rxd_wb->status & 0x1U)) { /* RxD is not done */
 658                         break;
 659                 }
 660
 661                 buff = &ring->buff_ring[ring->hw_head];
 662
 663                 is_err = (0x0000003CU & rxd_wb->status);
 664
 665                 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
 666                 is_err &= ~0x20U; /* exclude validity bit */
 667
 668                 pkt_type = 0xFFU & (rxd_wb->type >> 4);
 669
 670                 if (is_rx_check_sum_enabled) {
 671                         if (0x0U == (pkt_type & 0x3U))
 672                                 buff->is_ip_cso = (is_err & 0x08U) ? 0U : 1U;
 673
 674                         if (0x4U == (pkt_type & 0x1CU))
 675                                 buff->is_udp_cso = buff->is_cso_err ? 0U : 1U;
 676                         else if (0x0U == (pkt_type & 0x1CU))
 677                                 buff->is_tcp_cso = buff->is_cso_err ? 0U : 1U;
 678
 679                         /* Checksum offload workaround for small packets */
 680                         if (rxd_wb->pkt_len <= 60) {
 681                                 buff->is_ip_cso = 0U;
 682                                 buff->is_cso_err = 0U;
 683                         }
 684                 }
 685
 686                 is_err &= ~0x18U;
 687
 688                 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
 689
 690                 if (is_err || rxd_wb->type & 0x1000U) {
 691                         /* status error or DMA error */
 692                         buff->is_error = 1U;
 693                 }
 694                 if (self->aq_nic_cfg->is_rss) {
 695                         /* last 4 byte */
 696                         u16 rss_type = rxd_wb->type & 0xFU;
 697
 698                         if (rss_type && rss_type < 0x8U) {
 699                                 buff->is_hash_l4 = (rss_type == 0x4 ||
 700                                 rss_type == 0x5);
 701                                 buff->rss_hash = rxd_wb->rss_hash;
 702                         }
 703                 }
 704
 705                 if (HW_ATL_B0_RXD_WB_STAT2_EOP & rxd_wb->status) {
 706                         buff->len = rxd_wb->pkt_len %
 707                                 AQ_CFG_RX_FRAME_MAX;
 708                         buff->len = buff->len ?
 709                                 buff->len : AQ_CFG_RX_FRAME_MAX;
 710                         buff->next = 0U;
 711                         buff->is_eop = 1U;
 712                 } else {
 713                         buff->len =
 714                                 rxd_wb->pkt_len > AQ_CFG_RX_FRAME_MAX ?
 715                                 AQ_CFG_RX_FRAME_MAX : rxd_wb->pkt_len;
 716
 717                         if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT &
 718                                 rxd_wb->status) {
 719                                 /* LRO */
 720                                 buff->next = rxd_wb->next_desc_ptr;
 721                                 ++ring->stats.rx.lro_packets;
 722                         } else {
 723                                 /* jumbo */
 724                                 buff->next =
 725                                         aq_ring_next_dx(ring,
 726                                                         ring->hw_head);
 727                                 ++ring->stats.rx.jumbo_packets;
 728                         }
 729                 }
 730         }
 731
 732         return aq_hw_err_from_flags(self);
 733 }
 734
 735 static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
 736 {
 737         itr_irq_msk_setlsw_set(self, LODWORD(mask));
 738         return aq_hw_err_from_flags(self);
 739 }
 740
 741 static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
 742 {
 743         itr_irq_msk_clearlsw_set(self, LODWORD(mask));
 744         itr_irq_status_clearlsw_set(self, LODWORD(mask));
 745
 746         atomic_inc(&PHAL_ATLANTIC_B0->dpc);
 747         return aq_hw_err_from_flags(self);
 748 }
 749
 750 static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
 751 {
 752         *mask = itr_irq_statuslsw_get(self);
 753         return aq_hw_err_from_flags(self);
 754 }
 755
 756 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
 757
 758 static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
 759                                           unsigned int packet_filter)
 760 {
 761         unsigned int i = 0U;
 762
 763         rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
 764         rpfl2multicast_flr_en_set(self,
 765                                   IS_FILTER_ENABLED(IFF_ALLMULTI), 0);
 766
 767         rpfl2_accept_all_mc_packets_set(self,
 768                                         IS_FILTER_ENABLED(IFF_ALLMULTI));
 769
 770         rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
 771
 772         self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
 773
 774         for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
 775                 rpfl2_uc_flr_en_set(self,
 776                                     (self->aq_nic_cfg->is_mc_list_enabled &&
 777                                     (i <= self->aq_nic_cfg->mc_list_count)) ?
 778                                     1U : 0U, i);
 779
 780         return aq_hw_err_from_flags(self);
 781 }
 782
 783 #undef IS_FILTER_ENABLED
 784
 785 static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self,
 786                                            u8 ar_mac
 787                                            [AQ_CFG_MULTICAST_ADDRESS_MAX]
 788                                            [ETH_ALEN],
 789                                            u32 count)
 790 {
 791         int err = 0;
 792
 793         if (count > (HW_ATL_B0_MAC_MAX - HW_ATL_B0_MAC_MIN)) {
 794                 err = -EBADRQC;
 795                 goto err_exit;
 796         }
 797         for (self->aq_nic_cfg->mc_list_count = 0U;
 798                         self->aq_nic_cfg->mc_list_count < count;
 799                         ++self->aq_nic_cfg->mc_list_count) {
 800                 u32 i = self->aq_nic_cfg->mc_list_count;
 801                 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
 802                 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
 803                                         (ar_mac[i][4] << 8) | ar_mac[i][5];
 804
 805                 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
 806
 807                 rpfl2unicast_dest_addresslsw_set(self,
 808                                                  l, HW_ATL_B0_MAC_MIN + i);
 809
 810                 rpfl2unicast_dest_addressmsw_set(self,
 811                                                  h, HW_ATL_B0_MAC_MIN + i);
 812
 813                 rpfl2_uc_flr_en_set(self,
 814                                     (self->aq_nic_cfg->is_mc_list_enabled),
 815                                     HW_ATL_B0_MAC_MIN + i);
 816         }
 817
 818         err = aq_hw_err_from_flags(self);
 819
 820 err_exit:
 821         return err;
 822 }
 823
 824 static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
 825 {
 826         unsigned int i = 0U;
 827         u32 itr_tx = 2U;
 828         u32 itr_rx = 2U;
 829
 830         switch (self->aq_nic_cfg->itr) {
 831         case  AQ_CFG_INTERRUPT_MODERATION_ON:
 832         case  AQ_CFG_INTERRUPT_MODERATION_AUTO:
 833                 tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
 834                 tdm_tdm_intr_moder_en_set(self, 1U);
 835                 rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
 836                 rdm_rdm_intr_moder_en_set(self, 1U);
 837
 838                 if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
 839                         /* HW timers are in 2us units */
 840                         int tx_max_timer = self->aq_nic_cfg->tx_itr / 2;
 841                         int tx_min_timer = tx_max_timer / 2;
 842
 843                         int rx_max_timer = self->aq_nic_cfg->rx_itr / 2;
 844                         int rx_min_timer = rx_max_timer / 2;
 845
 846                         tx_max_timer = min(HW_ATL_INTR_MODER_MAX, tx_max_timer);
 847                         tx_min_timer = min(HW_ATL_INTR_MODER_MIN, tx_min_timer);
 848                         rx_max_timer = min(HW_ATL_INTR_MODER_MAX, rx_max_timer);
 849                         rx_min_timer = min(HW_ATL_INTR_MODER_MIN, rx_min_timer);
 850
 851                         itr_tx |= tx_min_timer << 0x8U;
 852                         itr_tx |= tx_max_timer << 0x10U;
 853                         itr_rx |= rx_min_timer << 0x8U;
 854                         itr_rx |= rx_max_timer << 0x10U;
 855                 } else {
 856                         static unsigned int hw_atl_b0_timers_table_tx_[][2] = {
 857                                 {0xfU, 0xffU}, /* 10Gbit */
 858                                 {0xfU, 0x1ffU}, /* 5Gbit */
 859                                 {0xfU, 0x1ffU}, /* 5Gbit 5GS */
 860                                 {0xfU, 0x1ffU}, /* 2.5Gbit */
 861                                 {0xfU, 0x1ffU}, /* 1Gbit */
 862                                 {0xfU, 0x1ffU}, /* 100Mbit */
 863                         };
 864
 865                         static unsigned int hw_atl_b0_timers_table_rx_[][2] = {
 866                                 {0x6U, 0x38U},/* 10Gbit */
 867                                 {0xCU, 0x70U},/* 5Gbit */
 868                                 {0xCU, 0x70U},/* 5Gbit 5GS */
 869                                 {0x18U, 0xE0U},/* 2.5Gbit */
 870                                 {0x30U, 0x80U},/* 1Gbit */
 871                                 {0x4U, 0x50U},/* 100Mbit */
 872                         };
 873
 874                         unsigned int speed_index =
 875                                         hw_atl_utils_mbps_2_speed_index(
 876                                                 self->aq_link_status.mbps);
 877
 878                         /* Update user visible ITR settings */
 879                         self->aq_nic_cfg->tx_itr = hw_atl_b0_timers_table_tx_
 880                                                         [speed_index][1] * 2;
 881                         self->aq_nic_cfg->rx_itr = hw_atl_b0_timers_table_rx_
 882                                                         [speed_index][1] * 2;
 883
 884                         itr_tx |= hw_atl_b0_timers_table_tx_
 885                                                 [speed_index][0] << 0x8U;
 886                         itr_tx |= hw_atl_b0_timers_table_tx_
 887                                                 [speed_index][1] << 0x10U;
 888
 889                         itr_rx |= hw_atl_b0_timers_table_rx_
 890                                                 [speed_index][0] << 0x8U;
 891                         itr_rx |= hw_atl_b0_timers_table_rx_
 892                                                 [speed_index][1] << 0x10U;
 893                 }
 894                 break;
 895         case AQ_CFG_INTERRUPT_MODERATION_OFF:
 896                 tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
 897                 tdm_tdm_intr_moder_en_set(self, 0U);
 898                 rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
 899                 rdm_rdm_intr_moder_en_set(self, 0U);
 900                 itr_tx = 0U;
 901                 itr_rx = 0U;
 902                 break;
 903         }
 904
 905         for (i = HW_ATL_B0_RINGS_MAX; i--;) {
 906                 reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
 907                 reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
 908         }
 909
 910         return aq_hw_err_from_flags(self);
 911 }
 912
 913 static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
 914 {
 915         hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
 916         return aq_hw_err_from_flags(self);
 917 }
 918
 919 static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
 920                                      struct aq_ring_s *ring)
 921 {
 922         tdm_tx_desc_en_set(self, 0U, ring->idx);
 923         return aq_hw_err_from_flags(self);
 924 }
 925
 926 static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
 927                                      struct aq_ring_s *ring)
 928 {
 929         rdm_rx_desc_en_set(self, 0U, ring->idx);
 930         return aq_hw_err_from_flags(self);
 931 }
 932
 933 static int hw_atl_b0_hw_set_speed(struct aq_hw_s *self, u32 speed)
 934 {
 935         int err = 0;
 936
 937         err = hw_atl_utils_mpi_set_speed(self, speed, MPI_INIT);
 938         if (err < 0)
 939                 goto err_exit;
 940
 941 err_exit:
 942         return err;
 943 }
 944
 945 static struct aq_hw_ops hw_atl_ops_ = {
 946         .create               = hw_atl_b0_create,
 947         .destroy              = hw_atl_b0_destroy,
 948         .get_hw_caps          = hw_atl_b0_get_hw_caps,
 949
 950         .hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
 951         .hw_set_mac_address   = hw_atl_b0_hw_mac_addr_set,
 952         .hw_get_link_status   = hw_atl_utils_mpi_get_link_status,
 953         .hw_set_link_speed    = hw_atl_b0_hw_set_speed,
 954         .hw_init              = hw_atl_b0_hw_init,
 955         .hw_deinit            = hw_atl_utils_hw_deinit,
 956         .hw_set_power         = hw_atl_utils_hw_set_power,
 957         .hw_reset             = hw_atl_b0_hw_reset,
 958         .hw_start             = hw_atl_b0_hw_start,
 959         .hw_ring_tx_start     = hw_atl_b0_hw_ring_tx_start,
 960         .hw_ring_tx_stop      = hw_atl_b0_hw_ring_tx_stop,
 961         .hw_ring_rx_start     = hw_atl_b0_hw_ring_rx_start,
 962         .hw_ring_rx_stop      = hw_atl_b0_hw_ring_rx_stop,
 963         .hw_stop              = hw_atl_b0_hw_stop,
 964
 965         .hw_ring_tx_xmit         = hw_atl_b0_hw_ring_tx_xmit,
 966         .hw_ring_tx_head_update  = hw_atl_b0_hw_ring_tx_head_update,
 967
 968         .hw_ring_rx_receive      = hw_atl_b0_hw_ring_rx_receive,
 969         .hw_ring_rx_fill         = hw_atl_b0_hw_ring_rx_fill,
 970
 971         .hw_irq_enable           = hw_atl_b0_hw_irq_enable,
 972         .hw_irq_disable          = hw_atl_b0_hw_irq_disable,
 973         .hw_irq_read             = hw_atl_b0_hw_irq_read,
 974
 975         .hw_ring_rx_init             = hw_atl_b0_hw_ring_rx_init,
 976         .hw_ring_tx_init             = hw_atl_b0_hw_ring_tx_init,
 977         .hw_packet_filter_set        = hw_atl_b0_hw_packet_filter_set,
 978         .hw_multicast_list_set       = hw_atl_b0_hw_multicast_list_set,
 979         .hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set,
 980         .hw_rss_set                  = hw_atl_b0_hw_rss_set,
 981         .hw_rss_hash_set             = hw_atl_b0_hw_rss_hash_set,
 982         .hw_get_regs                 = hw_atl_utils_hw_get_regs,
 983         .hw_update_stats             = hw_atl_utils_update_stats,
 984         .hw_get_hw_stats             = hw_atl_utils_get_hw_stats,
 985         .hw_get_fw_version           = hw_atl_utils_get_fw_version,
 986 };
 987
 988 struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev)
 989 {
 990         bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
 991         bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
 992                         (pdev->device == HW_ATL_DEVICE_ID_D100) ||
 993                         (pdev->device == HW_ATL_DEVICE_ID_D107) ||
 994                         (pdev->device == HW_ATL_DEVICE_ID_D108) ||
 995                         (pdev->device == HW_ATL_DEVICE_ID_D109));
 996
 997         bool is_rev_ok = (pdev->revision == 2U);
 998
 999         return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
1000 }