drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c

   1 /*
   2  * aQuantia Corporation Network Driver
   3  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  */
   9
  10 /* File hw_atl_llh.c: Definitions of bitfield and register access functions for
  11  * Atlantic registers.
  12  */
  13
  14 #include "hw_atl_llh.h"
  15 #include "hw_atl_llh_internal.h"
  16 #include "../aq_hw_utils.h"
  17
  18 /* global */
  19 void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
  20                                 u32 semaphore)
  21 {
  22         aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem);
  23 }
  24
  25 u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
  26 {
  27         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore));
  28 }
  29
  30 void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
  31 {
  32         aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR,
  33                             HW_ATL_GLB_REG_RES_DIS_MSK,
  34                             HW_ATL_GLB_REG_RES_DIS_SHIFT,
  35                             glb_reg_res_dis);
  36 }
  37
  38 void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
  39 {
  40         aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
  41                             HW_ATL_GLB_SOFT_RES_MSK,
  42                             HW_ATL_GLB_SOFT_RES_SHIFT, soft_res);
  43 }
  44
  45 u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw)
  46 {
  47         return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
  48                                   HW_ATL_GLB_SOFT_RES_MSK,
  49                                   HW_ATL_GLB_SOFT_RES_SHIFT);
  50 }
  51
  52 u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw)
  53 {
  54         return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_STAT_COUNTER7_ADR);
  55 }
  56
  57 u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
  58 {
  59         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
  60 }
  61
  62 /* stats */
  63 u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
  64 {
  65         return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
  66 }
  67
  68 u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
  69 {
  70         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
  71 }
  72
  73 u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
  74 {
  75         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
  76 }
  77
  78 u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
  79 {
  80         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
  81 }
  82
  83 u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
  84 {
  85         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
  86 }
  87
  88 u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
  89 {
  90         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW);
  91 }
  92
  93 u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
  94 {
  95         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW);
  96 }
  97
  98 u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
  99 {
 100         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW);
 101 }
 102
 103 u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
 104 {
 105         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW);
 106 }
 107
 108 /* interrupt */
 109 void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
 110                                      u32 irq_auto_masklsw)
 111 {
 112         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw);
 113 }
 114
 115 void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
 116                                   u32 rx)
 117 {
 118 /* register address for bitfield imr_rx{r}_en */
 119         static u32 itr_imr_rxren_adr[32] = {
 120                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 121                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 122                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 123                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 124                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 125                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 126                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 127                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 128                 };
 129
 130 /* bitmask for bitfield imr_rx{r}_en */
 131         static u32 itr_imr_rxren_msk[32] = {
 132                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 133                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 134                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 135                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 136                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 137                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 138                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 139                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U
 140                 };
 141
 142 /* lower bit position of bitfield imr_rx{r}_en */
 143         static u32 itr_imr_rxren_shift[32] = {
 144                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 145                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 146                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 147                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U
 148                 };
 149
 150         aq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx],
 151                             itr_imr_rxren_msk[rx],
 152                             itr_imr_rxren_shift[rx],
 153                             irq_map_en_rx);
 154 }
 155
 156 void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
 157                                   u32 tx)
 158 {
 159 /* register address for bitfield imr_tx{t}_en */
 160         static u32 itr_imr_txten_adr[32] = {
 161                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 162                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 163                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 164                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 165                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 166                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 167                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 168                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 169                 };
 170
 171 /* bitmask for bitfield imr_tx{t}_en */
 172         static u32 itr_imr_txten_msk[32] = {
 173                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 174                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 175                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 176                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 177                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 178                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 179                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 180                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U
 181                 };
 182
 183 /* lower bit position of bitfield imr_tx{t}_en */
 184         static u32 itr_imr_txten_shift[32] = {
 185                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 186                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 187                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 188                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U
 189                 };
 190
 191         aq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx],
 192                             itr_imr_txten_msk[tx],
 193                             itr_imr_txten_shift[tx],
 194                             irq_map_en_tx);
 195 }
 196
 197 void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
 198 {
 199 /* register address for bitfield imr_rx{r}[4:0] */
 200         static u32 itr_imr_rxr_adr[32] = {
 201                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 202                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 203                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 204                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 205                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 206                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 207                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 208                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 209                 };
 210
 211 /* bitmask for bitfield imr_rx{r}[4:0] */
 212         static u32 itr_imr_rxr_msk[32] = {
 213                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 214                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 215                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 216                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 217                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 218                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 219                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 220                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU
 221                 };
 222
 223 /* lower bit position of bitfield imr_rx{r}[4:0] */
 224         static u32 itr_imr_rxr_shift[32] = {
 225                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 226                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 227                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 228                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U
 229                 };
 230
 231         aq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx],
 232                             itr_imr_rxr_msk[rx],
 233                             itr_imr_rxr_shift[rx],
 234                             irq_map_rx);
 235 }
 236
 237 void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
 238 {
 239 /* register address for bitfield imr_tx{t}[4:0] */
 240         static u32 itr_imr_txt_adr[32] = {
 241                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 242                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 243                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 244                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 245                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 246                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 247                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 248                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 249                 };
 250
 251 /* bitmask for bitfield imr_tx{t}[4:0] */
 252         static u32 itr_imr_txt_msk[32] = {
 253                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 254                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 255                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 256                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 257                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 258                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 259                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 260                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U
 261                 };
 262
 263 /* lower bit position of bitfield imr_tx{t}[4:0] */
 264         static u32 itr_imr_txt_shift[32] = {
 265                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 266                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 267                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 268                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U
 269                 };
 270
 271         aq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx],
 272                             itr_imr_txt_msk[tx],
 273                             itr_imr_txt_shift[tx],
 274                             irq_map_tx);
 275 }
 276
 277 void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
 278                                      u32 irq_msk_clearlsw)
 279 {
 280         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw);
 281 }
 282
 283 void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
 284 {
 285         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw);
 286 }
 287
 288 void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
 289 {
 290         aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR,
 291                             HW_ATL_ITR_REG_RES_DSBL_MSK,
 292                             HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis);
 293 }
 294
 295 void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
 296                                         u32 irq_status_clearlsw)
 297 {
 298         aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw);
 299 }
 300
 301 u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
 302 {
 303         return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR);
 304 }
 305
 306 u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw)
 307 {
 308         return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
 309                                   HW_ATL_ITR_RES_SHIFT);
 310 }
 311
 312 void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
 313 {
 314         aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
 315                             HW_ATL_ITR_RES_SHIFT, res_irq);
 316 }
 317
 318 /* rdm */
 319 void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
 320 {
 321         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca),
 322                             HW_ATL_RDM_DCADCPUID_MSK,
 323                             HW_ATL_RDM_DCADCPUID_SHIFT, cpuid);
 324 }
 325
 326 void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
 327 {
 328         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK,
 329                             HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en);
 330 }
 331
 332 void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
 333 {
 334         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR,
 335                             HW_ATL_RDM_DCA_MODE_MSK,
 336                             HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode);
 337 }
 338
 339 void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
 340                                            u32 rx_desc_data_buff_size,
 341                                            u32 descriptor)
 342 {
 343         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor),
 344                             HW_ATL_RDM_DESCDDATA_SIZE_MSK,
 345                             HW_ATL_RDM_DESCDDATA_SIZE_SHIFT,
 346                             rx_desc_data_buff_size);
 347 }
 348
 349 void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
 350                                    u32 dca)
 351 {
 352         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca),
 353                             HW_ATL_RDM_DCADDESC_EN_MSK,
 354                             HW_ATL_RDM_DCADDESC_EN_SHIFT,
 355                             rx_desc_dca_en);
 356 }
 357
 358 void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
 359                                u32 descriptor)
 360 {
 361         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor),
 362                             HW_ATL_RDM_DESCDEN_MSK,
 363                             HW_ATL_RDM_DESCDEN_SHIFT,
 364                             rx_desc_en);
 365 }
 366
 367 void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
 368                                            u32 rx_desc_head_buff_size,
 369                                            u32 descriptor)
 370 {
 371         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor),
 372                             HW_ATL_RDM_DESCDHDR_SIZE_MSK,
 373                             HW_ATL_RDM_DESCDHDR_SIZE_SHIFT,
 374                             rx_desc_head_buff_size);
 375 }
 376
 377 void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
 378                                            u32 rx_desc_head_splitting,
 379                                            u32 descriptor)
 380 {
 381         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor),
 382                             HW_ATL_RDM_DESCDHDR_SPLIT_MSK,
 383                             HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT,
 384                             rx_desc_head_splitting);
 385 }
 386
 387 u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
 388 {
 389         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor),
 390                                   HW_ATL_RDM_DESCDHD_MSK,
 391                                   HW_ATL_RDM_DESCDHD_SHIFT);
 392 }
 393
 394 void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
 395                                 u32 descriptor)
 396 {
 397         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor),
 398                             HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT,
 399                             rx_desc_len);
 400 }
 401
 402 void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
 403                                 u32 descriptor)
 404 {
 405         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor),
 406                             HW_ATL_RDM_DESCDRESET_MSK,
 407                             HW_ATL_RDM_DESCDRESET_SHIFT,
 408                             rx_desc_res);
 409 }
 410
 411 void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
 412                                          u32 rx_desc_wr_wb_irq_en)
 413 {
 414         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR,
 415                             HW_ATL_RDM_INT_DESC_WRB_EN_MSK,
 416                             HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT,
 417                             rx_desc_wr_wb_irq_en);
 418 }
 419
 420 void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
 421                                    u32 dca)
 422 {
 423         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca),
 424                             HW_ATL_RDM_DCADHDR_EN_MSK,
 425                             HW_ATL_RDM_DCADHDR_EN_SHIFT,
 426                             rx_head_dca_en);
 427 }
 428
 429 void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
 430                                   u32 dca)
 431 {
 432         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca),
 433                             HW_ATL_RDM_DCADPAY_EN_MSK,
 434                             HW_ATL_RDM_DCADPAY_EN_SHIFT,
 435                             rx_pld_dca_en);
 436 }
 437
 438 void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
 439                                       u32 rdm_intr_moder_en)
 440 {
 441         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR,
 442                             HW_ATL_RDM_INT_RIM_EN_MSK,
 443                             HW_ATL_RDM_INT_RIM_EN_SHIFT,
 444                             rdm_intr_moder_en);
 445 }
 446
 447 /* reg */
 448 void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
 449                                 u32 regidx)
 450 {
 451         aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map);
 452 }
 453
 454 u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
 455 {
 456         return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR);
 457 }
 458
 459 void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
 460 {
 461         aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl);
 462 }
 463
 464 void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
 465 {
 466         aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr);
 467 }
 468
 469 void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 470                                                u32 rx_dma_desc_base_addrlsw,
 471                                                u32 descriptor)
 472 {
 473         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
 474                         rx_dma_desc_base_addrlsw);
 475 }
 476
 477 void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 478                                                u32 rx_dma_desc_base_addrmsw,
 479                                                u32 descriptor)
 480 {
 481         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
 482                         rx_dma_desc_base_addrmsw);
 483 }
 484
 485 u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
 486 {
 487         return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor));
 488 }
 489
 490 void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 491                                          u32 rx_dma_desc_tail_ptr,
 492                                          u32 descriptor)
 493 {
 494         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor),
 495                         rx_dma_desc_tail_ptr);
 496 }
 497
 498 void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
 499                                         u32 rx_flr_mcst_flr_msk)
 500 {
 501         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR,
 502                         rx_flr_mcst_flr_msk);
 503 }
 504
 505 void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
 506                                     u32 filter)
 507 {
 508         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter),
 509                         rx_flr_mcst_flr);
 510 }
 511
 512 void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
 513                                        u32 rx_flr_rss_control1)
 514 {
 515         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR,
 516                         rx_flr_rss_control1);
 517 }
 518
 519 void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw,
 520                                     u32 rx_filter_control2)
 521 {
 522         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2);
 523 }
 524
 525 void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 526                                        u32 rx_intr_moderation_ctl,
 527                                        u32 queue)
 528 {
 529         aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue),
 530                         rx_intr_moderation_ctl);
 531 }
 532
 533 void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
 534                                      u32 tx_dma_debug_ctl)
 535 {
 536         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl);
 537 }
 538
 539 void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 540                                                u32 tx_dma_desc_base_addrlsw,
 541                                                u32 descriptor)
 542 {
 543         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
 544                         tx_dma_desc_base_addrlsw);
 545 }
 546
 547 void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 548                                                u32 tx_dma_desc_base_addrmsw,
 549                                                u32 descriptor)
 550 {
 551         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
 552                         tx_dma_desc_base_addrmsw);
 553 }
 554
 555 void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 556                                          u32 tx_dma_desc_tail_ptr,
 557                                          u32 descriptor)
 558 {
 559         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor),
 560                         tx_dma_desc_tail_ptr);
 561 }
 562
 563 void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 564                                        u32 tx_intr_moderation_ctl,
 565                                        u32 queue)
 566 {
 567         aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue),
 568                         tx_intr_moderation_ctl);
 569 }
 570
 571 /* RPB: rx packet buffer */
 572 void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
 573 {
 574         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR,
 575                             HW_ATL_RPB_DMA_SYS_LBK_MSK,
 576                             HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);
 577 }
 578
 579 void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
 580                                            u32 rx_traf_class_mode)
 581 {
 582         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
 583                             HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
 584                             HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT,
 585                             rx_traf_class_mode);
 586 }
 587
 588 void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
 589 {
 590         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR,
 591                             HW_ATL_RPB_RX_BUF_EN_MSK,
 592                             HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en);
 593 }
 594
 595 void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 596                                                 u32 rx_buff_hi_threshold_per_tc,
 597                                                 u32 buffer)
 598 {
 599         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer),
 600                             HW_ATL_RPB_RXBHI_THRESH_MSK,
 601                             HW_ATL_RPB_RXBHI_THRESH_SHIFT,
 602                             rx_buff_hi_threshold_per_tc);
 603 }
 604
 605 void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 606                                                 u32 rx_buff_lo_threshold_per_tc,
 607                                                 u32 buffer)
 608 {
 609         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer),
 610                             HW_ATL_RPB_RXBLO_THRESH_MSK,
 611                             HW_ATL_RPB_RXBLO_THRESH_SHIFT,
 612                             rx_buff_lo_threshold_per_tc);
 613 }
 614
 615 void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)
 616 {
 617         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR,
 618                             HW_ATL_RPB_RX_FC_MODE_MSK,
 619                             HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
 620 }
 621
 622 void hw_atl_rdm_rx_dma_desc_cache_init_set(struct aq_hw_s *aq_hw, u32 init)
 623 {
 624         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
 625                             HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
 626                             HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT,
 627                             init);
 628 }
 629
 630 void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
 631                                             u32 rx_pkt_buff_size_per_tc, u32 buffer)
 632 {
 633         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer),
 634                             HW_ATL_RPB_RXBBUF_SIZE_MSK,
 635                             HW_ATL_RPB_RXBBUF_SIZE_SHIFT,
 636                             rx_pkt_buff_size_per_tc);
 637 }
 638
 639 void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
 640                                       u32 buffer)
 641 {
 642         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer),
 643                             HW_ATL_RPB_RXBXOFF_EN_MSK,
 644                             HW_ATL_RPB_RXBXOFF_EN_SHIFT,
 645                             rx_xoff_en_per_tc);
 646 }
 647
 648 /* rpf */
 649
 650 void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
 651                                                u32 l2broadcast_count_threshold)
 652 {
 653         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR,
 654                             HW_ATL_RPFL2BC_THRESH_MSK,
 655                             HW_ATL_RPFL2BC_THRESH_SHIFT,
 656                             l2broadcast_count_threshold);
 657 }
 658
 659 void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
 660 {
 661         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK,
 662                             HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en);
 663 }
 664
 665 void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
 666                                        u32 l2broadcast_flr_act)
 667 {
 668         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR,
 669                             HW_ATL_RPFL2BC_ACT_MSK,
 670                             HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act);
 671 }
 672
 673 void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
 674                                       u32 l2multicast_flr_en,
 675                                       u32 filter)
 676 {
 677         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter),
 678                             HW_ATL_RPFL2MC_ENF_MSK,
 679                             HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);
 680 }
 681
 682 void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
 683                                          u32 l2promiscuous_mode_en)
 684 {
 685         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,
 686                             HW_ATL_RPFL2PROMIS_MODE_MSK,
 687                             HW_ATL_RPFL2PROMIS_MODE_SHIFT,
 688                             l2promiscuous_mode_en);
 689 }
 690
 691 void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
 692                                      u32 l2unicast_flr_act,
 693                                      u32 filter)
 694 {
 695         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter),
 696                             HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT,
 697                             l2unicast_flr_act);
 698 }
 699
 700 void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
 701                                 u32 filter)
 702 {
 703         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter),
 704                             HW_ATL_RPFL2UC_ENF_MSK,
 705                             HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en);
 706 }
 707
 708 void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
 709                                              u32 l2unicast_dest_addresslsw,
 710                                              u32 filter)
 711 {
 712         aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter),
 713                         l2unicast_dest_addresslsw);
 714 }
 715
 716 void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
 717                                              u32 l2unicast_dest_addressmsw,
 718                                              u32 filter)
 719 {
 720         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter),
 721                             HW_ATL_RPFL2UC_DAFMSW_MSK,
 722                             HW_ATL_RPFL2UC_DAFMSW_SHIFT,
 723                             l2unicast_dest_addressmsw);
 724 }
 725
 726 void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
 727                                             u32 l2_accept_all_mc_packets)
 728 {
 729         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR,
 730                             HW_ATL_RPFL2MC_ACCEPT_ALL_MSK,
 731                             HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT,
 732                             l2_accept_all_mc_packets);
 733 }
 734
 735 void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
 736                                              u32 user_priority_tc_map, u32 tc)
 737 {
 738 /* register address for bitfield rx_tc_up{t}[2:0] */
 739         static u32 rpf_rpb_rx_tc_upt_adr[8] = {
 740                         0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U,
 741                         0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U
 742                 };
 743
 744 /* bitmask for bitfield rx_tc_up{t}[2:0] */
 745         static u32 rpf_rpb_rx_tc_upt_msk[8] = {
 746                         0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U,
 747                         0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U
 748                 };
 749
 750 /* lower bit position of bitfield rx_tc_up{t}[2:0] */
 751         static u32 rpf_rpb_rx_tc_upt_shft[8] = {
 752                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
 753                 };
 754
 755         aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc],
 756                             rpf_rpb_rx_tc_upt_msk[tc],
 757                             rpf_rpb_rx_tc_upt_shft[tc],
 758                             user_priority_tc_map);
 759 }
 760
 761 void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
 762 {
 763         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR,
 764                             HW_ATL_RPF_RSS_KEY_ADDR_MSK,
 765                             HW_ATL_RPF_RSS_KEY_ADDR_SHIFT,
 766                             rss_key_addr);
 767 }
 768
 769 void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
 770 {
 771         aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR,
 772                         rss_key_wr_data);
 773 }
 774
 775 u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
 776 {
 777         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
 778                                   HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
 779                                   HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT);
 780 }
 781
 782 void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
 783 {
 784         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
 785                             HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
 786                             HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT,
 787                             rss_key_wr_en);
 788 }
 789
 790 void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
 791                                        u32 rss_redir_tbl_addr)
 792 {
 793         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR,
 794                             HW_ATL_RPF_RSS_REDIR_ADDR_MSK,
 795                             HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT,
 796                             rss_redir_tbl_addr);
 797 }
 798
 799 void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
 800                                           u32 rss_redir_tbl_wr_data)
 801 {
 802         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR,
 803                             HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK,
 804                             HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT,
 805                             rss_redir_tbl_wr_data);
 806 }
 807
 808 u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
 809 {
 810         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
 811                                   HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
 812                                   HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT);
 813 }
 814
 815 void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
 816 {
 817         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
 818                             HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
 819                             HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en);
 820 }
 821
 822 void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
 823                                        u32 tpo_to_rpf_sys_lbk)
 824 {
 825         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR,
 826                             HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK,
 827                             HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT,
 828                             tpo_to_rpf_sys_lbk);
 829 }
 830
 831 void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
 832 {
 833         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR,
 834                             HW_ATL_RPF_VL_INNER_TPID_MSK,
 835                             HW_ATL_RPF_VL_INNER_TPID_SHIFT,
 836                             vlan_inner_etht);
 837 }
 838
 839 void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
 840 {
 841         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR,
 842                             HW_ATL_RPF_VL_OUTER_TPID_MSK,
 843                             HW_ATL_RPF_VL_OUTER_TPID_SHIFT,
 844                             vlan_outer_etht);
 845 }
 846
 847 void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
 848                                       u32 vlan_prom_mode_en)
 849 {
 850         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
 851                             HW_ATL_RPF_VL_PROMIS_MODE_MSK,
 852                             HW_ATL_RPF_VL_PROMIS_MODE_SHIFT,
 853                             vlan_prom_mode_en);
 854 }
 855
 856 void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
 857                                                  u32 vlan_acc_untagged_packets)
 858 {
 859         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR,
 860                             HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK,
 861                             HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT,
 862                             vlan_acc_untagged_packets);
 863 }
 864
 865 void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
 866                                       u32 vlan_untagged_act)
 867 {
 868         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR,
 869                             HW_ATL_RPF_VL_UNTAGGED_ACT_MSK,
 870                             HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT,
 871                             vlan_untagged_act);
 872 }
 873
 874 void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
 875                                 u32 filter)
 876 {
 877         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter),
 878                             HW_ATL_RPF_VL_EN_F_MSK,
 879                             HW_ATL_RPF_VL_EN_F_SHIFT,
 880                             vlan_flr_en);
 881 }
 882
 883 void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act,
 884                                  u32 filter)
 885 {
 886         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter),
 887                             HW_ATL_RPF_VL_ACT_F_MSK,
 888                             HW_ATL_RPF_VL_ACT_F_SHIFT,
 889                             vlan_flr_act);
 890 }
 891
 892 void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
 893                                 u32 filter)
 894 {
 895         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter),
 896                             HW_ATL_RPF_VL_ID_F_MSK,
 897                             HW_ATL_RPF_VL_ID_F_SHIFT,
 898                             vlan_id_flr);
 899 }
 900
 901 void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
 902                                 u32 filter)
 903 {
 904         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter),
 905                             HW_ATL_RPF_ET_ENF_MSK,
 906                             HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en);
 907 }
 908
 909 void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
 910                                           u32 etht_user_priority_en, u32 filter)
 911 {
 912         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter),
 913                             HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT,
 914                             etht_user_priority_en);
 915 }
 916
 917 void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
 918                                      u32 etht_rx_queue_en,
 919                                      u32 filter)
 920 {
 921         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter),
 922                             HW_ATL_RPF_ET_RXQFEN_MSK,
 923                             HW_ATL_RPF_ET_RXQFEN_SHIFT,
 924                             etht_rx_queue_en);
 925 }
 926
 927 void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
 928                                        u32 etht_user_priority,
 929                                        u32 filter)
 930 {
 931         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter),
 932                             HW_ATL_RPF_ET_UPF_MSK,
 933                             HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority);
 934 }
 935
 936 void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
 937                                   u32 filter)
 938 {
 939         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter),
 940                             HW_ATL_RPF_ET_RXQF_MSK,
 941                             HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue);
 942 }
 943
 944 void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
 945                                    u32 filter)
 946 {
 947         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter),
 948                             HW_ATL_RPF_ET_MNG_RXQF_MSK,
 949                             HW_ATL_RPF_ET_MNG_RXQF_SHIFT,
 950                             etht_mgt_queue);
 951 }
 952
 953 void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
 954                                  u32 filter)
 955 {
 956         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter),
 957                             HW_ATL_RPF_ET_ACTF_MSK,
 958                             HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act);
 959 }
 960
 961 void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
 962 {
 963         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter),
 964                             HW_ATL_RPF_ET_VALF_MSK,
 965                             HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);
 966 }
 967
 968 /* RPO: rx packet offload */
 969 void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
 970                                               u32 ipv4header_crc_offload_en)
 971 {
 972         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR,
 973                             HW_ATL_RPO_IPV4CHK_EN_MSK,
 974                             HW_ATL_RPO_IPV4CHK_EN_SHIFT,
 975                             ipv4header_crc_offload_en);
 976 }
 977
 978 void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
 979                                            u32 rx_desc_vlan_stripping,
 980                                            u32 descriptor)
 981 {
 982         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor),
 983                             HW_ATL_RPO_DESCDVL_STRIP_MSK,
 984                             HW_ATL_RPO_DESCDVL_STRIP_SHIFT,
 985                             rx_desc_vlan_stripping);
 986 }
 987
 988 void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
 989                                            u32 tcp_udp_crc_offload_en)
 990 {
 991         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR,
 992                             HW_ATL_RPOL4CHK_EN_MSK,
 993                             HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en);
 994 }
 995
 996 void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
 997 {
 998         aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en);
 999 }
1000
1001 void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
1002                                               u32 lro_patch_optimization_en)
1003 {
1004         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR,
1005                             HW_ATL_RPO_LRO_PTOPT_EN_MSK,
1006                             HW_ATL_RPO_LRO_PTOPT_EN_SHIFT,
1007                             lro_patch_optimization_en);
1008 }
1009
1010 void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
1011                                       u32 lro_qsessions_lim)
1012 {
1013         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR,
1014                             HW_ATL_RPO_LRO_QSES_LMT_MSK,
1015                             HW_ATL_RPO_LRO_QSES_LMT_SHIFT,
1016                             lro_qsessions_lim);
1017 }
1018
1019 void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
1020                                        u32 lro_total_desc_lim)
1021 {
1022         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR,
1023                             HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK,
1024                             HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT,
1025                             lro_total_desc_lim);
1026 }
1027
1028 void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
1029                                              u32 lro_min_pld_of_first_pkt)
1030 {
1031         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR,
1032                             HW_ATL_RPO_LRO_PKT_MIN_MSK,
1033                             HW_ATL_RPO_LRO_PKT_MIN_SHIFT,
1034                             lro_min_pld_of_first_pkt);
1035 }
1036
1037 void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
1038 {
1039         aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim);
1040 }
1041
1042 void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
1043                                                u32 lro_max_number_of_descriptors,
1044                                                u32 lro)
1045 {
1046 /* Register address for bitfield lro{L}_des_max[1:0] */
1047         static u32 rpo_lro_ldes_max_adr[32] = {
1048                         0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1049                         0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1050                         0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1051                         0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1052                         0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1053                         0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1054                         0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU,
1055                         0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU
1056                 };
1057
1058 /* Bitmask for bitfield lro{L}_des_max[1:0] */
1059         static u32 rpo_lro_ldes_max_msk[32] = {
1060                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1061                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1062                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1063                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1064                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1065                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1066                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1067                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U
1068                 };
1069
1070 /* Lower bit position of bitfield lro{L}_des_max[1:0] */
1071         static u32 rpo_lro_ldes_max_shift[32] = {
1072                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1073                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1074                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1075                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
1076                 };
1077
1078         aq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro],
1079                             rpo_lro_ldes_max_msk[lro],
1080                             rpo_lro_ldes_max_shift[lro],
1081                             lro_max_number_of_descriptors);
1082 }
1083
1084 void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
1085                                           u32 lro_time_base_divider)
1086 {
1087         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR,
1088                             HW_ATL_RPO_LRO_TB_DIV_MSK,
1089                             HW_ATL_RPO_LRO_TB_DIV_SHIFT,
1090                             lro_time_base_divider);
1091 }
1092
1093 void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
1094                                           u32 lro_inactive_interval)
1095 {
1096         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR,
1097                             HW_ATL_RPO_LRO_INA_IVAL_MSK,
1098                             HW_ATL_RPO_LRO_INA_IVAL_SHIFT,
1099                             lro_inactive_interval);
1100 }
1101
1102 void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
1103                                                 u32 lro_max_coal_interval)
1104 {
1105         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR,
1106                             HW_ATL_RPO_LRO_MAX_IVAL_MSK,
1107                             HW_ATL_RPO_LRO_MAX_IVAL_SHIFT,
1108                             lro_max_coal_interval);
1109 }
1110
1111 /* rx */
1112 void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
1113 {
1114         aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR,
1115                             HW_ATL_RX_REG_RES_DSBL_MSK,
1116                             HW_ATL_RX_REG_RES_DSBL_SHIFT,
1117                             rx_reg_res_dis);
1118 }
1119
1120 /* tdm */
1121 void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
1122 {
1123         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca),
1124                             HW_ATL_TDM_DCADCPUID_MSK,
1125                             HW_ATL_TDM_DCADCPUID_SHIFT, cpuid);
1126 }
1127
1128 void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
1129                                           u32 large_send_offload_en)
1130 {
1131         aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en);
1132 }
1133
1134 void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
1135 {
1136         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK,
1137                             HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en);
1138 }
1139
1140 void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
1141 {
1142         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR,
1143                             HW_ATL_TDM_DCA_MODE_MSK,
1144                             HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode);
1145 }
1146
1147 void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
1148                                    u32 dca)
1149 {
1150         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca),
1151                             HW_ATL_TDM_DCADDESC_EN_MSK,
1152                             HW_ATL_TDM_DCADDESC_EN_SHIFT,
1153                             tx_desc_dca_en);
1154 }
1155
1156 void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
1157                                u32 descriptor)
1158 {
1159         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor),
1160                             HW_ATL_TDM_DESCDEN_MSK,
1161                             HW_ATL_TDM_DESCDEN_SHIFT,
1162                             tx_desc_en);
1163 }
1164
1165 u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
1166 {
1167         return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor),
1168                                   HW_ATL_TDM_DESCDHD_MSK,
1169                                   HW_ATL_TDM_DESCDHD_SHIFT);
1170 }
1171
1172 void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
1173                                 u32 descriptor)
1174 {
1175         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor),
1176                             HW_ATL_TDM_DESCDLEN_MSK,
1177                             HW_ATL_TDM_DESCDLEN_SHIFT,
1178                             tx_desc_len);
1179 }
1180
1181 void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
1182                                          u32 tx_desc_wr_wb_irq_en)
1183 {
1184         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR,
1185                             HW_ATL_TDM_INT_DESC_WRB_EN_MSK,
1186                             HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT,
1187                             tx_desc_wr_wb_irq_en);
1188 }
1189
1190 void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
1191                                             u32 tx_desc_wr_wb_threshold,
1192                                             u32 descriptor)
1193 {
1194         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor),
1195                             HW_ATL_TDM_DESCDWRB_THRESH_MSK,
1196                             HW_ATL_TDM_DESCDWRB_THRESH_SHIFT,
1197                             tx_desc_wr_wb_threshold);
1198 }
1199
1200 void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
1201                                       u32 tdm_irq_moderation_en)
1202 {
1203         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR,
1204                             HW_ATL_TDM_INT_MOD_EN_MSK,
1205                             HW_ATL_TDM_INT_MOD_EN_SHIFT,
1206                             tdm_irq_moderation_en);
1207 }
1208
1209 /* thm */
1210 void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
1211                                               u32 lso_tcp_flag_of_first_pkt)
1212 {
1213         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR,
1214                             HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK,
1215                             HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT,
1216                             lso_tcp_flag_of_first_pkt);
1217 }
1218
1219 void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
1220                                              u32 lso_tcp_flag_of_last_pkt)
1221 {
1222         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR,
1223                             HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK,
1224                             HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT,
1225                             lso_tcp_flag_of_last_pkt);
1226 }
1227
1228 void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
1229                                                u32 lso_tcp_flag_of_middle_pkt)
1230 {
1231         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR,
1232                             HW_ATL_THM_LSO_TCP_FLAG_MID_MSK,
1233                             HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT,
1234                             lso_tcp_flag_of_middle_pkt);
1235 }
1236
1237 /* TPB: tx packet buffer */
1238 void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
1239 {
1240         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR,
1241                             HW_ATL_TPB_TX_BUF_EN_MSK,
1242                             HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);
1243 }
1244
1245 void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1246                                                 u32 tx_buff_hi_threshold_per_tc,
1247                                          u32 buffer)
1248 {
1249         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer),
1250                             HW_ATL_TPB_TXBHI_THRESH_MSK,
1251                             HW_ATL_TPB_TXBHI_THRESH_SHIFT,
1252                             tx_buff_hi_threshold_per_tc);
1253 }
1254
1255 void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1256                                                 u32 tx_buff_lo_threshold_per_tc,
1257                                          u32 buffer)
1258 {
1259         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer),
1260                             HW_ATL_TPB_TXBLO_THRESH_MSK,
1261                             HW_ATL_TPB_TXBLO_THRESH_SHIFT,
1262                             tx_buff_lo_threshold_per_tc);
1263 }
1264
1265 void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
1266 {
1267         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR,
1268                             HW_ATL_TPB_DMA_SYS_LBK_MSK,
1269                             HW_ATL_TPB_DMA_SYS_LBK_SHIFT,
1270                             tx_dma_sys_lbk_en);
1271 }
1272
1273 void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
1274                                             u32 tx_pkt_buff_size_per_tc, u32 buffer)
1275 {
1276         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),
1277                             HW_ATL_TPB_TXBBUF_SIZE_MSK,
1278                             HW_ATL_TPB_TXBBUF_SIZE_SHIFT,
1279                             tx_pkt_buff_size_per_tc);
1280 }
1281
1282 void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
1283 {
1284         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR,
1285                             HW_ATL_TPB_TX_SCP_INS_EN_MSK,
1286                             HW_ATL_TPB_TX_SCP_INS_EN_SHIFT,
1287                             tx_path_scp_ins_en);
1288 }
1289
1290 /* TPO: tx packet offload */
1291 void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1292                                               u32 ipv4header_crc_offload_en)
1293 {
1294         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR,
1295                             HW_ATL_TPO_IPV4CHK_EN_MSK,
1296                             HW_ATL_TPO_IPV4CHK_EN_SHIFT,
1297                             ipv4header_crc_offload_en);
1298 }
1299
1300 void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1301                                            u32 tcp_udp_crc_offload_en)
1302 {
1303         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR,
1304                             HW_ATL_TPOL4CHK_EN_MSK,
1305                             HW_ATL_TPOL4CHK_EN_SHIFT,
1306                             tcp_udp_crc_offload_en);
1307 }
1308
1309 void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
1310                                       u32 tx_pkt_sys_lbk_en)
1311 {
1312         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR,
1313                             HW_ATL_TPO_PKT_SYS_LBK_MSK,
1314                             HW_ATL_TPO_PKT_SYS_LBK_SHIFT,
1315                             tx_pkt_sys_lbk_en);
1316 }
1317
1318 /* TPS: tx packet scheduler */
1319 void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
1320                                               u32 tx_pkt_shed_data_arb_mode)
1321 {
1322         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR,
1323                             HW_ATL_TPS_DATA_TC_ARB_MODE_MSK,
1324                             HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT,
1325                             tx_pkt_shed_data_arb_mode);
1326 }
1327
1328 void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
1329                                                         u32 curr_time_res)
1330 {
1331         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR,
1332                             HW_ATL_TPS_DESC_RATE_TA_RST_MSK,
1333                             HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT,
1334                             curr_time_res);
1335 }
1336
1337 void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
1338                                               u32 tx_pkt_shed_desc_rate_lim)
1339 {
1340         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR,
1341                             HW_ATL_TPS_DESC_RATE_LIM_MSK,
1342                             HW_ATL_TPS_DESC_RATE_LIM_SHIFT,
1343                             tx_pkt_shed_desc_rate_lim);
1344 }
1345
1346 void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
1347                                                  u32 arb_mode)
1348 {
1349         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR,
1350                             HW_ATL_TPS_DESC_TC_ARB_MODE_MSK,
1351                             HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT,
1352                             arb_mode);
1353 }
1354
1355 void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
1356                                                    u32 max_credit,
1357                                                    u32 tc)
1358 {
1359         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc),
1360                             HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK,
1361                             HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT,
1362                             max_credit);
1363 }
1364
1365 void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
1366                                                u32 tx_pkt_shed_desc_tc_weight,
1367                                                u32 tc)
1368 {
1369         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc),
1370                             HW_ATL_TPS_DESC_TCTWEIGHT_MSK,
1371                             HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT,
1372                             tx_pkt_shed_desc_tc_weight);
1373 }
1374
1375 void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
1376                                                  u32 arb_mode)
1377 {
1378         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR,
1379                             HW_ATL_TPS_DESC_VM_ARB_MODE_MSK,
1380                             HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT,
1381                             arb_mode);
1382 }
1383
1384 void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
1385                                                    u32 max_credit,
1386                                                    u32 tc)
1387 {
1388         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
1389                             HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK,
1390                             HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT,
1391                             max_credit);
1392 }
1393
1394 void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
1395                                                u32 tx_pkt_shed_tc_data_weight,
1396                                                u32 tc)
1397 {
1398         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc),
1399                             HW_ATL_TPS_DATA_TCTWEIGHT_MSK,
1400                             HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT,
1401                             tx_pkt_shed_tc_data_weight);
1402 }
1403
1404 /* tx */
1405 void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
1406 {
1407         aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR,
1408                             HW_ATL_TX_REG_RES_DSBL_MSK,
1409                             HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis);
1410 }
1411
1412 /* msm */
1413 u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw)
1414 {
1415         return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR,
1416                                   HW_ATL_MSM_REG_ACCESS_BUSY_MSK,
1417                                   HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT);
1418 }
1419
1420 void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
1421                                                u32 reg_addr_for_indirect_addr)
1422 {
1423         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR,
1424                             HW_ATL_MSM_REG_ADDR_MSK,
1425                             HW_ATL_MSM_REG_ADDR_SHIFT,
1426                             reg_addr_for_indirect_addr);
1427 }
1428
1429 void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
1430 {
1431         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR,
1432                             HW_ATL_MSM_REG_RD_STROBE_MSK,
1433                             HW_ATL_MSM_REG_RD_STROBE_SHIFT,
1434                             reg_rd_strobe);
1435 }
1436
1437 u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
1438 {
1439         return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR);
1440 }
1441
1442 void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
1443 {
1444         aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data);
1445 }
1446
1447 void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
1448 {
1449         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR,
1450                             HW_ATL_MSM_REG_WR_STROBE_MSK,
1451                             HW_ATL_MSM_REG_WR_STROBE_SHIFT,
1452                             reg_wr_strobe);
1453 }
1454
1455 /* pci */
1456 void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
1457 {
1458         aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR,
1459                             HW_ATL_PCI_REG_RES_DSBL_MSK,
1460                             HW_ATL_PCI_REG_RES_DSBL_SHIFT,
1461                             pci_reg_res_dis);
1462 }
1463
1464 void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
1465                                         u32 glb_cpu_scratch_scp,
1466                                         u32 scratch_scp)
1467 {
1468         aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp),
1469                         glb_cpu_scratch_scp);
1470 }
1471
1472 void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr)
1473 {
1474         aq_hw_write_reg_bit(aq_hw, HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR,
1475                             HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK,
1476                             HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT,
1477                             up_force_intr);
1478 }