2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
10 /* File hw_atl_llh.h: Declarations of bitfield and register access functions for
17 #include <linux/types.h>
23 /* set global microprocessor semaphore */
24 void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
27 /* get global microprocessor semaphore */
28 u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore);
30 /* set global register reset disable */
31 void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis);
34 void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res);
37 u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw);
41 u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw);
43 /* get rx dma good octet counter lsw */
44 u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
46 /* get rx dma good packet counter lsw */
47 u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
49 /* get tx dma good octet counter lsw */
50 u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
52 /* get tx dma good packet counter lsw */
53 u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
55 /* get rx dma good octet counter msw */
56 u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
58 /* get rx dma good packet counter msw */
59 u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
61 /* get tx dma good octet counter msw */
62 u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
64 /* get tx dma good packet counter msw */
65 u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
67 /* get msm rx errors counter register */
68 u32 hw_atl_reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw);
70 /* get msm rx unicast frames counter register */
71 u32 hw_atl_reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
73 /* get msm rx multicast frames counter register */
74 u32 hw_atl_reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
76 /* get msm rx broadcast frames counter register */
77 u32 hw_atl_reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
79 /* get msm rx broadcast octets counter register 1 */
80 u32 hw_atl_reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
82 /* get msm rx unicast octets counter register 0 */
83 u32 hw_atl_reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
85 /* get rx dma statistics counter 7 */
86 u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw);
88 /* get msm tx errors counter register */
89 u32 hw_atl_reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw);
91 /* get msm tx unicast frames counter register */
92 u32 hw_atl_reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
94 /* get msm tx multicast frames counter register */
95 u32 hw_atl_reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
97 /* get msm tx broadcast frames counter register */
98 u32 hw_atl_reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
100 /* get msm tx multicast octets counter register 1 */
101 u32 hw_atl_reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw);
103 /* get msm tx broadcast octets counter register 1 */
104 u32 hw_atl_reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
106 /* get msm tx unicast octets counter register 0 */
107 u32 hw_atl_reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
109 /* get global mif identification */
110 u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw);
114 /* set interrupt auto mask lsw */
115 void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
116 u32 irq_auto_masklsw);
118 /* set interrupt mapping enable rx */
119 void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
122 /* set interrupt mapping enable tx */
123 void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
126 /* set interrupt mapping rx */
127 void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx);
129 /* set interrupt mapping tx */
130 void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx);
132 /* set interrupt mask clear lsw */
133 void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
134 u32 irq_msk_clearlsw);
136 /* set interrupt mask set lsw */
137 void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw);
139 /* set interrupt register reset disable */
140 void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis);
142 /* set interrupt status clear lsw */
143 void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
144 u32 irq_status_clearlsw);
146 /* get interrupt status lsw */
147 u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw);
149 /* get reset interrupt */
150 u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw);
152 /* set reset interrupt */
153 void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq);
158 void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
160 /* set rx dca enable */
161 void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en);
163 /* set rx dca mode */
164 void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode);
166 /* set rx descriptor data buffer size */
167 void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
168 u32 rx_desc_data_buff_size,
171 /* set rx descriptor dca enable */
172 void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
175 /* set rx descriptor enable */
176 void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
179 /* set rx descriptor header splitting */
180 void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
181 u32 rx_desc_head_splitting,
184 /* get rx descriptor head pointer */
185 u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
187 /* set rx descriptor length */
188 void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
191 /* set rx descriptor write-back interrupt enable */
192 void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
193 u32 rx_desc_wr_wb_irq_en);
195 /* set rx header dca enable */
196 void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
199 /* set rx payload dca enable */
200 void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
203 /* set rx descriptor header buffer size */
204 void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
205 u32 rx_desc_head_buff_size,
208 /* set rx descriptor reset */
209 void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
212 /* Set RDM Interrupt Moderation Enable */
213 void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
214 u32 rdm_intr_moder_en);
218 /* set general interrupt mapping register */
219 void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
222 /* get general interrupt status register */
223 u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw);
225 /* set interrupt global control register */
226 void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl);
228 /* set interrupt throttle register */
229 void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle);
231 /* set rx dma descriptor base address lsw */
232 void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
233 u32 rx_dma_desc_base_addrlsw,
236 /* set rx dma descriptor base address msw */
237 void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
238 u32 rx_dma_desc_base_addrmsw,
241 /* get rx dma descriptor status register */
242 u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor);
244 /* set rx dma descriptor tail pointer register */
245 void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
246 u32 rx_dma_desc_tail_ptr,
249 /* set rx filter multicast filter mask register */
250 void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
251 u32 rx_flr_mcst_flr_msk);
253 /* set rx filter multicast filter register */
254 void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
257 /* set rx filter rss control register 1 */
258 void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
259 u32 rx_flr_rss_control1);
261 /* Set RX Filter Control Register 2 */
262 void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_flr_control2);
264 /* Set RX Interrupt Moderation Control Register */
265 void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
266 u32 rx_intr_moderation_ctl,
269 /* set tx dma debug control */
270 void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
271 u32 tx_dma_debug_ctl);
273 /* set tx dma descriptor base address lsw */
274 void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
275 u32 tx_dma_desc_base_addrlsw,
278 /* set tx dma descriptor base address msw */
279 void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
280 u32 tx_dma_desc_base_addrmsw,
283 /* set tx dma descriptor tail pointer register */
284 void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
285 u32 tx_dma_desc_tail_ptr,
288 /* Set TX Interrupt Moderation Control Register */
289 void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
290 u32 tx_intr_moderation_ctl,
293 /* set global microprocessor scratch pad */
294 void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
295 u32 glb_cpu_scratch_scp,
300 /* set dma system loopback */
301 void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk);
303 /* set rx traffic class mode */
304 void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
305 u32 rx_traf_class_mode);
307 /* set rx buffer enable */
308 void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en);
310 /* set rx buffer high threshold (per tc) */
311 void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
312 u32 rx_buff_hi_threshold_per_tc,
315 /* set rx buffer low threshold (per tc) */
316 void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
317 u32 rx_buff_lo_threshold_per_tc,
320 /* set rx flow control mode */
321 void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode);
323 /* set rx packet buffer size (per tc) */
324 void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
325 u32 rx_pkt_buff_size_per_tc,
328 /* set rdm rx dma descriptor cache init */
329 void hw_atl_rdm_rx_dma_desc_cache_init_set(struct aq_hw_s *aq_hw, u32 init);
331 /* set rx xoff enable (per tc) */
332 void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
337 /* set l2 broadcast count threshold */
338 void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
339 u32 l2broadcast_count_threshold);
341 /* set l2 broadcast enable */
342 void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en);
344 /* set l2 broadcast filter action */
345 void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
346 u32 l2broadcast_flr_act);
348 /* set l2 multicast filter enable */
349 void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
350 u32 l2multicast_flr_en,
353 /* set l2 promiscuous mode enable */
354 void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
355 u32 l2promiscuous_mode_en);
357 /* set l2 unicast filter action */
358 void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
359 u32 l2unicast_flr_act,
362 /* set l2 unicast filter enable */
363 void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
366 /* set l2 unicast destination address lsw */
367 void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
368 u32 l2unicast_dest_addresslsw,
371 /* set l2 unicast destination address msw */
372 void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
373 u32 l2unicast_dest_addressmsw,
376 /* Set L2 Accept all Multicast packets */
377 void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
378 u32 l2_accept_all_mc_packets);
380 /* set user-priority tc mapping */
381 void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
382 u32 user_priority_tc_map, u32 tc);
384 /* set rss key address */
385 void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr);
387 /* set rss key write data */
388 void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data);
390 /* get rss key write enable */
391 u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw);
393 /* set rss key write enable */
394 void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en);
396 /* set rss redirection table address */
397 void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
398 u32 rss_redir_tbl_addr);
400 /* set rss redirection table write data */
401 void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
402 u32 rss_redir_tbl_wr_data);
404 /* get rss redirection write enable */
405 u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw);
407 /* set rss redirection write enable */
408 void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en);
410 /* set tpo to rpf system loopback */
411 void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
412 u32 tpo_to_rpf_sys_lbk);
414 /* set vlan inner ethertype */
415 void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht);
417 /* set vlan outer ethertype */
418 void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht);
420 /* set vlan promiscuous mode enable */
421 void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
422 u32 vlan_prom_mode_en);
424 /* Set VLAN untagged action */
425 void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
426 u32 vlan_untagged_act);
428 /* Set VLAN accept untagged packets */
429 void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
430 u32 vlan_acc_untagged_packets);
432 /* Set VLAN filter enable */
433 void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
436 /* Set VLAN Filter Action */
437 void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act,
440 /* Set VLAN ID Filter */
441 void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
444 /* set ethertype filter enable */
445 void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
448 /* set ethertype user-priority enable */
449 void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
450 u32 etht_user_priority_en,
453 /* set ethertype rx queue enable */
454 void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
455 u32 etht_rx_queue_en,
458 /* set ethertype rx queue */
459 void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
462 /* set ethertype user-priority */
463 void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
464 u32 etht_user_priority,
467 /* set ethertype management queue */
468 void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
471 /* set ethertype filter action */
472 void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
475 /* set ethertype filter */
476 void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter);
480 /* set ipv4 header checksum offload enable */
481 void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
482 u32 ipv4header_crc_offload_en);
484 /* set rx descriptor vlan stripping */
485 void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
486 u32 rx_desc_vlan_stripping,
489 /* set tcp/udp checksum offload enable */
490 void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
491 u32 tcp_udp_crc_offload_en);
493 /* Set LRO Patch Optimization Enable. */
494 void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
495 u32 lro_patch_optimization_en);
497 /* Set Large Receive Offload Enable */
498 void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en);
500 /* Set LRO Q Sessions Limit */
501 void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
502 u32 lro_qsessions_lim);
504 /* Set LRO Total Descriptor Limit */
505 void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
506 u32 lro_total_desc_lim);
508 /* Set LRO Min Payload of First Packet */
509 void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
510 u32 lro_min_pld_of_first_pkt);
512 /* Set LRO Packet Limit */
513 void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_packet_lim);
515 /* Set LRO Max Number of Descriptors */
516 void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
517 u32 lro_max_desc_num, u32 lro);
519 /* Set LRO Time Base Divider */
520 void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
521 u32 lro_time_base_divider);
523 /*Set LRO Inactive Interval */
524 void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
525 u32 lro_inactive_interval);
527 /*Set LRO Max Coalescing Interval */
528 void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
529 u32 lro_max_coal_interval);
533 /* set rx register reset disable */
534 void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis);
539 void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
541 /* set large send offload enable */
542 void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
543 u32 large_send_offload_en);
545 /* set tx descriptor enable */
546 void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
549 /* set tx dca enable */
550 void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en);
552 /* set tx dca mode */
553 void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode);
555 /* set tx descriptor dca enable */
556 void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
559 /* get tx descriptor head pointer */
560 u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
562 /* set tx descriptor length */
563 void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
566 /* set tx descriptor write-back interrupt enable */
567 void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
568 u32 tx_desc_wr_wb_irq_en);
570 /* set tx descriptor write-back threshold */
571 void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
572 u32 tx_desc_wr_wb_threshold,
575 /* Set TDM Interrupt Moderation Enable */
576 void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
577 u32 tdm_irq_moderation_en);
580 /* set lso tcp flag of first packet */
581 void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
582 u32 lso_tcp_flag_of_first_pkt);
584 /* set lso tcp flag of last packet */
585 void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
586 u32 lso_tcp_flag_of_last_pkt);
588 /* set lso tcp flag of middle packet */
589 void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
590 u32 lso_tcp_flag_of_middle_pkt);
594 /* set tx buffer enable */
595 void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en);
597 /* set tx buffer high threshold (per tc) */
598 void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
599 u32 tx_buff_hi_threshold_per_tc,
602 /* set tx buffer low threshold (per tc) */
603 void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
604 u32 tx_buff_lo_threshold_per_tc,
607 /* set tx dma system loopback enable */
608 void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en);
610 /* set tx packet buffer size (per tc) */
611 void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
612 u32 tx_pkt_buff_size_per_tc, u32 buffer);
614 /* set tx path pad insert enable */
615 void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en);
619 /* set ipv4 header checksum offload enable */
620 void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
621 u32 ipv4header_crc_offload_en);
623 /* set tcp/udp checksum offload enable */
624 void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
625 u32 tcp_udp_crc_offload_en);
627 /* set tx pkt system loopback enable */
628 void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
629 u32 tx_pkt_sys_lbk_en);
633 /* set tx packet scheduler data arbitration mode */
634 void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
635 u32 tx_pkt_shed_data_arb_mode);
637 /* set tx packet scheduler descriptor rate current time reset */
638 void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
641 /* set tx packet scheduler descriptor rate limit */
642 void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
643 u32 tx_pkt_shed_desc_rate_lim);
645 /* set tx packet scheduler descriptor tc arbitration mode */
646 void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
649 /* set tx packet scheduler descriptor tc max credit */
650 void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
654 /* set tx packet scheduler descriptor tc weight */
655 void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
656 u32 tx_pkt_shed_desc_tc_weight,
659 /* set tx packet scheduler descriptor vm arbitration mode */
660 void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
663 /* set tx packet scheduler tc data max credit */
664 void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
668 /* set tx packet scheduler tc data weight */
669 void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
670 u32 tx_pkt_shed_tc_data_weight,
675 /* set tx register reset disable */
676 void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis);
680 /* get register access status */
681 u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw);
683 /* set register address for indirect address */
684 void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
685 u32 reg_addr_for_indirect_addr);
687 /* set register read strobe */
688 void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe);
690 /* get register read data */
691 u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw);
693 /* set register write data */
694 void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data);
696 /* set register write strobe */
697 void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe);
701 /* set pci register reset disable */
702 void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis);
704 /* set uP Force Interrupt */
705 void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr);
707 #endif /* HW_ATL_LLH_H */