drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h

   1 /*
   2  * aQuantia Corporation Network Driver
   3  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  */
   9
  10 /* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware
  11  * abstraction layer.
  12  */
  13
  14 #ifndef HW_ATL_UTILS_H
  15 #define HW_ATL_UTILS_H
  16
  17 #define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
  18
  19 /* Hardware tx descriptor */
  20 struct __packed hw_atl_txd_s {
  21         u64 buf_addr;
  22         u32 ctl;
  23         u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
  24 };
  25
  26 /* Hardware tx context descriptor */
  27 struct __packed hw_atl_txc_s {
  28         u32 rsvd;
  29         u32 len;
  30         u32 ctl;
  31         u32 len2;
  32 };
  33
  34 /* Hardware rx descriptor */
  35 struct __packed hw_atl_rxd_s {
  36         u64 buf_addr;
  37         u64 hdr_addr;
  38 };
  39
  40 /* Hardware rx descriptor writeback */
  41 struct __packed hw_atl_rxd_wb_s {
  42         u32 type;
  43         u32 rss_hash;
  44         u16 status;
  45         u16 pkt_len;
  46         u16 next_desc_ptr;
  47         u16 vlan;
  48 };
  49
  50 struct __packed hw_atl_stats_s {
  51         u32 uprc;
  52         u32 mprc;
  53         u32 bprc;
  54         u32 erpt;
  55         u32 uptc;
  56         u32 mptc;
  57         u32 bptc;
  58         u32 erpr;
  59         u32 mbtc;
  60         u32 bbtc;
  61         u32 mbrc;
  62         u32 bbrc;
  63         u32 ubrc;
  64         u32 ubtc;
  65         u32 dpc;
  66 };
  67
  68 union __packed ip_addr {
  69         struct {
  70                 u8 addr[16];
  71         } v6;
  72         struct {
  73                 u8 padding[12];
  74                 u8 addr[4];
  75         } v4;
  76 };
  77
  78 struct __packed hw_aq_atl_utils_fw_rpc {
  79         u32 msg_id;
  80
  81         union {
  82                 struct {
  83                         u32 pong;
  84                 } msg_ping;
  85
  86                 struct {
  87                         u8 mac_addr[6];
  88                         u32 ip_addr_cnt;
  89
  90                         struct {
  91                                 union ip_addr addr;
  92                                 union ip_addr mask;
  93                         } ip[1];
  94                 } msg_arp;
  95
  96                 struct {
  97                         u32 len;
  98                         u8 packet[1514U];
  99                 } msg_inject;
 100
 101                 struct {
 102                         u32 priority;
 103                         u32 wol_packet_type;
 104                         u16 friendly_name_len;
 105                         u16 friendly_name[65];
 106                         u32 pattern_id;
 107                         u32 next_wol_pattern_offset;
 108
 109                         union {
 110                                 struct {
 111                                         u32 flags;
 112                                         u8 ipv4_source_address[4];
 113                                         u8 ipv4_dest_address[4];
 114                                         u16 tcp_source_port_number;
 115                                         u16 tcp_dest_port_number;
 116                                 } ipv4_tcp_syn_parameters;
 117
 118                                 struct {
 119                                         u32 flags;
 120                                         u8 ipv6_source_address[16];
 121                                         u8 ipv6_dest_address[16];
 122                                         u16 tcp_source_port_number;
 123                                         u16 tcp_dest_port_number;
 124                                 } ipv6_tcp_syn_parameters;
 125
 126                                 struct {
 127                                         u32 flags;
 128                                 } eapol_request_id_message_parameters;
 129
 130                                 struct {
 131                                         u32 flags;
 132                                         u32 mask_offset;
 133                                         u32 mask_size;
 134                                         u32 pattern_offset;
 135                                         u32 pattern_size;
 136                                 } wol_bit_map_pattern;
 137                         } wol_pattern;
 138                 } msg_wol;
 139
 140                 struct {
 141                         u32 is_wake_on_link_down;
 142                         u32 is_wake_on_link_up;
 143                 } msg_wolink;
 144         };
 145 };
 146
 147 struct __packed hw_aq_atl_utils_mbox_header {
 148         u32 version;
 149         u32 transaction_id;
 150         u32 error;
 151 };
 152
 153 struct __packed hw_aq_atl_utils_mbox {
 154         struct hw_aq_atl_utils_mbox_header header;
 155         struct hw_atl_stats_s stats;
 156 };
 157
 158 #define HAL_ATLANTIC_UTILS_CHIP_MIPS         0x00000001U
 159 #define HAL_ATLANTIC_UTILS_CHIP_TPO2         0x00000002U
 160 #define HAL_ATLANTIC_UTILS_CHIP_RPF2         0x00000004U
 161 #define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ       0x00000010U
 162 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0  0x01000000U
 163 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0  0x02000000U
 164 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1  0x04000000U
 165
 166 #define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
 167         self->chip_features)
 168
 169 enum hal_atl_utils_fw_state_e {
 170         MPI_DEINIT = 0,
 171         MPI_RESET = 1,
 172         MPI_INIT = 2,
 173         MPI_POWER = 4,
 174 };
 175
 176 #define HAL_ATLANTIC_RATE_10G        BIT(0)
 177 #define HAL_ATLANTIC_RATE_5G         BIT(1)
 178 #define HAL_ATLANTIC_RATE_5GSR       BIT(2)
 179 #define HAL_ATLANTIC_RATE_2GS        BIT(3)
 180 #define HAL_ATLANTIC_RATE_1G         BIT(4)
 181 #define HAL_ATLANTIC_RATE_100M       BIT(5)
 182 #define HAL_ATLANTIC_RATE_INVALID    BIT(6)
 183
 184 enum hw_atl_fw2x_rate {
 185         FW2X_RATE_100M    = 0x20,
 186         FW2X_RATE_1G      = 0x100,
 187         FW2X_RATE_2G5     = 0x200,
 188         FW2X_RATE_5G      = 0x400,
 189         FW2X_RATE_10G     = 0x800,
 190 };
 191
 192 enum hw_atl_fw2x_caps_lo {
 193         CAPS_LO_10BASET_HD = 0x00,
 194         CAPS_LO_10BASET_FD,
 195         CAPS_LO_100BASETX_HD,
 196         CAPS_LO_100BASET4_HD,
 197         CAPS_LO_100BASET2_HD,
 198         CAPS_LO_100BASETX_FD,
 199         CAPS_LO_100BASET2_FD,
 200         CAPS_LO_1000BASET_HD,
 201         CAPS_LO_1000BASET_FD,
 202         CAPS_LO_2P5GBASET_FD,
 203         CAPS_LO_5GBASET_FD,
 204         CAPS_LO_10GBASET_FD,
 205 };
 206
 207 enum hw_atl_fw2x_caps_hi {
 208         CAPS_HI_RESERVED1 = 0x00,
 209         CAPS_HI_10BASET_EEE,
 210         CAPS_HI_RESERVED2,
 211         CAPS_HI_PAUSE,
 212         CAPS_HI_ASYMMETRIC_PAUSE,
 213         CAPS_HI_100BASETX_EEE,
 214         CAPS_HI_RESERVED3,
 215         CAPS_HI_RESERVED4,
 216         CAPS_HI_1000BASET_FD_EEE,
 217         CAPS_HI_2P5GBASET_FD_EEE,
 218         CAPS_HI_5GBASET_FD_EEE,
 219         CAPS_HI_10GBASET_FD_EEE,
 220         CAPS_HI_RESERVED5,
 221         CAPS_HI_RESERVED6,
 222         CAPS_HI_RESERVED7,
 223         CAPS_HI_RESERVED8,
 224         CAPS_HI_RESERVED9,
 225         CAPS_HI_CABLE_DIAG,
 226         CAPS_HI_TEMPERATURE,
 227         CAPS_HI_DOWNSHIFT,
 228         CAPS_HI_PTP_AVB_EN,
 229         CAPS_HI_MEDIA_DETECT,
 230         CAPS_HI_LINK_DROP,
 231         CAPS_HI_SLEEP_PROXY,
 232         CAPS_HI_WOL,
 233         CAPS_HI_MAC_STOP,
 234         CAPS_HI_EXT_LOOPBACK,
 235         CAPS_HI_INT_LOOPBACK,
 236         CAPS_HI_EFUSE_AGENT,
 237         CAPS_HI_WOL_TIMER,
 238         CAPS_HI_STATISTICS,
 239         CAPS_HI_TRANSACTION_ID,
 240 };
 241
 242 enum hw_atl_fw2x_ctrl {
 243         CTRL_RESERVED1 = 0x00,
 244         CTRL_RESERVED2,
 245         CTRL_RESERVED3,
 246         CTRL_PAUSE,
 247         CTRL_ASYMMETRIC_PAUSE,
 248         CTRL_RESERVED4,
 249         CTRL_RESERVED5,
 250         CTRL_RESERVED6,
 251         CTRL_1GBASET_FD_EEE,
 252         CTRL_2P5GBASET_FD_EEE,
 253         CTRL_5GBASET_FD_EEE,
 254         CTRL_10GBASET_FD_EEE,
 255         CTRL_THERMAL_SHUTDOWN,
 256         CTRL_PHY_LOGS,
 257         CTRL_EEE_AUTO_DISABLE,
 258         CTRL_PFC,
 259         CTRL_WAKE_ON_LINK,
 260         CTRL_CABLE_DIAG,
 261         CTRL_TEMPERATURE,
 262         CTRL_DOWNSHIFT,
 263         CTRL_PTP_AVB,
 264         CTRL_RESERVED7,
 265         CTRL_LINK_DROP,
 266         CTRL_SLEEP_PROXY,
 267         CTRL_WOL,
 268         CTRL_MAC_STOP,
 269         CTRL_EXT_LOOPBACK,
 270         CTRL_INT_LOOPBACK,
 271         CTRL_RESERVED8,
 272         CTRL_WOL_TIMER,
 273         CTRL_STATISTICS,
 274         CTRL_FORCE_RECONNECT,
 275 };
 276
 277 struct aq_hw_s;
 278 struct aq_fw_ops;
 279 struct aq_hw_caps_s;
 280 struct aq_hw_link_status_s;
 281
 282 int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops);
 283
 284 int hw_atl_utils_soft_reset(struct aq_hw_s *self);
 285
 286 void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
 287
 288 int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
 289                                struct hw_aq_atl_utils_mbox_header *pmbox);
 290
 291 void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
 292                                  struct hw_aq_atl_utils_mbox *pmbox);
 293
 294 void hw_atl_utils_mpi_set(struct aq_hw_s *self,
 295                           enum hal_atl_utils_fw_state_e state,
 296                           u32 speed);
 297
 298 int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self);
 299
 300 int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
 301                                    u8 *mac);
 302
 303 unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps);
 304
 305 int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
 306                              const struct aq_hw_caps_s *aq_hw_caps,
 307                              u32 *regs_buff);
 308
 309 int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
 310                               unsigned int power_state);
 311
 312 int hw_atl_utils_hw_deinit(struct aq_hw_s *self);
 313
 314 int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
 315
 316 int hw_atl_utils_update_stats(struct aq_hw_s *self);
 317
 318 struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self);
 319 int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
 320                                   u32 *p, u32 cnt);
 321
 322 int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size);
 323
 324 int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
 325                              struct hw_aq_atl_utils_fw_rpc **rpc);
 326
 327 extern const struct aq_fw_ops aq_fw_1x_ops;
 328 extern const struct aq_fw_ops aq_fw_2x_ops;
 329
 330 #endif /* HW_ATL_UTILS_H */