2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
10 /* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
11 * Atlantic hardware abstraction layer.
15 #include "../aq_hw_utils.h"
16 #include "../aq_pci_func.h"
17 #include "../aq_ring.h"
18 #include "../aq_vec.h"
19 #include "hw_atl_utils.h"
20 #include "hw_atl_llh.h"
22 #define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
23 #define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
24 #define HW_ATL_FW2X_MPI_RPC_ADDR 0x334
26 #define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
27 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
29 #define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
30 #define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
32 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
33 static int aq_fw2x_set_state(struct aq_hw_s *self,
34 enum hal_atl_utils_fw_state_e state);
36 static int aq_fw2x_init(struct aq_hw_s *self)
40 /* check 10 times by 1ms */
41 AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
42 aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)),
44 AQ_HW_WAIT_FOR(0U != (self->rpc_addr =
45 aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)),
51 static int aq_fw2x_deinit(struct aq_hw_s *self)
53 int err = aq_fw2x_set_link_speed(self, 0);
56 err = aq_fw2x_set_state(self, MPI_DEINIT);
61 static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
63 enum hw_atl_fw2x_rate rate = 0;
65 if (speed & AQ_NIC_RATE_10G)
66 rate |= FW2X_RATE_10G;
68 if (speed & AQ_NIC_RATE_5G)
71 if (speed & AQ_NIC_RATE_5GSR)
74 if (speed & AQ_NIC_RATE_2GS)
75 rate |= FW2X_RATE_2G5;
77 if (speed & AQ_NIC_RATE_1G)
80 if (speed & AQ_NIC_RATE_100M)
81 rate |= FW2X_RATE_100M;
86 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
88 u32 val = link_speed_mask_2fw2x_ratemask(speed);
90 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
95 static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)
97 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)
98 *mpi_state |= BIT(CAPS_HI_PAUSE);
100 *mpi_state &= ~BIT(CAPS_HI_PAUSE);
102 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)
103 *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);
105 *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);
108 static int aq_fw2x_set_state(struct aq_hw_s *self,
109 enum hal_atl_utils_fw_state_e state)
111 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
115 mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
116 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
119 mpi_state |= BIT(CAPS_HI_LINK_DROP);
126 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
130 static int aq_fw2x_update_link_status(struct aq_hw_s *self)
132 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
133 u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
134 FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
135 struct aq_hw_link_status_s *link_status = &self->aq_link_status;
138 if (speed & FW2X_RATE_10G)
139 link_status->mbps = 10000;
140 else if (speed & FW2X_RATE_5G)
141 link_status->mbps = 5000;
142 else if (speed & FW2X_RATE_2G5)
143 link_status->mbps = 2500;
144 else if (speed & FW2X_RATE_1G)
145 link_status->mbps = 1000;
146 else if (speed & FW2X_RATE_100M)
147 link_status->mbps = 100;
149 link_status->mbps = 10000;
151 link_status->mbps = 0;
157 static int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
162 u32 mac_addr[2] = { 0 };
163 u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
165 if (efuse_addr != 0) {
166 err = hw_atl_utils_fw_downld_dwords(self,
167 efuse_addr + (40U * 4U),
169 ARRAY_SIZE(mac_addr));
172 mac_addr[0] = __swab32(mac_addr[0]);
173 mac_addr[1] = __swab32(mac_addr[1]);
176 ether_addr_copy(mac, (u8 *)mac_addr);
178 if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
179 unsigned int rnd = 0;
181 get_random_bytes(&rnd, sizeof(unsigned int));
188 mac[5] = (u8)(0xFFU & l);
190 mac[4] = (u8)(0xFFU & l);
192 mac[3] = (u8)(0xFFU & l);
194 mac[2] = (u8)(0xFFU & l);
195 mac[1] = (u8)(0xFFU & h);
197 mac[0] = (u8)(0xFFU & h);
202 static int aq_fw2x_update_stats(struct aq_hw_s *self)
205 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
206 u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
208 /* Toggle statistics bit for FW to update */
209 mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
210 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
212 /* Wait FW to report back */
213 AQ_HW_WAIT_FOR(orig_stats_val !=
214 (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
215 BIT(CAPS_HI_STATISTICS)),
220 return hw_atl_utils_update_stats(self);
223 static int aq_fw2x_renegotiate(struct aq_hw_s *self)
225 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
227 mpi_opts |= BIT(CTRL_FORCE_RECONNECT);
229 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
234 static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
236 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
238 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
240 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
245 const struct aq_fw_ops aq_fw_2x_ops = {
246 .init = aq_fw2x_init,
247 .deinit = aq_fw2x_deinit,
249 .renegotiate = aq_fw2x_renegotiate,
250 .get_mac_permanent = aq_fw2x_get_mac_permanent,
251 .set_link_speed = aq_fw2x_set_link_speed,
252 .set_state = aq_fw2x_set_state,
253 .update_link_status = aq_fw2x_update_link_status,
254 .update_stats = aq_fw2x_update_stats,
255 .set_flow_control = aq_fw2x_set_flow_control,