drivers/net/ethernet/broadcom/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/crc32.h>
  29 #include <linux/err.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/if_vlan.h>
  33
  34 #include <bcm63xx_dev_enet.h>
  35 #include "bcm63xx_enet.h"
  36
  37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  38 static char bcm_enet_driver_version[] = "1.0";
  39
  40 static int copybreak __read_mostly = 128;
  41 module_param(copybreak, int, 0);
  42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  43
  44 /* io registers memory shared between all devices */
  45 static void __iomem *bcm_enet_shared_base[3];
  46
  47 /*
  48  * io helpers to access mac registers
  49  */
  50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  51 {
  52         return bcm_readl(priv->base + off);
  53 }
  54
  55 static inline void enet_writel(struct bcm_enet_priv *priv,
  56                                u32 val, u32 off)
  57 {
  58         bcm_writel(val, priv->base + off);
  59 }
  60
  61 /*
  62  * io helpers to access switch registers
  63  */
  64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
  65 {
  66         return bcm_readl(priv->base + off);
  67 }
  68
  69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
  70                                  u32 val, u32 off)
  71 {
  72         bcm_writel(val, priv->base + off);
  73 }
  74
  75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
  76 {
  77         return bcm_readw(priv->base + off);
  78 }
  79
  80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
  81                                  u16 val, u32 off)
  82 {
  83         bcm_writew(val, priv->base + off);
  84 }
  85
  86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
  87 {
  88         return bcm_readb(priv->base + off);
  89 }
  90
  91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
  92                                  u8 val, u32 off)
  93 {
  94         bcm_writeb(val, priv->base + off);
  95 }
  96
  97
  98 /* io helpers to access shared registers */
  99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
 100 {
 101         return bcm_readl(bcm_enet_shared_base[0] + off);
 102 }
 103
 104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
 105                                        u32 val, u32 off)
 106 {
 107         bcm_writel(val, bcm_enet_shared_base[0] + off);
 108 }
 109
 110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 111 {
 112         return bcm_readl(bcm_enet_shared_base[1] +
 113                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 114 }
 115
 116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 117                                        u32 val, u32 off, int chan)
 118 {
 119         bcm_writel(val, bcm_enet_shared_base[1] +
 120                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 121 }
 122
 123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 124 {
 125         return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 126 }
 127
 128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 129                                        u32 val, u32 off, int chan)
 130 {
 131         bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 132 }
 133
 134 /*
 135  * write given data into mii register and wait for transfer to end
 136  * with timeout (average measured transfer time is 25us)
 137  */
 138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
 139 {
 140         int limit;
 141
 142         /* make sure mii interrupt status is cleared */
 143         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
 144
 145         enet_writel(priv, data, ENET_MIIDATA_REG);
 146         wmb();
 147
 148         /* busy wait on mii interrupt bit, with timeout */
 149         limit = 1000;
 150         do {
 151                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
 152                         break;
 153                 udelay(1);
 154         } while (limit-- > 0);
 155
 156         return (limit < 0) ? 1 : 0;
 157 }
 158
 159 /*
 160  * MII internal read callback
 161  */
 162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 163                               int regnum)
 164 {
 165         u32 tmp, val;
 166
 167         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 168         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 169         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 170         tmp |= ENET_MIIDATA_OP_READ_MASK;
 171
 172         if (do_mdio_op(priv, tmp))
 173                 return -1;
 174
 175         val = enet_readl(priv, ENET_MIIDATA_REG);
 176         val &= 0xffff;
 177         return val;
 178 }
 179
 180 /*
 181  * MII internal write callback
 182  */
 183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 184                                int regnum, u16 value)
 185 {
 186         u32 tmp;
 187
 188         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 189         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 190         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 191         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 192         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 193
 194         (void)do_mdio_op(priv, tmp);
 195         return 0;
 196 }
 197
 198 /*
 199  * MII read callback from phylib
 200  */
 201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 202                                      int regnum)
 203 {
 204         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 205 }
 206
 207 /*
 208  * MII write callback from phylib
 209  */
 210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 211                                       int regnum, u16 value)
 212 {
 213         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 214 }
 215
 216 /*
 217  * MII read callback from mii core
 218  */
 219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 220                                   int regnum)
 221 {
 222         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 223 }
 224
 225 /*
 226  * MII write callback from mii core
 227  */
 228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 229                                     int regnum, int value)
 230 {
 231         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 232 }
 233
 234 /*
 235  * refill rx queue
 236  */
 237 static int bcm_enet_refill_rx(struct net_device *dev)
 238 {
 239         struct bcm_enet_priv *priv;
 240
 241         priv = netdev_priv(dev);
 242
 243         while (priv->rx_desc_count < priv->rx_ring_size) {
 244                 struct bcm_enet_desc *desc;
 245                 struct sk_buff *skb;
 246                 dma_addr_t p;
 247                 int desc_idx;
 248                 u32 len_stat;
 249
 250                 desc_idx = priv->rx_dirty_desc;
 251                 desc = &priv->rx_desc_cpu[desc_idx];
 252
 253                 if (!priv->rx_skb[desc_idx]) {
 254                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 255                         if (!skb)
 256                                 break;
 257                         priv->rx_skb[desc_idx] = skb;
 258                         p = dma_map_single(&priv->pdev->dev, skb->data,
 259                                            priv->rx_skb_size,
 260                                            DMA_FROM_DEVICE);
 261                         desc->address = p;
 262                 }
 263
 264                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 265                 len_stat |= DMADESC_OWNER_MASK;
 266                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 267                         len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 268                         priv->rx_dirty_desc = 0;
 269                 } else {
 270                         priv->rx_dirty_desc++;
 271                 }
 272                 wmb();
 273                 desc->len_stat = len_stat;
 274
 275                 priv->rx_desc_count++;
 276
 277                 /* tell dma engine we allocated one buffer */
 278                 if (priv->dma_has_sram)
 279                         enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 280                 else
 281                         enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 282         }
 283
 284         /* If rx ring is still empty, set a timer to try allocating
 285          * again at a later time. */
 286         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 287                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 288                 priv->rx_timeout.expires = jiffies + HZ;
 289                 add_timer(&priv->rx_timeout);
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * timer callback to defer refill rx queue in case we're OOM
 297  */
 298 static void bcm_enet_refill_rx_timer(unsigned long data)
 299 {
 300         struct net_device *dev;
 301         struct bcm_enet_priv *priv;
 302
 303         dev = (struct net_device *)data;
 304         priv = netdev_priv(dev);
 305
 306         spin_lock(&priv->rx_lock);
 307         bcm_enet_refill_rx((struct net_device *)data);
 308         spin_unlock(&priv->rx_lock);
 309 }
 310
 311 /*
 312  * extract packet from rx queue
 313  */
 314 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 315 {
 316         struct bcm_enet_priv *priv;
 317         struct device *kdev;
 318         int processed;
 319
 320         priv = netdev_priv(dev);
 321         kdev = &priv->pdev->dev;
 322         processed = 0;
 323
 324         /* don't scan ring further than number of refilled
 325          * descriptor */
 326         if (budget > priv->rx_desc_count)
 327                 budget = priv->rx_desc_count;
 328
 329         do {
 330                 struct bcm_enet_desc *desc;
 331                 struct sk_buff *skb;
 332                 int desc_idx;
 333                 u32 len_stat;
 334                 unsigned int len;
 335
 336                 desc_idx = priv->rx_curr_desc;
 337                 desc = &priv->rx_desc_cpu[desc_idx];
 338
 339                 /* make sure we actually read the descriptor status at
 340                  * each loop */
 341                 rmb();
 342
 343                 len_stat = desc->len_stat;
 344
 345                 /* break if dma ownership belongs to hw */
 346                 if (len_stat & DMADESC_OWNER_MASK)
 347                         break;
 348
 349                 processed++;
 350                 priv->rx_curr_desc++;
 351                 if (priv->rx_curr_desc == priv->rx_ring_size)
 352                         priv->rx_curr_desc = 0;
 353                 priv->rx_desc_count--;
 354
 355                 /* if the packet does not have start of packet _and_
 356                  * end of packet flag set, then just recycle it */
 357                 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 358                         (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 359                         dev->stats.rx_dropped++;
 360                         continue;
 361                 }
 362
 363                 /* recycle packet if it's marked as bad */
 364                 if (!priv->enet_is_sw &&
 365                     unlikely(len_stat & DMADESC_ERR_MASK)) {
 366                         dev->stats.rx_errors++;
 367
 368                         if (len_stat & DMADESC_OVSIZE_MASK)
 369                                 dev->stats.rx_length_errors++;
 370                         if (len_stat & DMADESC_CRC_MASK)
 371                                 dev->stats.rx_crc_errors++;
 372                         if (len_stat & DMADESC_UNDER_MASK)
 373                                 dev->stats.rx_frame_errors++;
 374                         if (len_stat & DMADESC_OV_MASK)
 375                                 dev->stats.rx_fifo_errors++;
 376                         continue;
 377                 }
 378
 379                 /* valid packet */
 380                 skb = priv->rx_skb[desc_idx];
 381                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 382                 /* don't include FCS */
 383                 len -= 4;
 384
 385                 if (len < copybreak) {
 386                         struct sk_buff *nskb;
 387
 388                         nskb = napi_alloc_skb(&priv->napi, len);
 389                         if (!nskb) {
 390                                 /* forget packet, just rearm desc */
 391                                 dev->stats.rx_dropped++;
 392                                 continue;
 393                         }
 394
 395                         dma_sync_single_for_cpu(kdev, desc->address,
 396                                                 len, DMA_FROM_DEVICE);
 397                         memcpy(nskb->data, skb->data, len);
 398                         dma_sync_single_for_device(kdev, desc->address,
 399                                                    len, DMA_FROM_DEVICE);
 400                         skb = nskb;
 401                 } else {
 402                         dma_unmap_single(&priv->pdev->dev, desc->address,
 403                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 404                         priv->rx_skb[desc_idx] = NULL;
 405                 }
 406
 407                 skb_put(skb, len);
 408                 skb->protocol = eth_type_trans(skb, dev);
 409                 dev->stats.rx_packets++;
 410                 dev->stats.rx_bytes += len;
 411                 netif_receive_skb(skb);
 412
 413         } while (--budget > 0);
 414
 415         if (processed || !priv->rx_desc_count) {
 416                 bcm_enet_refill_rx(dev);
 417
 418                 /* kick rx dma */
 419                 enet_dmac_writel(priv, priv->dma_chan_en_mask,
 420                                          ENETDMAC_CHANCFG, priv->rx_chan);
 421         }
 422
 423         return processed;
 424 }
 425
 426
 427 /*
 428  * try to or force reclaim of transmitted buffers
 429  */
 430 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 431 {
 432         struct bcm_enet_priv *priv;
 433         int released;
 434
 435         priv = netdev_priv(dev);
 436         released = 0;
 437
 438         while (priv->tx_desc_count < priv->tx_ring_size) {
 439                 struct bcm_enet_desc *desc;
 440                 struct sk_buff *skb;
 441
 442                 /* We run in a bh and fight against start_xmit, which
 443                  * is called with bh disabled  */
 444                 spin_lock(&priv->tx_lock);
 445
 446                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 447
 448                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 449                         spin_unlock(&priv->tx_lock);
 450                         break;
 451                 }
 452
 453                 /* ensure other field of the descriptor were not read
 454                  * before we checked ownership */
 455                 rmb();
 456
 457                 skb = priv->tx_skb[priv->tx_dirty_desc];
 458                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 459                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 460                                  DMA_TO_DEVICE);
 461
 462                 priv->tx_dirty_desc++;
 463                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 464                         priv->tx_dirty_desc = 0;
 465                 priv->tx_desc_count++;
 466
 467                 spin_unlock(&priv->tx_lock);
 468
 469                 if (desc->len_stat & DMADESC_UNDER_MASK)
 470                         dev->stats.tx_errors++;
 471
 472                 dev_kfree_skb(skb);
 473                 released++;
 474         }
 475
 476         if (netif_queue_stopped(dev) && released)
 477                 netif_wake_queue(dev);
 478
 479         return released;
 480 }
 481
 482 /*
 483  * poll func, called by network core
 484  */
 485 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 486 {
 487         struct bcm_enet_priv *priv;
 488         struct net_device *dev;
 489         int rx_work_done;
 490
 491         priv = container_of(napi, struct bcm_enet_priv, napi);
 492         dev = priv->net_dev;
 493
 494         /* ack interrupts */
 495         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 496                          ENETDMAC_IR, priv->rx_chan);
 497         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 498                          ENETDMAC_IR, priv->tx_chan);
 499
 500         /* reclaim sent skb */
 501         bcm_enet_tx_reclaim(dev, 0);
 502
 503         spin_lock(&priv->rx_lock);
 504         rx_work_done = bcm_enet_receive_queue(dev, budget);
 505         spin_unlock(&priv->rx_lock);
 506
 507         if (rx_work_done >= budget) {
 508                 /* rx queue is not yet empty/clean */
 509                 return rx_work_done;
 510         }
 511
 512         /* no more packet in rx/tx queue, remove device from poll
 513          * queue */
 514         napi_complete(napi);
 515
 516         /* restore rx/tx interrupt */
 517         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 518                          ENETDMAC_IRMASK, priv->rx_chan);
 519         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 520                          ENETDMAC_IRMASK, priv->tx_chan);
 521
 522         return rx_work_done;
 523 }
 524
 525 /*
 526  * mac interrupt handler
 527  */
 528 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 529 {
 530         struct net_device *dev;
 531         struct bcm_enet_priv *priv;
 532         u32 stat;
 533
 534         dev = dev_id;
 535         priv = netdev_priv(dev);
 536
 537         stat = enet_readl(priv, ENET_IR_REG);
 538         if (!(stat & ENET_IR_MIB))
 539                 return IRQ_NONE;
 540
 541         /* clear & mask interrupt */
 542         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 543         enet_writel(priv, 0, ENET_IRMASK_REG);
 544
 545         /* read mib registers in workqueue */
 546         schedule_work(&priv->mib_update_task);
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 /*
 552  * rx/tx dma interrupt handler
 553  */
 554 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 555 {
 556         struct net_device *dev;
 557         struct bcm_enet_priv *priv;
 558
 559         dev = dev_id;
 560         priv = netdev_priv(dev);
 561
 562         /* mask rx/tx interrupts */
 563         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 564         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 565
 566         napi_schedule(&priv->napi);
 567
 568         return IRQ_HANDLED;
 569 }
 570
 571 /*
 572  * tx request callback
 573  */
 574 static netdev_tx_t
 575 bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 576 {
 577         struct bcm_enet_priv *priv;
 578         struct bcm_enet_desc *desc;
 579         u32 len_stat;
 580         netdev_tx_t ret;
 581
 582         priv = netdev_priv(dev);
 583
 584         /* lock against tx reclaim */
 585         spin_lock(&priv->tx_lock);
 586
 587         /* make sure  the tx hw queue  is not full,  should not happen
 588          * since we stop queue before it's the case */
 589         if (unlikely(!priv->tx_desc_count)) {
 590                 netif_stop_queue(dev);
 591                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 592                         "available?\n");
 593                 ret = NETDEV_TX_BUSY;
 594                 goto out_unlock;
 595         }
 596
 597         /* pad small packets sent on a switch device */
 598         if (priv->enet_is_sw && skb->len < 64) {
 599                 int needed = 64 - skb->len;
 600                 char *data;
 601
 602                 if (unlikely(skb_tailroom(skb) < needed)) {
 603                         struct sk_buff *nskb;
 604
 605                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 606                         if (!nskb) {
 607                                 ret = NETDEV_TX_BUSY;
 608                                 goto out_unlock;
 609                         }
 610                         dev_kfree_skb(skb);
 611                         skb = nskb;
 612                 }
 613                 data = skb_put(skb, needed);
 614                 memset(data, 0, needed);
 615         }
 616
 617         /* point to the next available desc */
 618         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 619         priv->tx_skb[priv->tx_curr_desc] = skb;
 620
 621         /* fill descriptor */
 622         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 623                                        DMA_TO_DEVICE);
 624
 625         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 626         len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 627                 DMADESC_APPEND_CRC |
 628                 DMADESC_OWNER_MASK;
 629
 630         priv->tx_curr_desc++;
 631         if (priv->tx_curr_desc == priv->tx_ring_size) {
 632                 priv->tx_curr_desc = 0;
 633                 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 634         }
 635         priv->tx_desc_count--;
 636
 637         /* dma might be already polling, make sure we update desc
 638          * fields in correct order */
 639         wmb();
 640         desc->len_stat = len_stat;
 641         wmb();
 642
 643         /* kick tx dma */
 644         enet_dmac_writel(priv, priv->dma_chan_en_mask,
 645                                  ENETDMAC_CHANCFG, priv->tx_chan);
 646
 647         /* stop queue if no more desc available */
 648         if (!priv->tx_desc_count)
 649                 netif_stop_queue(dev);
 650
 651         dev->stats.tx_bytes += skb->len;
 652         dev->stats.tx_packets++;
 653         ret = NETDEV_TX_OK;
 654
 655 out_unlock:
 656         spin_unlock(&priv->tx_lock);
 657         return ret;
 658 }
 659
 660 /*
 661  * Change the interface's mac address.
 662  */
 663 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 664 {
 665         struct bcm_enet_priv *priv;
 666         struct sockaddr *addr = p;
 667         u32 val;
 668
 669         priv = netdev_priv(dev);
 670         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 671
 672         /* use perfect match register 0 to store my mac address */
 673         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 674                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 675         enet_writel(priv, val, ENET_PML_REG(0));
 676
 677         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 678         val |= ENET_PMH_DATAVALID_MASK;
 679         enet_writel(priv, val, ENET_PMH_REG(0));
 680
 681         return 0;
 682 }
 683
 684 /*
 685  * Change rx mode (promiscuous/allmulti) and update multicast list
 686  */
 687 static void bcm_enet_set_multicast_list(struct net_device *dev)
 688 {
 689         struct bcm_enet_priv *priv;
 690         struct netdev_hw_addr *ha;
 691         u32 val;
 692         int i;
 693
 694         priv = netdev_priv(dev);
 695
 696         val = enet_readl(priv, ENET_RXCFG_REG);
 697
 698         if (dev->flags & IFF_PROMISC)
 699                 val |= ENET_RXCFG_PROMISC_MASK;
 700         else
 701                 val &= ~ENET_RXCFG_PROMISC_MASK;
 702
 703         /* only 3 perfect match registers left, first one is used for
 704          * own mac address */
 705         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 706                 val |= ENET_RXCFG_ALLMCAST_MASK;
 707         else
 708                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 709
 710         /* no need to set perfect match registers if we catch all
 711          * multicast */
 712         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 713                 enet_writel(priv, val, ENET_RXCFG_REG);
 714                 return;
 715         }
 716
 717         i = 0;
 718         netdev_for_each_mc_addr(ha, dev) {
 719                 u8 *dmi_addr;
 720                 u32 tmp;
 721
 722                 if (i == 3)
 723                         break;
 724                 /* update perfect match registers */
 725                 dmi_addr = ha->addr;
 726                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 727                         (dmi_addr[4] << 8) | dmi_addr[5];
 728                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 729
 730                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 731                 tmp |= ENET_PMH_DATAVALID_MASK;
 732                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 733         }
 734
 735         for (; i < 3; i++) {
 736                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 737                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 738         }
 739
 740         enet_writel(priv, val, ENET_RXCFG_REG);
 741 }
 742
 743 /*
 744  * set mac duplex parameters
 745  */
 746 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 747 {
 748         u32 val;
 749
 750         val = enet_readl(priv, ENET_TXCTL_REG);
 751         if (fullduplex)
 752                 val |= ENET_TXCTL_FD_MASK;
 753         else
 754                 val &= ~ENET_TXCTL_FD_MASK;
 755         enet_writel(priv, val, ENET_TXCTL_REG);
 756 }
 757
 758 /*
 759  * set mac flow control parameters
 760  */
 761 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 762 {
 763         u32 val;
 764
 765         /* rx flow control (pause frame handling) */
 766         val = enet_readl(priv, ENET_RXCFG_REG);
 767         if (rx_en)
 768                 val |= ENET_RXCFG_ENFLOW_MASK;
 769         else
 770                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 771         enet_writel(priv, val, ENET_RXCFG_REG);
 772
 773         if (!priv->dma_has_sram)
 774                 return;
 775
 776         /* tx flow control (pause frame generation) */
 777         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 778         if (tx_en)
 779                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 780         else
 781                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 782         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 783 }
 784
 785 /*
 786  * link changed callback (from phylib)
 787  */
 788 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 789 {
 790         struct bcm_enet_priv *priv;
 791         struct phy_device *phydev;
 792         int status_changed;
 793
 794         priv = netdev_priv(dev);
 795         phydev = dev->phydev;
 796         status_changed = 0;
 797
 798         if (priv->old_link != phydev->link) {
 799                 status_changed = 1;
 800                 priv->old_link = phydev->link;
 801         }
 802
 803         /* reflect duplex change in mac configuration */
 804         if (phydev->link && phydev->duplex != priv->old_duplex) {
 805                 bcm_enet_set_duplex(priv,
 806                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 807                 status_changed = 1;
 808                 priv->old_duplex = phydev->duplex;
 809         }
 810
 811         /* enable flow control if remote advertise it (trust phylib to
 812          * check that duplex is full */
 813         if (phydev->link && phydev->pause != priv->old_pause) {
 814                 int rx_pause_en, tx_pause_en;
 815
 816                 if (phydev->pause) {
 817                         /* pause was advertised by lpa and us */
 818                         rx_pause_en = 1;
 819                         tx_pause_en = 1;
 820                 } else if (!priv->pause_auto) {
 821                         /* pause setting overrided by user */
 822                         rx_pause_en = priv->pause_rx;
 823                         tx_pause_en = priv->pause_tx;
 824                 } else {
 825                         rx_pause_en = 0;
 826                         tx_pause_en = 0;
 827                 }
 828
 829                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 830                 status_changed = 1;
 831                 priv->old_pause = phydev->pause;
 832         }
 833
 834         if (status_changed) {
 835                 pr_info("%s: link %s", dev->name, phydev->link ?
 836                         "UP" : "DOWN");
 837                 if (phydev->link)
 838                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 839                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 840                                phydev->pause == 1 ? "rx&tx" : "off");
 841
 842                 pr_cont("\n");
 843         }
 844 }
 845
 846 /*
 847  * link changed callback (if phylib is not used)
 848  */
 849 static void bcm_enet_adjust_link(struct net_device *dev)
 850 {
 851         struct bcm_enet_priv *priv;
 852
 853         priv = netdev_priv(dev);
 854         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 855         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 856         netif_carrier_on(dev);
 857
 858         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 859                 dev->name,
 860                 priv->force_speed_100 ? 100 : 10,
 861                 priv->force_duplex_full ? "full" : "half",
 862                 priv->pause_rx ? "rx" : "off",
 863                 priv->pause_tx ? "tx" : "off");
 864 }
 865
 866 /*
 867  * open callback, allocate dma rings & buffers and start rx operation
 868  */
 869 static int bcm_enet_open(struct net_device *dev)
 870 {
 871         struct bcm_enet_priv *priv;
 872         struct sockaddr addr;
 873         struct device *kdev;
 874         struct phy_device *phydev;
 875         int i, ret;
 876         unsigned int size;
 877         char phy_id[MII_BUS_ID_SIZE + 3];
 878         void *p;
 879         u32 val;
 880
 881         priv = netdev_priv(dev);
 882         kdev = &priv->pdev->dev;
 883
 884         if (priv->has_phy) {
 885                 /* connect to PHY */
 886                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 887                          priv->mii_bus->id, priv->phy_id);
 888
 889                 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
 890                                      PHY_INTERFACE_MODE_MII);
 891
 892                 if (IS_ERR(phydev)) {
 893                         dev_err(kdev, "could not attach to PHY\n");
 894                         return PTR_ERR(phydev);
 895                 }
 896
 897                 /* mask with MAC supported features */
 898                 phydev->supported &= (SUPPORTED_10baseT_Half |
 899                                       SUPPORTED_10baseT_Full |
 900                                       SUPPORTED_100baseT_Half |
 901                                       SUPPORTED_100baseT_Full |
 902                                       SUPPORTED_Autoneg |
 903                                       SUPPORTED_Pause |
 904                                       SUPPORTED_MII);
 905                 phydev->advertising = phydev->supported;
 906
 907                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 908                         phydev->advertising |= SUPPORTED_Pause;
 909                 else
 910                         phydev->advertising &= ~SUPPORTED_Pause;
 911
 912                 phy_attached_info(phydev);
 913
 914                 priv->old_link = 0;
 915                 priv->old_duplex = -1;
 916                 priv->old_pause = -1;
 917         } else {
 918                 phydev = NULL;
 919         }
 920
 921         /* mask all interrupts and request them */
 922         enet_writel(priv, 0, ENET_IRMASK_REG);
 923         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 924         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 925
 926         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 927         if (ret)
 928                 goto out_phy_disconnect;
 929
 930         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
 931                           dev->name, dev);
 932         if (ret)
 933                 goto out_freeirq;
 934
 935         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 936                           0, dev->name, dev);
 937         if (ret)
 938                 goto out_freeirq_rx;
 939
 940         /* initialize perfect match registers */
 941         for (i = 0; i < 4; i++) {
 942                 enet_writel(priv, 0, ENET_PML_REG(i));
 943                 enet_writel(priv, 0, ENET_PMH_REG(i));
 944         }
 945
 946         /* write device mac address */
 947         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 948         bcm_enet_set_mac_address(dev, &addr);
 949
 950         /* allocate rx dma ring */
 951         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 952         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 953         if (!p) {
 954                 ret = -ENOMEM;
 955                 goto out_freeirq_tx;
 956         }
 957
 958         priv->rx_desc_alloc_size = size;
 959         priv->rx_desc_cpu = p;
 960
 961         /* allocate tx dma ring */
 962         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 963         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 964         if (!p) {
 965                 ret = -ENOMEM;
 966                 goto out_free_rx_ring;
 967         }
 968
 969         priv->tx_desc_alloc_size = size;
 970         priv->tx_desc_cpu = p;
 971
 972         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
 973                                GFP_KERNEL);
 974         if (!priv->tx_skb) {
 975                 ret = -ENOMEM;
 976                 goto out_free_tx_ring;
 977         }
 978
 979         priv->tx_desc_count = priv->tx_ring_size;
 980         priv->tx_dirty_desc = 0;
 981         priv->tx_curr_desc = 0;
 982         spin_lock_init(&priv->tx_lock);
 983
 984         /* init & fill rx ring with skbs */
 985         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
 986                                GFP_KERNEL);
 987         if (!priv->rx_skb) {
 988                 ret = -ENOMEM;
 989                 goto out_free_tx_skb;
 990         }
 991
 992         priv->rx_desc_count = 0;
 993         priv->rx_dirty_desc = 0;
 994         priv->rx_curr_desc = 0;
 995
 996         /* initialize flow control buffer allocation */
 997         if (priv->dma_has_sram)
 998                 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 999                                 ENETDMA_BUFALLOC_REG(priv->rx_chan));
1000         else
1001                 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
1002                                 ENETDMAC_BUFALLOC, priv->rx_chan);
1003
1004         if (bcm_enet_refill_rx(dev)) {
1005                 dev_err(kdev, "cannot allocate rx skb queue\n");
1006                 ret = -ENOMEM;
1007                 goto out;
1008         }
1009
1010         /* write rx & tx ring addresses */
1011         if (priv->dma_has_sram) {
1012                 enet_dmas_writel(priv, priv->rx_desc_dma,
1013                                  ENETDMAS_RSTART_REG, priv->rx_chan);
1014                 enet_dmas_writel(priv, priv->tx_desc_dma,
1015                          ENETDMAS_RSTART_REG, priv->tx_chan);
1016         } else {
1017                 enet_dmac_writel(priv, priv->rx_desc_dma,
1018                                 ENETDMAC_RSTART, priv->rx_chan);
1019                 enet_dmac_writel(priv, priv->tx_desc_dma,
1020                                 ENETDMAC_RSTART, priv->tx_chan);
1021         }
1022
1023         /* clear remaining state ram for rx & tx channel */
1024         if (priv->dma_has_sram) {
1025                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1026                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1027                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1028                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1029                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1030                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1031         } else {
1032                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1033                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1034         }
1035
1036         /* set max rx/tx length */
1037         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1038         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1039
1040         /* set dma maximum burst len */
1041         enet_dmac_writel(priv, priv->dma_maxburst,
1042                          ENETDMAC_MAXBURST, priv->rx_chan);
1043         enet_dmac_writel(priv, priv->dma_maxburst,
1044                          ENETDMAC_MAXBURST, priv->tx_chan);
1045
1046         /* set correct transmit fifo watermark */
1047         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1048
1049         /* set flow control low/high threshold to 1/3 / 2/3 */
1050         if (priv->dma_has_sram) {
1051                 val = priv->rx_ring_size / 3;
1052                 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1053                 val = (priv->rx_ring_size * 2) / 3;
1054                 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1055         } else {
1056                 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1057                 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1058                 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1059         }
1060
1061         /* all set, enable mac and interrupts, start dma engine and
1062          * kick rx dma channel */
1063         wmb();
1064         val = enet_readl(priv, ENET_CTL_REG);
1065         val |= ENET_CTL_ENABLE_MASK;
1066         enet_writel(priv, val, ENET_CTL_REG);
1067         if (priv->dma_has_sram)
1068                 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1069         enet_dmac_writel(priv, priv->dma_chan_en_mask,
1070                          ENETDMAC_CHANCFG, priv->rx_chan);
1071
1072         /* watch "mib counters about to overflow" interrupt */
1073         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1074         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1075
1076         /* watch "packet transferred" interrupt in rx and tx */
1077         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1078                          ENETDMAC_IR, priv->rx_chan);
1079         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1080                          ENETDMAC_IR, priv->tx_chan);
1081
1082         /* make sure we enable napi before rx interrupt  */
1083         napi_enable(&priv->napi);
1084
1085         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1086                          ENETDMAC_IRMASK, priv->rx_chan);
1087         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1088                          ENETDMAC_IRMASK, priv->tx_chan);
1089
1090         if (phydev)
1091                 phy_start(phydev);
1092         else
1093                 bcm_enet_adjust_link(dev);
1094
1095         netif_start_queue(dev);
1096         return 0;
1097
1098 out:
1099         for (i = 0; i < priv->rx_ring_size; i++) {
1100                 struct bcm_enet_desc *desc;
1101
1102                 if (!priv->rx_skb[i])
1103                         continue;
1104
1105                 desc = &priv->rx_desc_cpu[i];
1106                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1107                                  DMA_FROM_DEVICE);
1108                 kfree_skb(priv->rx_skb[i]);
1109         }
1110         kfree(priv->rx_skb);
1111
1112 out_free_tx_skb:
1113         kfree(priv->tx_skb);
1114
1115 out_free_tx_ring:
1116         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1117                           priv->tx_desc_cpu, priv->tx_desc_dma);
1118
1119 out_free_rx_ring:
1120         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1121                           priv->rx_desc_cpu, priv->rx_desc_dma);
1122
1123 out_freeirq_tx:
1124         free_irq(priv->irq_tx, dev);
1125
1126 out_freeirq_rx:
1127         free_irq(priv->irq_rx, dev);
1128
1129 out_freeirq:
1130         free_irq(dev->irq, dev);
1131
1132 out_phy_disconnect:
1133         if (phydev)
1134                 phy_disconnect(phydev);
1135
1136         return ret;
1137 }
1138
1139 /*
1140  * disable mac
1141  */
1142 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1143 {
1144         int limit;
1145         u32 val;
1146
1147         val = enet_readl(priv, ENET_CTL_REG);
1148         val |= ENET_CTL_DISABLE_MASK;
1149         enet_writel(priv, val, ENET_CTL_REG);
1150
1151         limit = 1000;
1152         do {
1153                 u32 val;
1154
1155                 val = enet_readl(priv, ENET_CTL_REG);
1156                 if (!(val & ENET_CTL_DISABLE_MASK))
1157                         break;
1158                 udelay(1);
1159         } while (limit--);
1160 }
1161
1162 /*
1163  * disable dma in given channel
1164  */
1165 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1166 {
1167         int limit;
1168
1169         enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1170
1171         limit = 1000;
1172         do {
1173                 u32 val;
1174
1175                 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1176                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1177                         break;
1178                 udelay(1);
1179         } while (limit--);
1180 }
1181
1182 /*
1183  * stop callback
1184  */
1185 static int bcm_enet_stop(struct net_device *dev)
1186 {
1187         struct bcm_enet_priv *priv;
1188         struct device *kdev;
1189         int i;
1190
1191         priv = netdev_priv(dev);
1192         kdev = &priv->pdev->dev;
1193
1194         netif_stop_queue(dev);
1195         napi_disable(&priv->napi);
1196         if (priv->has_phy)
1197                 phy_stop(dev->phydev);
1198         del_timer_sync(&priv->rx_timeout);
1199
1200         /* mask all interrupts */
1201         enet_writel(priv, 0, ENET_IRMASK_REG);
1202         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1203         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1204
1205         /* make sure no mib update is scheduled */
1206         cancel_work_sync(&priv->mib_update_task);
1207
1208         /* disable dma & mac */
1209         bcm_enet_disable_dma(priv, priv->tx_chan);
1210         bcm_enet_disable_dma(priv, priv->rx_chan);
1211         bcm_enet_disable_mac(priv);
1212
1213         /* force reclaim of all tx buffers */
1214         bcm_enet_tx_reclaim(dev, 1);
1215
1216         /* free the rx skb ring */
1217         for (i = 0; i < priv->rx_ring_size; i++) {
1218                 struct bcm_enet_desc *desc;
1219
1220                 if (!priv->rx_skb[i])
1221                         continue;
1222
1223                 desc = &priv->rx_desc_cpu[i];
1224                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1225                                  DMA_FROM_DEVICE);
1226                 kfree_skb(priv->rx_skb[i]);
1227         }
1228
1229         /* free remaining allocated memory */
1230         kfree(priv->rx_skb);
1231         kfree(priv->tx_skb);
1232         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1233                           priv->rx_desc_cpu, priv->rx_desc_dma);
1234         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1235                           priv->tx_desc_cpu, priv->tx_desc_dma);
1236         free_irq(priv->irq_tx, dev);
1237         free_irq(priv->irq_rx, dev);
1238         free_irq(dev->irq, dev);
1239
1240         /* release phy */
1241         if (priv->has_phy)
1242                 phy_disconnect(dev->phydev);
1243
1244         return 0;
1245 }
1246
1247 /*
1248  * ethtool callbacks
1249  */
1250 struct bcm_enet_stats {
1251         char stat_string[ETH_GSTRING_LEN];
1252         int sizeof_stat;
1253         int stat_offset;
1254         int mib_reg;
1255 };
1256
1257 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1258                      offsetof(struct bcm_enet_priv, m)
1259 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m),          \
1260                      offsetof(struct net_device_stats, m)
1261
1262 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1263         { "rx_packets", DEV_STAT(rx_packets), -1 },
1264         { "tx_packets", DEV_STAT(tx_packets), -1 },
1265         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1266         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1267         { "rx_errors", DEV_STAT(rx_errors), -1 },
1268         { "tx_errors", DEV_STAT(tx_errors), -1 },
1269         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1270         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1271
1272         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1273         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1274         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1275         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1276         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1277         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1278         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1279         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1280         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1281         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1282         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1283         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1284         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1285         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1286         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1287         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1288         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1289         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1290         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1291         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1292         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1293
1294         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1295         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1296         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1297         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1298         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1299         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1300         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1301         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1302         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1303         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1304         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1305         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1306         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1307         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1308         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1309         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1310         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1311         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1312         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1313         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1314         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1315         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1316
1317 };
1318
1319 #define BCM_ENET_STATS_LEN      ARRAY_SIZE(bcm_enet_gstrings_stats)
1320
1321 static const u32 unused_mib_regs[] = {
1322         ETH_MIB_TX_ALL_OCTETS,
1323         ETH_MIB_TX_ALL_PKTS,
1324         ETH_MIB_RX_ALL_OCTETS,
1325         ETH_MIB_RX_ALL_PKTS,
1326 };
1327
1328
1329 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1330                                  struct ethtool_drvinfo *drvinfo)
1331 {
1332         strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1333         strlcpy(drvinfo->version, bcm_enet_driver_version,
1334                 sizeof(drvinfo->version));
1335         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1336         strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1337 }
1338
1339 static int bcm_enet_get_sset_count(struct net_device *netdev,
1340                                         int string_set)
1341 {
1342         switch (string_set) {
1343         case ETH_SS_STATS:
1344                 return BCM_ENET_STATS_LEN;
1345         default:
1346                 return -EINVAL;
1347         }
1348 }
1349
1350 static void bcm_enet_get_strings(struct net_device *netdev,
1351                                  u32 stringset, u8 *data)
1352 {
1353         int i;
1354
1355         switch (stringset) {
1356         case ETH_SS_STATS:
1357                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1358                         memcpy(data + i * ETH_GSTRING_LEN,
1359                                bcm_enet_gstrings_stats[i].stat_string,
1360                                ETH_GSTRING_LEN);
1361                 }
1362                 break;
1363         }
1364 }
1365
1366 static void update_mib_counters(struct bcm_enet_priv *priv)
1367 {
1368         int i;
1369
1370         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1371                 const struct bcm_enet_stats *s;
1372                 u32 val;
1373                 char *p;
1374
1375                 s = &bcm_enet_gstrings_stats[i];
1376                 if (s->mib_reg == -1)
1377                         continue;
1378
1379                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1380                 p = (char *)priv + s->stat_offset;
1381
1382                 if (s->sizeof_stat == sizeof(u64))
1383                         *(u64 *)p += val;
1384                 else
1385                         *(u32 *)p += val;
1386         }
1387
1388         /* also empty unused mib counters to make sure mib counter
1389          * overflow interrupt is cleared */
1390         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1391                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1392 }
1393
1394 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1395 {
1396         struct bcm_enet_priv *priv;
1397
1398         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1399         mutex_lock(&priv->mib_update_lock);
1400         update_mib_counters(priv);
1401         mutex_unlock(&priv->mib_update_lock);
1402
1403         /* reenable mib interrupt */
1404         if (netif_running(priv->net_dev))
1405                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1406 }
1407
1408 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1409                                        struct ethtool_stats *stats,
1410                                        u64 *data)
1411 {
1412         struct bcm_enet_priv *priv;
1413         int i;
1414
1415         priv = netdev_priv(netdev);
1416
1417         mutex_lock(&priv->mib_update_lock);
1418         update_mib_counters(priv);
1419
1420         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1421                 const struct bcm_enet_stats *s;
1422                 char *p;
1423
1424                 s = &bcm_enet_gstrings_stats[i];
1425                 if (s->mib_reg == -1)
1426                         p = (char *)&netdev->stats;
1427                 else
1428                         p = (char *)priv;
1429                 p += s->stat_offset;
1430                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1431                         *(u64 *)p : *(u32 *)p;
1432         }
1433         mutex_unlock(&priv->mib_update_lock);
1434 }
1435
1436 static int bcm_enet_nway_reset(struct net_device *dev)
1437 {
1438         struct bcm_enet_priv *priv;
1439
1440         priv = netdev_priv(dev);
1441         if (priv->has_phy) {
1442                 if (!dev->phydev)
1443                         return -ENODEV;
1444                 return genphy_restart_aneg(dev->phydev);
1445         }
1446
1447         return -EOPNOTSUPP;
1448 }
1449
1450 static int bcm_enet_get_link_ksettings(struct net_device *dev,
1451                                        struct ethtool_link_ksettings *cmd)
1452 {
1453         struct bcm_enet_priv *priv;
1454         u32 supported, advertising;
1455
1456         priv = netdev_priv(dev);
1457
1458         if (priv->has_phy) {
1459                 if (!dev->phydev)
1460                         return -ENODEV;
1461                 return phy_ethtool_ksettings_get(dev->phydev, cmd);
1462         } else {
1463                 cmd->base.autoneg = 0;
1464                 cmd->base.speed = (priv->force_speed_100) ?
1465                         SPEED_100 : SPEED_10;
1466                 cmd->base.duplex = (priv->force_duplex_full) ?
1467                         DUPLEX_FULL : DUPLEX_HALF;
1468                 supported = ADVERTISED_10baseT_Half |
1469                         ADVERTISED_10baseT_Full |
1470                         ADVERTISED_100baseT_Half |
1471                         ADVERTISED_100baseT_Full;
1472                 advertising = 0;
1473                 ethtool_convert_legacy_u32_to_link_mode(
1474                         cmd->link_modes.supported, supported);
1475                 ethtool_convert_legacy_u32_to_link_mode(
1476                         cmd->link_modes.advertising, advertising);
1477                 cmd->base.port = PORT_MII;
1478         }
1479         return 0;
1480 }
1481
1482 static int bcm_enet_set_link_ksettings(struct net_device *dev,
1483                                        const struct ethtool_link_ksettings *cmd)
1484 {
1485         struct bcm_enet_priv *priv;
1486
1487         priv = netdev_priv(dev);
1488         if (priv->has_phy) {
1489                 if (!dev->phydev)
1490                         return -ENODEV;
1491                 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1492         } else {
1493
1494                 if (cmd->base.autoneg ||
1495                     (cmd->base.speed != SPEED_100 &&
1496                      cmd->base.speed != SPEED_10) ||
1497                     cmd->base.port != PORT_MII)
1498                         return -EINVAL;
1499
1500                 priv->force_speed_100 =
1501                         (cmd->base.speed == SPEED_100) ? 1 : 0;
1502                 priv->force_duplex_full =
1503                         (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1504
1505                 if (netif_running(dev))
1506                         bcm_enet_adjust_link(dev);
1507                 return 0;
1508         }
1509 }
1510
1511 static void bcm_enet_get_ringparam(struct net_device *dev,
1512                                    struct ethtool_ringparam *ering)
1513 {
1514         struct bcm_enet_priv *priv;
1515
1516         priv = netdev_priv(dev);
1517
1518         /* rx/tx ring is actually only limited by memory */
1519         ering->rx_max_pending = 8192;
1520         ering->tx_max_pending = 8192;
1521         ering->rx_pending = priv->rx_ring_size;
1522         ering->tx_pending = priv->tx_ring_size;
1523 }
1524
1525 static int bcm_enet_set_ringparam(struct net_device *dev,
1526                                   struct ethtool_ringparam *ering)
1527 {
1528         struct bcm_enet_priv *priv;
1529         int was_running;
1530
1531         priv = netdev_priv(dev);
1532
1533         was_running = 0;
1534         if (netif_running(dev)) {
1535                 bcm_enet_stop(dev);
1536                 was_running = 1;
1537         }
1538
1539         priv->rx_ring_size = ering->rx_pending;
1540         priv->tx_ring_size = ering->tx_pending;
1541
1542         if (was_running) {
1543                 int err;
1544
1545                 err = bcm_enet_open(dev);
1546                 if (err)
1547                         dev_close(dev);
1548                 else
1549                         bcm_enet_set_multicast_list(dev);
1550         }
1551         return 0;
1552 }
1553
1554 static void bcm_enet_get_pauseparam(struct net_device *dev,
1555                                     struct ethtool_pauseparam *ecmd)
1556 {
1557         struct bcm_enet_priv *priv;
1558
1559         priv = netdev_priv(dev);
1560         ecmd->autoneg = priv->pause_auto;
1561         ecmd->rx_pause = priv->pause_rx;
1562         ecmd->tx_pause = priv->pause_tx;
1563 }
1564
1565 static int bcm_enet_set_pauseparam(struct net_device *dev,
1566                                    struct ethtool_pauseparam *ecmd)
1567 {
1568         struct bcm_enet_priv *priv;
1569
1570         priv = netdev_priv(dev);
1571
1572         if (priv->has_phy) {
1573                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1574                         /* asymetric pause mode not supported,
1575                          * actually possible but integrated PHY has RO
1576                          * asym_pause bit */
1577                         return -EINVAL;
1578                 }
1579         } else {
1580                 /* no pause autoneg on direct mii connection */
1581                 if (ecmd->autoneg)
1582                         return -EINVAL;
1583         }
1584
1585         priv->pause_auto = ecmd->autoneg;
1586         priv->pause_rx = ecmd->rx_pause;
1587         priv->pause_tx = ecmd->tx_pause;
1588
1589         return 0;
1590 }
1591
1592 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1593         .get_strings            = bcm_enet_get_strings,
1594         .get_sset_count         = bcm_enet_get_sset_count,
1595         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1596         .nway_reset             = bcm_enet_nway_reset,
1597         .get_drvinfo            = bcm_enet_get_drvinfo,
1598         .get_link               = ethtool_op_get_link,
1599         .get_ringparam          = bcm_enet_get_ringparam,
1600         .set_ringparam          = bcm_enet_set_ringparam,
1601         .get_pauseparam         = bcm_enet_get_pauseparam,
1602         .set_pauseparam         = bcm_enet_set_pauseparam,
1603         .get_link_ksettings     = bcm_enet_get_link_ksettings,
1604         .set_link_ksettings     = bcm_enet_set_link_ksettings,
1605 };
1606
1607 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1608 {
1609         struct bcm_enet_priv *priv;
1610
1611         priv = netdev_priv(dev);
1612         if (priv->has_phy) {
1613                 if (!dev->phydev)
1614                         return -ENODEV;
1615                 return phy_mii_ioctl(dev->phydev, rq, cmd);
1616         } else {
1617                 struct mii_if_info mii;
1618
1619                 mii.dev = dev;
1620                 mii.mdio_read = bcm_enet_mdio_read_mii;
1621                 mii.mdio_write = bcm_enet_mdio_write_mii;
1622                 mii.phy_id = 0;
1623                 mii.phy_id_mask = 0x3f;
1624                 mii.reg_num_mask = 0x1f;
1625                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1626         }
1627 }
1628
1629 /*
1630  * calculate actual hardware mtu
1631  */
1632 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1633 {
1634         int actual_mtu;
1635
1636         actual_mtu = mtu;
1637
1638         /* add ethernet header + vlan tag size */
1639         actual_mtu += VLAN_ETH_HLEN;
1640
1641         if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1642                 return -EINVAL;
1643
1644         /*
1645          * setup maximum size before we get overflow mark in
1646          * descriptor, note that this will not prevent reception of
1647          * big frames, they will be split into multiple buffers
1648          * anyway
1649          */
1650         priv->hw_mtu = actual_mtu;
1651
1652         /*
1653          * align rx buffer size to dma burst len, account FCS since
1654          * it's appended
1655          */
1656         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1657                                   priv->dma_maxburst * 4);
1658         return 0;
1659 }
1660
1661 /*
1662  * adjust mtu, can't be called while device is running
1663  */
1664 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1665 {
1666         int ret;
1667
1668         if (netif_running(dev))
1669                 return -EBUSY;
1670
1671         ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1672         if (ret)
1673                 return ret;
1674         dev->mtu = new_mtu;
1675         return 0;
1676 }
1677
1678 /*
1679  * preinit hardware to allow mii operation while device is down
1680  */
1681 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1682 {
1683         u32 val;
1684         int limit;
1685
1686         /* make sure mac is disabled */
1687         bcm_enet_disable_mac(priv);
1688
1689         /* soft reset mac */
1690         val = ENET_CTL_SRESET_MASK;
1691         enet_writel(priv, val, ENET_CTL_REG);
1692         wmb();
1693
1694         limit = 1000;
1695         do {
1696                 val = enet_readl(priv, ENET_CTL_REG);
1697                 if (!(val & ENET_CTL_SRESET_MASK))
1698                         break;
1699                 udelay(1);
1700         } while (limit--);
1701
1702         /* select correct mii interface */
1703         val = enet_readl(priv, ENET_CTL_REG);
1704         if (priv->use_external_mii)
1705                 val |= ENET_CTL_EPHYSEL_MASK;
1706         else
1707                 val &= ~ENET_CTL_EPHYSEL_MASK;
1708         enet_writel(priv, val, ENET_CTL_REG);
1709
1710         /* turn on mdc clock */
1711         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1712                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1713
1714         /* set mib counters to self-clear when read */
1715         val = enet_readl(priv, ENET_MIBCTL_REG);
1716         val |= ENET_MIBCTL_RDCLEAR_MASK;
1717         enet_writel(priv, val, ENET_MIBCTL_REG);
1718 }
1719
1720 static const struct net_device_ops bcm_enet_ops = {
1721         .ndo_open               = bcm_enet_open,
1722         .ndo_stop               = bcm_enet_stop,
1723         .ndo_start_xmit         = bcm_enet_start_xmit,
1724         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1725         .ndo_set_rx_mode        = bcm_enet_set_multicast_list,
1726         .ndo_do_ioctl           = bcm_enet_ioctl,
1727         .ndo_change_mtu         = bcm_enet_change_mtu,
1728 };
1729
1730 /*
1731  * allocate netdevice, request register memory and register device.
1732  */
1733 static int bcm_enet_probe(struct platform_device *pdev)
1734 {
1735         struct bcm_enet_priv *priv;
1736         struct net_device *dev;
1737         struct bcm63xx_enet_platform_data *pd;
1738         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1739         struct mii_bus *bus;
1740         const char *clk_name;
1741         int i, ret;
1742
1743         /* stop if shared driver failed, assume driver->probe will be
1744          * called in the same order we register devices (correct ?) */
1745         if (!bcm_enet_shared_base[0])
1746                 return -ENODEV;
1747
1748         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1749         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1750         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1751         if (!res_irq || !res_irq_rx || !res_irq_tx)
1752                 return -ENODEV;
1753
1754         ret = 0;
1755         dev = alloc_etherdev(sizeof(*priv));
1756         if (!dev)
1757                 return -ENOMEM;
1758         priv = netdev_priv(dev);
1759
1760         priv->enet_is_sw = false;
1761         priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1762
1763         ret = compute_hw_mtu(priv, dev->mtu);
1764         if (ret)
1765                 goto out;
1766
1767         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1768         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1769         if (IS_ERR(priv->base)) {
1770                 ret = PTR_ERR(priv->base);
1771                 goto out;
1772         }
1773
1774         dev->irq = priv->irq = res_irq->start;
1775         priv->irq_rx = res_irq_rx->start;
1776         priv->irq_tx = res_irq_tx->start;
1777         priv->mac_id = pdev->id;
1778
1779         /* get rx & tx dma channel id for this mac */
1780         if (priv->mac_id == 0) {
1781                 priv->rx_chan = 0;
1782                 priv->tx_chan = 1;
1783                 clk_name = "enet0";
1784         } else {
1785                 priv->rx_chan = 2;
1786                 priv->tx_chan = 3;
1787                 clk_name = "enet1";
1788         }
1789
1790         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1791         if (IS_ERR(priv->mac_clk)) {
1792                 ret = PTR_ERR(priv->mac_clk);
1793                 goto out;
1794         }
1795         ret = clk_prepare_enable(priv->mac_clk);
1796         if (ret)
1797                 goto out_put_clk_mac;
1798
1799         /* initialize default and fetch platform data */
1800         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1801         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1802
1803         pd = dev_get_platdata(&pdev->dev);
1804         if (pd) {
1805                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1806                 priv->has_phy = pd->has_phy;
1807                 priv->phy_id = pd->phy_id;
1808                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1809                 priv->phy_interrupt = pd->phy_interrupt;
1810                 priv->use_external_mii = !pd->use_internal_phy;
1811                 priv->pause_auto = pd->pause_auto;
1812                 priv->pause_rx = pd->pause_rx;
1813                 priv->pause_tx = pd->pause_tx;
1814                 priv->force_duplex_full = pd->force_duplex_full;
1815                 priv->force_speed_100 = pd->force_speed_100;
1816                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1817                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1818                 priv->dma_chan_width = pd->dma_chan_width;
1819                 priv->dma_has_sram = pd->dma_has_sram;
1820                 priv->dma_desc_shift = pd->dma_desc_shift;
1821         }
1822
1823         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1824                 /* using internal PHY, enable clock */
1825                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1826                 if (IS_ERR(priv->phy_clk)) {
1827                         ret = PTR_ERR(priv->phy_clk);
1828                         priv->phy_clk = NULL;
1829                         goto out_disable_clk_mac;
1830                 }
1831                 ret = clk_prepare_enable(priv->phy_clk);
1832                 if (ret)
1833                         goto out_put_clk_phy;
1834         }
1835
1836         /* do minimal hardware init to be able to probe mii bus */
1837         bcm_enet_hw_preinit(priv);
1838
1839         /* MII bus registration */
1840         if (priv->has_phy) {
1841
1842                 priv->mii_bus = mdiobus_alloc();
1843                 if (!priv->mii_bus) {
1844                         ret = -ENOMEM;
1845                         goto out_uninit_hw;
1846                 }
1847
1848                 bus = priv->mii_bus;
1849                 bus->name = "bcm63xx_enet MII bus";
1850                 bus->parent = &pdev->dev;
1851                 bus->priv = priv;
1852                 bus->read = bcm_enet_mdio_read_phylib;
1853                 bus->write = bcm_enet_mdio_write_phylib;
1854                 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1855
1856                 /* only probe bus where we think the PHY is, because
1857                  * the mdio read operation return 0 instead of 0xffff
1858                  * if a slave is not present on hw */
1859                 bus->phy_mask = ~(1 << priv->phy_id);
1860
1861                 if (priv->has_phy_interrupt)
1862                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1863
1864                 ret = mdiobus_register(bus);
1865                 if (ret) {
1866                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1867                         goto out_free_mdio;
1868                 }
1869         } else {
1870
1871                 /* run platform code to initialize PHY device */
1872                 if (pd && pd->mii_config &&
1873                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1874                                    bcm_enet_mdio_write_mii)) {
1875                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1876                         goto out_uninit_hw;
1877                 }
1878         }
1879
1880         spin_lock_init(&priv->rx_lock);
1881
1882         /* init rx timeout (used for oom) */
1883         init_timer(&priv->rx_timeout);
1884         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1885         priv->rx_timeout.data = (unsigned long)dev;
1886
1887         /* init the mib update lock&work */
1888         mutex_init(&priv->mib_update_lock);
1889         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1890
1891         /* zero mib counters */
1892         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1893                 enet_writel(priv, 0, ENET_MIB_REG(i));
1894
1895         /* register netdevice */
1896         dev->netdev_ops = &bcm_enet_ops;
1897         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1898
1899         dev->ethtool_ops = &bcm_enet_ethtool_ops;
1900         SET_NETDEV_DEV(dev, &pdev->dev);
1901
1902         ret = register_netdev(dev);
1903         if (ret)
1904                 goto out_unregister_mdio;
1905
1906         netif_carrier_off(dev);
1907         platform_set_drvdata(pdev, dev);
1908         priv->pdev = pdev;
1909         priv->net_dev = dev;
1910
1911         return 0;
1912
1913 out_unregister_mdio:
1914         if (priv->mii_bus)
1915                 mdiobus_unregister(priv->mii_bus);
1916
1917 out_free_mdio:
1918         if (priv->mii_bus)
1919                 mdiobus_free(priv->mii_bus);
1920
1921 out_uninit_hw:
1922         /* turn off mdc clock */
1923         enet_writel(priv, 0, ENET_MIISC_REG);
1924         if (priv->phy_clk)
1925                 clk_disable_unprepare(priv->phy_clk);
1926
1927 out_put_clk_phy:
1928         if (priv->phy_clk)
1929                 clk_put(priv->phy_clk);
1930
1931 out_disable_clk_mac:
1932         clk_disable_unprepare(priv->mac_clk);
1933 out_put_clk_mac:
1934         clk_put(priv->mac_clk);
1935 out:
1936         free_netdev(dev);
1937         return ret;
1938 }
1939
1940
1941 /*
1942  * exit func, stops hardware and unregisters netdevice
1943  */
1944 static int bcm_enet_remove(struct platform_device *pdev)
1945 {
1946         struct bcm_enet_priv *priv;
1947         struct net_device *dev;
1948
1949         /* stop netdevice */
1950         dev = platform_get_drvdata(pdev);
1951         priv = netdev_priv(dev);
1952         unregister_netdev(dev);
1953
1954         /* turn off mdc clock */
1955         enet_writel(priv, 0, ENET_MIISC_REG);
1956
1957         if (priv->has_phy) {
1958                 mdiobus_unregister(priv->mii_bus);
1959                 mdiobus_free(priv->mii_bus);
1960         } else {
1961                 struct bcm63xx_enet_platform_data *pd;
1962
1963                 pd = dev_get_platdata(&pdev->dev);
1964                 if (pd && pd->mii_config)
1965                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1966                                        bcm_enet_mdio_write_mii);
1967         }
1968
1969         /* disable hw block clocks */
1970         if (priv->phy_clk) {
1971                 clk_disable_unprepare(priv->phy_clk);
1972                 clk_put(priv->phy_clk);
1973         }
1974         clk_disable_unprepare(priv->mac_clk);
1975         clk_put(priv->mac_clk);
1976
1977         free_netdev(dev);
1978         return 0;
1979 }
1980
1981 struct platform_driver bcm63xx_enet_driver = {
1982         .probe  = bcm_enet_probe,
1983         .remove = bcm_enet_remove,
1984         .driver = {
1985                 .name   = "bcm63xx_enet",
1986                 .owner  = THIS_MODULE,
1987         },
1988 };
1989
1990 /*
1991  * switch mii access callbacks
1992  */
1993 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1994                                 int ext, int phy_id, int location)
1995 {
1996         u32 reg;
1997         int ret;
1998
1999         spin_lock_bh(&priv->enetsw_mdio_lock);
2000         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2001
2002         reg = ENETSW_MDIOC_RD_MASK |
2003                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2004                 (location << ENETSW_MDIOC_REG_SHIFT);
2005
2006         if (ext)
2007                 reg |= ENETSW_MDIOC_EXT_MASK;
2008
2009         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2010         udelay(50);
2011         ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
2012         spin_unlock_bh(&priv->enetsw_mdio_lock);
2013         return ret;
2014 }
2015
2016 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
2017                                  int ext, int phy_id, int location,
2018                                  uint16_t data)
2019 {
2020         u32 reg;
2021
2022         spin_lock_bh(&priv->enetsw_mdio_lock);
2023         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2024
2025         reg = ENETSW_MDIOC_WR_MASK |
2026                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2027                 (location << ENETSW_MDIOC_REG_SHIFT);
2028
2029         if (ext)
2030                 reg |= ENETSW_MDIOC_EXT_MASK;
2031
2032         reg |= data;
2033
2034         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2035         udelay(50);
2036         spin_unlock_bh(&priv->enetsw_mdio_lock);
2037 }
2038
2039 static inline int bcm_enet_port_is_rgmii(int portid)
2040 {
2041         return portid >= ENETSW_RGMII_PORT0;
2042 }
2043
2044 /*
2045  * enet sw PHY polling
2046  */
2047 static void swphy_poll_timer(unsigned long data)
2048 {
2049         struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2050         unsigned int i;
2051
2052         for (i = 0; i < priv->num_ports; i++) {
2053                 struct bcm63xx_enetsw_port *port;
2054                 int val, j, up, advertise, lpa, speed, duplex, media;
2055                 int external_phy = bcm_enet_port_is_rgmii(i);
2056                 u8 override;
2057
2058                 port = &priv->used_ports[i];
2059                 if (!port->used)
2060                         continue;
2061
2062                 if (port->bypass_link)
2063                         continue;
2064
2065                 /* dummy read to clear */
2066                 for (j = 0; j < 2; j++)
2067                         val = bcmenet_sw_mdio_read(priv, external_phy,
2068                                                    port->phy_id, MII_BMSR);
2069
2070                 if (val == 0xffff)
2071                         continue;
2072
2073                 up = (val & BMSR_LSTATUS) ? 1 : 0;
2074                 if (!(up ^ priv->sw_port_link[i]))
2075                         continue;
2076
2077                 priv->sw_port_link[i] = up;
2078
2079                 /* link changed */
2080                 if (!up) {
2081                         dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2082                                  port->name);
2083                         enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2084                                       ENETSW_PORTOV_REG(i));
2085                         enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2086                                       ENETSW_PTCTRL_TXDIS_MASK,
2087                                       ENETSW_PTCTRL_REG(i));
2088                         continue;
2089                 }
2090
2091                 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2092                                                  port->phy_id, MII_ADVERTISE);
2093
2094                 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2095                                            MII_LPA);
2096
2097                 /* figure out media and duplex from advertise and LPA values */
2098                 media = mii_nway_result(lpa & advertise);
2099                 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2100
2101                 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2102                         speed = 100;
2103                 else
2104                         speed = 10;
2105
2106                 if (val & BMSR_ESTATEN) {
2107                         advertise = bcmenet_sw_mdio_read(priv, external_phy,
2108                                                 port->phy_id, MII_CTRL1000);
2109
2110                         lpa = bcmenet_sw_mdio_read(priv, external_phy,
2111                                                 port->phy_id, MII_STAT1000);
2112
2113                         if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2114                                         && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2115                                 speed = 1000;
2116                                 duplex = (lpa & LPA_1000FULL);
2117                         }
2118                 }
2119
2120                 dev_info(&priv->pdev->dev,
2121                          "link UP on %s, %dMbps, %s-duplex\n",
2122                          port->name, speed, duplex ? "full" : "half");
2123
2124                 override = ENETSW_PORTOV_ENABLE_MASK |
2125                         ENETSW_PORTOV_LINKUP_MASK;
2126
2127                 if (speed == 1000)
2128                         override |= ENETSW_IMPOV_1000_MASK;
2129                 else if (speed == 100)
2130                         override |= ENETSW_IMPOV_100_MASK;
2131                 if (duplex)
2132                         override |= ENETSW_IMPOV_FDX_MASK;
2133
2134                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2135                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2136         }
2137
2138         priv->swphy_poll.expires = jiffies + HZ;
2139         add_timer(&priv->swphy_poll);
2140 }
2141
2142 /*
2143  * open callback, allocate dma rings & buffers and start rx operation
2144  */
2145 static int bcm_enetsw_open(struct net_device *dev)
2146 {
2147         struct bcm_enet_priv *priv;
2148         struct device *kdev;
2149         int i, ret;
2150         unsigned int size;
2151         void *p;
2152         u32 val;
2153
2154         priv = netdev_priv(dev);
2155         kdev = &priv->pdev->dev;
2156
2157         /* mask all interrupts and request them */
2158         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2159         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2160
2161         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2162                           0, dev->name, dev);
2163         if (ret)
2164                 goto out_freeirq;
2165
2166         if (priv->irq_tx != -1) {
2167                 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2168                                   0, dev->name, dev);
2169                 if (ret)
2170                         goto out_freeirq_rx;
2171         }
2172
2173         /* allocate rx dma ring */
2174         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2175         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2176         if (!p) {
2177                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2178                 ret = -ENOMEM;
2179                 goto out_freeirq_tx;
2180         }
2181
2182         memset(p, 0, size);
2183         priv->rx_desc_alloc_size = size;
2184         priv->rx_desc_cpu = p;
2185
2186         /* allocate tx dma ring */
2187         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2188         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2189         if (!p) {
2190                 dev_err(kdev, "cannot allocate tx ring\n");
2191                 ret = -ENOMEM;
2192                 goto out_free_rx_ring;
2193         }
2194
2195         memset(p, 0, size);
2196         priv->tx_desc_alloc_size = size;
2197         priv->tx_desc_cpu = p;
2198
2199         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2200                                GFP_KERNEL);
2201         if (!priv->tx_skb) {
2202                 dev_err(kdev, "cannot allocate rx skb queue\n");
2203                 ret = -ENOMEM;
2204                 goto out_free_tx_ring;
2205         }
2206
2207         priv->tx_desc_count = priv->tx_ring_size;
2208         priv->tx_dirty_desc = 0;
2209         priv->tx_curr_desc = 0;
2210         spin_lock_init(&priv->tx_lock);
2211
2212         /* init & fill rx ring with skbs */
2213         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2214                                GFP_KERNEL);
2215         if (!priv->rx_skb) {
2216                 dev_err(kdev, "cannot allocate rx skb queue\n");
2217                 ret = -ENOMEM;
2218                 goto out_free_tx_skb;
2219         }
2220
2221         priv->rx_desc_count = 0;
2222         priv->rx_dirty_desc = 0;
2223         priv->rx_curr_desc = 0;
2224
2225         /* disable all ports */
2226         for (i = 0; i < priv->num_ports; i++) {
2227                 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2228                               ENETSW_PORTOV_REG(i));
2229                 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2230                               ENETSW_PTCTRL_TXDIS_MASK,
2231                               ENETSW_PTCTRL_REG(i));
2232
2233                 priv->sw_port_link[i] = 0;
2234         }
2235
2236         /* reset mib */
2237         val = enetsw_readb(priv, ENETSW_GMCR_REG);
2238         val |= ENETSW_GMCR_RST_MIB_MASK;
2239         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2240         mdelay(1);
2241         val &= ~ENETSW_GMCR_RST_MIB_MASK;
2242         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2243         mdelay(1);
2244
2245         /* force CPU port state */
2246         val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2247         val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2248         enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2249
2250         /* enable switch forward engine */
2251         val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2252         val |= ENETSW_SWMODE_FWD_EN_MASK;
2253         enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2254
2255         /* enable jumbo on all ports */
2256         enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2257         enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2258
2259         /* initialize flow control buffer allocation */
2260         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2261                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
2262
2263         if (bcm_enet_refill_rx(dev)) {
2264                 dev_err(kdev, "cannot allocate rx skb queue\n");
2265                 ret = -ENOMEM;
2266                 goto out;
2267         }
2268
2269         /* write rx & tx ring addresses */
2270         enet_dmas_writel(priv, priv->rx_desc_dma,
2271                          ENETDMAS_RSTART_REG, priv->rx_chan);
2272         enet_dmas_writel(priv, priv->tx_desc_dma,
2273                          ENETDMAS_RSTART_REG, priv->tx_chan);
2274
2275         /* clear remaining state ram for rx & tx channel */
2276         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2277         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2278         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2279         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2280         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2281         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2282
2283         /* set dma maximum burst len */
2284         enet_dmac_writel(priv, priv->dma_maxburst,
2285                          ENETDMAC_MAXBURST, priv->rx_chan);
2286         enet_dmac_writel(priv, priv->dma_maxburst,
2287                          ENETDMAC_MAXBURST, priv->tx_chan);
2288
2289         /* set flow control low/high threshold to 1/3 / 2/3 */
2290         val = priv->rx_ring_size / 3;
2291         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2292         val = (priv->rx_ring_size * 2) / 3;
2293         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2294
2295         /* all set, enable mac and interrupts, start dma engine and
2296          * kick rx dma channel
2297          */
2298         wmb();
2299         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2300         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2301                          ENETDMAC_CHANCFG, priv->rx_chan);
2302
2303         /* watch "packet transferred" interrupt in rx and tx */
2304         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2305                          ENETDMAC_IR, priv->rx_chan);
2306         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2307                          ENETDMAC_IR, priv->tx_chan);
2308
2309         /* make sure we enable napi before rx interrupt  */
2310         napi_enable(&priv->napi);
2311
2312         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2313                          ENETDMAC_IRMASK, priv->rx_chan);
2314         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2315                          ENETDMAC_IRMASK, priv->tx_chan);
2316
2317         netif_carrier_on(dev);
2318         netif_start_queue(dev);
2319
2320         /* apply override config for bypass_link ports here. */
2321         for (i = 0; i < priv->num_ports; i++) {
2322                 struct bcm63xx_enetsw_port *port;
2323                 u8 override;
2324                 port = &priv->used_ports[i];
2325                 if (!port->used)
2326                         continue;
2327
2328                 if (!port->bypass_link)
2329                         continue;
2330
2331                 override = ENETSW_PORTOV_ENABLE_MASK |
2332                         ENETSW_PORTOV_LINKUP_MASK;
2333
2334                 switch (port->force_speed) {
2335                 case 1000:
2336                         override |= ENETSW_IMPOV_1000_MASK;
2337                         break;
2338                 case 100:
2339                         override |= ENETSW_IMPOV_100_MASK;
2340                         break;
2341                 case 10:
2342                         break;
2343                 default:
2344                         pr_warn("invalid forced speed on port %s: assume 10\n",
2345                                port->name);
2346                         break;
2347                 }
2348
2349                 if (port->force_duplex_full)
2350                         override |= ENETSW_IMPOV_FDX_MASK;
2351
2352
2353                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2354                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2355         }
2356
2357         /* start phy polling timer */
2358         init_timer(&priv->swphy_poll);
2359         priv->swphy_poll.function = swphy_poll_timer;
2360         priv->swphy_poll.data = (unsigned long)priv;
2361         priv->swphy_poll.expires = jiffies;
2362         add_timer(&priv->swphy_poll);
2363         return 0;
2364
2365 out:
2366         for (i = 0; i < priv->rx_ring_size; i++) {
2367                 struct bcm_enet_desc *desc;
2368
2369                 if (!priv->rx_skb[i])
2370                         continue;
2371
2372                 desc = &priv->rx_desc_cpu[i];
2373                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2374                                  DMA_FROM_DEVICE);
2375                 kfree_skb(priv->rx_skb[i]);
2376         }
2377         kfree(priv->rx_skb);
2378
2379 out_free_tx_skb:
2380         kfree(priv->tx_skb);
2381
2382 out_free_tx_ring:
2383         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2384                           priv->tx_desc_cpu, priv->tx_desc_dma);
2385
2386 out_free_rx_ring:
2387         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2388                           priv->rx_desc_cpu, priv->rx_desc_dma);
2389
2390 out_freeirq_tx:
2391         if (priv->irq_tx != -1)
2392                 free_irq(priv->irq_tx, dev);
2393
2394 out_freeirq_rx:
2395         free_irq(priv->irq_rx, dev);
2396
2397 out_freeirq:
2398         return ret;
2399 }
2400
2401 /* stop callback */
2402 static int bcm_enetsw_stop(struct net_device *dev)
2403 {
2404         struct bcm_enet_priv *priv;
2405         struct device *kdev;
2406         int i;
2407
2408         priv = netdev_priv(dev);
2409         kdev = &priv->pdev->dev;
2410
2411         del_timer_sync(&priv->swphy_poll);
2412         netif_stop_queue(dev);
2413         napi_disable(&priv->napi);
2414         del_timer_sync(&priv->rx_timeout);
2415
2416         /* mask all interrupts */
2417         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2418         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2419
2420         /* disable dma & mac */
2421         bcm_enet_disable_dma(priv, priv->tx_chan);
2422         bcm_enet_disable_dma(priv, priv->rx_chan);
2423
2424         /* force reclaim of all tx buffers */
2425         bcm_enet_tx_reclaim(dev, 1);
2426
2427         /* free the rx skb ring */
2428         for (i = 0; i < priv->rx_ring_size; i++) {
2429                 struct bcm_enet_desc *desc;
2430
2431                 if (!priv->rx_skb[i])
2432                         continue;
2433
2434                 desc = &priv->rx_desc_cpu[i];
2435                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2436                                  DMA_FROM_DEVICE);
2437                 kfree_skb(priv->rx_skb[i]);
2438         }
2439
2440         /* free remaining allocated memory */
2441         kfree(priv->rx_skb);
2442         kfree(priv->tx_skb);
2443         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2444                           priv->rx_desc_cpu, priv->rx_desc_dma);
2445         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2446                           priv->tx_desc_cpu, priv->tx_desc_dma);
2447         if (priv->irq_tx != -1)
2448                 free_irq(priv->irq_tx, dev);
2449         free_irq(priv->irq_rx, dev);
2450
2451         return 0;
2452 }
2453
2454 /* try to sort out phy external status by walking the used_port field
2455  * in the bcm_enet_priv structure. in case the phy address is not
2456  * assigned to any physical port on the switch, assume it is external
2457  * (and yell at the user).
2458  */
2459 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2460 {
2461         int i;
2462
2463         for (i = 0; i < priv->num_ports; ++i) {
2464                 if (!priv->used_ports[i].used)
2465                         continue;
2466                 if (priv->used_ports[i].phy_id == phy_id)
2467                         return bcm_enet_port_is_rgmii(i);
2468         }
2469
2470         printk_once(KERN_WARNING  "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2471                     phy_id);
2472         return 1;
2473 }
2474
2475 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2476  * external/internal status of the given phy_id first.
2477  */
2478 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2479                                     int location)
2480 {
2481         struct bcm_enet_priv *priv;
2482
2483         priv = netdev_priv(dev);
2484         return bcmenet_sw_mdio_read(priv,
2485                                     bcm_enetsw_phy_is_external(priv, phy_id),
2486                                     phy_id, location);
2487 }
2488
2489 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2490  * external/internal status of the given phy_id first.
2491  */
2492 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2493                                       int location,
2494                                       int val)
2495 {
2496         struct bcm_enet_priv *priv;
2497
2498         priv = netdev_priv(dev);
2499         bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2500                               phy_id, location, val);
2501 }
2502
2503 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2504 {
2505         struct mii_if_info mii;
2506
2507         mii.dev = dev;
2508         mii.mdio_read = bcm_enetsw_mii_mdio_read;
2509         mii.mdio_write = bcm_enetsw_mii_mdio_write;
2510         mii.phy_id = 0;
2511         mii.phy_id_mask = 0x3f;
2512         mii.reg_num_mask = 0x1f;
2513         return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2514
2515 }
2516
2517 static const struct net_device_ops bcm_enetsw_ops = {
2518         .ndo_open               = bcm_enetsw_open,
2519         .ndo_stop               = bcm_enetsw_stop,
2520         .ndo_start_xmit         = bcm_enet_start_xmit,
2521         .ndo_change_mtu         = bcm_enet_change_mtu,
2522         .ndo_do_ioctl           = bcm_enetsw_ioctl,
2523 };
2524
2525
2526 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2527         { "rx_packets", DEV_STAT(rx_packets), -1 },
2528         { "tx_packets", DEV_STAT(tx_packets), -1 },
2529         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2530         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2531         { "rx_errors", DEV_STAT(rx_errors), -1 },
2532         { "tx_errors", DEV_STAT(tx_errors), -1 },
2533         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2534         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2535
2536         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2537         { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2538         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2539         { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2540         { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2541         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2542         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2543         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2544         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2545         { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2546           ETHSW_MIB_RX_1024_1522 },
2547         { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2548           ETHSW_MIB_RX_1523_2047 },
2549         { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2550           ETHSW_MIB_RX_2048_4095 },
2551         { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2552           ETHSW_MIB_RX_4096_8191 },
2553         { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2554           ETHSW_MIB_RX_8192_9728 },
2555         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2556         { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2557         { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2558         { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2559         { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2560
2561         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2562         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2563         { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2564         { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2565         { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2566         { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2567
2568 };
2569
2570 #define BCM_ENETSW_STATS_LEN    \
2571         (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2572
2573 static void bcm_enetsw_get_strings(struct net_device *netdev,
2574                                    u32 stringset, u8 *data)
2575 {
2576         int i;
2577
2578         switch (stringset) {
2579         case ETH_SS_STATS:
2580                 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2581                         memcpy(data + i * ETH_GSTRING_LEN,
2582                                bcm_enetsw_gstrings_stats[i].stat_string,
2583                                ETH_GSTRING_LEN);
2584                 }
2585                 break;
2586         }
2587 }
2588
2589 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2590                                      int string_set)
2591 {
2592         switch (string_set) {
2593         case ETH_SS_STATS:
2594                 return BCM_ENETSW_STATS_LEN;
2595         default:
2596                 return -EINVAL;
2597         }
2598 }
2599
2600 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2601                                    struct ethtool_drvinfo *drvinfo)
2602 {
2603         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2604         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2605         strncpy(drvinfo->fw_version, "N/A", 32);
2606         strncpy(drvinfo->bus_info, "bcm63xx", 32);
2607 }
2608
2609 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2610                                          struct ethtool_stats *stats,
2611                                          u64 *data)
2612 {
2613         struct bcm_enet_priv *priv;
2614         int i;
2615
2616         priv = netdev_priv(netdev);
2617
2618         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2619                 const struct bcm_enet_stats *s;
2620                 u32 lo, hi;
2621                 char *p;
2622                 int reg;
2623
2624                 s = &bcm_enetsw_gstrings_stats[i];
2625
2626                 reg = s->mib_reg;
2627                 if (reg == -1)
2628                         continue;
2629
2630                 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2631                 p = (char *)priv + s->stat_offset;
2632
2633                 if (s->sizeof_stat == sizeof(u64)) {
2634                         hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2635                         *(u64 *)p = ((u64)hi << 32 | lo);
2636                 } else {
2637                         *(u32 *)p = lo;
2638                 }
2639         }
2640
2641         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2642                 const struct bcm_enet_stats *s;
2643                 char *p;
2644
2645                 s = &bcm_enetsw_gstrings_stats[i];
2646
2647                 if (s->mib_reg == -1)
2648                         p = (char *)&netdev->stats + s->stat_offset;
2649                 else
2650                         p = (char *)priv + s->stat_offset;
2651
2652                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2653                         *(u64 *)p : *(u32 *)p;
2654         }
2655 }
2656
2657 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2658                                      struct ethtool_ringparam *ering)
2659 {
2660         struct bcm_enet_priv *priv;
2661
2662         priv = netdev_priv(dev);
2663
2664         /* rx/tx ring is actually only limited by memory */
2665         ering->rx_max_pending = 8192;
2666         ering->tx_max_pending = 8192;
2667         ering->rx_mini_max_pending = 0;
2668         ering->rx_jumbo_max_pending = 0;
2669         ering->rx_pending = priv->rx_ring_size;
2670         ering->tx_pending = priv->tx_ring_size;
2671 }
2672
2673 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2674                                     struct ethtool_ringparam *ering)
2675 {
2676         struct bcm_enet_priv *priv;
2677         int was_running;
2678
2679         priv = netdev_priv(dev);
2680
2681         was_running = 0;
2682         if (netif_running(dev)) {
2683                 bcm_enetsw_stop(dev);
2684                 was_running = 1;
2685         }
2686
2687         priv->rx_ring_size = ering->rx_pending;
2688         priv->tx_ring_size = ering->tx_pending;
2689
2690         if (was_running) {
2691                 int err;
2692
2693                 err = bcm_enetsw_open(dev);
2694                 if (err)
2695                         dev_close(dev);
2696         }
2697         return 0;
2698 }
2699
2700 static struct ethtool_ops bcm_enetsw_ethtool_ops = {
2701         .get_strings            = bcm_enetsw_get_strings,
2702         .get_sset_count         = bcm_enetsw_get_sset_count,
2703         .get_ethtool_stats      = bcm_enetsw_get_ethtool_stats,
2704         .get_drvinfo            = bcm_enetsw_get_drvinfo,
2705         .get_ringparam          = bcm_enetsw_get_ringparam,
2706         .set_ringparam          = bcm_enetsw_set_ringparam,
2707 };
2708
2709 /* allocate netdevice, request register memory and register device. */
2710 static int bcm_enetsw_probe(struct platform_device *pdev)
2711 {
2712         struct bcm_enet_priv *priv;
2713         struct net_device *dev;
2714         struct bcm63xx_enetsw_platform_data *pd;
2715         struct resource *res_mem;
2716         int ret, irq_rx, irq_tx;
2717
2718         /* stop if shared driver failed, assume driver->probe will be
2719          * called in the same order we register devices (correct ?)
2720          */
2721         if (!bcm_enet_shared_base[0])
2722                 return -ENODEV;
2723
2724         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2725         irq_rx = platform_get_irq(pdev, 0);
2726         irq_tx = platform_get_irq(pdev, 1);
2727         if (!res_mem || irq_rx < 0)
2728                 return -ENODEV;
2729
2730         ret = 0;
2731         dev = alloc_etherdev(sizeof(*priv));
2732         if (!dev)
2733                 return -ENOMEM;
2734         priv = netdev_priv(dev);
2735         memset(priv, 0, sizeof(*priv));
2736
2737         /* initialize default and fetch platform data */
2738         priv->enet_is_sw = true;
2739         priv->irq_rx = irq_rx;
2740         priv->irq_tx = irq_tx;
2741         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2742         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2743         priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2744
2745         pd = dev_get_platdata(&pdev->dev);
2746         if (pd) {
2747                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2748                 memcpy(priv->used_ports, pd->used_ports,
2749                        sizeof(pd->used_ports));
2750                 priv->num_ports = pd->num_ports;
2751                 priv->dma_has_sram = pd->dma_has_sram;
2752                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2753                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2754                 priv->dma_chan_width = pd->dma_chan_width;
2755         }
2756
2757         ret = compute_hw_mtu(priv, dev->mtu);
2758         if (ret)
2759                 goto out;
2760
2761         if (!request_mem_region(res_mem->start, resource_size(res_mem),
2762                                 "bcm63xx_enetsw")) {
2763                 ret = -EBUSY;
2764                 goto out;
2765         }
2766
2767         priv->base = ioremap(res_mem->start, resource_size(res_mem));
2768         if (priv->base == NULL) {
2769                 ret = -ENOMEM;
2770                 goto out_release_mem;
2771         }
2772
2773         priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2774         if (IS_ERR(priv->mac_clk)) {
2775                 ret = PTR_ERR(priv->mac_clk);
2776                 goto out_unmap;
2777         }
2778         ret = clk_prepare_enable(priv->mac_clk);
2779         if (ret)
2780                 goto out_put_clk;
2781
2782         priv->rx_chan = 0;
2783         priv->tx_chan = 1;
2784         spin_lock_init(&priv->rx_lock);
2785
2786         /* init rx timeout (used for oom) */
2787         init_timer(&priv->rx_timeout);
2788         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2789         priv->rx_timeout.data = (unsigned long)dev;
2790
2791         /* register netdevice */
2792         dev->netdev_ops = &bcm_enetsw_ops;
2793         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2794         dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2795         SET_NETDEV_DEV(dev, &pdev->dev);
2796
2797         spin_lock_init(&priv->enetsw_mdio_lock);
2798
2799         ret = register_netdev(dev);
2800         if (ret)
2801                 goto out_disable_clk;
2802
2803         netif_carrier_off(dev);
2804         platform_set_drvdata(pdev, dev);
2805         priv->pdev = pdev;
2806         priv->net_dev = dev;
2807
2808         return 0;
2809
2810 out_disable_clk:
2811         clk_disable_unprepare(priv->mac_clk);
2812
2813 out_put_clk:
2814         clk_put(priv->mac_clk);
2815
2816 out_unmap:
2817         iounmap(priv->base);
2818
2819 out_release_mem:
2820         release_mem_region(res_mem->start, resource_size(res_mem));
2821 out:
2822         free_netdev(dev);
2823         return ret;
2824 }
2825
2826
2827 /* exit func, stops hardware and unregisters netdevice */
2828 static int bcm_enetsw_remove(struct platform_device *pdev)
2829 {
2830         struct bcm_enet_priv *priv;
2831         struct net_device *dev;
2832         struct resource *res;
2833
2834         /* stop netdevice */
2835         dev = platform_get_drvdata(pdev);
2836         priv = netdev_priv(dev);
2837         unregister_netdev(dev);
2838
2839         /* release device resources */
2840         iounmap(priv->base);
2841         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2842         release_mem_region(res->start, resource_size(res));
2843
2844         clk_disable_unprepare(priv->mac_clk);
2845         clk_put(priv->mac_clk);
2846
2847         free_netdev(dev);
2848         return 0;
2849 }
2850
2851 struct platform_driver bcm63xx_enetsw_driver = {
2852         .probe  = bcm_enetsw_probe,
2853         .remove = bcm_enetsw_remove,
2854         .driver = {
2855                 .name   = "bcm63xx_enetsw",
2856                 .owner  = THIS_MODULE,
2857         },
2858 };
2859
2860 /* reserve & remap memory space shared between all macs */
2861 static int bcm_enet_shared_probe(struct platform_device *pdev)
2862 {
2863         struct resource *res;
2864         void __iomem *p[3];
2865         unsigned int i;
2866
2867         memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2868
2869         for (i = 0; i < 3; i++) {
2870                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2871                 p[i] = devm_ioremap_resource(&pdev->dev, res);
2872                 if (IS_ERR(p[i]))
2873                         return PTR_ERR(p[i]);
2874         }
2875
2876         memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2877
2878         return 0;
2879 }
2880
2881 static int bcm_enet_shared_remove(struct platform_device *pdev)
2882 {
2883         return 0;
2884 }
2885
2886 /* this "shared" driver is needed because both macs share a single
2887  * address space
2888  */
2889 struct platform_driver bcm63xx_enet_shared_driver = {
2890         .probe  = bcm_enet_shared_probe,
2891         .remove = bcm_enet_shared_remove,
2892         .driver = {
2893                 .name   = "bcm63xx_enet_shared",
2894                 .owner  = THIS_MODULE,
2895         },
2896 };
2897
2898 static struct platform_driver * const drivers[] = {
2899         &bcm63xx_enet_shared_driver,
2900         &bcm63xx_enet_driver,
2901         &bcm63xx_enetsw_driver,
2902 };
2903
2904 /* entry point */
2905 static int __init bcm_enet_init(void)
2906 {
2907         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2908 }
2909
2910 static void __exit bcm_enet_exit(void)
2911 {
2912         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2913 }
2914
2915
2916 module_init(bcm_enet_init);
2917 module_exit(bcm_enet_exit);
2918
2919 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2920 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2921 MODULE_LICENSE("GPL");