drivers/net/ethernet/broadcom/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/crc32.h>
  29 #include <linux/err.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/if_vlan.h>
  33
  34 #include <bcm63xx_dev_enet.h>
  35 #include "bcm63xx_enet.h"
  36
  37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  38 static char bcm_enet_driver_version[] = "1.0";
  39
  40 static int copybreak __read_mostly = 128;
  41 module_param(copybreak, int, 0);
  42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  43
  44 /* io registers memory shared between all devices */
  45 static void __iomem *bcm_enet_shared_base[3];
  46
  47 /*
  48  * io helpers to access mac registers
  49  */
  50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  51 {
  52         return bcm_readl(priv->base + off);
  53 }
  54
  55 static inline void enet_writel(struct bcm_enet_priv *priv,
  56                                u32 val, u32 off)
  57 {
  58         bcm_writel(val, priv->base + off);
  59 }
  60
  61 /*
  62  * io helpers to access switch registers
  63  */
  64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
  65 {
  66         return bcm_readl(priv->base + off);
  67 }
  68
  69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
  70                                  u32 val, u32 off)
  71 {
  72         bcm_writel(val, priv->base + off);
  73 }
  74
  75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
  76 {
  77         return bcm_readw(priv->base + off);
  78 }
  79
  80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
  81                                  u16 val, u32 off)
  82 {
  83         bcm_writew(val, priv->base + off);
  84 }
  85
  86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
  87 {
  88         return bcm_readb(priv->base + off);
  89 }
  90
  91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
  92                                  u8 val, u32 off)
  93 {
  94         bcm_writeb(val, priv->base + off);
  95 }
  96
  97
  98 /* io helpers to access shared registers */
  99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
 100 {
 101         return bcm_readl(bcm_enet_shared_base[0] + off);
 102 }
 103
 104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
 105                                        u32 val, u32 off)
 106 {
 107         bcm_writel(val, bcm_enet_shared_base[0] + off);
 108 }
 109
 110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 111 {
 112         return bcm_readl(bcm_enet_shared_base[1] +
 113                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 114 }
 115
 116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 117                                        u32 val, u32 off, int chan)
 118 {
 119         bcm_writel(val, bcm_enet_shared_base[1] +
 120                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 121 }
 122
 123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 124 {
 125         return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 126 }
 127
 128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 129                                        u32 val, u32 off, int chan)
 130 {
 131         bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 132 }
 133
 134 /*
 135  * write given data into mii register and wait for transfer to end
 136  * with timeout (average measured transfer time is 25us)
 137  */
 138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
 139 {
 140         int limit;
 141
 142         /* make sure mii interrupt status is cleared */
 143         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
 144
 145         enet_writel(priv, data, ENET_MIIDATA_REG);
 146         wmb();
 147
 148         /* busy wait on mii interrupt bit, with timeout */
 149         limit = 1000;
 150         do {
 151                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
 152                         break;
 153                 udelay(1);
 154         } while (limit-- > 0);
 155
 156         return (limit < 0) ? 1 : 0;
 157 }
 158
 159 /*
 160  * MII internal read callback
 161  */
 162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 163                               int regnum)
 164 {
 165         u32 tmp, val;
 166
 167         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 168         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 169         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 170         tmp |= ENET_MIIDATA_OP_READ_MASK;
 171
 172         if (do_mdio_op(priv, tmp))
 173                 return -1;
 174
 175         val = enet_readl(priv, ENET_MIIDATA_REG);
 176         val &= 0xffff;
 177         return val;
 178 }
 179
 180 /*
 181  * MII internal write callback
 182  */
 183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 184                                int regnum, u16 value)
 185 {
 186         u32 tmp;
 187
 188         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 189         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 190         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 191         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 192         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 193
 194         (void)do_mdio_op(priv, tmp);
 195         return 0;
 196 }
 197
 198 /*
 199  * MII read callback from phylib
 200  */
 201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 202                                      int regnum)
 203 {
 204         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 205 }
 206
 207 /*
 208  * MII write callback from phylib
 209  */
 210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 211                                       int regnum, u16 value)
 212 {
 213         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 214 }
 215
 216 /*
 217  * MII read callback from mii core
 218  */
 219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 220                                   int regnum)
 221 {
 222         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 223 }
 224
 225 /*
 226  * MII write callback from mii core
 227  */
 228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 229                                     int regnum, int value)
 230 {
 231         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 232 }
 233
 234 /*
 235  * refill rx queue
 236  */
 237 static int bcm_enet_refill_rx(struct net_device *dev)
 238 {
 239         struct bcm_enet_priv *priv;
 240
 241         priv = netdev_priv(dev);
 242
 243         while (priv->rx_desc_count < priv->rx_ring_size) {
 244                 struct bcm_enet_desc *desc;
 245                 struct sk_buff *skb;
 246                 dma_addr_t p;
 247                 int desc_idx;
 248                 u32 len_stat;
 249
 250                 desc_idx = priv->rx_dirty_desc;
 251                 desc = &priv->rx_desc_cpu[desc_idx];
 252
 253                 if (!priv->rx_skb[desc_idx]) {
 254                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 255                         if (!skb)
 256                                 break;
 257                         priv->rx_skb[desc_idx] = skb;
 258                         p = dma_map_single(&priv->pdev->dev, skb->data,
 259                                            priv->rx_skb_size,
 260                                            DMA_FROM_DEVICE);
 261                         desc->address = p;
 262                 }
 263
 264                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 265                 len_stat |= DMADESC_OWNER_MASK;
 266                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 267                         len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 268                         priv->rx_dirty_desc = 0;
 269                 } else {
 270                         priv->rx_dirty_desc++;
 271                 }
 272                 wmb();
 273                 desc->len_stat = len_stat;
 274
 275                 priv->rx_desc_count++;
 276
 277                 /* tell dma engine we allocated one buffer */
 278                 if (priv->dma_has_sram)
 279                         enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 280                 else
 281                         enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 282         }
 283
 284         /* If rx ring is still empty, set a timer to try allocating
 285          * again at a later time. */
 286         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 287                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 288                 priv->rx_timeout.expires = jiffies + HZ;
 289                 add_timer(&priv->rx_timeout);
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * timer callback to defer refill rx queue in case we're OOM
 297  */
 298 static void bcm_enet_refill_rx_timer(unsigned long data)
 299 {
 300         struct net_device *dev;
 301         struct bcm_enet_priv *priv;
 302
 303         dev = (struct net_device *)data;
 304         priv = netdev_priv(dev);
 305
 306         spin_lock(&priv->rx_lock);
 307         bcm_enet_refill_rx((struct net_device *)data);
 308         spin_unlock(&priv->rx_lock);
 309 }
 310
 311 /*
 312  * extract packet from rx queue
 313  */
 314 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 315 {
 316         struct bcm_enet_priv *priv;
 317         struct device *kdev;
 318         int processed;
 319
 320         priv = netdev_priv(dev);
 321         kdev = &priv->pdev->dev;
 322         processed = 0;
 323
 324         /* don't scan ring further than number of refilled
 325          * descriptor */
 326         if (budget > priv->rx_desc_count)
 327                 budget = priv->rx_desc_count;
 328
 329         do {
 330                 struct bcm_enet_desc *desc;
 331                 struct sk_buff *skb;
 332                 int desc_idx;
 333                 u32 len_stat;
 334                 unsigned int len;
 335
 336                 desc_idx = priv->rx_curr_desc;
 337                 desc = &priv->rx_desc_cpu[desc_idx];
 338
 339                 /* make sure we actually read the descriptor status at
 340                  * each loop */
 341                 rmb();
 342
 343                 len_stat = desc->len_stat;
 344
 345                 /* break if dma ownership belongs to hw */
 346                 if (len_stat & DMADESC_OWNER_MASK)
 347                         break;
 348
 349                 processed++;
 350                 priv->rx_curr_desc++;
 351                 if (priv->rx_curr_desc == priv->rx_ring_size)
 352                         priv->rx_curr_desc = 0;
 353                 priv->rx_desc_count--;
 354
 355                 /* if the packet does not have start of packet _and_
 356                  * end of packet flag set, then just recycle it */
 357                 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 358                         (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 359                         dev->stats.rx_dropped++;
 360                         continue;
 361                 }
 362
 363                 /* recycle packet if it's marked as bad */
 364                 if (!priv->enet_is_sw &&
 365                     unlikely(len_stat & DMADESC_ERR_MASK)) {
 366                         dev->stats.rx_errors++;
 367
 368                         if (len_stat & DMADESC_OVSIZE_MASK)
 369                                 dev->stats.rx_length_errors++;
 370                         if (len_stat & DMADESC_CRC_MASK)
 371                                 dev->stats.rx_crc_errors++;
 372                         if (len_stat & DMADESC_UNDER_MASK)
 373                                 dev->stats.rx_frame_errors++;
 374                         if (len_stat & DMADESC_OV_MASK)
 375                                 dev->stats.rx_fifo_errors++;
 376                         continue;
 377                 }
 378
 379                 /* valid packet */
 380                 skb = priv->rx_skb[desc_idx];
 381                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 382                 /* don't include FCS */
 383                 len -= 4;
 384
 385                 if (len < copybreak) {
 386                         struct sk_buff *nskb;
 387
 388                         nskb = napi_alloc_skb(&priv->napi, len);
 389                         if (!nskb) {
 390                                 /* forget packet, just rearm desc */
 391                                 dev->stats.rx_dropped++;
 392                                 continue;
 393                         }
 394
 395                         dma_sync_single_for_cpu(kdev, desc->address,
 396                                                 len, DMA_FROM_DEVICE);
 397                         memcpy(nskb->data, skb->data, len);
 398                         dma_sync_single_for_device(kdev, desc->address,
 399                                                    len, DMA_FROM_DEVICE);
 400                         skb = nskb;
 401                 } else {
 402                         dma_unmap_single(&priv->pdev->dev, desc->address,
 403                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 404                         priv->rx_skb[desc_idx] = NULL;
 405                 }
 406
 407                 skb_put(skb, len);
 408                 skb->protocol = eth_type_trans(skb, dev);
 409                 dev->stats.rx_packets++;
 410                 dev->stats.rx_bytes += len;
 411                 netif_receive_skb(skb);
 412
 413         } while (--budget > 0);
 414
 415         if (processed || !priv->rx_desc_count) {
 416                 bcm_enet_refill_rx(dev);
 417
 418                 /* kick rx dma */
 419                 enet_dmac_writel(priv, priv->dma_chan_en_mask,
 420                                          ENETDMAC_CHANCFG, priv->rx_chan);
 421         }
 422
 423         return processed;
 424 }
 425
 426
 427 /*
 428  * try to or force reclaim of transmitted buffers
 429  */
 430 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 431 {
 432         struct bcm_enet_priv *priv;
 433         int released;
 434
 435         priv = netdev_priv(dev);
 436         released = 0;
 437
 438         while (priv->tx_desc_count < priv->tx_ring_size) {
 439                 struct bcm_enet_desc *desc;
 440                 struct sk_buff *skb;
 441
 442                 /* We run in a bh and fight against start_xmit, which
 443                  * is called with bh disabled  */
 444                 spin_lock(&priv->tx_lock);
 445
 446                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 447
 448                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 449                         spin_unlock(&priv->tx_lock);
 450                         break;
 451                 }
 452
 453                 /* ensure other field of the descriptor were not read
 454                  * before we checked ownership */
 455                 rmb();
 456
 457                 skb = priv->tx_skb[priv->tx_dirty_desc];
 458                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 459                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 460                                  DMA_TO_DEVICE);
 461
 462                 priv->tx_dirty_desc++;
 463                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 464                         priv->tx_dirty_desc = 0;
 465                 priv->tx_desc_count++;
 466
 467                 spin_unlock(&priv->tx_lock);
 468
 469                 if (desc->len_stat & DMADESC_UNDER_MASK)
 470                         dev->stats.tx_errors++;
 471
 472                 dev_kfree_skb(skb);
 473                 released++;
 474         }
 475
 476         if (netif_queue_stopped(dev) && released)
 477                 netif_wake_queue(dev);
 478
 479         return released;
 480 }
 481
 482 /*
 483  * poll func, called by network core
 484  */
 485 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 486 {
 487         struct bcm_enet_priv *priv;
 488         struct net_device *dev;
 489         int rx_work_done;
 490
 491         priv = container_of(napi, struct bcm_enet_priv, napi);
 492         dev = priv->net_dev;
 493
 494         /* ack interrupts */
 495         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 496                          ENETDMAC_IR, priv->rx_chan);
 497         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 498                          ENETDMAC_IR, priv->tx_chan);
 499
 500         /* reclaim sent skb */
 501         bcm_enet_tx_reclaim(dev, 0);
 502
 503         spin_lock(&priv->rx_lock);
 504         rx_work_done = bcm_enet_receive_queue(dev, budget);
 505         spin_unlock(&priv->rx_lock);
 506
 507         if (rx_work_done >= budget) {
 508                 /* rx queue is not yet empty/clean */
 509                 return rx_work_done;
 510         }
 511
 512         /* no more packet in rx/tx queue, remove device from poll
 513          * queue */
 514         napi_complete(napi);
 515
 516         /* restore rx/tx interrupt */
 517         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 518                          ENETDMAC_IRMASK, priv->rx_chan);
 519         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 520                          ENETDMAC_IRMASK, priv->tx_chan);
 521
 522         return rx_work_done;
 523 }
 524
 525 /*
 526  * mac interrupt handler
 527  */
 528 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 529 {
 530         struct net_device *dev;
 531         struct bcm_enet_priv *priv;
 532         u32 stat;
 533
 534         dev = dev_id;
 535         priv = netdev_priv(dev);
 536
 537         stat = enet_readl(priv, ENET_IR_REG);
 538         if (!(stat & ENET_IR_MIB))
 539                 return IRQ_NONE;
 540
 541         /* clear & mask interrupt */
 542         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 543         enet_writel(priv, 0, ENET_IRMASK_REG);
 544
 545         /* read mib registers in workqueue */
 546         schedule_work(&priv->mib_update_task);
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 /*
 552  * rx/tx dma interrupt handler
 553  */
 554 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 555 {
 556         struct net_device *dev;
 557         struct bcm_enet_priv *priv;
 558
 559         dev = dev_id;
 560         priv = netdev_priv(dev);
 561
 562         /* mask rx/tx interrupts */
 563         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 564         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 565
 566         napi_schedule(&priv->napi);
 567
 568         return IRQ_HANDLED;
 569 }
 570
 571 /*
 572  * tx request callback
 573  */
 574 static netdev_tx_t
 575 bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 576 {
 577         struct bcm_enet_priv *priv;
 578         struct bcm_enet_desc *desc;
 579         u32 len_stat;
 580         netdev_tx_t ret;
 581
 582         priv = netdev_priv(dev);
 583
 584         /* lock against tx reclaim */
 585         spin_lock(&priv->tx_lock);
 586
 587         /* make sure  the tx hw queue  is not full,  should not happen
 588          * since we stop queue before it's the case */
 589         if (unlikely(!priv->tx_desc_count)) {
 590                 netif_stop_queue(dev);
 591                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 592                         "available?\n");
 593                 ret = NETDEV_TX_BUSY;
 594                 goto out_unlock;
 595         }
 596
 597         /* pad small packets sent on a switch device */
 598         if (priv->enet_is_sw && skb->len < 64) {
 599                 int needed = 64 - skb->len;
 600                 char *data;
 601
 602                 if (unlikely(skb_tailroom(skb) < needed)) {
 603                         struct sk_buff *nskb;
 604
 605                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 606                         if (!nskb) {
 607                                 ret = NETDEV_TX_BUSY;
 608                                 goto out_unlock;
 609                         }
 610                         dev_kfree_skb(skb);
 611                         skb = nskb;
 612                 }
 613                 data = skb_put(skb, needed);
 614                 memset(data, 0, needed);
 615         }
 616
 617         /* point to the next available desc */
 618         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 619         priv->tx_skb[priv->tx_curr_desc] = skb;
 620
 621         /* fill descriptor */
 622         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 623                                        DMA_TO_DEVICE);
 624
 625         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 626         len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 627                 DMADESC_APPEND_CRC |
 628                 DMADESC_OWNER_MASK;
 629
 630         priv->tx_curr_desc++;
 631         if (priv->tx_curr_desc == priv->tx_ring_size) {
 632                 priv->tx_curr_desc = 0;
 633                 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 634         }
 635         priv->tx_desc_count--;
 636
 637         /* dma might be already polling, make sure we update desc
 638          * fields in correct order */
 639         wmb();
 640         desc->len_stat = len_stat;
 641         wmb();
 642
 643         /* kick tx dma */
 644         enet_dmac_writel(priv, priv->dma_chan_en_mask,
 645                                  ENETDMAC_CHANCFG, priv->tx_chan);
 646
 647         /* stop queue if no more desc available */
 648         if (!priv->tx_desc_count)
 649                 netif_stop_queue(dev);
 650
 651         dev->stats.tx_bytes += skb->len;
 652         dev->stats.tx_packets++;
 653         ret = NETDEV_TX_OK;
 654
 655 out_unlock:
 656         spin_unlock(&priv->tx_lock);
 657         return ret;
 658 }
 659
 660 /*
 661  * Change the interface's mac address.
 662  */
 663 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 664 {
 665         struct bcm_enet_priv *priv;
 666         struct sockaddr *addr = p;
 667         u32 val;
 668
 669         priv = netdev_priv(dev);
 670         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 671
 672         /* use perfect match register 0 to store my mac address */
 673         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 674                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 675         enet_writel(priv, val, ENET_PML_REG(0));
 676
 677         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 678         val |= ENET_PMH_DATAVALID_MASK;
 679         enet_writel(priv, val, ENET_PMH_REG(0));
 680
 681         return 0;
 682 }
 683
 684 /*
 685  * Change rx mode (promiscuous/allmulti) and update multicast list
 686  */
 687 static void bcm_enet_set_multicast_list(struct net_device *dev)
 688 {
 689         struct bcm_enet_priv *priv;
 690         struct netdev_hw_addr *ha;
 691         u32 val;
 692         int i;
 693
 694         priv = netdev_priv(dev);
 695
 696         val = enet_readl(priv, ENET_RXCFG_REG);
 697
 698         if (dev->flags & IFF_PROMISC)
 699                 val |= ENET_RXCFG_PROMISC_MASK;
 700         else
 701                 val &= ~ENET_RXCFG_PROMISC_MASK;
 702
 703         /* only 3 perfect match registers left, first one is used for
 704          * own mac address */
 705         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 706                 val |= ENET_RXCFG_ALLMCAST_MASK;
 707         else
 708                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 709
 710         /* no need to set perfect match registers if we catch all
 711          * multicast */
 712         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 713                 enet_writel(priv, val, ENET_RXCFG_REG);
 714                 return;
 715         }
 716
 717         i = 0;
 718         netdev_for_each_mc_addr(ha, dev) {
 719                 u8 *dmi_addr;
 720                 u32 tmp;
 721
 722                 if (i == 3)
 723                         break;
 724                 /* update perfect match registers */
 725                 dmi_addr = ha->addr;
 726                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 727                         (dmi_addr[4] << 8) | dmi_addr[5];
 728                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 729
 730                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 731                 tmp |= ENET_PMH_DATAVALID_MASK;
 732                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 733         }
 734
 735         for (; i < 3; i++) {
 736                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 737                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 738         }
 739
 740         enet_writel(priv, val, ENET_RXCFG_REG);
 741 }
 742
 743 /*
 744  * set mac duplex parameters
 745  */
 746 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 747 {
 748         u32 val;
 749
 750         val = enet_readl(priv, ENET_TXCTL_REG);
 751         if (fullduplex)
 752                 val |= ENET_TXCTL_FD_MASK;
 753         else
 754                 val &= ~ENET_TXCTL_FD_MASK;
 755         enet_writel(priv, val, ENET_TXCTL_REG);
 756 }
 757
 758 /*
 759  * set mac flow control parameters
 760  */
 761 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 762 {
 763         u32 val;
 764
 765         /* rx flow control (pause frame handling) */
 766         val = enet_readl(priv, ENET_RXCFG_REG);
 767         if (rx_en)
 768                 val |= ENET_RXCFG_ENFLOW_MASK;
 769         else
 770                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 771         enet_writel(priv, val, ENET_RXCFG_REG);
 772
 773         if (!priv->dma_has_sram)
 774                 return;
 775
 776         /* tx flow control (pause frame generation) */
 777         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 778         if (tx_en)
 779                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 780         else
 781                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 782         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 783 }
 784
 785 /*
 786  * link changed callback (from phylib)
 787  */
 788 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 789 {
 790         struct bcm_enet_priv *priv;
 791         struct phy_device *phydev;
 792         int status_changed;
 793
 794         priv = netdev_priv(dev);
 795         phydev = priv->phydev;
 796         status_changed = 0;
 797
 798         if (priv->old_link != phydev->link) {
 799                 status_changed = 1;
 800                 priv->old_link = phydev->link;
 801         }
 802
 803         /* reflect duplex change in mac configuration */
 804         if (phydev->link && phydev->duplex != priv->old_duplex) {
 805                 bcm_enet_set_duplex(priv,
 806                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 807                 status_changed = 1;
 808                 priv->old_duplex = phydev->duplex;
 809         }
 810
 811         /* enable flow control if remote advertise it (trust phylib to
 812          * check that duplex is full */
 813         if (phydev->link && phydev->pause != priv->old_pause) {
 814                 int rx_pause_en, tx_pause_en;
 815
 816                 if (phydev->pause) {
 817                         /* pause was advertised by lpa and us */
 818                         rx_pause_en = 1;
 819                         tx_pause_en = 1;
 820                 } else if (!priv->pause_auto) {
 821                         /* pause setting overrided by user */
 822                         rx_pause_en = priv->pause_rx;
 823                         tx_pause_en = priv->pause_tx;
 824                 } else {
 825                         rx_pause_en = 0;
 826                         tx_pause_en = 0;
 827                 }
 828
 829                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 830                 status_changed = 1;
 831                 priv->old_pause = phydev->pause;
 832         }
 833
 834         if (status_changed) {
 835                 pr_info("%s: link %s", dev->name, phydev->link ?
 836                         "UP" : "DOWN");
 837                 if (phydev->link)
 838                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 839                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 840                                phydev->pause == 1 ? "rx&tx" : "off");
 841
 842                 pr_cont("\n");
 843         }
 844 }
 845
 846 /*
 847  * link changed callback (if phylib is not used)
 848  */
 849 static void bcm_enet_adjust_link(struct net_device *dev)
 850 {
 851         struct bcm_enet_priv *priv;
 852
 853         priv = netdev_priv(dev);
 854         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 855         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 856         netif_carrier_on(dev);
 857
 858         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 859                 dev->name,
 860                 priv->force_speed_100 ? 100 : 10,
 861                 priv->force_duplex_full ? "full" : "half",
 862                 priv->pause_rx ? "rx" : "off",
 863                 priv->pause_tx ? "tx" : "off");
 864 }
 865
 866 /*
 867  * open callback, allocate dma rings & buffers and start rx operation
 868  */
 869 static int bcm_enet_open(struct net_device *dev)
 870 {
 871         struct bcm_enet_priv *priv;
 872         struct sockaddr addr;
 873         struct device *kdev;
 874         struct phy_device *phydev;
 875         int i, ret;
 876         unsigned int size;
 877         char phy_id[MII_BUS_ID_SIZE + 3];
 878         void *p;
 879         u32 val;
 880
 881         priv = netdev_priv(dev);
 882         kdev = &priv->pdev->dev;
 883
 884         if (priv->has_phy) {
 885                 /* connect to PHY */
 886                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 887                          priv->mii_bus->id, priv->phy_id);
 888
 889                 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
 890                                      PHY_INTERFACE_MODE_MII);
 891
 892                 if (IS_ERR(phydev)) {
 893                         dev_err(kdev, "could not attach to PHY\n");
 894                         return PTR_ERR(phydev);
 895                 }
 896
 897                 /* mask with MAC supported features */
 898                 phydev->supported &= (SUPPORTED_10baseT_Half |
 899                                       SUPPORTED_10baseT_Full |
 900                                       SUPPORTED_100baseT_Half |
 901                                       SUPPORTED_100baseT_Full |
 902                                       SUPPORTED_Autoneg |
 903                                       SUPPORTED_Pause |
 904                                       SUPPORTED_MII);
 905                 phydev->advertising = phydev->supported;
 906
 907                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 908                         phydev->advertising |= SUPPORTED_Pause;
 909                 else
 910                         phydev->advertising &= ~SUPPORTED_Pause;
 911
 912                 dev_info(kdev, "attached PHY at address %d [%s]\n",
 913                          phydev->addr, phydev->drv->name);
 914
 915                 priv->old_link = 0;
 916                 priv->old_duplex = -1;
 917                 priv->old_pause = -1;
 918                 priv->phydev = phydev;
 919         }
 920
 921         /* mask all interrupts and request them */
 922         enet_writel(priv, 0, ENET_IRMASK_REG);
 923         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 924         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 925
 926         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 927         if (ret)
 928                 goto out_phy_disconnect;
 929
 930         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
 931                           dev->name, dev);
 932         if (ret)
 933                 goto out_freeirq;
 934
 935         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 936                           0, dev->name, dev);
 937         if (ret)
 938                 goto out_freeirq_rx;
 939
 940         /* initialize perfect match registers */
 941         for (i = 0; i < 4; i++) {
 942                 enet_writel(priv, 0, ENET_PML_REG(i));
 943                 enet_writel(priv, 0, ENET_PMH_REG(i));
 944         }
 945
 946         /* write device mac address */
 947         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 948         bcm_enet_set_mac_address(dev, &addr);
 949
 950         /* allocate rx dma ring */
 951         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 952         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 953         if (!p) {
 954                 ret = -ENOMEM;
 955                 goto out_freeirq_tx;
 956         }
 957
 958         priv->rx_desc_alloc_size = size;
 959         priv->rx_desc_cpu = p;
 960
 961         /* allocate tx dma ring */
 962         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 963         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 964         if (!p) {
 965                 ret = -ENOMEM;
 966                 goto out_free_rx_ring;
 967         }
 968
 969         priv->tx_desc_alloc_size = size;
 970         priv->tx_desc_cpu = p;
 971
 972         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
 973                                GFP_KERNEL);
 974         if (!priv->tx_skb) {
 975                 ret = -ENOMEM;
 976                 goto out_free_tx_ring;
 977         }
 978
 979         priv->tx_desc_count = priv->tx_ring_size;
 980         priv->tx_dirty_desc = 0;
 981         priv->tx_curr_desc = 0;
 982         spin_lock_init(&priv->tx_lock);
 983
 984         /* init & fill rx ring with skbs */
 985         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
 986                                GFP_KERNEL);
 987         if (!priv->rx_skb) {
 988                 ret = -ENOMEM;
 989                 goto out_free_tx_skb;
 990         }
 991
 992         priv->rx_desc_count = 0;
 993         priv->rx_dirty_desc = 0;
 994         priv->rx_curr_desc = 0;
 995
 996         /* initialize flow control buffer allocation */
 997         if (priv->dma_has_sram)
 998                 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 999                                 ENETDMA_BUFALLOC_REG(priv->rx_chan));
1000         else
1001                 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
1002                                 ENETDMAC_BUFALLOC, priv->rx_chan);
1003
1004         if (bcm_enet_refill_rx(dev)) {
1005                 dev_err(kdev, "cannot allocate rx skb queue\n");
1006                 ret = -ENOMEM;
1007                 goto out;
1008         }
1009
1010         /* write rx & tx ring addresses */
1011         if (priv->dma_has_sram) {
1012                 enet_dmas_writel(priv, priv->rx_desc_dma,
1013                                  ENETDMAS_RSTART_REG, priv->rx_chan);
1014                 enet_dmas_writel(priv, priv->tx_desc_dma,
1015                          ENETDMAS_RSTART_REG, priv->tx_chan);
1016         } else {
1017                 enet_dmac_writel(priv, priv->rx_desc_dma,
1018                                 ENETDMAC_RSTART, priv->rx_chan);
1019                 enet_dmac_writel(priv, priv->tx_desc_dma,
1020                                 ENETDMAC_RSTART, priv->tx_chan);
1021         }
1022
1023         /* clear remaining state ram for rx & tx channel */
1024         if (priv->dma_has_sram) {
1025                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1026                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1027                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1028                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1029                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1030                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1031         } else {
1032                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1033                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1034         }
1035
1036         /* set max rx/tx length */
1037         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1038         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1039
1040         /* set dma maximum burst len */
1041         enet_dmac_writel(priv, priv->dma_maxburst,
1042                          ENETDMAC_MAXBURST, priv->rx_chan);
1043         enet_dmac_writel(priv, priv->dma_maxburst,
1044                          ENETDMAC_MAXBURST, priv->tx_chan);
1045
1046         /* set correct transmit fifo watermark */
1047         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1048
1049         /* set flow control low/high threshold to 1/3 / 2/3 */
1050         if (priv->dma_has_sram) {
1051                 val = priv->rx_ring_size / 3;
1052                 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1053                 val = (priv->rx_ring_size * 2) / 3;
1054                 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1055         } else {
1056                 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1057                 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1058                 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1059         }
1060
1061         /* all set, enable mac and interrupts, start dma engine and
1062          * kick rx dma channel */
1063         wmb();
1064         val = enet_readl(priv, ENET_CTL_REG);
1065         val |= ENET_CTL_ENABLE_MASK;
1066         enet_writel(priv, val, ENET_CTL_REG);
1067         if (priv->dma_has_sram)
1068                 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1069         enet_dmac_writel(priv, priv->dma_chan_en_mask,
1070                          ENETDMAC_CHANCFG, priv->rx_chan);
1071
1072         /* watch "mib counters about to overflow" interrupt */
1073         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1074         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1075
1076         /* watch "packet transferred" interrupt in rx and tx */
1077         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1078                          ENETDMAC_IR, priv->rx_chan);
1079         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1080                          ENETDMAC_IR, priv->tx_chan);
1081
1082         /* make sure we enable napi before rx interrupt  */
1083         napi_enable(&priv->napi);
1084
1085         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1086                          ENETDMAC_IRMASK, priv->rx_chan);
1087         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1088                          ENETDMAC_IRMASK, priv->tx_chan);
1089
1090         if (priv->has_phy)
1091                 phy_start(priv->phydev);
1092         else
1093                 bcm_enet_adjust_link(dev);
1094
1095         netif_start_queue(dev);
1096         return 0;
1097
1098 out:
1099         for (i = 0; i < priv->rx_ring_size; i++) {
1100                 struct bcm_enet_desc *desc;
1101
1102                 if (!priv->rx_skb[i])
1103                         continue;
1104
1105                 desc = &priv->rx_desc_cpu[i];
1106                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1107                                  DMA_FROM_DEVICE);
1108                 kfree_skb(priv->rx_skb[i]);
1109         }
1110         kfree(priv->rx_skb);
1111
1112 out_free_tx_skb:
1113         kfree(priv->tx_skb);
1114
1115 out_free_tx_ring:
1116         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1117                           priv->tx_desc_cpu, priv->tx_desc_dma);
1118
1119 out_free_rx_ring:
1120         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1121                           priv->rx_desc_cpu, priv->rx_desc_dma);
1122
1123 out_freeirq_tx:
1124         free_irq(priv->irq_tx, dev);
1125
1126 out_freeirq_rx:
1127         free_irq(priv->irq_rx, dev);
1128
1129 out_freeirq:
1130         free_irq(dev->irq, dev);
1131
1132 out_phy_disconnect:
1133         phy_disconnect(priv->phydev);
1134
1135         return ret;
1136 }
1137
1138 /*
1139  * disable mac
1140  */
1141 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1142 {
1143         int limit;
1144         u32 val;
1145
1146         val = enet_readl(priv, ENET_CTL_REG);
1147         val |= ENET_CTL_DISABLE_MASK;
1148         enet_writel(priv, val, ENET_CTL_REG);
1149
1150         limit = 1000;
1151         do {
1152                 u32 val;
1153
1154                 val = enet_readl(priv, ENET_CTL_REG);
1155                 if (!(val & ENET_CTL_DISABLE_MASK))
1156                         break;
1157                 udelay(1);
1158         } while (limit--);
1159 }
1160
1161 /*
1162  * disable dma in given channel
1163  */
1164 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1165 {
1166         int limit;
1167
1168         enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1169
1170         limit = 1000;
1171         do {
1172                 u32 val;
1173
1174                 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1175                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1176                         break;
1177                 udelay(1);
1178         } while (limit--);
1179 }
1180
1181 /*
1182  * stop callback
1183  */
1184 static int bcm_enet_stop(struct net_device *dev)
1185 {
1186         struct bcm_enet_priv *priv;
1187         struct device *kdev;
1188         int i;
1189
1190         priv = netdev_priv(dev);
1191         kdev = &priv->pdev->dev;
1192
1193         netif_stop_queue(dev);
1194         napi_disable(&priv->napi);
1195         if (priv->has_phy)
1196                 phy_stop(priv->phydev);
1197         del_timer_sync(&priv->rx_timeout);
1198
1199         /* mask all interrupts */
1200         enet_writel(priv, 0, ENET_IRMASK_REG);
1201         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1202         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1203
1204         /* make sure no mib update is scheduled */
1205         cancel_work_sync(&priv->mib_update_task);
1206
1207         /* disable dma & mac */
1208         bcm_enet_disable_dma(priv, priv->tx_chan);
1209         bcm_enet_disable_dma(priv, priv->rx_chan);
1210         bcm_enet_disable_mac(priv);
1211
1212         /* force reclaim of all tx buffers */
1213         bcm_enet_tx_reclaim(dev, 1);
1214
1215         /* free the rx skb ring */
1216         for (i = 0; i < priv->rx_ring_size; i++) {
1217                 struct bcm_enet_desc *desc;
1218
1219                 if (!priv->rx_skb[i])
1220                         continue;
1221
1222                 desc = &priv->rx_desc_cpu[i];
1223                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1224                                  DMA_FROM_DEVICE);
1225                 kfree_skb(priv->rx_skb[i]);
1226         }
1227
1228         /* free remaining allocated memory */
1229         kfree(priv->rx_skb);
1230         kfree(priv->tx_skb);
1231         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1232                           priv->rx_desc_cpu, priv->rx_desc_dma);
1233         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1234                           priv->tx_desc_cpu, priv->tx_desc_dma);
1235         free_irq(priv->irq_tx, dev);
1236         free_irq(priv->irq_rx, dev);
1237         free_irq(dev->irq, dev);
1238
1239         /* release phy */
1240         if (priv->has_phy) {
1241                 phy_disconnect(priv->phydev);
1242                 priv->phydev = NULL;
1243         }
1244
1245         return 0;
1246 }
1247
1248 /*
1249  * ethtool callbacks
1250  */
1251 struct bcm_enet_stats {
1252         char stat_string[ETH_GSTRING_LEN];
1253         int sizeof_stat;
1254         int stat_offset;
1255         int mib_reg;
1256 };
1257
1258 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1259                      offsetof(struct bcm_enet_priv, m)
1260 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m),          \
1261                      offsetof(struct net_device_stats, m)
1262
1263 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1264         { "rx_packets", DEV_STAT(rx_packets), -1 },
1265         { "tx_packets", DEV_STAT(tx_packets), -1 },
1266         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1267         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1268         { "rx_errors", DEV_STAT(rx_errors), -1 },
1269         { "tx_errors", DEV_STAT(tx_errors), -1 },
1270         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1271         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1272
1273         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1274         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1275         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1276         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1277         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1278         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1279         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1280         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1281         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1282         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1283         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1284         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1285         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1286         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1287         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1288         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1289         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1290         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1291         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1292         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1293         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1294
1295         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1296         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1297         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1298         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1299         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1300         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1301         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1302         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1303         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1304         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1305         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1306         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1307         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1308         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1309         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1310         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1311         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1312         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1313         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1314         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1315         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1316         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1317
1318 };
1319
1320 #define BCM_ENET_STATS_LEN      ARRAY_SIZE(bcm_enet_gstrings_stats)
1321
1322 static const u32 unused_mib_regs[] = {
1323         ETH_MIB_TX_ALL_OCTETS,
1324         ETH_MIB_TX_ALL_PKTS,
1325         ETH_MIB_RX_ALL_OCTETS,
1326         ETH_MIB_RX_ALL_PKTS,
1327 };
1328
1329
1330 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1331                                  struct ethtool_drvinfo *drvinfo)
1332 {
1333         strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1334         strlcpy(drvinfo->version, bcm_enet_driver_version,
1335                 sizeof(drvinfo->version));
1336         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1337         strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1338 }
1339
1340 static int bcm_enet_get_sset_count(struct net_device *netdev,
1341                                         int string_set)
1342 {
1343         switch (string_set) {
1344         case ETH_SS_STATS:
1345                 return BCM_ENET_STATS_LEN;
1346         default:
1347                 return -EINVAL;
1348         }
1349 }
1350
1351 static void bcm_enet_get_strings(struct net_device *netdev,
1352                                  u32 stringset, u8 *data)
1353 {
1354         int i;
1355
1356         switch (stringset) {
1357         case ETH_SS_STATS:
1358                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1359                         memcpy(data + i * ETH_GSTRING_LEN,
1360                                bcm_enet_gstrings_stats[i].stat_string,
1361                                ETH_GSTRING_LEN);
1362                 }
1363                 break;
1364         }
1365 }
1366
1367 static void update_mib_counters(struct bcm_enet_priv *priv)
1368 {
1369         int i;
1370
1371         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1372                 const struct bcm_enet_stats *s;
1373                 u32 val;
1374                 char *p;
1375
1376                 s = &bcm_enet_gstrings_stats[i];
1377                 if (s->mib_reg == -1)
1378                         continue;
1379
1380                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1381                 p = (char *)priv + s->stat_offset;
1382
1383                 if (s->sizeof_stat == sizeof(u64))
1384                         *(u64 *)p += val;
1385                 else
1386                         *(u32 *)p += val;
1387         }
1388
1389         /* also empty unused mib counters to make sure mib counter
1390          * overflow interrupt is cleared */
1391         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1392                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1393 }
1394
1395 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1396 {
1397         struct bcm_enet_priv *priv;
1398
1399         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1400         mutex_lock(&priv->mib_update_lock);
1401         update_mib_counters(priv);
1402         mutex_unlock(&priv->mib_update_lock);
1403
1404         /* reenable mib interrupt */
1405         if (netif_running(priv->net_dev))
1406                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1407 }
1408
1409 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1410                                        struct ethtool_stats *stats,
1411                                        u64 *data)
1412 {
1413         struct bcm_enet_priv *priv;
1414         int i;
1415
1416         priv = netdev_priv(netdev);
1417
1418         mutex_lock(&priv->mib_update_lock);
1419         update_mib_counters(priv);
1420
1421         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1422                 const struct bcm_enet_stats *s;
1423                 char *p;
1424
1425                 s = &bcm_enet_gstrings_stats[i];
1426                 if (s->mib_reg == -1)
1427                         p = (char *)&netdev->stats;
1428                 else
1429                         p = (char *)priv;
1430                 p += s->stat_offset;
1431                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1432                         *(u64 *)p : *(u32 *)p;
1433         }
1434         mutex_unlock(&priv->mib_update_lock);
1435 }
1436
1437 static int bcm_enet_nway_reset(struct net_device *dev)
1438 {
1439         struct bcm_enet_priv *priv;
1440
1441         priv = netdev_priv(dev);
1442         if (priv->has_phy) {
1443                 if (!priv->phydev)
1444                         return -ENODEV;
1445                 return genphy_restart_aneg(priv->phydev);
1446         }
1447
1448         return -EOPNOTSUPP;
1449 }
1450
1451 static int bcm_enet_get_settings(struct net_device *dev,
1452                                  struct ethtool_cmd *cmd)
1453 {
1454         struct bcm_enet_priv *priv;
1455
1456         priv = netdev_priv(dev);
1457
1458         cmd->maxrxpkt = 0;
1459         cmd->maxtxpkt = 0;
1460
1461         if (priv->has_phy) {
1462                 if (!priv->phydev)
1463                         return -ENODEV;
1464                 return phy_ethtool_gset(priv->phydev, cmd);
1465         } else {
1466                 cmd->autoneg = 0;
1467                 ethtool_cmd_speed_set(cmd, ((priv->force_speed_100)
1468                                             ? SPEED_100 : SPEED_10));
1469                 cmd->duplex = (priv->force_duplex_full) ?
1470                         DUPLEX_FULL : DUPLEX_HALF;
1471                 cmd->supported = ADVERTISED_10baseT_Half  |
1472                         ADVERTISED_10baseT_Full |
1473                         ADVERTISED_100baseT_Half |
1474                         ADVERTISED_100baseT_Full;
1475                 cmd->advertising = 0;
1476                 cmd->port = PORT_MII;
1477                 cmd->transceiver = XCVR_EXTERNAL;
1478         }
1479         return 0;
1480 }
1481
1482 static int bcm_enet_set_settings(struct net_device *dev,
1483                                  struct ethtool_cmd *cmd)
1484 {
1485         struct bcm_enet_priv *priv;
1486
1487         priv = netdev_priv(dev);
1488         if (priv->has_phy) {
1489                 if (!priv->phydev)
1490                         return -ENODEV;
1491                 return phy_ethtool_sset(priv->phydev, cmd);
1492         } else {
1493
1494                 if (cmd->autoneg ||
1495                     (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) ||
1496                     cmd->port != PORT_MII)
1497                         return -EINVAL;
1498
1499                 priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0;
1500                 priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0;
1501
1502                 if (netif_running(dev))
1503                         bcm_enet_adjust_link(dev);
1504                 return 0;
1505         }
1506 }
1507
1508 static void bcm_enet_get_ringparam(struct net_device *dev,
1509                                    struct ethtool_ringparam *ering)
1510 {
1511         struct bcm_enet_priv *priv;
1512
1513         priv = netdev_priv(dev);
1514
1515         /* rx/tx ring is actually only limited by memory */
1516         ering->rx_max_pending = 8192;
1517         ering->tx_max_pending = 8192;
1518         ering->rx_pending = priv->rx_ring_size;
1519         ering->tx_pending = priv->tx_ring_size;
1520 }
1521
1522 static int bcm_enet_set_ringparam(struct net_device *dev,
1523                                   struct ethtool_ringparam *ering)
1524 {
1525         struct bcm_enet_priv *priv;
1526         int was_running;
1527
1528         priv = netdev_priv(dev);
1529
1530         was_running = 0;
1531         if (netif_running(dev)) {
1532                 bcm_enet_stop(dev);
1533                 was_running = 1;
1534         }
1535
1536         priv->rx_ring_size = ering->rx_pending;
1537         priv->tx_ring_size = ering->tx_pending;
1538
1539         if (was_running) {
1540                 int err;
1541
1542                 err = bcm_enet_open(dev);
1543                 if (err)
1544                         dev_close(dev);
1545                 else
1546                         bcm_enet_set_multicast_list(dev);
1547         }
1548         return 0;
1549 }
1550
1551 static void bcm_enet_get_pauseparam(struct net_device *dev,
1552                                     struct ethtool_pauseparam *ecmd)
1553 {
1554         struct bcm_enet_priv *priv;
1555
1556         priv = netdev_priv(dev);
1557         ecmd->autoneg = priv->pause_auto;
1558         ecmd->rx_pause = priv->pause_rx;
1559         ecmd->tx_pause = priv->pause_tx;
1560 }
1561
1562 static int bcm_enet_set_pauseparam(struct net_device *dev,
1563                                    struct ethtool_pauseparam *ecmd)
1564 {
1565         struct bcm_enet_priv *priv;
1566
1567         priv = netdev_priv(dev);
1568
1569         if (priv->has_phy) {
1570                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1571                         /* asymetric pause mode not supported,
1572                          * actually possible but integrated PHY has RO
1573                          * asym_pause bit */
1574                         return -EINVAL;
1575                 }
1576         } else {
1577                 /* no pause autoneg on direct mii connection */
1578                 if (ecmd->autoneg)
1579                         return -EINVAL;
1580         }
1581
1582         priv->pause_auto = ecmd->autoneg;
1583         priv->pause_rx = ecmd->rx_pause;
1584         priv->pause_tx = ecmd->tx_pause;
1585
1586         return 0;
1587 }
1588
1589 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1590         .get_strings            = bcm_enet_get_strings,
1591         .get_sset_count         = bcm_enet_get_sset_count,
1592         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1593         .nway_reset             = bcm_enet_nway_reset,
1594         .get_settings           = bcm_enet_get_settings,
1595         .set_settings           = bcm_enet_set_settings,
1596         .get_drvinfo            = bcm_enet_get_drvinfo,
1597         .get_link               = ethtool_op_get_link,
1598         .get_ringparam          = bcm_enet_get_ringparam,
1599         .set_ringparam          = bcm_enet_set_ringparam,
1600         .get_pauseparam         = bcm_enet_get_pauseparam,
1601         .set_pauseparam         = bcm_enet_set_pauseparam,
1602 };
1603
1604 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1605 {
1606         struct bcm_enet_priv *priv;
1607
1608         priv = netdev_priv(dev);
1609         if (priv->has_phy) {
1610                 if (!priv->phydev)
1611                         return -ENODEV;
1612                 return phy_mii_ioctl(priv->phydev, rq, cmd);
1613         } else {
1614                 struct mii_if_info mii;
1615
1616                 mii.dev = dev;
1617                 mii.mdio_read = bcm_enet_mdio_read_mii;
1618                 mii.mdio_write = bcm_enet_mdio_write_mii;
1619                 mii.phy_id = 0;
1620                 mii.phy_id_mask = 0x3f;
1621                 mii.reg_num_mask = 0x1f;
1622                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1623         }
1624 }
1625
1626 /*
1627  * calculate actual hardware mtu
1628  */
1629 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1630 {
1631         int actual_mtu;
1632
1633         actual_mtu = mtu;
1634
1635         /* add ethernet header + vlan tag size */
1636         actual_mtu += VLAN_ETH_HLEN;
1637
1638         if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1639                 return -EINVAL;
1640
1641         /*
1642          * setup maximum size before we get overflow mark in
1643          * descriptor, note that this will not prevent reception of
1644          * big frames, they will be split into multiple buffers
1645          * anyway
1646          */
1647         priv->hw_mtu = actual_mtu;
1648
1649         /*
1650          * align rx buffer size to dma burst len, account FCS since
1651          * it's appended
1652          */
1653         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1654                                   priv->dma_maxburst * 4);
1655         return 0;
1656 }
1657
1658 /*
1659  * adjust mtu, can't be called while device is running
1660  */
1661 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1662 {
1663         int ret;
1664
1665         if (netif_running(dev))
1666                 return -EBUSY;
1667
1668         ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1669         if (ret)
1670                 return ret;
1671         dev->mtu = new_mtu;
1672         return 0;
1673 }
1674
1675 /*
1676  * preinit hardware to allow mii operation while device is down
1677  */
1678 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1679 {
1680         u32 val;
1681         int limit;
1682
1683         /* make sure mac is disabled */
1684         bcm_enet_disable_mac(priv);
1685
1686         /* soft reset mac */
1687         val = ENET_CTL_SRESET_MASK;
1688         enet_writel(priv, val, ENET_CTL_REG);
1689         wmb();
1690
1691         limit = 1000;
1692         do {
1693                 val = enet_readl(priv, ENET_CTL_REG);
1694                 if (!(val & ENET_CTL_SRESET_MASK))
1695                         break;
1696                 udelay(1);
1697         } while (limit--);
1698
1699         /* select correct mii interface */
1700         val = enet_readl(priv, ENET_CTL_REG);
1701         if (priv->use_external_mii)
1702                 val |= ENET_CTL_EPHYSEL_MASK;
1703         else
1704                 val &= ~ENET_CTL_EPHYSEL_MASK;
1705         enet_writel(priv, val, ENET_CTL_REG);
1706
1707         /* turn on mdc clock */
1708         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1709                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1710
1711         /* set mib counters to self-clear when read */
1712         val = enet_readl(priv, ENET_MIBCTL_REG);
1713         val |= ENET_MIBCTL_RDCLEAR_MASK;
1714         enet_writel(priv, val, ENET_MIBCTL_REG);
1715 }
1716
1717 static const struct net_device_ops bcm_enet_ops = {
1718         .ndo_open               = bcm_enet_open,
1719         .ndo_stop               = bcm_enet_stop,
1720         .ndo_start_xmit         = bcm_enet_start_xmit,
1721         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1722         .ndo_set_rx_mode        = bcm_enet_set_multicast_list,
1723         .ndo_do_ioctl           = bcm_enet_ioctl,
1724         .ndo_change_mtu         = bcm_enet_change_mtu,
1725 };
1726
1727 /*
1728  * allocate netdevice, request register memory and register device.
1729  */
1730 static int bcm_enet_probe(struct platform_device *pdev)
1731 {
1732         struct bcm_enet_priv *priv;
1733         struct net_device *dev;
1734         struct bcm63xx_enet_platform_data *pd;
1735         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1736         struct mii_bus *bus;
1737         const char *clk_name;
1738         int i, ret;
1739
1740         /* stop if shared driver failed, assume driver->probe will be
1741          * called in the same order we register devices (correct ?) */
1742         if (!bcm_enet_shared_base[0])
1743                 return -ENODEV;
1744
1745         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1746         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1747         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1748         if (!res_irq || !res_irq_rx || !res_irq_tx)
1749                 return -ENODEV;
1750
1751         ret = 0;
1752         dev = alloc_etherdev(sizeof(*priv));
1753         if (!dev)
1754                 return -ENOMEM;
1755         priv = netdev_priv(dev);
1756
1757         priv->enet_is_sw = false;
1758         priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1759
1760         ret = compute_hw_mtu(priv, dev->mtu);
1761         if (ret)
1762                 goto out;
1763
1764         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1765         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1766         if (IS_ERR(priv->base)) {
1767                 ret = PTR_ERR(priv->base);
1768                 goto out;
1769         }
1770
1771         dev->irq = priv->irq = res_irq->start;
1772         priv->irq_rx = res_irq_rx->start;
1773         priv->irq_tx = res_irq_tx->start;
1774         priv->mac_id = pdev->id;
1775
1776         /* get rx & tx dma channel id for this mac */
1777         if (priv->mac_id == 0) {
1778                 priv->rx_chan = 0;
1779                 priv->tx_chan = 1;
1780                 clk_name = "enet0";
1781         } else {
1782                 priv->rx_chan = 2;
1783                 priv->tx_chan = 3;
1784                 clk_name = "enet1";
1785         }
1786
1787         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1788         if (IS_ERR(priv->mac_clk)) {
1789                 ret = PTR_ERR(priv->mac_clk);
1790                 goto out;
1791         }
1792         ret = clk_prepare_enable(priv->mac_clk);
1793         if (ret)
1794                 goto out_put_clk_mac;
1795
1796         /* initialize default and fetch platform data */
1797         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1798         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1799
1800         pd = dev_get_platdata(&pdev->dev);
1801         if (pd) {
1802                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1803                 priv->has_phy = pd->has_phy;
1804                 priv->phy_id = pd->phy_id;
1805                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1806                 priv->phy_interrupt = pd->phy_interrupt;
1807                 priv->use_external_mii = !pd->use_internal_phy;
1808                 priv->pause_auto = pd->pause_auto;
1809                 priv->pause_rx = pd->pause_rx;
1810                 priv->pause_tx = pd->pause_tx;
1811                 priv->force_duplex_full = pd->force_duplex_full;
1812                 priv->force_speed_100 = pd->force_speed_100;
1813                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1814                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1815                 priv->dma_chan_width = pd->dma_chan_width;
1816                 priv->dma_has_sram = pd->dma_has_sram;
1817                 priv->dma_desc_shift = pd->dma_desc_shift;
1818         }
1819
1820         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1821                 /* using internal PHY, enable clock */
1822                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1823                 if (IS_ERR(priv->phy_clk)) {
1824                         ret = PTR_ERR(priv->phy_clk);
1825                         priv->phy_clk = NULL;
1826                         goto out_disable_clk_mac;
1827                 }
1828                 ret = clk_prepare_enable(priv->phy_clk);
1829                 if (ret)
1830                         goto out_put_clk_phy;
1831         }
1832
1833         /* do minimal hardware init to be able to probe mii bus */
1834         bcm_enet_hw_preinit(priv);
1835
1836         /* MII bus registration */
1837         if (priv->has_phy) {
1838
1839                 priv->mii_bus = mdiobus_alloc();
1840                 if (!priv->mii_bus) {
1841                         ret = -ENOMEM;
1842                         goto out_uninit_hw;
1843                 }
1844
1845                 bus = priv->mii_bus;
1846                 bus->name = "bcm63xx_enet MII bus";
1847                 bus->parent = &pdev->dev;
1848                 bus->priv = priv;
1849                 bus->read = bcm_enet_mdio_read_phylib;
1850                 bus->write = bcm_enet_mdio_write_phylib;
1851                 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1852
1853                 /* only probe bus where we think the PHY is, because
1854                  * the mdio read operation return 0 instead of 0xffff
1855                  * if a slave is not present on hw */
1856                 bus->phy_mask = ~(1 << priv->phy_id);
1857
1858                 bus->irq = devm_kzalloc(&pdev->dev, sizeof(int) * PHY_MAX_ADDR,
1859                                         GFP_KERNEL);
1860                 if (!bus->irq) {
1861                         ret = -ENOMEM;
1862                         goto out_free_mdio;
1863                 }
1864
1865                 if (priv->has_phy_interrupt)
1866                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1867                 else
1868                         bus->irq[priv->phy_id] = PHY_POLL;
1869
1870                 ret = mdiobus_register(bus);
1871                 if (ret) {
1872                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1873                         goto out_free_mdio;
1874                 }
1875         } else {
1876
1877                 /* run platform code to initialize PHY device */
1878                 if (pd->mii_config &&
1879                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1880                                    bcm_enet_mdio_write_mii)) {
1881                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1882                         goto out_uninit_hw;
1883                 }
1884         }
1885
1886         spin_lock_init(&priv->rx_lock);
1887
1888         /* init rx timeout (used for oom) */
1889         init_timer(&priv->rx_timeout);
1890         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1891         priv->rx_timeout.data = (unsigned long)dev;
1892
1893         /* init the mib update lock&work */
1894         mutex_init(&priv->mib_update_lock);
1895         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1896
1897         /* zero mib counters */
1898         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1899                 enet_writel(priv, 0, ENET_MIB_REG(i));
1900
1901         /* register netdevice */
1902         dev->netdev_ops = &bcm_enet_ops;
1903         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1904
1905         dev->ethtool_ops = &bcm_enet_ethtool_ops;
1906         SET_NETDEV_DEV(dev, &pdev->dev);
1907
1908         ret = register_netdev(dev);
1909         if (ret)
1910                 goto out_unregister_mdio;
1911
1912         netif_carrier_off(dev);
1913         platform_set_drvdata(pdev, dev);
1914         priv->pdev = pdev;
1915         priv->net_dev = dev;
1916
1917         return 0;
1918
1919 out_unregister_mdio:
1920         if (priv->mii_bus)
1921                 mdiobus_unregister(priv->mii_bus);
1922
1923 out_free_mdio:
1924         if (priv->mii_bus)
1925                 mdiobus_free(priv->mii_bus);
1926
1927 out_uninit_hw:
1928         /* turn off mdc clock */
1929         enet_writel(priv, 0, ENET_MIISC_REG);
1930         if (priv->phy_clk)
1931                 clk_disable_unprepare(priv->phy_clk);
1932
1933 out_put_clk_phy:
1934         if (priv->phy_clk)
1935                 clk_put(priv->phy_clk);
1936
1937 out_disable_clk_mac:
1938         clk_disable_unprepare(priv->mac_clk);
1939 out_put_clk_mac:
1940         clk_put(priv->mac_clk);
1941 out:
1942         free_netdev(dev);
1943         return ret;
1944 }
1945
1946
1947 /*
1948  * exit func, stops hardware and unregisters netdevice
1949  */
1950 static int bcm_enet_remove(struct platform_device *pdev)
1951 {
1952         struct bcm_enet_priv *priv;
1953         struct net_device *dev;
1954
1955         /* stop netdevice */
1956         dev = platform_get_drvdata(pdev);
1957         priv = netdev_priv(dev);
1958         unregister_netdev(dev);
1959
1960         /* turn off mdc clock */
1961         enet_writel(priv, 0, ENET_MIISC_REG);
1962
1963         if (priv->has_phy) {
1964                 mdiobus_unregister(priv->mii_bus);
1965                 mdiobus_free(priv->mii_bus);
1966         } else {
1967                 struct bcm63xx_enet_platform_data *pd;
1968
1969                 pd = dev_get_platdata(&pdev->dev);
1970                 if (pd && pd->mii_config)
1971                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1972                                        bcm_enet_mdio_write_mii);
1973         }
1974
1975         /* disable hw block clocks */
1976         if (priv->phy_clk) {
1977                 clk_disable_unprepare(priv->phy_clk);
1978                 clk_put(priv->phy_clk);
1979         }
1980         clk_disable_unprepare(priv->mac_clk);
1981         clk_put(priv->mac_clk);
1982
1983         free_netdev(dev);
1984         return 0;
1985 }
1986
1987 struct platform_driver bcm63xx_enet_driver = {
1988         .probe  = bcm_enet_probe,
1989         .remove = bcm_enet_remove,
1990         .driver = {
1991                 .name   = "bcm63xx_enet",
1992                 .owner  = THIS_MODULE,
1993         },
1994 };
1995
1996 /*
1997  * switch mii access callbacks
1998  */
1999 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
2000                                 int ext, int phy_id, int location)
2001 {
2002         u32 reg;
2003         int ret;
2004
2005         spin_lock_bh(&priv->enetsw_mdio_lock);
2006         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2007
2008         reg = ENETSW_MDIOC_RD_MASK |
2009                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2010                 (location << ENETSW_MDIOC_REG_SHIFT);
2011
2012         if (ext)
2013                 reg |= ENETSW_MDIOC_EXT_MASK;
2014
2015         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2016         udelay(50);
2017         ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
2018         spin_unlock_bh(&priv->enetsw_mdio_lock);
2019         return ret;
2020 }
2021
2022 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
2023                                  int ext, int phy_id, int location,
2024                                  uint16_t data)
2025 {
2026         u32 reg;
2027
2028         spin_lock_bh(&priv->enetsw_mdio_lock);
2029         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2030
2031         reg = ENETSW_MDIOC_WR_MASK |
2032                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2033                 (location << ENETSW_MDIOC_REG_SHIFT);
2034
2035         if (ext)
2036                 reg |= ENETSW_MDIOC_EXT_MASK;
2037
2038         reg |= data;
2039
2040         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2041         udelay(50);
2042         spin_unlock_bh(&priv->enetsw_mdio_lock);
2043 }
2044
2045 static inline int bcm_enet_port_is_rgmii(int portid)
2046 {
2047         return portid >= ENETSW_RGMII_PORT0;
2048 }
2049
2050 /*
2051  * enet sw PHY polling
2052  */
2053 static void swphy_poll_timer(unsigned long data)
2054 {
2055         struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2056         unsigned int i;
2057
2058         for (i = 0; i < priv->num_ports; i++) {
2059                 struct bcm63xx_enetsw_port *port;
2060                 int val, j, up, advertise, lpa, speed, duplex, media;
2061                 int external_phy = bcm_enet_port_is_rgmii(i);
2062                 u8 override;
2063
2064                 port = &priv->used_ports[i];
2065                 if (!port->used)
2066                         continue;
2067
2068                 if (port->bypass_link)
2069                         continue;
2070
2071                 /* dummy read to clear */
2072                 for (j = 0; j < 2; j++)
2073                         val = bcmenet_sw_mdio_read(priv, external_phy,
2074                                                    port->phy_id, MII_BMSR);
2075
2076                 if (val == 0xffff)
2077                         continue;
2078
2079                 up = (val & BMSR_LSTATUS) ? 1 : 0;
2080                 if (!(up ^ priv->sw_port_link[i]))
2081                         continue;
2082
2083                 priv->sw_port_link[i] = up;
2084
2085                 /* link changed */
2086                 if (!up) {
2087                         dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2088                                  port->name);
2089                         enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2090                                       ENETSW_PORTOV_REG(i));
2091                         enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2092                                       ENETSW_PTCTRL_TXDIS_MASK,
2093                                       ENETSW_PTCTRL_REG(i));
2094                         continue;
2095                 }
2096
2097                 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2098                                                  port->phy_id, MII_ADVERTISE);
2099
2100                 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2101                                            MII_LPA);
2102
2103                 /* figure out media and duplex from advertise and LPA values */
2104                 media = mii_nway_result(lpa & advertise);
2105                 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2106
2107                 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2108                         speed = 100;
2109                 else
2110                         speed = 10;
2111
2112                 if (val & BMSR_ESTATEN) {
2113                         advertise = bcmenet_sw_mdio_read(priv, external_phy,
2114                                                 port->phy_id, MII_CTRL1000);
2115
2116                         lpa = bcmenet_sw_mdio_read(priv, external_phy,
2117                                                 port->phy_id, MII_STAT1000);
2118
2119                         if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2120                                         && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2121                                 speed = 1000;
2122                                 duplex = (lpa & LPA_1000FULL);
2123                         }
2124                 }
2125
2126                 dev_info(&priv->pdev->dev,
2127                          "link UP on %s, %dMbps, %s-duplex\n",
2128                          port->name, speed, duplex ? "full" : "half");
2129
2130                 override = ENETSW_PORTOV_ENABLE_MASK |
2131                         ENETSW_PORTOV_LINKUP_MASK;
2132
2133                 if (speed == 1000)
2134                         override |= ENETSW_IMPOV_1000_MASK;
2135                 else if (speed == 100)
2136                         override |= ENETSW_IMPOV_100_MASK;
2137                 if (duplex)
2138                         override |= ENETSW_IMPOV_FDX_MASK;
2139
2140                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2141                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2142         }
2143
2144         priv->swphy_poll.expires = jiffies + HZ;
2145         add_timer(&priv->swphy_poll);
2146 }
2147
2148 /*
2149  * open callback, allocate dma rings & buffers and start rx operation
2150  */
2151 static int bcm_enetsw_open(struct net_device *dev)
2152 {
2153         struct bcm_enet_priv *priv;
2154         struct device *kdev;
2155         int i, ret;
2156         unsigned int size;
2157         void *p;
2158         u32 val;
2159
2160         priv = netdev_priv(dev);
2161         kdev = &priv->pdev->dev;
2162
2163         /* mask all interrupts and request them */
2164         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2165         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2166
2167         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2168                           0, dev->name, dev);
2169         if (ret)
2170                 goto out_freeirq;
2171
2172         if (priv->irq_tx != -1) {
2173                 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2174                                   0, dev->name, dev);
2175                 if (ret)
2176                         goto out_freeirq_rx;
2177         }
2178
2179         /* allocate rx dma ring */
2180         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2181         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2182         if (!p) {
2183                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2184                 ret = -ENOMEM;
2185                 goto out_freeirq_tx;
2186         }
2187
2188         memset(p, 0, size);
2189         priv->rx_desc_alloc_size = size;
2190         priv->rx_desc_cpu = p;
2191
2192         /* allocate tx dma ring */
2193         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2194         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2195         if (!p) {
2196                 dev_err(kdev, "cannot allocate tx ring\n");
2197                 ret = -ENOMEM;
2198                 goto out_free_rx_ring;
2199         }
2200
2201         memset(p, 0, size);
2202         priv->tx_desc_alloc_size = size;
2203         priv->tx_desc_cpu = p;
2204
2205         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2206                                GFP_KERNEL);
2207         if (!priv->tx_skb) {
2208                 dev_err(kdev, "cannot allocate rx skb queue\n");
2209                 ret = -ENOMEM;
2210                 goto out_free_tx_ring;
2211         }
2212
2213         priv->tx_desc_count = priv->tx_ring_size;
2214         priv->tx_dirty_desc = 0;
2215         priv->tx_curr_desc = 0;
2216         spin_lock_init(&priv->tx_lock);
2217
2218         /* init & fill rx ring with skbs */
2219         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2220                                GFP_KERNEL);
2221         if (!priv->rx_skb) {
2222                 dev_err(kdev, "cannot allocate rx skb queue\n");
2223                 ret = -ENOMEM;
2224                 goto out_free_tx_skb;
2225         }
2226
2227         priv->rx_desc_count = 0;
2228         priv->rx_dirty_desc = 0;
2229         priv->rx_curr_desc = 0;
2230
2231         /* disable all ports */
2232         for (i = 0; i < priv->num_ports; i++) {
2233                 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2234                               ENETSW_PORTOV_REG(i));
2235                 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2236                               ENETSW_PTCTRL_TXDIS_MASK,
2237                               ENETSW_PTCTRL_REG(i));
2238
2239                 priv->sw_port_link[i] = 0;
2240         }
2241
2242         /* reset mib */
2243         val = enetsw_readb(priv, ENETSW_GMCR_REG);
2244         val |= ENETSW_GMCR_RST_MIB_MASK;
2245         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2246         mdelay(1);
2247         val &= ~ENETSW_GMCR_RST_MIB_MASK;
2248         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2249         mdelay(1);
2250
2251         /* force CPU port state */
2252         val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2253         val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2254         enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2255
2256         /* enable switch forward engine */
2257         val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2258         val |= ENETSW_SWMODE_FWD_EN_MASK;
2259         enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2260
2261         /* enable jumbo on all ports */
2262         enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2263         enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2264
2265         /* initialize flow control buffer allocation */
2266         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2267                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
2268
2269         if (bcm_enet_refill_rx(dev)) {
2270                 dev_err(kdev, "cannot allocate rx skb queue\n");
2271                 ret = -ENOMEM;
2272                 goto out;
2273         }
2274
2275         /* write rx & tx ring addresses */
2276         enet_dmas_writel(priv, priv->rx_desc_dma,
2277                          ENETDMAS_RSTART_REG, priv->rx_chan);
2278         enet_dmas_writel(priv, priv->tx_desc_dma,
2279                          ENETDMAS_RSTART_REG, priv->tx_chan);
2280
2281         /* clear remaining state ram for rx & tx channel */
2282         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2283         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2284         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2285         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2286         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2287         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2288
2289         /* set dma maximum burst len */
2290         enet_dmac_writel(priv, priv->dma_maxburst,
2291                          ENETDMAC_MAXBURST, priv->rx_chan);
2292         enet_dmac_writel(priv, priv->dma_maxburst,
2293                          ENETDMAC_MAXBURST, priv->tx_chan);
2294
2295         /* set flow control low/high threshold to 1/3 / 2/3 */
2296         val = priv->rx_ring_size / 3;
2297         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2298         val = (priv->rx_ring_size * 2) / 3;
2299         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2300
2301         /* all set, enable mac and interrupts, start dma engine and
2302          * kick rx dma channel
2303          */
2304         wmb();
2305         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2306         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2307                          ENETDMAC_CHANCFG, priv->rx_chan);
2308
2309         /* watch "packet transferred" interrupt in rx and tx */
2310         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2311                          ENETDMAC_IR, priv->rx_chan);
2312         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2313                          ENETDMAC_IR, priv->tx_chan);
2314
2315         /* make sure we enable napi before rx interrupt  */
2316         napi_enable(&priv->napi);
2317
2318         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2319                          ENETDMAC_IRMASK, priv->rx_chan);
2320         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2321                          ENETDMAC_IRMASK, priv->tx_chan);
2322
2323         netif_carrier_on(dev);
2324         netif_start_queue(dev);
2325
2326         /* apply override config for bypass_link ports here. */
2327         for (i = 0; i < priv->num_ports; i++) {
2328                 struct bcm63xx_enetsw_port *port;
2329                 u8 override;
2330                 port = &priv->used_ports[i];
2331                 if (!port->used)
2332                         continue;
2333
2334                 if (!port->bypass_link)
2335                         continue;
2336
2337                 override = ENETSW_PORTOV_ENABLE_MASK |
2338                         ENETSW_PORTOV_LINKUP_MASK;
2339
2340                 switch (port->force_speed) {
2341                 case 1000:
2342                         override |= ENETSW_IMPOV_1000_MASK;
2343                         break;
2344                 case 100:
2345                         override |= ENETSW_IMPOV_100_MASK;
2346                         break;
2347                 case 10:
2348                         break;
2349                 default:
2350                         pr_warn("invalid forced speed on port %s: assume 10\n",
2351                                port->name);
2352                         break;
2353                 }
2354
2355                 if (port->force_duplex_full)
2356                         override |= ENETSW_IMPOV_FDX_MASK;
2357
2358
2359                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2360                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2361         }
2362
2363         /* start phy polling timer */
2364         init_timer(&priv->swphy_poll);
2365         priv->swphy_poll.function = swphy_poll_timer;
2366         priv->swphy_poll.data = (unsigned long)priv;
2367         priv->swphy_poll.expires = jiffies;
2368         add_timer(&priv->swphy_poll);
2369         return 0;
2370
2371 out:
2372         for (i = 0; i < priv->rx_ring_size; i++) {
2373                 struct bcm_enet_desc *desc;
2374
2375                 if (!priv->rx_skb[i])
2376                         continue;
2377
2378                 desc = &priv->rx_desc_cpu[i];
2379                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2380                                  DMA_FROM_DEVICE);
2381                 kfree_skb(priv->rx_skb[i]);
2382         }
2383         kfree(priv->rx_skb);
2384
2385 out_free_tx_skb:
2386         kfree(priv->tx_skb);
2387
2388 out_free_tx_ring:
2389         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2390                           priv->tx_desc_cpu, priv->tx_desc_dma);
2391
2392 out_free_rx_ring:
2393         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2394                           priv->rx_desc_cpu, priv->rx_desc_dma);
2395
2396 out_freeirq_tx:
2397         if (priv->irq_tx != -1)
2398                 free_irq(priv->irq_tx, dev);
2399
2400 out_freeirq_rx:
2401         free_irq(priv->irq_rx, dev);
2402
2403 out_freeirq:
2404         return ret;
2405 }
2406
2407 /* stop callback */
2408 static int bcm_enetsw_stop(struct net_device *dev)
2409 {
2410         struct bcm_enet_priv *priv;
2411         struct device *kdev;
2412         int i;
2413
2414         priv = netdev_priv(dev);
2415         kdev = &priv->pdev->dev;
2416
2417         del_timer_sync(&priv->swphy_poll);
2418         netif_stop_queue(dev);
2419         napi_disable(&priv->napi);
2420         del_timer_sync(&priv->rx_timeout);
2421
2422         /* mask all interrupts */
2423         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2424         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2425
2426         /* disable dma & mac */
2427         bcm_enet_disable_dma(priv, priv->tx_chan);
2428         bcm_enet_disable_dma(priv, priv->rx_chan);
2429
2430         /* force reclaim of all tx buffers */
2431         bcm_enet_tx_reclaim(dev, 1);
2432
2433         /* free the rx skb ring */
2434         for (i = 0; i < priv->rx_ring_size; i++) {
2435                 struct bcm_enet_desc *desc;
2436
2437                 if (!priv->rx_skb[i])
2438                         continue;
2439
2440                 desc = &priv->rx_desc_cpu[i];
2441                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2442                                  DMA_FROM_DEVICE);
2443                 kfree_skb(priv->rx_skb[i]);
2444         }
2445
2446         /* free remaining allocated memory */
2447         kfree(priv->rx_skb);
2448         kfree(priv->tx_skb);
2449         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2450                           priv->rx_desc_cpu, priv->rx_desc_dma);
2451         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2452                           priv->tx_desc_cpu, priv->tx_desc_dma);
2453         if (priv->irq_tx != -1)
2454                 free_irq(priv->irq_tx, dev);
2455         free_irq(priv->irq_rx, dev);
2456
2457         return 0;
2458 }
2459
2460 /* try to sort out phy external status by walking the used_port field
2461  * in the bcm_enet_priv structure. in case the phy address is not
2462  * assigned to any physical port on the switch, assume it is external
2463  * (and yell at the user).
2464  */
2465 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2466 {
2467         int i;
2468
2469         for (i = 0; i < priv->num_ports; ++i) {
2470                 if (!priv->used_ports[i].used)
2471                         continue;
2472                 if (priv->used_ports[i].phy_id == phy_id)
2473                         return bcm_enet_port_is_rgmii(i);
2474         }
2475
2476         printk_once(KERN_WARNING  "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2477                     phy_id);
2478         return 1;
2479 }
2480
2481 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2482  * external/internal status of the given phy_id first.
2483  */
2484 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2485                                     int location)
2486 {
2487         struct bcm_enet_priv *priv;
2488
2489         priv = netdev_priv(dev);
2490         return bcmenet_sw_mdio_read(priv,
2491                                     bcm_enetsw_phy_is_external(priv, phy_id),
2492                                     phy_id, location);
2493 }
2494
2495 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2496  * external/internal status of the given phy_id first.
2497  */
2498 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2499                                       int location,
2500                                       int val)
2501 {
2502         struct bcm_enet_priv *priv;
2503
2504         priv = netdev_priv(dev);
2505         bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2506                               phy_id, location, val);
2507 }
2508
2509 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2510 {
2511         struct mii_if_info mii;
2512
2513         mii.dev = dev;
2514         mii.mdio_read = bcm_enetsw_mii_mdio_read;
2515         mii.mdio_write = bcm_enetsw_mii_mdio_write;
2516         mii.phy_id = 0;
2517         mii.phy_id_mask = 0x3f;
2518         mii.reg_num_mask = 0x1f;
2519         return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2520
2521 }
2522
2523 static const struct net_device_ops bcm_enetsw_ops = {
2524         .ndo_open               = bcm_enetsw_open,
2525         .ndo_stop               = bcm_enetsw_stop,
2526         .ndo_start_xmit         = bcm_enet_start_xmit,
2527         .ndo_change_mtu         = bcm_enet_change_mtu,
2528         .ndo_do_ioctl           = bcm_enetsw_ioctl,
2529 };
2530
2531
2532 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2533         { "rx_packets", DEV_STAT(rx_packets), -1 },
2534         { "tx_packets", DEV_STAT(tx_packets), -1 },
2535         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2536         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2537         { "rx_errors", DEV_STAT(rx_errors), -1 },
2538         { "tx_errors", DEV_STAT(tx_errors), -1 },
2539         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2540         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2541
2542         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2543         { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2544         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2545         { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2546         { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2547         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2548         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2549         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2550         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2551         { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2552           ETHSW_MIB_RX_1024_1522 },
2553         { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2554           ETHSW_MIB_RX_1523_2047 },
2555         { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2556           ETHSW_MIB_RX_2048_4095 },
2557         { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2558           ETHSW_MIB_RX_4096_8191 },
2559         { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2560           ETHSW_MIB_RX_8192_9728 },
2561         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2562         { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2563         { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2564         { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2565         { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2566
2567         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2568         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2569         { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2570         { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2571         { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2572         { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2573
2574 };
2575
2576 #define BCM_ENETSW_STATS_LEN    \
2577         (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2578
2579 static void bcm_enetsw_get_strings(struct net_device *netdev,
2580                                    u32 stringset, u8 *data)
2581 {
2582         int i;
2583
2584         switch (stringset) {
2585         case ETH_SS_STATS:
2586                 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2587                         memcpy(data + i * ETH_GSTRING_LEN,
2588                                bcm_enetsw_gstrings_stats[i].stat_string,
2589                                ETH_GSTRING_LEN);
2590                 }
2591                 break;
2592         }
2593 }
2594
2595 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2596                                      int string_set)
2597 {
2598         switch (string_set) {
2599         case ETH_SS_STATS:
2600                 return BCM_ENETSW_STATS_LEN;
2601         default:
2602                 return -EINVAL;
2603         }
2604 }
2605
2606 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2607                                    struct ethtool_drvinfo *drvinfo)
2608 {
2609         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2610         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2611         strncpy(drvinfo->fw_version, "N/A", 32);
2612         strncpy(drvinfo->bus_info, "bcm63xx", 32);
2613 }
2614
2615 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2616                                          struct ethtool_stats *stats,
2617                                          u64 *data)
2618 {
2619         struct bcm_enet_priv *priv;
2620         int i;
2621
2622         priv = netdev_priv(netdev);
2623
2624         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2625                 const struct bcm_enet_stats *s;
2626                 u32 lo, hi;
2627                 char *p;
2628                 int reg;
2629
2630                 s = &bcm_enetsw_gstrings_stats[i];
2631
2632                 reg = s->mib_reg;
2633                 if (reg == -1)
2634                         continue;
2635
2636                 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2637                 p = (char *)priv + s->stat_offset;
2638
2639                 if (s->sizeof_stat == sizeof(u64)) {
2640                         hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2641                         *(u64 *)p = ((u64)hi << 32 | lo);
2642                 } else {
2643                         *(u32 *)p = lo;
2644                 }
2645         }
2646
2647         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2648                 const struct bcm_enet_stats *s;
2649                 char *p;
2650
2651                 s = &bcm_enetsw_gstrings_stats[i];
2652
2653                 if (s->mib_reg == -1)
2654                         p = (char *)&netdev->stats + s->stat_offset;
2655                 else
2656                         p = (char *)priv + s->stat_offset;
2657
2658                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2659                         *(u64 *)p : *(u32 *)p;
2660         }
2661 }
2662
2663 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2664                                      struct ethtool_ringparam *ering)
2665 {
2666         struct bcm_enet_priv *priv;
2667
2668         priv = netdev_priv(dev);
2669
2670         /* rx/tx ring is actually only limited by memory */
2671         ering->rx_max_pending = 8192;
2672         ering->tx_max_pending = 8192;
2673         ering->rx_mini_max_pending = 0;
2674         ering->rx_jumbo_max_pending = 0;
2675         ering->rx_pending = priv->rx_ring_size;
2676         ering->tx_pending = priv->tx_ring_size;
2677 }
2678
2679 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2680                                     struct ethtool_ringparam *ering)
2681 {
2682         struct bcm_enet_priv *priv;
2683         int was_running;
2684
2685         priv = netdev_priv(dev);
2686
2687         was_running = 0;
2688         if (netif_running(dev)) {
2689                 bcm_enetsw_stop(dev);
2690                 was_running = 1;
2691         }
2692
2693         priv->rx_ring_size = ering->rx_pending;
2694         priv->tx_ring_size = ering->tx_pending;
2695
2696         if (was_running) {
2697                 int err;
2698
2699                 err = bcm_enetsw_open(dev);
2700                 if (err)
2701                         dev_close(dev);
2702         }
2703         return 0;
2704 }
2705
2706 static struct ethtool_ops bcm_enetsw_ethtool_ops = {
2707         .get_strings            = bcm_enetsw_get_strings,
2708         .get_sset_count         = bcm_enetsw_get_sset_count,
2709         .get_ethtool_stats      = bcm_enetsw_get_ethtool_stats,
2710         .get_drvinfo            = bcm_enetsw_get_drvinfo,
2711         .get_ringparam          = bcm_enetsw_get_ringparam,
2712         .set_ringparam          = bcm_enetsw_set_ringparam,
2713 };
2714
2715 /* allocate netdevice, request register memory and register device. */
2716 static int bcm_enetsw_probe(struct platform_device *pdev)
2717 {
2718         struct bcm_enet_priv *priv;
2719         struct net_device *dev;
2720         struct bcm63xx_enetsw_platform_data *pd;
2721         struct resource *res_mem;
2722         int ret, irq_rx, irq_tx;
2723
2724         /* stop if shared driver failed, assume driver->probe will be
2725          * called in the same order we register devices (correct ?)
2726          */
2727         if (!bcm_enet_shared_base[0])
2728                 return -ENODEV;
2729
2730         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2731         irq_rx = platform_get_irq(pdev, 0);
2732         irq_tx = platform_get_irq(pdev, 1);
2733         if (!res_mem || irq_rx < 0)
2734                 return -ENODEV;
2735
2736         ret = 0;
2737         dev = alloc_etherdev(sizeof(*priv));
2738         if (!dev)
2739                 return -ENOMEM;
2740         priv = netdev_priv(dev);
2741         memset(priv, 0, sizeof(*priv));
2742
2743         /* initialize default and fetch platform data */
2744         priv->enet_is_sw = true;
2745         priv->irq_rx = irq_rx;
2746         priv->irq_tx = irq_tx;
2747         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2748         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2749         priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2750
2751         pd = dev_get_platdata(&pdev->dev);
2752         if (pd) {
2753                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2754                 memcpy(priv->used_ports, pd->used_ports,
2755                        sizeof(pd->used_ports));
2756                 priv->num_ports = pd->num_ports;
2757                 priv->dma_has_sram = pd->dma_has_sram;
2758                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2759                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2760                 priv->dma_chan_width = pd->dma_chan_width;
2761         }
2762
2763         ret = compute_hw_mtu(priv, dev->mtu);
2764         if (ret)
2765                 goto out;
2766
2767         if (!request_mem_region(res_mem->start, resource_size(res_mem),
2768                                 "bcm63xx_enetsw")) {
2769                 ret = -EBUSY;
2770                 goto out;
2771         }
2772
2773         priv->base = ioremap(res_mem->start, resource_size(res_mem));
2774         if (priv->base == NULL) {
2775                 ret = -ENOMEM;
2776                 goto out_release_mem;
2777         }
2778
2779         priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2780         if (IS_ERR(priv->mac_clk)) {
2781                 ret = PTR_ERR(priv->mac_clk);
2782                 goto out_unmap;
2783         }
2784         ret = clk_prepare_enable(priv->mac_clk);
2785         if (ret)
2786                 goto out_put_clk;
2787
2788         priv->rx_chan = 0;
2789         priv->tx_chan = 1;
2790         spin_lock_init(&priv->rx_lock);
2791
2792         /* init rx timeout (used for oom) */
2793         init_timer(&priv->rx_timeout);
2794         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2795         priv->rx_timeout.data = (unsigned long)dev;
2796
2797         /* register netdevice */
2798         dev->netdev_ops = &bcm_enetsw_ops;
2799         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2800         dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2801         SET_NETDEV_DEV(dev, &pdev->dev);
2802
2803         spin_lock_init(&priv->enetsw_mdio_lock);
2804
2805         ret = register_netdev(dev);
2806         if (ret)
2807                 goto out_disable_clk;
2808
2809         netif_carrier_off(dev);
2810         platform_set_drvdata(pdev, dev);
2811         priv->pdev = pdev;
2812         priv->net_dev = dev;
2813
2814         return 0;
2815
2816 out_disable_clk:
2817         clk_disable_unprepare(priv->mac_clk);
2818
2819 out_put_clk:
2820         clk_put(priv->mac_clk);
2821
2822 out_unmap:
2823         iounmap(priv->base);
2824
2825 out_release_mem:
2826         release_mem_region(res_mem->start, resource_size(res_mem));
2827 out:
2828         free_netdev(dev);
2829         return ret;
2830 }
2831
2832
2833 /* exit func, stops hardware and unregisters netdevice */
2834 static int bcm_enetsw_remove(struct platform_device *pdev)
2835 {
2836         struct bcm_enet_priv *priv;
2837         struct net_device *dev;
2838         struct resource *res;
2839
2840         /* stop netdevice */
2841         dev = platform_get_drvdata(pdev);
2842         priv = netdev_priv(dev);
2843         unregister_netdev(dev);
2844
2845         /* release device resources */
2846         iounmap(priv->base);
2847         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2848         release_mem_region(res->start, resource_size(res));
2849
2850         clk_disable_unprepare(priv->mac_clk);
2851         clk_put(priv->mac_clk);
2852
2853         free_netdev(dev);
2854         return 0;
2855 }
2856
2857 struct platform_driver bcm63xx_enetsw_driver = {
2858         .probe  = bcm_enetsw_probe,
2859         .remove = bcm_enetsw_remove,
2860         .driver = {
2861                 .name   = "bcm63xx_enetsw",
2862                 .owner  = THIS_MODULE,
2863         },
2864 };
2865
2866 /* reserve & remap memory space shared between all macs */
2867 static int bcm_enet_shared_probe(struct platform_device *pdev)
2868 {
2869         struct resource *res;
2870         void __iomem *p[3];
2871         unsigned int i;
2872
2873         memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2874
2875         for (i = 0; i < 3; i++) {
2876                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2877                 p[i] = devm_ioremap_resource(&pdev->dev, res);
2878                 if (IS_ERR(p[i]))
2879                         return PTR_ERR(p[i]);
2880         }
2881
2882         memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2883
2884         return 0;
2885 }
2886
2887 static int bcm_enet_shared_remove(struct platform_device *pdev)
2888 {
2889         return 0;
2890 }
2891
2892 /* this "shared" driver is needed because both macs share a single
2893  * address space
2894  */
2895 struct platform_driver bcm63xx_enet_shared_driver = {
2896         .probe  = bcm_enet_shared_probe,
2897         .remove = bcm_enet_shared_remove,
2898         .driver = {
2899                 .name   = "bcm63xx_enet_shared",
2900                 .owner  = THIS_MODULE,
2901         },
2902 };
2903
2904 /* entry point */
2905 static int __init bcm_enet_init(void)
2906 {
2907         int ret;
2908
2909         ret = platform_driver_register(&bcm63xx_enet_shared_driver);
2910         if (ret)
2911                 return ret;
2912
2913         ret = platform_driver_register(&bcm63xx_enet_driver);
2914         if (ret)
2915                 platform_driver_unregister(&bcm63xx_enet_shared_driver);
2916
2917         ret = platform_driver_register(&bcm63xx_enetsw_driver);
2918         if (ret) {
2919                 platform_driver_unregister(&bcm63xx_enet_driver);
2920                 platform_driver_unregister(&bcm63xx_enet_shared_driver);
2921         }
2922
2923         return ret;
2924 }
2925
2926 static void __exit bcm_enet_exit(void)
2927 {
2928         platform_driver_unregister(&bcm63xx_enet_driver);
2929         platform_driver_unregister(&bcm63xx_enetsw_driver);
2930         platform_driver_unregister(&bcm63xx_enet_shared_driver);
2931 }
2932
2933
2934 module_init(bcm_enet_init);
2935 module_exit(bcm_enet_exit);
2936
2937 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2938 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2939 MODULE_LICENSE("GPL");