drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: QLogic Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12  * Written by: Eliezer Tamir
  13  * Based on code from Michael Chan's bnx2 driver
  14  * UDP CSUM errata workaround by Arik Gendelman
  15  * Slowpath and fastpath rework by Vladislav Zolotarov
  16  * Statistics and Link management by Yitchak Gertner
  17  *
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/ethtool.h>
  23 #include <linux/netdevice.h>
  24 #include <linux/types.h>
  25 #include <linux/sched.h>
  26 #include <linux/crc32.h>
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29 #include "bnx2x_dump.h"
  30 #include "bnx2x_init.h"
  31
  32 /* Note: in the format strings below %s is replaced by the queue-name which is
  33  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  34  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  35  */
  36 #define MAX_QUEUE_NAME_LEN      4
  37 static const struct {
  38         long offset;
  39         int size;
  40         char string[ETH_GSTRING_LEN];
  41 } bnx2x_q_stats_arr[] = {
  42 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  43         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  44                                                 8, "[%s]: rx_ucast_packets" },
  45         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  46                                                 8, "[%s]: rx_mcast_packets" },
  47         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  48                                                 8, "[%s]: rx_bcast_packets" },
  49         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  50         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  51                                          4, "[%s]: rx_phy_ip_err_discards"},
  52         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  53                                          4, "[%s]: rx_skb_alloc_discard" },
  54         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  55         { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" },
  56         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  57 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_ucast_packets" },
  59         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_mcast_packets" },
  61         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  62                                                 8, "[%s]: tx_bcast_packets" },
  63         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  64                                                 8, "[%s]: tpa_aggregations" },
  65         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  66                                         8, "[%s]: tpa_aggregated_frames"},
  67         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
  68         { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
  69                                         4, "[%s]: driver_filtered_tx_pkt" }
  70 };
  71
  72 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  73
  74 static const struct {
  75         long offset;
  76         int size;
  77         bool is_port_stat;
  78         char string[ETH_GSTRING_LEN];
  79 } bnx2x_stats_arr[] = {
  80 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  81                                 8, false, "rx_bytes" },
  82         { STATS_OFFSET32(error_bytes_received_hi),
  83                                 8, false, "rx_error_bytes" },
  84         { STATS_OFFSET32(total_unicast_packets_received_hi),
  85                                 8, false, "rx_ucast_packets" },
  86         { STATS_OFFSET32(total_multicast_packets_received_hi),
  87                                 8, false, "rx_mcast_packets" },
  88         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  89                                 8, false, "rx_bcast_packets" },
  90         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  91                                 8, true, "rx_crc_errors" },
  92         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  93                                 8, true, "rx_align_errors" },
  94         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  95                                 8, true, "rx_undersize_packets" },
  96         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  97                                 8, true, "rx_oversize_packets" },
  98 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
  99                                 8, true, "rx_fragments" },
 100         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 101                                 8, true, "rx_jabbers" },
 102         { STATS_OFFSET32(no_buff_discard_hi),
 103                                 8, false, "rx_discards" },
 104         { STATS_OFFSET32(mac_filter_discard),
 105                                 4, true, "rx_filtered_packets" },
 106         { STATS_OFFSET32(mf_tag_discard),
 107                                 4, true, "rx_mf_tag_discard" },
 108         { STATS_OFFSET32(pfc_frames_received_hi),
 109                                 8, true, "pfc_frames_received" },
 110         { STATS_OFFSET32(pfc_frames_sent_hi),
 111                                 8, true, "pfc_frames_sent" },
 112         { STATS_OFFSET32(brb_drop_hi),
 113                                 8, true, "rx_brb_discard" },
 114         { STATS_OFFSET32(brb_truncate_hi),
 115                                 8, true, "rx_brb_truncate" },
 116         { STATS_OFFSET32(pause_frames_received_hi),
 117                                 8, true, "rx_pause_frames" },
 118         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 119                                 8, true, "rx_mac_ctrl_frames" },
 120         { STATS_OFFSET32(nig_timer_max),
 121                                 4, true, "rx_constant_pause_events" },
 122 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 123                                 4, false, "rx_phy_ip_err_discards"},
 124         { STATS_OFFSET32(rx_skb_alloc_failed),
 125                                 4, false, "rx_skb_alloc_discard" },
 126         { STATS_OFFSET32(hw_csum_err),
 127                                 4, false, "rx_csum_offload_errors" },
 128         { STATS_OFFSET32(driver_xoff),
 129                                 4, false, "tx_exhaustion_events" },
 130         { STATS_OFFSET32(total_bytes_transmitted_hi),
 131                                 8, false, "tx_bytes" },
 132         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 133                                 8, true, "tx_error_bytes" },
 134         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 135                                 8, false, "tx_ucast_packets" },
 136         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 137                                 8, false, "tx_mcast_packets" },
 138         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 139                                 8, false, "tx_bcast_packets" },
 140         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 141                                 8, true, "tx_mac_errors" },
 142         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 143                                 8, true, "tx_carrier_errors" },
 144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 145                                 8, true, "tx_single_collisions" },
 146         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 147                                 8, true, "tx_multi_collisions" },
 148         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 149                                 8, true, "tx_deferred" },
 150         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 151                                 8, true, "tx_excess_collisions" },
 152         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 153                                 8, true, "tx_late_collisions" },
 154         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 155                                 8, true, "tx_total_collisions" },
 156         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 157                                 8, true, "tx_64_byte_packets" },
 158         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 159                                 8, true, "tx_65_to_127_byte_packets" },
 160         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 161                                 8, true, "tx_128_to_255_byte_packets" },
 162         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 163                                 8, true, "tx_256_to_511_byte_packets" },
 164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 165                                 8, true, "tx_512_to_1023_byte_packets" },
 166         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 167                                 8, true, "tx_1024_to_1522_byte_packets" },
 168         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 169                                 8, true, "tx_1523_to_9022_byte_packets" },
 170         { STATS_OFFSET32(pause_frames_sent_hi),
 171                                 8, true, "tx_pause_frames" },
 172         { STATS_OFFSET32(total_tpa_aggregations_hi),
 173                                 8, false, "tpa_aggregations" },
 174         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 175                                 8, false, "tpa_aggregated_frames"},
 176         { STATS_OFFSET32(total_tpa_bytes_hi),
 177                                 8, false, "tpa_bytes"},
 178         { STATS_OFFSET32(recoverable_error),
 179                                 4, false, "recoverable_errors" },
 180         { STATS_OFFSET32(unrecoverable_error),
 181                                 4, false, "unrecoverable_errors" },
 182         { STATS_OFFSET32(driver_filtered_tx_pkt),
 183                                 4, false, "driver_filtered_tx_pkt" },
 184         { STATS_OFFSET32(eee_tx_lpi),
 185                                 4, true, "Tx LPI entry count"},
 186         { STATS_OFFSET32(ptp_skip_tx_ts),
 187                                 4, false, "ptp_skipped_tx_tstamp" },
 188 };
 189
 190 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 191
 192 static int bnx2x_get_port_type(struct bnx2x *bp)
 193 {
 194         int port_type;
 195         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 196         switch (bp->link_params.phy[phy_idx].media_type) {
 197         case ETH_PHY_SFPP_10G_FIBER:
 198         case ETH_PHY_SFP_1G_FIBER:
 199         case ETH_PHY_XFP_FIBER:
 200         case ETH_PHY_KR:
 201         case ETH_PHY_CX4:
 202                 port_type = PORT_FIBRE;
 203                 break;
 204         case ETH_PHY_DA_TWINAX:
 205                 port_type = PORT_DA;
 206                 break;
 207         case ETH_PHY_BASE_T:
 208                 port_type = PORT_TP;
 209                 break;
 210         case ETH_PHY_NOT_PRESENT:
 211                 port_type = PORT_NONE;
 212                 break;
 213         case ETH_PHY_UNSPECIFIED:
 214         default:
 215                 port_type = PORT_OTHER;
 216                 break;
 217         }
 218         return port_type;
 219 }
 220
 221 static int bnx2x_get_vf_settings(struct net_device *dev,
 222                                  struct ethtool_cmd *cmd)
 223 {
 224         struct bnx2x *bp = netdev_priv(dev);
 225
 226         if (bp->state == BNX2X_STATE_OPEN) {
 227                 if (test_bit(BNX2X_LINK_REPORT_FD,
 228                              &bp->vf_link_vars.link_report_flags))
 229                         cmd->duplex = DUPLEX_FULL;
 230                 else
 231                         cmd->duplex = DUPLEX_HALF;
 232
 233                 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
 234         } else {
 235                 cmd->duplex = DUPLEX_UNKNOWN;
 236                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 237         }
 238
 239         cmd->port               = PORT_OTHER;
 240         cmd->phy_address        = 0;
 241         cmd->transceiver        = XCVR_INTERNAL;
 242         cmd->autoneg            = AUTONEG_DISABLE;
 243         cmd->maxtxpkt           = 0;
 244         cmd->maxrxpkt           = 0;
 245
 246         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 247            "  supported 0x%x  advertising 0x%x  speed %u\n"
 248            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 249            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 250            cmd->cmd, cmd->supported, cmd->advertising,
 251            ethtool_cmd_speed(cmd),
 252            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 253            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 254
 255         return 0;
 256 }
 257
 258 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 259 {
 260         struct bnx2x *bp = netdev_priv(dev);
 261         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 262         u32 media_type;
 263
 264         /* Dual Media boards present all available port types */
 265         cmd->supported = bp->port.supported[cfg_idx] |
 266                 (bp->port.supported[cfg_idx ^ 1] &
 267                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 268         cmd->advertising = bp->port.advertising[cfg_idx];
 269         media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
 270         if (media_type == ETH_PHY_SFP_1G_FIBER) {
 271                 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
 272                 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
 273         }
 274
 275         if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
 276             !(bp->flags & MF_FUNC_DIS)) {
 277                 cmd->duplex = bp->link_vars.duplex;
 278
 279                 if (IS_MF(bp) && !BP_NOMCP(bp))
 280                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 281                 else
 282                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 283         } else {
 284                 cmd->duplex = DUPLEX_UNKNOWN;
 285                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 286         }
 287
 288         cmd->port = bnx2x_get_port_type(bp);
 289
 290         cmd->phy_address = bp->mdio.prtad;
 291         cmd->transceiver = XCVR_INTERNAL;
 292
 293         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 294                 cmd->autoneg = AUTONEG_ENABLE;
 295         else
 296                 cmd->autoneg = AUTONEG_DISABLE;
 297
 298         /* Publish LP advertised speeds and FC */
 299         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 300                 u32 status = bp->link_vars.link_status;
 301
 302                 cmd->lp_advertising |= ADVERTISED_Autoneg;
 303                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 304                         cmd->lp_advertising |= ADVERTISED_Pause;
 305                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 306                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
 307
 308                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 309                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
 310                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 311                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
 312                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 313                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
 314                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 315                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
 316                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 317                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
 318                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
 319                         if (media_type == ETH_PHY_KR) {
 320                                 cmd->lp_advertising |=
 321                                         ADVERTISED_1000baseKX_Full;
 322                         } else {
 323                                 cmd->lp_advertising |=
 324                                         ADVERTISED_1000baseT_Full;
 325                         }
 326                 }
 327                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 328                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
 329                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
 330                         if (media_type == ETH_PHY_KR) {
 331                                 cmd->lp_advertising |=
 332                                         ADVERTISED_10000baseKR_Full;
 333                         } else {
 334                                 cmd->lp_advertising |=
 335                                         ADVERTISED_10000baseT_Full;
 336                         }
 337                 }
 338                 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
 339                         cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
 340         }
 341
 342         cmd->maxtxpkt = 0;
 343         cmd->maxrxpkt = 0;
 344
 345         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 346            "  supported 0x%x  advertising 0x%x  speed %u\n"
 347            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 348            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 349            cmd->cmd, cmd->supported, cmd->advertising,
 350            ethtool_cmd_speed(cmd),
 351            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 352            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 353
 354         return 0;
 355 }
 356
 357 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 358 {
 359         struct bnx2x *bp = netdev_priv(dev);
 360         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 361         u32 speed, phy_idx;
 362
 363         if (IS_MF_SD(bp))
 364                 return 0;
 365
 366         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 367            "  supported 0x%x  advertising 0x%x  speed %u\n"
 368            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 369            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 370            cmd->cmd, cmd->supported, cmd->advertising,
 371            ethtool_cmd_speed(cmd),
 372            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 373            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 374
 375         speed = ethtool_cmd_speed(cmd);
 376
 377         /* If received a request for an unknown duplex, assume full*/
 378         if (cmd->duplex == DUPLEX_UNKNOWN)
 379                 cmd->duplex = DUPLEX_FULL;
 380
 381         if (IS_MF_SI(bp)) {
 382                 u32 part;
 383                 u32 line_speed = bp->link_vars.line_speed;
 384
 385                 /* use 10G if no link detected */
 386                 if (!line_speed)
 387                         line_speed = 10000;
 388
 389                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 390                         DP(BNX2X_MSG_ETHTOOL,
 391                            "To set speed BC %X or higher is required, please upgrade BC\n",
 392                            REQ_BC_VER_4_SET_MF_BW);
 393                         return -EINVAL;
 394                 }
 395
 396                 part = (speed * 100) / line_speed;
 397
 398                 if (line_speed < speed || !part) {
 399                         DP(BNX2X_MSG_ETHTOOL,
 400                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 401                         return -EINVAL;
 402                 }
 403
 404                 if (bp->state != BNX2X_STATE_OPEN)
 405                         /* store value for following "load" */
 406                         bp->pending_max = part;
 407                 else
 408                         bnx2x_update_max_mf_config(bp, part);
 409
 410                 return 0;
 411         }
 412
 413         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 414         old_multi_phy_config = bp->link_params.multi_phy_config;
 415         if (cmd->port != bnx2x_get_port_type(bp)) {
 416                 switch (cmd->port) {
 417                 case PORT_TP:
 418                         if (!(bp->port.supported[0] & SUPPORTED_TP ||
 419                               bp->port.supported[1] & SUPPORTED_TP)) {
 420                                 DP(BNX2X_MSG_ETHTOOL,
 421                                    "Unsupported port type\n");
 422                                 return -EINVAL;
 423                         }
 424                         bp->link_params.multi_phy_config &=
 425                                 ~PORT_HW_CFG_PHY_SELECTION_MASK;
 426                         if (bp->link_params.multi_phy_config &
 427                             PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 428                                 bp->link_params.multi_phy_config |=
 429                                 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 430                         else
 431                                 bp->link_params.multi_phy_config |=
 432                                 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 433                         break;
 434                 case PORT_FIBRE:
 435                 case PORT_DA:
 436                 case PORT_NONE:
 437                         if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 438                               bp->port.supported[1] & SUPPORTED_FIBRE)) {
 439                                 DP(BNX2X_MSG_ETHTOOL,
 440                                    "Unsupported port type\n");
 441                                 return -EINVAL;
 442                         }
 443                         bp->link_params.multi_phy_config &=
 444                                 ~PORT_HW_CFG_PHY_SELECTION_MASK;
 445                         if (bp->link_params.multi_phy_config &
 446                             PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 447                                 bp->link_params.multi_phy_config |=
 448                                 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 449                         else
 450                                 bp->link_params.multi_phy_config |=
 451                                 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 452                         break;
 453                 default:
 454                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 455                         return -EINVAL;
 456                 }
 457         }
 458         /* Save new config in case command complete successfully */
 459         new_multi_phy_config = bp->link_params.multi_phy_config;
 460         /* Get the new cfg_idx */
 461         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 462         /* Restore old config in case command failed */
 463         bp->link_params.multi_phy_config = old_multi_phy_config;
 464         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 465
 466         if (cmd->autoneg == AUTONEG_ENABLE) {
 467                 u32 an_supported_speed = bp->port.supported[cfg_idx];
 468                 if (bp->link_params.phy[EXT_PHY1].type ==
 469                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 470                         an_supported_speed |= (SUPPORTED_100baseT_Half |
 471                                                SUPPORTED_100baseT_Full);
 472                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 473                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 474                         return -EINVAL;
 475                 }
 476
 477                 /* advertise the requested speed and duplex if supported */
 478                 if (cmd->advertising & ~an_supported_speed) {
 479                         DP(BNX2X_MSG_ETHTOOL,
 480                            "Advertisement parameters are not supported\n");
 481                         return -EINVAL;
 482                 }
 483
 484                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 485                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 486                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 487                                          cmd->advertising);
 488                 if (cmd->advertising) {
 489
 490                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 491                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 492                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 493                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 494                         }
 495                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 496                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 497                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 498
 499                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 500                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 501                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 502
 503                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 504                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 505                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 506                         }
 507                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 508                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 509                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 510                         }
 511                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 512                                                 ADVERTISED_1000baseKX_Full))
 513                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 514                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 515
 516                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 517                                                 ADVERTISED_10000baseKX4_Full |
 518                                                 ADVERTISED_10000baseKR_Full))
 519                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 520                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 521
 522                         if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
 523                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 524                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
 525                 }
 526         } else { /* forced speed */
 527                 /* advertise the requested speed and duplex if supported */
 528                 switch (speed) {
 529                 case SPEED_10:
 530                         if (cmd->duplex == DUPLEX_FULL) {
 531                                 if (!(bp->port.supported[cfg_idx] &
 532                                       SUPPORTED_10baseT_Full)) {
 533                                         DP(BNX2X_MSG_ETHTOOL,
 534                                            "10M full not supported\n");
 535                                         return -EINVAL;
 536                                 }
 537
 538                                 advertising = (ADVERTISED_10baseT_Full |
 539                                                ADVERTISED_TP);
 540                         } else {
 541                                 if (!(bp->port.supported[cfg_idx] &
 542                                       SUPPORTED_10baseT_Half)) {
 543                                         DP(BNX2X_MSG_ETHTOOL,
 544                                            "10M half not supported\n");
 545                                         return -EINVAL;
 546                                 }
 547
 548                                 advertising = (ADVERTISED_10baseT_Half |
 549                                                ADVERTISED_TP);
 550                         }
 551                         break;
 552
 553                 case SPEED_100:
 554                         if (cmd->duplex == DUPLEX_FULL) {
 555                                 if (!(bp->port.supported[cfg_idx] &
 556                                                 SUPPORTED_100baseT_Full)) {
 557                                         DP(BNX2X_MSG_ETHTOOL,
 558                                            "100M full not supported\n");
 559                                         return -EINVAL;
 560                                 }
 561
 562                                 advertising = (ADVERTISED_100baseT_Full |
 563                                                ADVERTISED_TP);
 564                         } else {
 565                                 if (!(bp->port.supported[cfg_idx] &
 566                                                 SUPPORTED_100baseT_Half)) {
 567                                         DP(BNX2X_MSG_ETHTOOL,
 568                                            "100M half not supported\n");
 569                                         return -EINVAL;
 570                                 }
 571
 572                                 advertising = (ADVERTISED_100baseT_Half |
 573                                                ADVERTISED_TP);
 574                         }
 575                         break;
 576
 577                 case SPEED_1000:
 578                         if (cmd->duplex != DUPLEX_FULL) {
 579                                 DP(BNX2X_MSG_ETHTOOL,
 580                                    "1G half not supported\n");
 581                                 return -EINVAL;
 582                         }
 583
 584                         if (bp->port.supported[cfg_idx] &
 585                              SUPPORTED_1000baseT_Full) {
 586                                 advertising = (ADVERTISED_1000baseT_Full |
 587                                                ADVERTISED_TP);
 588
 589                         } else if (bp->port.supported[cfg_idx] &
 590                                    SUPPORTED_1000baseKX_Full) {
 591                                 advertising = ADVERTISED_1000baseKX_Full;
 592                         } else {
 593                                 DP(BNX2X_MSG_ETHTOOL,
 594                                    "1G full not supported\n");
 595                                 return -EINVAL;
 596                         }
 597
 598                         break;
 599
 600                 case SPEED_2500:
 601                         if (cmd->duplex != DUPLEX_FULL) {
 602                                 DP(BNX2X_MSG_ETHTOOL,
 603                                    "2.5G half not supported\n");
 604                                 return -EINVAL;
 605                         }
 606
 607                         if (!(bp->port.supported[cfg_idx]
 608                               & SUPPORTED_2500baseX_Full)) {
 609                                 DP(BNX2X_MSG_ETHTOOL,
 610                                    "2.5G full not supported\n");
 611                                 return -EINVAL;
 612                         }
 613
 614                         advertising = (ADVERTISED_2500baseX_Full |
 615                                        ADVERTISED_TP);
 616                         break;
 617
 618                 case SPEED_10000:
 619                         if (cmd->duplex != DUPLEX_FULL) {
 620                                 DP(BNX2X_MSG_ETHTOOL,
 621                                    "10G half not supported\n");
 622                                 return -EINVAL;
 623                         }
 624                         phy_idx = bnx2x_get_cur_phy_idx(bp);
 625                         if ((bp->port.supported[cfg_idx] &
 626                              SUPPORTED_10000baseT_Full) &&
 627                             (bp->link_params.phy[phy_idx].media_type !=
 628                              ETH_PHY_SFP_1G_FIBER)) {
 629                                 advertising = (ADVERTISED_10000baseT_Full |
 630                                                ADVERTISED_FIBRE);
 631                         } else if (bp->port.supported[cfg_idx] &
 632                                SUPPORTED_10000baseKR_Full) {
 633                                 advertising = (ADVERTISED_10000baseKR_Full |
 634                                                ADVERTISED_FIBRE);
 635                         } else {
 636                                 DP(BNX2X_MSG_ETHTOOL,
 637                                    "10G full not supported\n");
 638                                 return -EINVAL;
 639                         }
 640
 641                         break;
 642
 643                 default:
 644                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 645                         return -EINVAL;
 646                 }
 647
 648                 bp->link_params.req_line_speed[cfg_idx] = speed;
 649                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 650                 bp->port.advertising[cfg_idx] = advertising;
 651         }
 652
 653         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 654            "  req_duplex %d  advertising 0x%x\n",
 655            bp->link_params.req_line_speed[cfg_idx],
 656            bp->link_params.req_duplex[cfg_idx],
 657            bp->port.advertising[cfg_idx]);
 658
 659         /* Set new config */
 660         bp->link_params.multi_phy_config = new_multi_phy_config;
 661         if (netif_running(dev)) {
 662                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 663                 bnx2x_force_link_reset(bp);
 664                 bnx2x_link_set(bp);
 665         }
 666
 667         return 0;
 668 }
 669
 670 #define DUMP_ALL_PRESETS                0x1FFF
 671 #define DUMP_MAX_PRESETS                13
 672
 673 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
 674 {
 675         if (CHIP_IS_E1(bp))
 676                 return dump_num_registers[0][preset-1];
 677         else if (CHIP_IS_E1H(bp))
 678                 return dump_num_registers[1][preset-1];
 679         else if (CHIP_IS_E2(bp))
 680                 return dump_num_registers[2][preset-1];
 681         else if (CHIP_IS_E3A0(bp))
 682                 return dump_num_registers[3][preset-1];
 683         else if (CHIP_IS_E3B0(bp))
 684                 return dump_num_registers[4][preset-1];
 685         else
 686                 return 0;
 687 }
 688
 689 static int __bnx2x_get_regs_len(struct bnx2x *bp)
 690 {
 691         u32 preset_idx;
 692         int regdump_len = 0;
 693
 694         /* Calculate the total preset regs length */
 695         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
 696                 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
 697
 698         return regdump_len;
 699 }
 700
 701 static int bnx2x_get_regs_len(struct net_device *dev)
 702 {
 703         struct bnx2x *bp = netdev_priv(dev);
 704         int regdump_len = 0;
 705
 706         if (IS_VF(bp))
 707                 return 0;
 708
 709         regdump_len = __bnx2x_get_regs_len(bp);
 710         regdump_len *= 4;
 711         regdump_len += sizeof(struct dump_header);
 712
 713         return regdump_len;
 714 }
 715
 716 #define IS_E1_REG(chips)        ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
 717 #define IS_E1H_REG(chips)       ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
 718 #define IS_E2_REG(chips)        ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
 719 #define IS_E3A0_REG(chips)      ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
 720 #define IS_E3B0_REG(chips)      ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
 721
 722 #define IS_REG_IN_PRESET(presets, idx)  \
 723                 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
 724
 725 /******* Paged registers info selectors ********/
 726 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 727 {
 728         if (CHIP_IS_E2(bp))
 729                 return page_vals_e2;
 730         else if (CHIP_IS_E3(bp))
 731                 return page_vals_e3;
 732         else
 733                 return NULL;
 734 }
 735
 736 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 737 {
 738         if (CHIP_IS_E2(bp))
 739                 return PAGE_MODE_VALUES_E2;
 740         else if (CHIP_IS_E3(bp))
 741                 return PAGE_MODE_VALUES_E3;
 742         else
 743                 return 0;
 744 }
 745
 746 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 747 {
 748         if (CHIP_IS_E2(bp))
 749                 return page_write_regs_e2;
 750         else if (CHIP_IS_E3(bp))
 751                 return page_write_regs_e3;
 752         else
 753                 return NULL;
 754 }
 755
 756 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 757 {
 758         if (CHIP_IS_E2(bp))
 759                 return PAGE_WRITE_REGS_E2;
 760         else if (CHIP_IS_E3(bp))
 761                 return PAGE_WRITE_REGS_E3;
 762         else
 763                 return 0;
 764 }
 765
 766 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 767 {
 768         if (CHIP_IS_E2(bp))
 769                 return page_read_regs_e2;
 770         else if (CHIP_IS_E3(bp))
 771                 return page_read_regs_e3;
 772         else
 773                 return NULL;
 774 }
 775
 776 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 777 {
 778         if (CHIP_IS_E2(bp))
 779                 return PAGE_READ_REGS_E2;
 780         else if (CHIP_IS_E3(bp))
 781                 return PAGE_READ_REGS_E3;
 782         else
 783                 return 0;
 784 }
 785
 786 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
 787                                        const struct reg_addr *reg_info)
 788 {
 789         if (CHIP_IS_E1(bp))
 790                 return IS_E1_REG(reg_info->chips);
 791         else if (CHIP_IS_E1H(bp))
 792                 return IS_E1H_REG(reg_info->chips);
 793         else if (CHIP_IS_E2(bp))
 794                 return IS_E2_REG(reg_info->chips);
 795         else if (CHIP_IS_E3A0(bp))
 796                 return IS_E3A0_REG(reg_info->chips);
 797         else if (CHIP_IS_E3B0(bp))
 798                 return IS_E3B0_REG(reg_info->chips);
 799         else
 800                 return false;
 801 }
 802
 803 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
 804         const struct wreg_addr *wreg_info)
 805 {
 806         if (CHIP_IS_E1(bp))
 807                 return IS_E1_REG(wreg_info->chips);
 808         else if (CHIP_IS_E1H(bp))
 809                 return IS_E1H_REG(wreg_info->chips);
 810         else if (CHIP_IS_E2(bp))
 811                 return IS_E2_REG(wreg_info->chips);
 812         else if (CHIP_IS_E3A0(bp))
 813                 return IS_E3A0_REG(wreg_info->chips);
 814         else if (CHIP_IS_E3B0(bp))
 815                 return IS_E3B0_REG(wreg_info->chips);
 816         else
 817                 return false;
 818 }
 819
 820 /**
 821  * bnx2x_read_pages_regs - read "paged" registers
 822  *
 823  * @bp          device handle
 824  * @p           output buffer
 825  *
 826  * Reads "paged" memories: memories that may only be read by first writing to a
 827  * specific address ("write address") and then reading from a specific address
 828  * ("read address"). There may be more than one write address per "page" and
 829  * more than one read address per write address.
 830  */
 831 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
 832 {
 833         u32 i, j, k, n;
 834
 835         /* addresses of the paged registers */
 836         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 837         /* number of paged registers */
 838         int num_pages = __bnx2x_get_page_reg_num(bp);
 839         /* write addresses */
 840         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 841         /* number of write addresses */
 842         int write_num = __bnx2x_get_page_write_num(bp);
 843         /* read addresses info */
 844         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 845         /* number of read addresses */
 846         int read_num = __bnx2x_get_page_read_num(bp);
 847         u32 addr, size;
 848
 849         for (i = 0; i < num_pages; i++) {
 850                 for (j = 0; j < write_num; j++) {
 851                         REG_WR(bp, write_addr[j], page_addr[i]);
 852
 853                         for (k = 0; k < read_num; k++) {
 854                                 if (IS_REG_IN_PRESET(read_addr[k].presets,
 855                                                      preset)) {
 856                                         size = read_addr[k].size;
 857                                         for (n = 0; n < size; n++) {
 858                                                 addr = read_addr[k].addr + n*4;
 859                                                 *p++ = REG_RD(bp, addr);
 860                                         }
 861                                 }
 862                         }
 863                 }
 864         }
 865 }
 866
 867 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
 868 {
 869         u32 i, j, addr;
 870         const struct wreg_addr *wreg_addr_p = NULL;
 871
 872         if (CHIP_IS_E1(bp))
 873                 wreg_addr_p = &wreg_addr_e1;
 874         else if (CHIP_IS_E1H(bp))
 875                 wreg_addr_p = &wreg_addr_e1h;
 876         else if (CHIP_IS_E2(bp))
 877                 wreg_addr_p = &wreg_addr_e2;
 878         else if (CHIP_IS_E3A0(bp))
 879                 wreg_addr_p = &wreg_addr_e3;
 880         else if (CHIP_IS_E3B0(bp))
 881                 wreg_addr_p = &wreg_addr_e3b0;
 882
 883         /* Read the idle_chk registers */
 884         for (i = 0; i < IDLE_REGS_COUNT; i++) {
 885                 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
 886                     IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
 887                         for (j = 0; j < idle_reg_addrs[i].size; j++)
 888                                 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
 889                 }
 890         }
 891
 892         /* Read the regular registers */
 893         for (i = 0; i < REGS_COUNT; i++) {
 894                 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
 895                     IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
 896                         for (j = 0; j < reg_addrs[i].size; j++)
 897                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 898                 }
 899         }
 900
 901         /* Read the CAM registers */
 902         if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
 903             IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
 904                 for (i = 0; i < wreg_addr_p->size; i++) {
 905                         *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
 906
 907                         /* In case of wreg_addr register, read additional
 908                            registers from read_regs array
 909                         */
 910                         for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
 911                                 addr = *(wreg_addr_p->read_regs);
 912                                 *p++ = REG_RD(bp, addr + j*4);
 913                         }
 914                 }
 915         }
 916
 917         /* Paged registers are supported in E2 & E3 only */
 918         if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
 919                 /* Read "paged" registers */
 920                 bnx2x_read_pages_regs(bp, p, preset);
 921         }
 922
 923         return 0;
 924 }
 925
 926 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 927 {
 928         u32 preset_idx;
 929
 930         /* Read all registers, by reading all preset registers */
 931         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
 932                 /* Skip presets with IOR */
 933                 if ((preset_idx == 2) ||
 934                     (preset_idx == 5) ||
 935                     (preset_idx == 8) ||
 936                     (preset_idx == 11))
 937                         continue;
 938                 __bnx2x_get_preset_regs(bp, p, preset_idx);
 939                 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
 940         }
 941 }
 942
 943 static void bnx2x_get_regs(struct net_device *dev,
 944                            struct ethtool_regs *regs, void *_p)
 945 {
 946         u32 *p = _p;
 947         struct bnx2x *bp = netdev_priv(dev);
 948         struct dump_header dump_hdr = {0};
 949
 950         regs->version = 2;
 951         memset(p, 0, regs->len);
 952
 953         if (!netif_running(bp->dev))
 954                 return;
 955
 956         /* Disable parity attentions as long as following dump may
 957          * cause false alarms by reading never written registers. We
 958          * will re-enable parity attentions right after the dump.
 959          */
 960
 961         bnx2x_disable_blocks_parity(bp);
 962
 963         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
 964         dump_hdr.preset = DUMP_ALL_PRESETS;
 965         dump_hdr.version = BNX2X_DUMP_VERSION;
 966
 967         /* dump_meta_data presents OR of CHIP and PATH. */
 968         if (CHIP_IS_E1(bp)) {
 969                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
 970         } else if (CHIP_IS_E1H(bp)) {
 971                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
 972         } else if (CHIP_IS_E2(bp)) {
 973                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
 974                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 975         } else if (CHIP_IS_E3A0(bp)) {
 976                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
 977                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 978         } else if (CHIP_IS_E3B0(bp)) {
 979                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
 980                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 981         }
 982
 983         memcpy(p, &dump_hdr, sizeof(struct dump_header));
 984         p += dump_hdr.header_size + 1;
 985
 986         /* This isn't really an error, but since attention handling is going
 987          * to print the GRC timeouts using this macro, we use the same.
 988          */
 989         BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n");
 990
 991         /* Actually read the registers */
 992         __bnx2x_get_regs(bp, p);
 993
 994         /* Re-enable parity attentions */
 995         bnx2x_clear_blocks_parity(bp);
 996         bnx2x_enable_blocks_parity(bp);
 997 }
 998
 999 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
1000 {
1001         struct bnx2x *bp = netdev_priv(dev);
1002         int regdump_len = 0;
1003
1004         regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1005         regdump_len *= 4;
1006         regdump_len += sizeof(struct dump_header);
1007
1008         return regdump_len;
1009 }
1010
1011 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1012 {
1013         struct bnx2x *bp = netdev_priv(dev);
1014
1015         /* Use the ethtool_dump "flag" field as the dump preset index */
1016         if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1017                 return -EINVAL;
1018
1019         bp->dump_preset_idx = val->flag;
1020         return 0;
1021 }
1022
1023 static int bnx2x_get_dump_flag(struct net_device *dev,
1024                                struct ethtool_dump *dump)
1025 {
1026         struct bnx2x *bp = netdev_priv(dev);
1027
1028         dump->version = BNX2X_DUMP_VERSION;
1029         dump->flag = bp->dump_preset_idx;
1030         /* Calculate the requested preset idx length */
1031         dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1032         DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1033            bp->dump_preset_idx, dump->len);
1034         return 0;
1035 }
1036
1037 static int bnx2x_get_dump_data(struct net_device *dev,
1038                                struct ethtool_dump *dump,
1039                                void *buffer)
1040 {
1041         u32 *p = buffer;
1042         struct bnx2x *bp = netdev_priv(dev);
1043         struct dump_header dump_hdr = {0};
1044
1045         /* Disable parity attentions as long as following dump may
1046          * cause false alarms by reading never written registers. We
1047          * will re-enable parity attentions right after the dump.
1048          */
1049
1050         bnx2x_disable_blocks_parity(bp);
1051
1052         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1053         dump_hdr.preset = bp->dump_preset_idx;
1054         dump_hdr.version = BNX2X_DUMP_VERSION;
1055
1056         DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1057
1058         /* dump_meta_data presents OR of CHIP and PATH. */
1059         if (CHIP_IS_E1(bp)) {
1060                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1061         } else if (CHIP_IS_E1H(bp)) {
1062                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1063         } else if (CHIP_IS_E2(bp)) {
1064                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1065                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1066         } else if (CHIP_IS_E3A0(bp)) {
1067                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1068                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1069         } else if (CHIP_IS_E3B0(bp)) {
1070                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1071                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1072         }
1073
1074         memcpy(p, &dump_hdr, sizeof(struct dump_header));
1075         p += dump_hdr.header_size + 1;
1076
1077         /* Actually read the registers */
1078         __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1079
1080         /* Re-enable parity attentions */
1081         bnx2x_clear_blocks_parity(bp);
1082         bnx2x_enable_blocks_parity(bp);
1083
1084         return 0;
1085 }
1086
1087 static void bnx2x_get_drvinfo(struct net_device *dev,
1088                               struct ethtool_drvinfo *info)
1089 {
1090         struct bnx2x *bp = netdev_priv(dev);
1091
1092         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1093         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1094
1095         bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1096
1097         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1098 }
1099
1100 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1101 {
1102         struct bnx2x *bp = netdev_priv(dev);
1103
1104         if (bp->flags & NO_WOL_FLAG) {
1105                 wol->supported = 0;
1106                 wol->wolopts = 0;
1107         } else {
1108                 wol->supported = WAKE_MAGIC;
1109                 if (bp->wol)
1110                         wol->wolopts = WAKE_MAGIC;
1111                 else
1112                         wol->wolopts = 0;
1113         }
1114         memset(&wol->sopass, 0, sizeof(wol->sopass));
1115 }
1116
1117 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1118 {
1119         struct bnx2x *bp = netdev_priv(dev);
1120
1121         if (wol->wolopts & ~WAKE_MAGIC) {
1122                 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1123                 return -EINVAL;
1124         }
1125
1126         if (wol->wolopts & WAKE_MAGIC) {
1127                 if (bp->flags & NO_WOL_FLAG) {
1128                         DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1129                         return -EINVAL;
1130                 }
1131                 bp->wol = 1;
1132         } else
1133                 bp->wol = 0;
1134
1135         if (SHMEM2_HAS(bp, curr_cfg))
1136                 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1137
1138         return 0;
1139 }
1140
1141 static u32 bnx2x_get_msglevel(struct net_device *dev)
1142 {
1143         struct bnx2x *bp = netdev_priv(dev);
1144
1145         return bp->msg_enable;
1146 }
1147
1148 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1149 {
1150         struct bnx2x *bp = netdev_priv(dev);
1151
1152         if (capable(CAP_NET_ADMIN)) {
1153                 /* dump MCP trace */
1154                 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1155                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
1156                 bp->msg_enable = level;
1157         }
1158 }
1159
1160 static int bnx2x_nway_reset(struct net_device *dev)
1161 {
1162         struct bnx2x *bp = netdev_priv(dev);
1163
1164         if (!bp->port.pmf)
1165                 return 0;
1166
1167         if (netif_running(dev)) {
1168                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1169                 bnx2x_force_link_reset(bp);
1170                 bnx2x_link_set(bp);
1171         }
1172
1173         return 0;
1174 }
1175
1176 static u32 bnx2x_get_link(struct net_device *dev)
1177 {
1178         struct bnx2x *bp = netdev_priv(dev);
1179
1180         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1181                 return 0;
1182
1183         if (IS_VF(bp))
1184                 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1185                                  &bp->vf_link_vars.link_report_flags);
1186
1187         return bp->link_vars.link_up;
1188 }
1189
1190 static int bnx2x_get_eeprom_len(struct net_device *dev)
1191 {
1192         struct bnx2x *bp = netdev_priv(dev);
1193
1194         return bp->common.flash_size;
1195 }
1196
1197 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1198  * had we done things the other way around, if two pfs from the same port would
1199  * attempt to access nvram at the same time, we could run into a scenario such
1200  * as:
1201  * pf A takes the port lock.
1202  * pf B succeeds in taking the same lock since they are from the same port.
1203  * pf A takes the per pf misc lock. Performs eeprom access.
1204  * pf A finishes. Unlocks the per pf misc lock.
1205  * Pf B takes the lock and proceeds to perform it's own access.
1206  * pf A unlocks the per port lock, while pf B is still working (!).
1207  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1208  * access corrupted by pf B)
1209  */
1210 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1211 {
1212         int port = BP_PORT(bp);
1213         int count, i;
1214         u32 val;
1215
1216         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1217         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1218
1219         /* adjust timeout for emulation/FPGA */
1220         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1221         if (CHIP_REV_IS_SLOW(bp))
1222                 count *= 100;
1223
1224         /* request access to nvram interface */
1225         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1226                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1227
1228         for (i = 0; i < count*10; i++) {
1229                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1230                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1231                         break;
1232
1233                 udelay(5);
1234         }
1235
1236         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1237                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1238                    "cannot get access to nvram interface\n");
1239                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1240                 return -EBUSY;
1241         }
1242
1243         return 0;
1244 }
1245
1246 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1247 {
1248         int port = BP_PORT(bp);
1249         int count, i;
1250         u32 val;
1251
1252         /* adjust timeout for emulation/FPGA */
1253         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1254         if (CHIP_REV_IS_SLOW(bp))
1255                 count *= 100;
1256
1257         /* relinquish nvram interface */
1258         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1259                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1260
1261         for (i = 0; i < count*10; i++) {
1262                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1263                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1264                         break;
1265
1266                 udelay(5);
1267         }
1268
1269         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1270                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1271                    "cannot free access to nvram interface\n");
1272                 return -EBUSY;
1273         }
1274
1275         /* release HW lock: protect against other PFs in PF Direct Assignment */
1276         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1277         return 0;
1278 }
1279
1280 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1281 {
1282         u32 val;
1283
1284         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1285
1286         /* enable both bits, even on read */
1287         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1288                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1289                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1290 }
1291
1292 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1293 {
1294         u32 val;
1295
1296         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1297
1298         /* disable both bits, even after read */
1299         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1300                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1301                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1302 }
1303
1304 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1305                                   u32 cmd_flags)
1306 {
1307         int count, i, rc;
1308         u32 val;
1309
1310         /* build the command word */
1311         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1312
1313         /* need to clear DONE bit separately */
1314         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1315
1316         /* address of the NVRAM to read from */
1317         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1318                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1319
1320         /* issue a read command */
1321         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1322
1323         /* adjust timeout for emulation/FPGA */
1324         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1325         if (CHIP_REV_IS_SLOW(bp))
1326                 count *= 100;
1327
1328         /* wait for completion */
1329         *ret_val = 0;
1330         rc = -EBUSY;
1331         for (i = 0; i < count; i++) {
1332                 udelay(5);
1333                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1334
1335                 if (val & MCPR_NVM_COMMAND_DONE) {
1336                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1337                         /* we read nvram data in cpu order
1338                          * but ethtool sees it as an array of bytes
1339                          * converting to big-endian will do the work
1340                          */
1341                         *ret_val = cpu_to_be32(val);
1342                         rc = 0;
1343                         break;
1344                 }
1345         }
1346         if (rc == -EBUSY)
1347                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1348                    "nvram read timeout expired\n");
1349         return rc;
1350 }
1351
1352 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1353                      int buf_size)
1354 {
1355         int rc;
1356         u32 cmd_flags;
1357         __be32 val;
1358
1359         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1360                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1361                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1362                    offset, buf_size);
1363                 return -EINVAL;
1364         }
1365
1366         if (offset + buf_size > bp->common.flash_size) {
1367                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1368                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1369                    offset, buf_size, bp->common.flash_size);
1370                 return -EINVAL;
1371         }
1372
1373         /* request access to nvram interface */
1374         rc = bnx2x_acquire_nvram_lock(bp);
1375         if (rc)
1376                 return rc;
1377
1378         /* enable access to nvram interface */
1379         bnx2x_enable_nvram_access(bp);
1380
1381         /* read the first word(s) */
1382         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1383         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1384                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1385                 memcpy(ret_buf, &val, 4);
1386
1387                 /* advance to the next dword */
1388                 offset += sizeof(u32);
1389                 ret_buf += sizeof(u32);
1390                 buf_size -= sizeof(u32);
1391                 cmd_flags = 0;
1392         }
1393
1394         if (rc == 0) {
1395                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1396                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1397                 memcpy(ret_buf, &val, 4);
1398         }
1399
1400         /* disable access to nvram interface */
1401         bnx2x_disable_nvram_access(bp);
1402         bnx2x_release_nvram_lock(bp);
1403
1404         return rc;
1405 }
1406
1407 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1408                               int buf_size)
1409 {
1410         int rc;
1411
1412         rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1413
1414         if (!rc) {
1415                 __be32 *be = (__be32 *)buf;
1416
1417                 while ((buf_size -= 4) >= 0)
1418                         *buf++ = be32_to_cpu(*be++);
1419         }
1420
1421         return rc;
1422 }
1423
1424 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1425 {
1426         int rc = 1;
1427         u16 pm = 0;
1428         struct net_device *dev = pci_get_drvdata(bp->pdev);
1429
1430         if (bp->pdev->pm_cap)
1431                 rc = pci_read_config_word(bp->pdev,
1432                                           bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1433
1434         if ((rc && !netif_running(dev)) ||
1435             (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1436                 return false;
1437
1438         return true;
1439 }
1440
1441 static int bnx2x_get_eeprom(struct net_device *dev,
1442                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1443 {
1444         struct bnx2x *bp = netdev_priv(dev);
1445
1446         if (!bnx2x_is_nvm_accessible(bp)) {
1447                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1448                    "cannot access eeprom when the interface is down\n");
1449                 return -EAGAIN;
1450         }
1451
1452         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1453            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1454            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1455            eeprom->len, eeprom->len);
1456
1457         /* parameters already validated in ethtool_get_eeprom */
1458
1459         return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1460 }
1461
1462 static int bnx2x_get_module_eeprom(struct net_device *dev,
1463                                    struct ethtool_eeprom *ee,
1464                                    u8 *data)
1465 {
1466         struct bnx2x *bp = netdev_priv(dev);
1467         int rc = -EINVAL, phy_idx;
1468         u8 *user_data = data;
1469         unsigned int start_addr = ee->offset, xfer_size = 0;
1470
1471         if (!bnx2x_is_nvm_accessible(bp)) {
1472                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1473                    "cannot access eeprom when the interface is down\n");
1474                 return -EAGAIN;
1475         }
1476
1477         phy_idx = bnx2x_get_cur_phy_idx(bp);
1478
1479         /* Read A0 section */
1480         if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1481                 /* Limit transfer size to the A0 section boundary */
1482                 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1483                         xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1484                 else
1485                         xfer_size = ee->len;
1486                 bnx2x_acquire_phy_lock(bp);
1487                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1488                                                   &bp->link_params,
1489                                                   I2C_DEV_ADDR_A0,
1490                                                   start_addr,
1491                                                   xfer_size,
1492                                                   user_data);
1493                 bnx2x_release_phy_lock(bp);
1494                 if (rc) {
1495                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1496
1497                         return -EINVAL;
1498                 }
1499                 user_data += xfer_size;
1500                 start_addr += xfer_size;
1501         }
1502
1503         /* Read A2 section */
1504         if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1505             (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1506                 xfer_size = ee->len - xfer_size;
1507                 /* Limit transfer size to the A2 section boundary */
1508                 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1509                         xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1510                 start_addr -= ETH_MODULE_SFF_8079_LEN;
1511                 bnx2x_acquire_phy_lock(bp);
1512                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1513                                                   &bp->link_params,
1514                                                   I2C_DEV_ADDR_A2,
1515                                                   start_addr,
1516                                                   xfer_size,
1517                                                   user_data);
1518                 bnx2x_release_phy_lock(bp);
1519                 if (rc) {
1520                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1521                         return -EINVAL;
1522                 }
1523         }
1524         return rc;
1525 }
1526
1527 static int bnx2x_get_module_info(struct net_device *dev,
1528                                  struct ethtool_modinfo *modinfo)
1529 {
1530         struct bnx2x *bp = netdev_priv(dev);
1531         int phy_idx, rc;
1532         u8 sff8472_comp, diag_type;
1533
1534         if (!bnx2x_is_nvm_accessible(bp)) {
1535                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1536                    "cannot access eeprom when the interface is down\n");
1537                 return -EAGAIN;
1538         }
1539         phy_idx = bnx2x_get_cur_phy_idx(bp);
1540         bnx2x_acquire_phy_lock(bp);
1541         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1542                                           &bp->link_params,
1543                                           I2C_DEV_ADDR_A0,
1544                                           SFP_EEPROM_SFF_8472_COMP_ADDR,
1545                                           SFP_EEPROM_SFF_8472_COMP_SIZE,
1546                                           &sff8472_comp);
1547         bnx2x_release_phy_lock(bp);
1548         if (rc) {
1549                 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1550                 return -EINVAL;
1551         }
1552
1553         bnx2x_acquire_phy_lock(bp);
1554         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1555                                           &bp->link_params,
1556                                           I2C_DEV_ADDR_A0,
1557                                           SFP_EEPROM_DIAG_TYPE_ADDR,
1558                                           SFP_EEPROM_DIAG_TYPE_SIZE,
1559                                           &diag_type);
1560         bnx2x_release_phy_lock(bp);
1561         if (rc) {
1562                 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1563                 return -EINVAL;
1564         }
1565
1566         if (!sff8472_comp ||
1567             (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ) ||
1568             !(diag_type & SFP_EEPROM_DDM_IMPLEMENTED)) {
1569                 modinfo->type = ETH_MODULE_SFF_8079;
1570                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1571         } else {
1572                 modinfo->type = ETH_MODULE_SFF_8472;
1573                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1574         }
1575         return 0;
1576 }
1577
1578 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1579                                    u32 cmd_flags)
1580 {
1581         int count, i, rc;
1582
1583         /* build the command word */
1584         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1585
1586         /* need to clear DONE bit separately */
1587         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1588
1589         /* write the data */
1590         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1591
1592         /* address of the NVRAM to write to */
1593         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1594                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1595
1596         /* issue the write command */
1597         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1598
1599         /* adjust timeout for emulation/FPGA */
1600         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1601         if (CHIP_REV_IS_SLOW(bp))
1602                 count *= 100;
1603
1604         /* wait for completion */
1605         rc = -EBUSY;
1606         for (i = 0; i < count; i++) {
1607                 udelay(5);
1608                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1609                 if (val & MCPR_NVM_COMMAND_DONE) {
1610                         rc = 0;
1611                         break;
1612                 }
1613         }
1614
1615         if (rc == -EBUSY)
1616                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1617                    "nvram write timeout expired\n");
1618         return rc;
1619 }
1620
1621 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1622
1623 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1624                               int buf_size)
1625 {
1626         int rc;
1627         u32 cmd_flags, align_offset, val;
1628         __be32 val_be;
1629
1630         if (offset + buf_size > bp->common.flash_size) {
1631                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1632                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1633                    offset, buf_size, bp->common.flash_size);
1634                 return -EINVAL;
1635         }
1636
1637         /* request access to nvram interface */
1638         rc = bnx2x_acquire_nvram_lock(bp);
1639         if (rc)
1640                 return rc;
1641
1642         /* enable access to nvram interface */
1643         bnx2x_enable_nvram_access(bp);
1644
1645         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1646         align_offset = (offset & ~0x03);
1647         rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1648
1649         if (rc == 0) {
1650                 /* nvram data is returned as an array of bytes
1651                  * convert it back to cpu order
1652                  */
1653                 val = be32_to_cpu(val_be);
1654
1655                 val &= ~le32_to_cpu((__force __le32)
1656                                     (0xff << BYTE_OFFSET(offset)));
1657                 val |= le32_to_cpu((__force __le32)
1658                                    (*data_buf << BYTE_OFFSET(offset)));
1659
1660                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1661                                              cmd_flags);
1662         }
1663
1664         /* disable access to nvram interface */
1665         bnx2x_disable_nvram_access(bp);
1666         bnx2x_release_nvram_lock(bp);
1667
1668         return rc;
1669 }
1670
1671 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1672                              int buf_size)
1673 {
1674         int rc;
1675         u32 cmd_flags;
1676         u32 val;
1677         u32 written_so_far;
1678
1679         if (buf_size == 1)      /* ethtool */
1680                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1681
1682         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1683                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1684                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1685                    offset, buf_size);
1686                 return -EINVAL;
1687         }
1688
1689         if (offset + buf_size > bp->common.flash_size) {
1690                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1691                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1692                    offset, buf_size, bp->common.flash_size);
1693                 return -EINVAL;
1694         }
1695
1696         /* request access to nvram interface */
1697         rc = bnx2x_acquire_nvram_lock(bp);
1698         if (rc)
1699                 return rc;
1700
1701         /* enable access to nvram interface */
1702         bnx2x_enable_nvram_access(bp);
1703
1704         written_so_far = 0;
1705         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1706         while ((written_so_far < buf_size) && (rc == 0)) {
1707                 if (written_so_far == (buf_size - sizeof(u32)))
1708                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1709                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1710                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1711                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1712                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1713
1714                 memcpy(&val, data_buf, 4);
1715
1716                 /* Notice unlike bnx2x_nvram_read_dword() this will not
1717                  * change val using be32_to_cpu(), which causes data to flip
1718                  * if the eeprom is read and then written back. This is due
1719                  * to tools utilizing this functionality that would break
1720                  * if this would be resolved.
1721                  */
1722                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1723
1724                 /* advance to the next dword */
1725                 offset += sizeof(u32);
1726                 data_buf += sizeof(u32);
1727                 written_so_far += sizeof(u32);
1728
1729                 /* At end of each 4Kb page, release nvram lock to allow MFW
1730                  * chance to take it for its own use.
1731                  */
1732                 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1733                     (written_so_far < buf_size)) {
1734                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1735                            "Releasing NVM lock after offset 0x%x\n",
1736                            (u32)(offset - sizeof(u32)));
1737                         bnx2x_release_nvram_lock(bp);
1738                         usleep_range(1000, 2000);
1739                         rc = bnx2x_acquire_nvram_lock(bp);
1740                         if (rc)
1741                                 return rc;
1742                 }
1743
1744                 cmd_flags = 0;
1745         }
1746
1747         /* disable access to nvram interface */
1748         bnx2x_disable_nvram_access(bp);
1749         bnx2x_release_nvram_lock(bp);
1750
1751         return rc;
1752 }
1753
1754 static int bnx2x_set_eeprom(struct net_device *dev,
1755                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1756 {
1757         struct bnx2x *bp = netdev_priv(dev);
1758         int port = BP_PORT(bp);
1759         int rc = 0;
1760         u32 ext_phy_config;
1761
1762         if (!bnx2x_is_nvm_accessible(bp)) {
1763                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1764                    "cannot access eeprom when the interface is down\n");
1765                 return -EAGAIN;
1766         }
1767
1768         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1769            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1770            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1771            eeprom->len, eeprom->len);
1772
1773         /* parameters already validated in ethtool_set_eeprom */
1774
1775         /* PHY eeprom can be accessed only by the PMF */
1776         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1777             !bp->port.pmf) {
1778                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1779                    "wrong magic or interface is not pmf\n");
1780                 return -EINVAL;
1781         }
1782
1783         ext_phy_config =
1784                 SHMEM_RD(bp,
1785                          dev_info.port_hw_config[port].external_phy_config);
1786
1787         if (eeprom->magic == 0x50485950) {
1788                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1789                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1790
1791                 bnx2x_acquire_phy_lock(bp);
1792                 rc |= bnx2x_link_reset(&bp->link_params,
1793                                        &bp->link_vars, 0);
1794                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1795                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1796                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1797                                        MISC_REGISTERS_GPIO_HIGH, port);
1798                 bnx2x_release_phy_lock(bp);
1799                 bnx2x_link_report(bp);
1800
1801         } else if (eeprom->magic == 0x50485952) {
1802                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1803                 if (bp->state == BNX2X_STATE_OPEN) {
1804                         bnx2x_acquire_phy_lock(bp);
1805                         rc |= bnx2x_link_reset(&bp->link_params,
1806                                                &bp->link_vars, 1);
1807
1808                         rc |= bnx2x_phy_init(&bp->link_params,
1809                                              &bp->link_vars);
1810                         bnx2x_release_phy_lock(bp);
1811                         bnx2x_calc_fc_adv(bp);
1812                 }
1813         } else if (eeprom->magic == 0x53985943) {
1814                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1815                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1816                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1817
1818                         /* DSP Remove Download Mode */
1819                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1820                                        MISC_REGISTERS_GPIO_LOW, port);
1821
1822                         bnx2x_acquire_phy_lock(bp);
1823
1824                         bnx2x_sfx7101_sp_sw_reset(bp,
1825                                                 &bp->link_params.phy[EXT_PHY1]);
1826
1827                         /* wait 0.5 sec to allow it to run */
1828                         msleep(500);
1829                         bnx2x_ext_phy_hw_reset(bp, port);
1830                         msleep(500);
1831                         bnx2x_release_phy_lock(bp);
1832                 }
1833         } else
1834                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1835
1836         return rc;
1837 }
1838
1839 static int bnx2x_get_coalesce(struct net_device *dev,
1840                               struct ethtool_coalesce *coal)
1841 {
1842         struct bnx2x *bp = netdev_priv(dev);
1843
1844         memset(coal, 0, sizeof(struct ethtool_coalesce));
1845
1846         coal->rx_coalesce_usecs = bp->rx_ticks;
1847         coal->tx_coalesce_usecs = bp->tx_ticks;
1848
1849         return 0;
1850 }
1851
1852 static int bnx2x_set_coalesce(struct net_device *dev,
1853                               struct ethtool_coalesce *coal)
1854 {
1855         struct bnx2x *bp = netdev_priv(dev);
1856
1857         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1858         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1859                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1860
1861         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1862         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1863                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1864
1865         if (netif_running(dev))
1866                 bnx2x_update_coalesce(bp);
1867
1868         return 0;
1869 }
1870
1871 static void bnx2x_get_ringparam(struct net_device *dev,
1872                                 struct ethtool_ringparam *ering)
1873 {
1874         struct bnx2x *bp = netdev_priv(dev);
1875
1876         ering->rx_max_pending = MAX_RX_AVAIL;
1877
1878         /* If size isn't already set, we give an estimation of the number
1879          * of buffers we'll have. We're neglecting some possible conditions
1880          * [we couldn't know for certain at this point if number of queues
1881          * might shrink] but the number would be correct for the likely
1882          * scenario.
1883          */
1884         if (bp->rx_ring_size)
1885                 ering->rx_pending = bp->rx_ring_size;
1886         else if (BNX2X_NUM_RX_QUEUES(bp))
1887                 ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp);
1888         else
1889                 ering->rx_pending = MAX_RX_AVAIL;
1890
1891         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1892         ering->tx_pending = bp->tx_ring_size;
1893 }
1894
1895 static int bnx2x_set_ringparam(struct net_device *dev,
1896                                struct ethtool_ringparam *ering)
1897 {
1898         struct bnx2x *bp = netdev_priv(dev);
1899
1900         DP(BNX2X_MSG_ETHTOOL,
1901            "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1902            ering->rx_pending, ering->tx_pending);
1903
1904         if (pci_num_vf(bp->pdev)) {
1905                 DP(BNX2X_MSG_IOV,
1906                    "VFs are enabled, can not change ring parameters\n");
1907                 return -EPERM;
1908         }
1909
1910         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1911                 DP(BNX2X_MSG_ETHTOOL,
1912                    "Handling parity error recovery. Try again later\n");
1913                 return -EAGAIN;
1914         }
1915
1916         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1917             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1918                                                     MIN_RX_SIZE_TPA)) ||
1919             (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1920             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1921                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1922                 return -EINVAL;
1923         }
1924
1925         bp->rx_ring_size = ering->rx_pending;
1926         bp->tx_ring_size = ering->tx_pending;
1927
1928         return bnx2x_reload_if_running(dev);
1929 }
1930
1931 static void bnx2x_get_pauseparam(struct net_device *dev,
1932                                  struct ethtool_pauseparam *epause)
1933 {
1934         struct bnx2x *bp = netdev_priv(dev);
1935         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1936         int cfg_reg;
1937
1938         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1939                            BNX2X_FLOW_CTRL_AUTO);
1940
1941         if (!epause->autoneg)
1942                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1943         else
1944                 cfg_reg = bp->link_params.req_fc_auto_adv;
1945
1946         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1947                             BNX2X_FLOW_CTRL_RX);
1948         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1949                             BNX2X_FLOW_CTRL_TX);
1950
1951         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1952            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1953            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1954 }
1955
1956 static int bnx2x_set_pauseparam(struct net_device *dev,
1957                                 struct ethtool_pauseparam *epause)
1958 {
1959         struct bnx2x *bp = netdev_priv(dev);
1960         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1961         if (IS_MF(bp))
1962                 return 0;
1963
1964         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1965            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1966            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1967
1968         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1969
1970         if (epause->rx_pause)
1971                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1972
1973         if (epause->tx_pause)
1974                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1975
1976         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1977                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1978
1979         if (epause->autoneg) {
1980                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1981                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1982                         return -EINVAL;
1983                 }
1984
1985                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1986                         bp->link_params.req_flow_ctrl[cfg_idx] =
1987                                 BNX2X_FLOW_CTRL_AUTO;
1988                 }
1989                 bp->link_params.req_fc_auto_adv = 0;
1990                 if (epause->rx_pause)
1991                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1992
1993                 if (epause->tx_pause)
1994                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1995
1996                 if (!bp->link_params.req_fc_auto_adv)
1997                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1998         }
1999
2000         DP(BNX2X_MSG_ETHTOOL,
2001            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
2002
2003         if (netif_running(dev)) {
2004                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2005                 bnx2x_force_link_reset(bp);
2006                 bnx2x_link_set(bp);
2007         }
2008
2009         return 0;
2010 }
2011
2012 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
2013         "register_test (offline)    ",
2014         "memory_test (offline)      ",
2015         "int_loopback_test (offline)",
2016         "ext_loopback_test (offline)",
2017         "nvram_test (online)        ",
2018         "interrupt_test (online)    ",
2019         "link_test (online)         "
2020 };
2021
2022 enum {
2023         BNX2X_PRI_FLAG_ISCSI,
2024         BNX2X_PRI_FLAG_FCOE,
2025         BNX2X_PRI_FLAG_STORAGE,
2026         BNX2X_PRI_FLAG_LEN,
2027 };
2028
2029 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2030         "iSCSI offload support",
2031         "FCoE offload support",
2032         "Storage only interface"
2033 };
2034
2035 static u32 bnx2x_eee_to_adv(u32 eee_adv)
2036 {
2037         u32 modes = 0;
2038
2039         if (eee_adv & SHMEM_EEE_100M_ADV)
2040                 modes |= ADVERTISED_100baseT_Full;
2041         if (eee_adv & SHMEM_EEE_1G_ADV)
2042                 modes |= ADVERTISED_1000baseT_Full;
2043         if (eee_adv & SHMEM_EEE_10G_ADV)
2044                 modes |= ADVERTISED_10000baseT_Full;
2045
2046         return modes;
2047 }
2048
2049 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2050 {
2051         u32 eee_adv = 0;
2052         if (modes & ADVERTISED_100baseT_Full)
2053                 eee_adv |= SHMEM_EEE_100M_ADV;
2054         if (modes & ADVERTISED_1000baseT_Full)
2055                 eee_adv |= SHMEM_EEE_1G_ADV;
2056         if (modes & ADVERTISED_10000baseT_Full)
2057                 eee_adv |= SHMEM_EEE_10G_ADV;
2058
2059         return eee_adv << shift;
2060 }
2061
2062 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2063 {
2064         struct bnx2x *bp = netdev_priv(dev);
2065         u32 eee_cfg;
2066
2067         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2068                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2069                 return -EOPNOTSUPP;
2070         }
2071
2072         eee_cfg = bp->link_vars.eee_status;
2073
2074         edata->supported =
2075                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2076                                  SHMEM_EEE_SUPPORTED_SHIFT);
2077
2078         edata->advertised =
2079                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2080                                  SHMEM_EEE_ADV_STATUS_SHIFT);
2081         edata->lp_advertised =
2082                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2083                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2084
2085         /* SHMEM value is in 16u units --> Convert to 1u units. */
2086         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2087
2088         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
2089         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
2090         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2091
2092         return 0;
2093 }
2094
2095 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2096 {
2097         struct bnx2x *bp = netdev_priv(dev);
2098         u32 eee_cfg;
2099         u32 advertised;
2100
2101         if (IS_MF(bp))
2102                 return 0;
2103
2104         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2105                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2106                 return -EOPNOTSUPP;
2107         }
2108
2109         eee_cfg = bp->link_vars.eee_status;
2110
2111         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2112                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2113                 return -EOPNOTSUPP;
2114         }
2115
2116         advertised = bnx2x_adv_to_eee(edata->advertised,
2117                                       SHMEM_EEE_ADV_STATUS_SHIFT);
2118         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2119                 DP(BNX2X_MSG_ETHTOOL,
2120                    "Direct manipulation of EEE advertisement is not supported\n");
2121                 return -EINVAL;
2122         }
2123
2124         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2125                 DP(BNX2X_MSG_ETHTOOL,
2126                    "Maximal Tx Lpi timer supported is %x(u)\n",
2127                    EEE_MODE_TIMER_MASK);
2128                 return -EINVAL;
2129         }
2130         if (edata->tx_lpi_enabled &&
2131             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2132                 DP(BNX2X_MSG_ETHTOOL,
2133                    "Minimal Tx Lpi timer supported is %d(u)\n",
2134                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2135                 return -EINVAL;
2136         }
2137
2138         /* All is well; Apply changes*/
2139         if (edata->eee_enabled)
2140                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2141         else
2142                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2143
2144         if (edata->tx_lpi_enabled)
2145                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2146         else
2147                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2148
2149         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2150         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2151                                     EEE_MODE_TIMER_MASK) |
2152                                     EEE_MODE_OVERRIDE_NVRAM |
2153                                     EEE_MODE_OUTPUT_TIME;
2154
2155         /* Restart link to propagate changes */
2156         if (netif_running(dev)) {
2157                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2158                 bnx2x_force_link_reset(bp);
2159                 bnx2x_link_set(bp);
2160         }
2161
2162         return 0;
2163 }
2164
2165 enum {
2166         BNX2X_CHIP_E1_OFST = 0,
2167         BNX2X_CHIP_E1H_OFST,
2168         BNX2X_CHIP_E2_OFST,
2169         BNX2X_CHIP_E3_OFST,
2170         BNX2X_CHIP_E3B0_OFST,
2171         BNX2X_CHIP_MAX_OFST
2172 };
2173
2174 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
2175 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
2176 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
2177 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
2178 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
2179
2180 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2181 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2182
2183 static int bnx2x_test_registers(struct bnx2x *bp)
2184 {
2185         int idx, i, rc = -ENODEV;
2186         u32 wr_val = 0, hw;
2187         int port = BP_PORT(bp);
2188         static const struct {
2189                 u32 hw;
2190                 u32 offset0;
2191                 u32 offset1;
2192                 u32 mask;
2193         } reg_tbl[] = {
2194 /* 0 */         { BNX2X_CHIP_MASK_ALL,
2195                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2196                 { BNX2X_CHIP_MASK_ALL,
2197                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
2198                 { BNX2X_CHIP_MASK_E1X,
2199                         HC_REG_AGG_INT_0,               4, 0x000003ff },
2200                 { BNX2X_CHIP_MASK_ALL,
2201                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
2202                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2203                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
2204                 { BNX2X_CHIP_MASK_E3B0,
2205                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
2206                 { BNX2X_CHIP_MASK_ALL,
2207                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
2208                 { BNX2X_CHIP_MASK_ALL,
2209                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
2210                 { BNX2X_CHIP_MASK_ALL,
2211                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2212                 { BNX2X_CHIP_MASK_ALL,
2213                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
2214 /* 10 */        { BNX2X_CHIP_MASK_ALL,
2215                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2216                 { BNX2X_CHIP_MASK_ALL,
2217                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
2218                 { BNX2X_CHIP_MASK_ALL,
2219                         QM_REG_CONNNUM_0,               4, 0x000fffff },
2220                 { BNX2X_CHIP_MASK_ALL,
2221                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
2222                 { BNX2X_CHIP_MASK_ALL,
2223                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
2224                 { BNX2X_CHIP_MASK_ALL,
2225                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
2226                 { BNX2X_CHIP_MASK_ALL,
2227                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2228                 { BNX2X_CHIP_MASK_ALL,
2229                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
2230                 { BNX2X_CHIP_MASK_ALL,
2231                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
2232                 { BNX2X_CHIP_MASK_ALL,
2233                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
2234 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2235                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
2236                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2237                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
2238                 { BNX2X_CHIP_MASK_ALL,
2239                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
2240                 { BNX2X_CHIP_MASK_ALL,
2241                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
2242                 { BNX2X_CHIP_MASK_ALL,
2243                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
2244                 { BNX2X_CHIP_MASK_ALL,
2245                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
2246                 { BNX2X_CHIP_MASK_ALL,
2247                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
2248                 { BNX2X_CHIP_MASK_ALL,
2249                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
2250                 { BNX2X_CHIP_MASK_ALL,
2251                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
2252                 { BNX2X_CHIP_MASK_ALL,
2253                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
2254 /* 30 */        { BNX2X_CHIP_MASK_ALL,
2255                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
2256                 { BNX2X_CHIP_MASK_ALL,
2257                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
2258                 { BNX2X_CHIP_MASK_ALL,
2259                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2260                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2261                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
2262                 { BNX2X_CHIP_MASK_ALL,
2263                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2264                 { BNX2X_CHIP_MASK_ALL,
2265                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2266                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2267                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2268                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2269                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
2270
2271                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2272         };
2273
2274         if (!bnx2x_is_nvm_accessible(bp)) {
2275                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2276                    "cannot access eeprom when the interface is down\n");
2277                 return rc;
2278         }
2279
2280         if (CHIP_IS_E1(bp))
2281                 hw = BNX2X_CHIP_MASK_E1;
2282         else if (CHIP_IS_E1H(bp))
2283                 hw = BNX2X_CHIP_MASK_E1H;
2284         else if (CHIP_IS_E2(bp))
2285                 hw = BNX2X_CHIP_MASK_E2;
2286         else if (CHIP_IS_E3B0(bp))
2287                 hw = BNX2X_CHIP_MASK_E3B0;
2288         else /* e3 A0 */
2289                 hw = BNX2X_CHIP_MASK_E3;
2290
2291         /* Repeat the test twice:
2292          * First by writing 0x00000000, second by writing 0xffffffff
2293          */
2294         for (idx = 0; idx < 2; idx++) {
2295
2296                 switch (idx) {
2297                 case 0:
2298                         wr_val = 0;
2299                         break;
2300                 case 1:
2301                         wr_val = 0xffffffff;
2302                         break;
2303                 }
2304
2305                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2306                         u32 offset, mask, save_val, val;
2307                         if (!(hw & reg_tbl[i].hw))
2308                                 continue;
2309
2310                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2311                         mask = reg_tbl[i].mask;
2312
2313                         save_val = REG_RD(bp, offset);
2314
2315                         REG_WR(bp, offset, wr_val & mask);
2316
2317                         val = REG_RD(bp, offset);
2318
2319                         /* Restore the original register's value */
2320                         REG_WR(bp, offset, save_val);
2321
2322                         /* verify value is as expected */
2323                         if ((val & mask) != (wr_val & mask)) {
2324                                 DP(BNX2X_MSG_ETHTOOL,
2325                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2326                                    offset, val, wr_val, mask);
2327                                 goto test_reg_exit;
2328                         }
2329                 }
2330         }
2331
2332         rc = 0;
2333
2334 test_reg_exit:
2335         return rc;
2336 }
2337
2338 static int bnx2x_test_memory(struct bnx2x *bp)
2339 {
2340         int i, j, rc = -ENODEV;
2341         u32 val, index;
2342         static const struct {
2343                 u32 offset;
2344                 int size;
2345         } mem_tbl[] = {
2346                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2347                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2348                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2349                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2350                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2351                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2352                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2353
2354                 { 0xffffffff, 0 }
2355         };
2356
2357         static const struct {
2358                 char *name;
2359                 u32 offset;
2360                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2361         } prty_tbl[] = {
2362                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2363                         {0x3ffc0, 0,   0, 0} },
2364                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2365                         {0x2,     0x2, 0, 0} },
2366                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2367                         {0,       0,   0, 0} },
2368                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2369                         {0x3ffc0, 0,   0, 0} },
2370                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2371                         {0x3ffc0, 0,   0, 0} },
2372                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2373                         {0x3ffc1, 0,   0, 0} },
2374
2375                 { NULL, 0xffffffff, {0, 0, 0, 0} }
2376         };
2377
2378         if (!bnx2x_is_nvm_accessible(bp)) {
2379                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2380                    "cannot access eeprom when the interface is down\n");
2381                 return rc;
2382         }
2383
2384         if (CHIP_IS_E1(bp))
2385                 index = BNX2X_CHIP_E1_OFST;
2386         else if (CHIP_IS_E1H(bp))
2387                 index = BNX2X_CHIP_E1H_OFST;
2388         else if (CHIP_IS_E2(bp))
2389                 index = BNX2X_CHIP_E2_OFST;
2390         else /* e3 */
2391                 index = BNX2X_CHIP_E3_OFST;
2392
2393         /* pre-Check the parity status */
2394         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2395                 val = REG_RD(bp, prty_tbl[i].offset);
2396                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2397                         DP(BNX2X_MSG_ETHTOOL,
2398                            "%s is 0x%x\n", prty_tbl[i].name, val);
2399                         goto test_mem_exit;
2400                 }
2401         }
2402
2403         /* Go through all the memories */
2404         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2405                 for (j = 0; j < mem_tbl[i].size; j++)
2406                         REG_RD(bp, mem_tbl[i].offset + j*4);
2407
2408         /* Check the parity status */
2409         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2410                 val = REG_RD(bp, prty_tbl[i].offset);
2411                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2412                         DP(BNX2X_MSG_ETHTOOL,
2413                            "%s is 0x%x\n", prty_tbl[i].name, val);
2414                         goto test_mem_exit;
2415                 }
2416         }
2417
2418         rc = 0;
2419
2420 test_mem_exit:
2421         return rc;
2422 }
2423
2424 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2425 {
2426         int cnt = 1400;
2427
2428         if (link_up) {
2429                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2430                         msleep(20);
2431
2432                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2433                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2434
2435                 cnt = 1400;
2436                 while (!bp->link_vars.link_up && cnt--)
2437                         msleep(20);
2438
2439                 if (cnt <= 0 && !bp->link_vars.link_up)
2440                         DP(BNX2X_MSG_ETHTOOL,
2441                            "Timeout waiting for link init\n");
2442         }
2443 }
2444
2445 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2446 {
2447         unsigned int pkt_size, num_pkts, i;
2448         struct sk_buff *skb;
2449         unsigned char *packet;
2450         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2451         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2452         struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2453         u16 tx_start_idx, tx_idx;
2454         u16 rx_start_idx, rx_idx;
2455         u16 pkt_prod, bd_prod;
2456         struct sw_tx_bd *tx_buf;
2457         struct eth_tx_start_bd *tx_start_bd;
2458         dma_addr_t mapping;
2459         union eth_rx_cqe *cqe;
2460         u8 cqe_fp_flags, cqe_fp_type;
2461         struct sw_rx_bd *rx_buf;
2462         u16 len;
2463         int rc = -ENODEV;
2464         u8 *data;
2465         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2466                                                        txdata->txq_index);
2467
2468         /* check the loopback mode */
2469         switch (loopback_mode) {
2470         case BNX2X_PHY_LOOPBACK:
2471                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2472                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2473                         return -EINVAL;
2474                 }
2475                 break;
2476         case BNX2X_MAC_LOOPBACK:
2477                 if (CHIP_IS_E3(bp)) {
2478                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2479                         if (bp->port.supported[cfg_idx] &
2480                             (SUPPORTED_10000baseT_Full |
2481                              SUPPORTED_20000baseMLD2_Full |
2482                              SUPPORTED_20000baseKR2_Full))
2483                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2484                         else
2485                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2486                 } else
2487                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2488
2489                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2490                 break;
2491         case BNX2X_EXT_LOOPBACK:
2492                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2493                         DP(BNX2X_MSG_ETHTOOL,
2494                            "Can't configure external loopback\n");
2495                         return -EINVAL;
2496                 }
2497                 break;
2498         default:
2499                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2500                 return -EINVAL;
2501         }
2502
2503         /* prepare the loopback packet */
2504         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2505                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2506         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2507         if (!skb) {
2508                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2509                 rc = -ENOMEM;
2510                 goto test_loopback_exit;
2511         }
2512         packet = skb_put(skb, pkt_size);
2513         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2514         eth_zero_addr(packet + ETH_ALEN);
2515         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2516         for (i = ETH_HLEN; i < pkt_size; i++)
2517                 packet[i] = (unsigned char) (i & 0xff);
2518         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2519                                  skb_headlen(skb), DMA_TO_DEVICE);
2520         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2521                 rc = -ENOMEM;
2522                 dev_kfree_skb(skb);
2523                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2524                 goto test_loopback_exit;
2525         }
2526
2527         /* send the loopback packet */
2528         num_pkts = 0;
2529         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2530         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2531
2532         netdev_tx_sent_queue(txq, skb->len);
2533
2534         pkt_prod = txdata->tx_pkt_prod++;
2535         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2536         tx_buf->first_bd = txdata->tx_bd_prod;
2537         tx_buf->skb = skb;
2538         tx_buf->flags = 0;
2539
2540         bd_prod = TX_BD(txdata->tx_bd_prod);
2541         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2542         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2543         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2544         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2545         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2546         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2547         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2548         SET_FLAG(tx_start_bd->general_data,
2549                  ETH_TX_START_BD_HDR_NBDS,
2550                  1);
2551         SET_FLAG(tx_start_bd->general_data,
2552                  ETH_TX_START_BD_PARSE_NBDS,
2553                  0);
2554
2555         /* turn on parsing and get a BD */
2556         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2557
2558         if (CHIP_IS_E1x(bp)) {
2559                 u16 global_data = 0;
2560                 struct eth_tx_parse_bd_e1x  *pbd_e1x =
2561                         &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2562                 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2563                 SET_FLAG(global_data,
2564                          ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2565                 pbd_e1x->global_data = cpu_to_le16(global_data);
2566         } else {
2567                 u32 parsing_data = 0;
2568                 struct eth_tx_parse_bd_e2  *pbd_e2 =
2569                         &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2570                 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2571                 SET_FLAG(parsing_data,
2572                          ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2573                 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2574         }
2575         wmb();
2576
2577         txdata->tx_db.data.prod += 2;
2578         barrier();
2579         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2580
2581         mmiowb();
2582         barrier();
2583
2584         num_pkts++;
2585         txdata->tx_bd_prod += 2; /* start + pbd */
2586
2587         udelay(100);
2588
2589         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2590         if (tx_idx != tx_start_idx + num_pkts)
2591                 goto test_loopback_exit;
2592
2593         /* Unlike HC IGU won't generate an interrupt for status block
2594          * updates that have been performed while interrupts were
2595          * disabled.
2596          */
2597         if (bp->common.int_block == INT_BLOCK_IGU) {
2598                 /* Disable local BHes to prevent a dead-lock situation between
2599                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2600                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2601                  */
2602                 local_bh_disable();
2603                 bnx2x_tx_int(bp, txdata);
2604                 local_bh_enable();
2605         }
2606
2607         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2608         if (rx_idx != rx_start_idx + num_pkts)
2609                 goto test_loopback_exit;
2610
2611         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2612         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2613         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2614         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2615                 goto test_loopback_rx_exit;
2616
2617         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2618         if (len != pkt_size)
2619                 goto test_loopback_rx_exit;
2620
2621         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2622         dma_sync_single_for_cpu(&bp->pdev->dev,
2623                                    dma_unmap_addr(rx_buf, mapping),
2624                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2625         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2626         for (i = ETH_HLEN; i < pkt_size; i++)
2627                 if (*(data + i) != (unsigned char) (i & 0xff))
2628                         goto test_loopback_rx_exit;
2629
2630         rc = 0;
2631
2632 test_loopback_rx_exit:
2633
2634         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2635         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2636         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2637         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2638
2639         /* Update producers */
2640         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2641                              fp_rx->rx_sge_prod);
2642
2643 test_loopback_exit:
2644         bp->link_params.loopback_mode = LOOPBACK_NONE;
2645
2646         return rc;
2647 }
2648
2649 static int bnx2x_test_loopback(struct bnx2x *bp)
2650 {
2651         int rc = 0, res;
2652
2653         if (BP_NOMCP(bp))
2654                 return rc;
2655
2656         if (!netif_running(bp->dev))
2657                 return BNX2X_LOOPBACK_FAILED;
2658
2659         bnx2x_netif_stop(bp, 1);
2660         bnx2x_acquire_phy_lock(bp);
2661
2662         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2663         if (res) {
2664                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2665                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2666         }
2667
2668         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2669         if (res) {
2670                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2671                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2672         }
2673
2674         bnx2x_release_phy_lock(bp);
2675         bnx2x_netif_start(bp);
2676
2677         return rc;
2678 }
2679
2680 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2681 {
2682         int rc;
2683         u8 is_serdes =
2684                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2685
2686         if (BP_NOMCP(bp))
2687                 return -ENODEV;
2688
2689         if (!netif_running(bp->dev))
2690                 return BNX2X_EXT_LOOPBACK_FAILED;
2691
2692         bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2693         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2694         if (rc) {
2695                 DP(BNX2X_MSG_ETHTOOL,
2696                    "Can't perform self-test, nic_load (for external lb) failed\n");
2697                 return -ENODEV;
2698         }
2699         bnx2x_wait_for_link(bp, 1, is_serdes);
2700
2701         bnx2x_netif_stop(bp, 1);
2702
2703         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2704         if (rc)
2705                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2706
2707         bnx2x_netif_start(bp);
2708
2709         return rc;
2710 }
2711
2712 struct code_entry {
2713         u32 sram_start_addr;
2714         u32 code_attribute;
2715 #define CODE_IMAGE_TYPE_MASK                    0xf0800003
2716 #define CODE_IMAGE_VNTAG_PROFILES_DATA          0xd0000003
2717 #define CODE_IMAGE_LENGTH_MASK                  0x007ffffc
2718 #define CODE_IMAGE_TYPE_EXTENDED_DIR            0xe0000000
2719         u32 nvm_start_addr;
2720 };
2721
2722 #define CODE_ENTRY_MAX                  16
2723 #define CODE_ENTRY_EXTENDED_DIR_IDX     15
2724 #define MAX_IMAGES_IN_EXTENDED_DIR      64
2725 #define NVRAM_DIR_OFFSET                0x14
2726
2727 #define EXTENDED_DIR_EXISTS(code)                                         \
2728         ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2729          (code & CODE_IMAGE_LENGTH_MASK) != 0)
2730
2731 #define CRC32_RESIDUAL                  0xdebb20e3
2732 #define CRC_BUFF_SIZE                   256
2733
2734 static int bnx2x_nvram_crc(struct bnx2x *bp,
2735                            int offset,
2736                            int size,
2737                            u8 *buff)
2738 {
2739         u32 crc = ~0;
2740         int rc = 0, done = 0;
2741
2742         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2743            "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2744
2745         while (done < size) {
2746                 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2747
2748                 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2749
2750                 if (rc)
2751                         return rc;
2752
2753                 crc = crc32_le(crc, buff, count);
2754                 done += count;
2755         }
2756
2757         if (crc != CRC32_RESIDUAL)
2758                 rc = -EINVAL;
2759
2760         return rc;
2761 }
2762
2763 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2764                                 struct code_entry *entry,
2765                                 u8 *buff)
2766 {
2767         size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2768         u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2769         int rc;
2770
2771         /* Zero-length images and AFEX profiles do not have CRC */
2772         if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2773                 return 0;
2774
2775         rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2776         if (rc)
2777                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2778                    "image %x has failed crc test (rc %d)\n", type, rc);
2779
2780         return rc;
2781 }
2782
2783 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2784 {
2785         int rc;
2786         struct code_entry entry;
2787
2788         rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2789         if (rc)
2790                 return rc;
2791
2792         return bnx2x_test_nvram_dir(bp, &entry, buff);
2793 }
2794
2795 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2796 {
2797         u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2798         struct code_entry entry;
2799         int i;
2800
2801         rc = bnx2x_nvram_read32(bp,
2802                                 dir_offset +
2803                                 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2804                                 (u32 *)&entry, sizeof(entry));
2805         if (rc)
2806                 return rc;
2807
2808         if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2809                 return 0;
2810
2811         rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2812                                 &cnt, sizeof(u32));
2813         if (rc)
2814                 return rc;
2815
2816         dir_offset = entry.nvm_start_addr + 8;
2817
2818         for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2819                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2820                                               sizeof(struct code_entry) * i,
2821                                           buff);
2822                 if (rc)
2823                         return rc;
2824         }
2825
2826         return 0;
2827 }
2828
2829 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2830 {
2831         u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2832         int i;
2833
2834         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2835
2836         for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2837                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2838                                               sizeof(struct code_entry) * i,
2839                                           buff);
2840                 if (rc)
2841                         return rc;
2842         }
2843
2844         return bnx2x_test_nvram_ext_dirs(bp, buff);
2845 }
2846
2847 struct crc_pair {
2848         int offset;
2849         int size;
2850 };
2851
2852 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2853                                 const struct crc_pair *nvram_tbl, u8 *buf)
2854 {
2855         int i;
2856
2857         for (i = 0; nvram_tbl[i].size; i++) {
2858                 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2859                                          nvram_tbl[i].size, buf);
2860                 if (rc) {
2861                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2862                            "nvram_tbl[%d] has failed crc test (rc %d)\n",
2863                            i, rc);
2864                         return rc;
2865                 }
2866         }
2867
2868         return 0;
2869 }
2870
2871 static int bnx2x_test_nvram(struct bnx2x *bp)
2872 {
2873         const struct crc_pair nvram_tbl[] = {
2874                 {     0,  0x14 }, /* bootstrap */
2875                 {  0x14,  0xec }, /* dir */
2876                 { 0x100, 0x350 }, /* manuf_info */
2877                 { 0x450,  0xf0 }, /* feature_info */
2878                 { 0x640,  0x64 }, /* upgrade_key_info */
2879                 { 0x708,  0x70 }, /* manuf_key_info */
2880                 {     0,     0 }
2881         };
2882         const struct crc_pair nvram_tbl2[] = {
2883                 { 0x7e8, 0x350 }, /* manuf_info2 */
2884                 { 0xb38,  0xf0 }, /* feature_info */
2885                 {     0,     0 }
2886         };
2887
2888         u8 *buf;
2889         int rc;
2890         u32 magic;
2891
2892         if (BP_NOMCP(bp))
2893                 return 0;
2894
2895         buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2896         if (!buf) {
2897                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2898                 rc = -ENOMEM;
2899                 goto test_nvram_exit;
2900         }
2901
2902         rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2903         if (rc) {
2904                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2905                    "magic value read (rc %d)\n", rc);
2906                 goto test_nvram_exit;
2907         }
2908
2909         if (magic != 0x669955aa) {
2910                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2911                    "wrong magic value (0x%08x)\n", magic);
2912                 rc = -ENODEV;
2913                 goto test_nvram_exit;
2914         }
2915
2916         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2917         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2918         if (rc)
2919                 goto test_nvram_exit;
2920
2921         if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2922                 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2923                            SHARED_HW_CFG_HIDE_PORT1;
2924
2925                 if (!hide) {
2926                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2927                            "Port 1 CRC test-set\n");
2928                         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2929                         if (rc)
2930                                 goto test_nvram_exit;
2931                 }
2932         }
2933
2934         rc = bnx2x_test_nvram_dirs(bp, buf);
2935
2936 test_nvram_exit:
2937         kfree(buf);
2938         return rc;
2939 }
2940
2941 /* Send an EMPTY ramrod on the first queue */
2942 static int bnx2x_test_intr(struct bnx2x *bp)
2943 {
2944         struct bnx2x_queue_state_params params = {NULL};
2945
2946         if (!netif_running(bp->dev)) {
2947                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2948                    "cannot access eeprom when the interface is down\n");
2949                 return -ENODEV;
2950         }
2951
2952         params.q_obj = &bp->sp_objs->q_obj;
2953         params.cmd = BNX2X_Q_CMD_EMPTY;
2954
2955         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2956
2957         return bnx2x_queue_state_change(bp, &params);
2958 }
2959
2960 static void bnx2x_self_test(struct net_device *dev,
2961                             struct ethtool_test *etest, u64 *buf)
2962 {
2963         struct bnx2x *bp = netdev_priv(dev);
2964         u8 is_serdes, link_up;
2965         int rc, cnt = 0;
2966
2967         if (pci_num_vf(bp->pdev)) {
2968                 DP(BNX2X_MSG_IOV,
2969                    "VFs are enabled, can not perform self test\n");
2970                 return;
2971         }
2972
2973         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2974                 netdev_err(bp->dev,
2975                            "Handling parity error recovery. Try again later\n");
2976                 etest->flags |= ETH_TEST_FL_FAILED;
2977                 return;
2978         }
2979
2980         DP(BNX2X_MSG_ETHTOOL,
2981            "Self-test command parameters: offline = %d, external_lb = %d\n",
2982            (etest->flags & ETH_TEST_FL_OFFLINE),
2983            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2984
2985         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2986
2987         if (bnx2x_test_nvram(bp) != 0) {
2988                 if (!IS_MF(bp))
2989                         buf[4] = 1;
2990                 else
2991                         buf[0] = 1;
2992                 etest->flags |= ETH_TEST_FL_FAILED;
2993         }
2994
2995         if (!netif_running(dev)) {
2996                 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2997                 return;
2998         }
2999
3000         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
3001         link_up = bp->link_vars.link_up;
3002         /* offline tests are not supported in MF mode */
3003         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
3004                 int port = BP_PORT(bp);
3005                 u32 val;
3006
3007                 /* save current value of input enable for TX port IF */
3008                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
3009                 /* disable input for TX port IF */
3010                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
3011
3012                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3013                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
3014                 if (rc) {
3015                         etest->flags |= ETH_TEST_FL_FAILED;
3016                         DP(BNX2X_MSG_ETHTOOL,
3017                            "Can't perform self-test, nic_load (for offline) failed\n");
3018                         return;
3019                 }
3020
3021                 /* wait until link state is restored */
3022                 bnx2x_wait_for_link(bp, 1, is_serdes);
3023
3024                 if (bnx2x_test_registers(bp) != 0) {
3025                         buf[0] = 1;
3026                         etest->flags |= ETH_TEST_FL_FAILED;
3027                 }
3028                 if (bnx2x_test_memory(bp) != 0) {
3029                         buf[1] = 1;
3030                         etest->flags |= ETH_TEST_FL_FAILED;
3031                 }
3032
3033                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
3034                 if (buf[2] != 0)
3035                         etest->flags |= ETH_TEST_FL_FAILED;
3036
3037                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3038                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3039                         if (buf[3] != 0)
3040                                 etest->flags |= ETH_TEST_FL_FAILED;
3041                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3042                 }
3043
3044                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3045
3046                 /* restore input for TX port IF */
3047                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3048                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3049                 if (rc) {
3050                         etest->flags |= ETH_TEST_FL_FAILED;
3051                         DP(BNX2X_MSG_ETHTOOL,
3052                            "Can't perform self-test, nic_load (for online) failed\n");
3053                         return;
3054                 }
3055                 /* wait until link state is restored */
3056                 bnx2x_wait_for_link(bp, link_up, is_serdes);
3057         }
3058
3059         if (bnx2x_test_intr(bp) != 0) {
3060                 if (!IS_MF(bp))
3061                         buf[5] = 1;
3062                 else
3063                         buf[1] = 1;
3064                 etest->flags |= ETH_TEST_FL_FAILED;
3065         }
3066
3067         if (link_up) {
3068                 cnt = 100;
3069                 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3070                         msleep(20);
3071         }
3072
3073         if (!cnt) {
3074                 if (!IS_MF(bp))
3075                         buf[6] = 1;
3076                 else
3077                         buf[2] = 1;
3078                 etest->flags |= ETH_TEST_FL_FAILED;
3079         }
3080 }
3081
3082 #define IS_PORT_STAT(i)         (bnx2x_stats_arr[i].is_port_stat)
3083 #define HIDE_PORT_STAT(bp)      IS_VF(bp)
3084
3085 /* ethtool statistics are displayed for all regular ethernet queues and the
3086  * fcoe L2 queue if not disabled
3087  */
3088 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3089 {
3090         return BNX2X_NUM_ETH_QUEUES(bp);
3091 }
3092
3093 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3094 {
3095         struct bnx2x *bp = netdev_priv(dev);
3096         int i, num_strings = 0;
3097
3098         switch (stringset) {
3099         case ETH_SS_STATS:
3100                 if (is_multi(bp)) {
3101                         num_strings = bnx2x_num_stat_queues(bp) *
3102                                       BNX2X_NUM_Q_STATS;
3103                 } else
3104                         num_strings = 0;
3105                 if (HIDE_PORT_STAT(bp)) {
3106                         for (i = 0; i < BNX2X_NUM_STATS; i++)
3107                                 if (!IS_PORT_STAT(i))
3108                                         num_strings++;
3109                 } else
3110                         num_strings += BNX2X_NUM_STATS;
3111
3112                 return num_strings;
3113
3114         case ETH_SS_TEST:
3115                 return BNX2X_NUM_TESTS(bp);
3116
3117         case ETH_SS_PRIV_FLAGS:
3118                 return BNX2X_PRI_FLAG_LEN;
3119
3120         default:
3121                 return -EINVAL;
3122         }
3123 }
3124
3125 static u32 bnx2x_get_private_flags(struct net_device *dev)
3126 {
3127         struct bnx2x *bp = netdev_priv(dev);
3128         u32 flags = 0;
3129
3130         flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3131         flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3132         flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3133
3134         return flags;
3135 }
3136
3137 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3138 {
3139         struct bnx2x *bp = netdev_priv(dev);
3140         int i, j, k, start;
3141         char queue_name[MAX_QUEUE_NAME_LEN+1];
3142
3143         switch (stringset) {
3144         case ETH_SS_STATS:
3145                 k = 0;
3146                 if (is_multi(bp)) {
3147                         for_each_eth_queue(bp, i) {
3148                                 memset(queue_name, 0, sizeof(queue_name));
3149                                 sprintf(queue_name, "%d", i);
3150                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3151                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3152                                                 ETH_GSTRING_LEN,
3153                                                 bnx2x_q_stats_arr[j].string,
3154                                                 queue_name);
3155                                 k += BNX2X_NUM_Q_STATS;
3156                         }
3157                 }
3158
3159                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3160                         if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3161                                 continue;
3162                         strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3163                                    bnx2x_stats_arr[i].string);
3164                         j++;
3165                 }
3166
3167                 break;
3168
3169         case ETH_SS_TEST:
3170                 /* First 4 tests cannot be done in MF mode */
3171                 if (!IS_MF(bp))
3172                         start = 0;
3173                 else
3174                         start = 4;
3175                 memcpy(buf, bnx2x_tests_str_arr + start,
3176                        ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3177                 break;
3178
3179         case ETH_SS_PRIV_FLAGS:
3180                 memcpy(buf, bnx2x_private_arr,
3181                        ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3182                 break;
3183         }
3184 }
3185
3186 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3187                                     struct ethtool_stats *stats, u64 *buf)
3188 {
3189         struct bnx2x *bp = netdev_priv(dev);
3190         u32 *hw_stats, *offset;
3191         int i, j, k = 0;
3192
3193         if (is_multi(bp)) {
3194                 for_each_eth_queue(bp, i) {
3195                         hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3196                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3197                                 if (bnx2x_q_stats_arr[j].size == 0) {
3198                                         /* skip this counter */
3199                                         buf[k + j] = 0;
3200                                         continue;
3201                                 }
3202                                 offset = (hw_stats +
3203                                           bnx2x_q_stats_arr[j].offset);
3204                                 if (bnx2x_q_stats_arr[j].size == 4) {
3205                                         /* 4-byte counter */
3206                                         buf[k + j] = (u64) *offset;
3207                                         continue;
3208                                 }
3209                                 /* 8-byte counter */
3210                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3211                         }
3212                         k += BNX2X_NUM_Q_STATS;
3213                 }
3214         }
3215
3216         hw_stats = (u32 *)&bp->eth_stats;
3217         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3218                 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3219                         continue;
3220                 if (bnx2x_stats_arr[i].size == 0) {
3221                         /* skip this counter */
3222                         buf[k + j] = 0;
3223                         j++;
3224                         continue;
3225                 }
3226                 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3227                 if (bnx2x_stats_arr[i].size == 4) {
3228                         /* 4-byte counter */
3229                         buf[k + j] = (u64) *offset;
3230                         j++;
3231                         continue;
3232                 }
3233                 /* 8-byte counter */
3234                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3235                 j++;
3236         }
3237 }
3238
3239 static int bnx2x_set_phys_id(struct net_device *dev,
3240                              enum ethtool_phys_id_state state)
3241 {
3242         struct bnx2x *bp = netdev_priv(dev);
3243
3244         if (!bnx2x_is_nvm_accessible(bp)) {
3245                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3246                    "cannot access eeprom when the interface is down\n");
3247                 return -EAGAIN;
3248         }
3249
3250         switch (state) {
3251         case ETHTOOL_ID_ACTIVE:
3252                 return 1;       /* cycle on/off once per second */
3253
3254         case ETHTOOL_ID_ON:
3255                 bnx2x_acquire_phy_lock(bp);
3256                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3257                               LED_MODE_ON, SPEED_1000);
3258                 bnx2x_release_phy_lock(bp);
3259                 break;
3260
3261         case ETHTOOL_ID_OFF:
3262                 bnx2x_acquire_phy_lock(bp);
3263                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3264                               LED_MODE_FRONT_PANEL_OFF, 0);
3265                 bnx2x_release_phy_lock(bp);
3266                 break;
3267
3268         case ETHTOOL_ID_INACTIVE:
3269                 bnx2x_acquire_phy_lock(bp);
3270                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3271                               LED_MODE_OPER,
3272                               bp->link_vars.line_speed);
3273                 bnx2x_release_phy_lock(bp);
3274         }
3275
3276         return 0;
3277 }
3278
3279 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3280 {
3281         switch (info->flow_type) {
3282         case TCP_V4_FLOW:
3283         case TCP_V6_FLOW:
3284                 info->data = RXH_IP_SRC | RXH_IP_DST |
3285                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3286                 break;
3287         case UDP_V4_FLOW:
3288                 if (bp->rss_conf_obj.udp_rss_v4)
3289                         info->data = RXH_IP_SRC | RXH_IP_DST |
3290                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3291                 else
3292                         info->data = RXH_IP_SRC | RXH_IP_DST;
3293                 break;
3294         case UDP_V6_FLOW:
3295                 if (bp->rss_conf_obj.udp_rss_v6)
3296                         info->data = RXH_IP_SRC | RXH_IP_DST |
3297                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3298                 else
3299                         info->data = RXH_IP_SRC | RXH_IP_DST;
3300                 break;
3301         case IPV4_FLOW:
3302         case IPV6_FLOW:
3303                 info->data = RXH_IP_SRC | RXH_IP_DST;
3304                 break;
3305         default:
3306                 info->data = 0;
3307                 break;
3308         }
3309
3310         return 0;
3311 }
3312
3313 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3314                            u32 *rules __always_unused)
3315 {
3316         struct bnx2x *bp = netdev_priv(dev);
3317
3318         switch (info->cmd) {
3319         case ETHTOOL_GRXRINGS:
3320                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3321                 return 0;
3322         case ETHTOOL_GRXFH:
3323                 return bnx2x_get_rss_flags(bp, info);
3324         default:
3325                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3326                 return -EOPNOTSUPP;
3327         }
3328 }
3329
3330 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3331 {
3332         int udp_rss_requested;
3333
3334         DP(BNX2X_MSG_ETHTOOL,
3335            "Set rss flags command parameters: flow type = %d, data = %llu\n",
3336            info->flow_type, info->data);
3337
3338         switch (info->flow_type) {
3339         case TCP_V4_FLOW:
3340         case TCP_V6_FLOW:
3341                 /* For TCP only 4-tupple hash is supported */
3342                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3343                                   RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3344                         DP(BNX2X_MSG_ETHTOOL,
3345                            "Command parameters not supported\n");
3346                         return -EINVAL;
3347                 }
3348                 return 0;
3349
3350         case UDP_V4_FLOW:
3351         case UDP_V6_FLOW:
3352                 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3353                 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3354                                    RXH_L4_B_0_1 | RXH_L4_B_2_3))
3355                         udp_rss_requested = 1;
3356                 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3357                         udp_rss_requested = 0;
3358                 else
3359                         return -EINVAL;
3360
3361                 if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3362                         DP(BNX2X_MSG_ETHTOOL,
3363                            "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3364                         return -EINVAL;
3365                 }
3366
3367                 if ((info->flow_type == UDP_V4_FLOW) &&
3368                     (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3369                         bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3370                         DP(BNX2X_MSG_ETHTOOL,
3371                            "rss re-configured, UDP 4-tupple %s\n",
3372                            udp_rss_requested ? "enabled" : "disabled");
3373                         if (bp->state == BNX2X_STATE_OPEN)
3374                                 return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3375                                                  true);
3376                 } else if ((info->flow_type == UDP_V6_FLOW) &&
3377                            (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3378                         bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3379                         DP(BNX2X_MSG_ETHTOOL,
3380                            "rss re-configured, UDP 4-tupple %s\n",
3381                            udp_rss_requested ? "enabled" : "disabled");
3382                         if (bp->state == BNX2X_STATE_OPEN)
3383                                 return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3384                                                  true);
3385                 }
3386                 return 0;
3387
3388         case IPV4_FLOW:
3389         case IPV6_FLOW:
3390                 /* For IP only 2-tupple hash is supported */
3391                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3392                         DP(BNX2X_MSG_ETHTOOL,
3393                            "Command parameters not supported\n");
3394                         return -EINVAL;
3395                 }
3396                 return 0;
3397
3398         case SCTP_V4_FLOW:
3399         case AH_ESP_V4_FLOW:
3400         case AH_V4_FLOW:
3401         case ESP_V4_FLOW:
3402         case SCTP_V6_FLOW:
3403         case AH_ESP_V6_FLOW:
3404         case AH_V6_FLOW:
3405         case ESP_V6_FLOW:
3406         case IP_USER_FLOW:
3407         case ETHER_FLOW:
3408                 /* RSS is not supported for these protocols */
3409                 if (info->data) {
3410                         DP(BNX2X_MSG_ETHTOOL,
3411                            "Command parameters not supported\n");
3412                         return -EINVAL;
3413                 }
3414                 return 0;
3415
3416         default:
3417                 return -EINVAL;
3418         }
3419 }
3420
3421 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3422 {
3423         struct bnx2x *bp = netdev_priv(dev);
3424
3425         switch (info->cmd) {
3426         case ETHTOOL_SRXFH:
3427                 return bnx2x_set_rss_flags(bp, info);
3428         default:
3429                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3430                 return -EOPNOTSUPP;
3431         }
3432 }
3433
3434 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3435 {
3436         return T_ETH_INDIRECTION_TABLE_SIZE;
3437 }
3438
3439 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3440                           u8 *hfunc)
3441 {
3442         struct bnx2x *bp = netdev_priv(dev);
3443         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3444         size_t i;
3445
3446         if (hfunc)
3447                 *hfunc = ETH_RSS_HASH_TOP;
3448         if (!indir)
3449                 return 0;
3450
3451         /* Get the current configuration of the RSS indirection table */
3452         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3453
3454         /*
3455          * We can't use a memcpy() as an internal storage of an
3456          * indirection table is a u8 array while indir->ring_index
3457          * points to an array of u32.
3458          *
3459          * Indirection table contains the FW Client IDs, so we need to
3460          * align the returned table to the Client ID of the leading RSS
3461          * queue.
3462          */
3463         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3464                 indir[i] = ind_table[i] - bp->fp->cl_id;
3465
3466         return 0;
3467 }
3468
3469 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3470                           const u8 *key, const u8 hfunc)
3471 {
3472         struct bnx2x *bp = netdev_priv(dev);
3473         size_t i;
3474
3475         /* We require at least one supported parameter to be changed and no
3476          * change in any of the unsupported parameters
3477          */
3478         if (key ||
3479             (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3480                 return -EOPNOTSUPP;
3481
3482         if (!indir)
3483                 return 0;
3484
3485         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3486                 /*
3487                  * The same as in bnx2x_get_rxfh: we can't use a memcpy()
3488                  * as an internal storage of an indirection table is a u8 array
3489                  * while indir->ring_index points to an array of u32.
3490                  *
3491                  * Indirection table contains the FW Client IDs, so we need to
3492                  * align the received table to the Client ID of the leading RSS
3493                  * queue
3494                  */
3495                 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3496         }
3497
3498         if (bp->state == BNX2X_STATE_OPEN)
3499                 return bnx2x_config_rss_eth(bp, false);
3500
3501         return 0;
3502 }
3503
3504 /**
3505  * bnx2x_get_channels - gets the number of RSS queues.
3506  *
3507  * @dev:                net device
3508  * @channels:           returns the number of max / current queues
3509  */
3510 static void bnx2x_get_channels(struct net_device *dev,
3511                                struct ethtool_channels *channels)
3512 {
3513         struct bnx2x *bp = netdev_priv(dev);
3514
3515         channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3516         channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3517 }
3518
3519 /**
3520  * bnx2x_change_num_queues - change the number of RSS queues.
3521  *
3522  * @bp:                 bnx2x private structure
3523  *
3524  * Re-configure interrupt mode to get the new number of MSI-X
3525  * vectors and re-add NAPI objects.
3526  */
3527 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3528 {
3529         bnx2x_disable_msi(bp);
3530         bp->num_ethernet_queues = num_rss;
3531         bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3532         BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3533         bnx2x_set_int_mode(bp);
3534 }
3535
3536 /**
3537  * bnx2x_set_channels - sets the number of RSS queues.
3538  *
3539  * @dev:                net device
3540  * @channels:           includes the number of queues requested
3541  */
3542 static int bnx2x_set_channels(struct net_device *dev,
3543                               struct ethtool_channels *channels)
3544 {
3545         struct bnx2x *bp = netdev_priv(dev);
3546
3547         DP(BNX2X_MSG_ETHTOOL,
3548            "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3549            channels->rx_count, channels->tx_count, channels->other_count,
3550            channels->combined_count);
3551
3552         if (pci_num_vf(bp->pdev)) {
3553                 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3554                 return -EPERM;
3555         }
3556
3557         /* We don't support separate rx / tx channels.
3558          * We don't allow setting 'other' channels.
3559          */
3560         if (channels->rx_count || channels->tx_count || channels->other_count
3561             || (channels->combined_count == 0) ||
3562             (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3563                 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3564                 return -EINVAL;
3565         }
3566
3567         /* Check if there was a change in the active parameters */
3568         if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3569                 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3570                 return 0;
3571         }
3572
3573         /* Set the requested number of queues in bp context.
3574          * Note that the actual number of queues created during load may be
3575          * less than requested if memory is low.
3576          */
3577         if (unlikely(!netif_running(dev))) {
3578                 bnx2x_change_num_queues(bp, channels->combined_count);
3579                 return 0;
3580         }
3581         bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3582         bnx2x_change_num_queues(bp, channels->combined_count);
3583         return bnx2x_nic_load(bp, LOAD_NORMAL);
3584 }
3585
3586 static int bnx2x_get_ts_info(struct net_device *dev,
3587                              struct ethtool_ts_info *info)
3588 {
3589         struct bnx2x *bp = netdev_priv(dev);
3590
3591         if (bp->flags & PTP_SUPPORTED) {
3592                 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3593                                         SOF_TIMESTAMPING_RX_SOFTWARE |
3594                                         SOF_TIMESTAMPING_SOFTWARE |
3595                                         SOF_TIMESTAMPING_TX_HARDWARE |
3596                                         SOF_TIMESTAMPING_RX_HARDWARE |
3597                                         SOF_TIMESTAMPING_RAW_HARDWARE;
3598
3599                 if (bp->ptp_clock)
3600                         info->phc_index = ptp_clock_index(bp->ptp_clock);
3601                 else
3602                         info->phc_index = -1;
3603
3604                 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3605                                    (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3606                                    (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3607                                    (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3608
3609                 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3610
3611                 return 0;
3612         }
3613
3614         return ethtool_op_get_ts_info(dev, info);
3615 }
3616
3617 static const struct ethtool_ops bnx2x_ethtool_ops = {
3618         .get_settings           = bnx2x_get_settings,
3619         .set_settings           = bnx2x_set_settings,
3620         .get_drvinfo            = bnx2x_get_drvinfo,
3621         .get_regs_len           = bnx2x_get_regs_len,
3622         .get_regs               = bnx2x_get_regs,
3623         .get_dump_flag          = bnx2x_get_dump_flag,
3624         .get_dump_data          = bnx2x_get_dump_data,
3625         .set_dump               = bnx2x_set_dump,
3626         .get_wol                = bnx2x_get_wol,
3627         .set_wol                = bnx2x_set_wol,
3628         .get_msglevel           = bnx2x_get_msglevel,
3629         .set_msglevel           = bnx2x_set_msglevel,
3630         .nway_reset             = bnx2x_nway_reset,
3631         .get_link               = bnx2x_get_link,
3632         .get_eeprom_len         = bnx2x_get_eeprom_len,
3633         .get_eeprom             = bnx2x_get_eeprom,
3634         .set_eeprom             = bnx2x_set_eeprom,
3635         .get_coalesce           = bnx2x_get_coalesce,
3636         .set_coalesce           = bnx2x_set_coalesce,
3637         .get_ringparam          = bnx2x_get_ringparam,
3638         .set_ringparam          = bnx2x_set_ringparam,
3639         .get_pauseparam         = bnx2x_get_pauseparam,
3640         .set_pauseparam         = bnx2x_set_pauseparam,
3641         .self_test              = bnx2x_self_test,
3642         .get_sset_count         = bnx2x_get_sset_count,
3643         .get_priv_flags         = bnx2x_get_private_flags,
3644         .get_strings            = bnx2x_get_strings,
3645         .set_phys_id            = bnx2x_set_phys_id,
3646         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3647         .get_rxnfc              = bnx2x_get_rxnfc,
3648         .set_rxnfc              = bnx2x_set_rxnfc,
3649         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3650         .get_rxfh               = bnx2x_get_rxfh,
3651         .set_rxfh               = bnx2x_set_rxfh,
3652         .get_channels           = bnx2x_get_channels,
3653         .set_channels           = bnx2x_set_channels,
3654         .get_module_info        = bnx2x_get_module_info,
3655         .get_module_eeprom      = bnx2x_get_module_eeprom,
3656         .get_eee                = bnx2x_get_eee,
3657         .set_eee                = bnx2x_set_eee,
3658         .get_ts_info            = bnx2x_get_ts_info,
3659 };
3660
3661 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3662         .get_settings           = bnx2x_get_vf_settings,
3663         .get_drvinfo            = bnx2x_get_drvinfo,
3664         .get_msglevel           = bnx2x_get_msglevel,
3665         .set_msglevel           = bnx2x_set_msglevel,
3666         .get_link               = bnx2x_get_link,
3667         .get_coalesce           = bnx2x_get_coalesce,
3668         .get_ringparam          = bnx2x_get_ringparam,
3669         .set_ringparam          = bnx2x_set_ringparam,
3670         .get_sset_count         = bnx2x_get_sset_count,
3671         .get_strings            = bnx2x_get_strings,
3672         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3673         .get_rxnfc              = bnx2x_get_rxnfc,
3674         .set_rxnfc              = bnx2x_set_rxnfc,
3675         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3676         .get_rxfh               = bnx2x_get_rxfh,
3677         .set_rxfh               = bnx2x_set_rxfh,
3678         .get_channels           = bnx2x_get_channels,
3679         .set_channels           = bnx2x_set_channels,
3680 };
3681
3682 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3683 {
3684         netdev->ethtool_ops = (IS_PF(bp)) ?
3685                 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3686 }