drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  * Copyright (c) 2014 QLogic Corporation
   3  * All rights reserved
   4  *
   5  * Unless you and QLogic execute a separate written software license
   6  * agreement governing use of this software, this software is licensed to you
   7  * under the terms of the GNU General Public License version 2, available
   8  * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
   9  *
  10  * Notwithstanding the above, under no circumstances may you combine this
  11  * software in any way with any other Qlogic software provided under a
  12  * license other than the GPL, without Qlogic's express prior written
  13  * consent.
  14  *
  15  * Written by Yaniv Rosner
  16  *
  17  */
  18
  19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  20
  21 #include <linux/kernel.h>
  22 #include <linux/errno.h>
  23 #include <linux/pci.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/delay.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/mutex.h>
  28
  29 #include "bnx2x.h"
  30 #include "bnx2x_cmn.h"
  31
  32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
  33                                              struct link_params *params,
  34                                              u8 dev_addr, u16 addr, u8 byte_cnt,
  35                                              u8 *o_buf, u8);
  36 /********************************************************/
  37 #define MDIO_ACCESS_TIMEOUT             1000
  38 #define WC_LANE_MAX                     4
  39 #define I2C_SWITCH_WIDTH                2
  40 #define I2C_BSC0                        0
  41 #define I2C_BSC1                        1
  42 #define I2C_WA_RETRY_CNT                3
  43 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
  44 #define MCPR_IMC_COMMAND_READ_OP        1
  45 #define MCPR_IMC_COMMAND_WRITE_OP       2
  46
  47 /* LED Blink rate that will achieve ~15.9Hz */
  48 #define LED_BLINK_RATE_VAL_E3           354
  49 #define LED_BLINK_RATE_VAL_E1X_E2       480
  50 /***********************************************************/
  51 /*                      Shortcut definitions               */
  52 /***********************************************************/
  53
  54 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  55
  56 #define NIG_STATUS_EMAC0_MI_INT \
  57                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  58 #define NIG_STATUS_XGXS0_LINK10G \
  59                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  60 #define NIG_STATUS_XGXS0_LINK_STATUS \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  64 #define NIG_STATUS_SERDES0_LINK_STATUS \
  65                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  66 #define NIG_MASK_MI_INT \
  67                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  68 #define NIG_MASK_XGXS0_LINK10G \
  69                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  70 #define NIG_MASK_XGXS0_LINK_STATUS \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  72 #define NIG_MASK_SERDES0_LINK_STATUS \
  73                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  74
  75 #define MDIO_AN_CL73_OR_37_COMPLETE \
  76                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  77                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  78
  79 #define XGXS_RESET_BITS \
  80         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  83          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  84          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  85
  86 #define SERDES_RESET_BITS \
  87         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  89          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  90          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  91
  92 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  93 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  94 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  95 #define AUTONEG_PARALLEL \
  96                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  97 #define AUTONEG_SGMII_FIBER_AUTODET \
  98                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  99 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 100
 101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 102                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 104                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 105 #define GP_STATUS_SPEED_MASK \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 107 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 108 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 109 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 110 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 111 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 112 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 113 #define GP_STATUS_10G_HIG \
 114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 115 #define GP_STATUS_10G_CX4 \
 116                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 118 #define GP_STATUS_10G_KX4 \
 119                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 121 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 123 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 124 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
 125 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 126 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 127 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 128 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 129 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 130 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 131 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 132 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 133 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 134 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 135 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 136 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 137 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 138 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 139 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 140
 141 #define LINK_UPDATE_MASK \
 142                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
 143                          LINK_STATUS_LINK_UP | \
 144                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
 145                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
 146                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
 147                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
 148                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
 149                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
 150                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 151
 152 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 153         #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
 154         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 155         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 156         #define SFP_EEPROM_CON_TYPE_VAL_RJ45    0x22
 157
 158
 159 #define SFP_EEPROM_10G_COMP_CODE_ADDR           0x3
 160         #define SFP_EEPROM_10G_COMP_CODE_SR_MASK        (1<<4)
 161         #define SFP_EEPROM_10G_COMP_CODE_LR_MASK        (1<<5)
 162         #define SFP_EEPROM_10G_COMP_CODE_LRM_MASK       (1<<6)
 163
 164 #define SFP_EEPROM_1G_COMP_CODE_ADDR            0x6
 165         #define SFP_EEPROM_1G_COMP_CODE_SX      (1<<0)
 166         #define SFP_EEPROM_1G_COMP_CODE_LX      (1<<1)
 167         #define SFP_EEPROM_1G_COMP_CODE_CX      (1<<2)
 168         #define SFP_EEPROM_1G_COMP_CODE_BASE_T  (1<<3)
 169
 170 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 171         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 172         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 173
 174 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 175         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 176 #define SFP_EEPROM_OPTIONS_SIZE                 2
 177
 178 #define EDC_MODE_LINEAR                         0x0022
 179 #define EDC_MODE_LIMITING                               0x0044
 180 #define EDC_MODE_PASSIVE_DAC                    0x0055
 181 #define EDC_MODE_ACTIVE_DAC                     0x0066
 182
 183 /* ETS defines*/
 184 #define DCBX_INVALID_COS                                        (0xFF)
 185
 186 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 187 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 188 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 189 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 190 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 191
 192 #define MAX_PACKET_SIZE                                 (9700)
 193 #define MAX_KR_LINK_RETRY                               4
 194 #define DEFAULT_TX_DRV_BRDCT            2
 195 #define DEFAULT_TX_DRV_IFIR             0
 196 #define DEFAULT_TX_DRV_POST2            3
 197 #define DEFAULT_TX_DRV_IPRE_DRIVER      6
 198
 199 /**********************************************************/
 200 /*                     INTERFACE                          */
 201 /**********************************************************/
 202
 203 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 204         bnx2x_cl45_write(_bp, _phy, \
 205                 (_phy)->def_md_devad, \
 206                 (_bank + (_addr & 0xf)), \
 207                 _val)
 208
 209 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 210         bnx2x_cl45_read(_bp, _phy, \
 211                 (_phy)->def_md_devad, \
 212                 (_bank + (_addr & 0xf)), \
 213                 _val)
 214
 215 static int bnx2x_check_half_open_conn(struct link_params *params,
 216                                       struct link_vars *vars, u8 notify);
 217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
 218                                       struct link_params *params);
 219
 220 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 221 {
 222         u32 val = REG_RD(bp, reg);
 223
 224         val |= bits;
 225         REG_WR(bp, reg, val);
 226         return val;
 227 }
 228
 229 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 230 {
 231         u32 val = REG_RD(bp, reg);
 232
 233         val &= ~bits;
 234         REG_WR(bp, reg, val);
 235         return val;
 236 }
 237
 238 /*
 239  * bnx2x_check_lfa - This function checks if link reinitialization is required,
 240  *                   or link flap can be avoided.
 241  *
 242  * @params:     link parameters
 243  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
 244  *         condition code.
 245  */
 246 static int bnx2x_check_lfa(struct link_params *params)
 247 {
 248         u32 link_status, cfg_idx, lfa_mask, cfg_size;
 249         u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
 250         u32 saved_val, req_val, eee_status;
 251         struct bnx2x *bp = params->bp;
 252
 253         additional_config =
 254                 REG_RD(bp, params->lfa_base +
 255                            offsetof(struct shmem_lfa, additional_config));
 256
 257         /* NOTE: must be first condition checked -
 258         * to verify DCC bit is cleared in any case!
 259         */
 260         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
 261                 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
 262                 REG_WR(bp, params->lfa_base +
 263                            offsetof(struct shmem_lfa, additional_config),
 264                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
 265                 return LFA_DCC_LFA_DISABLED;
 266         }
 267
 268         /* Verify that link is up */
 269         link_status = REG_RD(bp, params->shmem_base +
 270                              offsetof(struct shmem_region,
 271                                       port_mb[params->port].link_status));
 272         if (!(link_status & LINK_STATUS_LINK_UP))
 273                 return LFA_LINK_DOWN;
 274
 275         /* if loaded after BOOT from SAN, don't flap the link in any case and
 276          * rely on link set by preboot driver
 277          */
 278         if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
 279                 return 0;
 280
 281         /* Verify that loopback mode is not set */
 282         if (params->loopback_mode)
 283                 return LFA_LOOPBACK_ENABLED;
 284
 285         /* Verify that MFW supports LFA */
 286         if (!params->lfa_base)
 287                 return LFA_MFW_IS_TOO_OLD;
 288
 289         if (params->num_phys == 3) {
 290                 cfg_size = 2;
 291                 lfa_mask = 0xffffffff;
 292         } else {
 293                 cfg_size = 1;
 294                 lfa_mask = 0xffff;
 295         }
 296
 297         /* Compare Duplex */
 298         saved_val = REG_RD(bp, params->lfa_base +
 299                            offsetof(struct shmem_lfa, req_duplex));
 300         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
 301         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 302                 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
 303                                (saved_val & lfa_mask), (req_val & lfa_mask));
 304                 return LFA_DUPLEX_MISMATCH;
 305         }
 306         /* Compare Flow Control */
 307         saved_val = REG_RD(bp, params->lfa_base +
 308                            offsetof(struct shmem_lfa, req_flow_ctrl));
 309         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
 310         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 311                 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
 312                                (saved_val & lfa_mask), (req_val & lfa_mask));
 313                 return LFA_FLOW_CTRL_MISMATCH;
 314         }
 315         /* Compare Link Speed */
 316         saved_val = REG_RD(bp, params->lfa_base +
 317                            offsetof(struct shmem_lfa, req_line_speed));
 318         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
 319         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 320                 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
 321                                (saved_val & lfa_mask), (req_val & lfa_mask));
 322                 return LFA_LINK_SPEED_MISMATCH;
 323         }
 324
 325         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
 326                 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
 327                                             offsetof(struct shmem_lfa,
 328                                                      speed_cap_mask[cfg_idx]));
 329
 330                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
 331                         DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
 332                                        cur_speed_cap_mask,
 333                                        params->speed_cap_mask[cfg_idx]);
 334                         return LFA_SPEED_CAP_MISMATCH;
 335                 }
 336         }
 337
 338         cur_req_fc_auto_adv =
 339                 REG_RD(bp, params->lfa_base +
 340                        offsetof(struct shmem_lfa, additional_config)) &
 341                 REQ_FC_AUTO_ADV_MASK;
 342
 343         if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
 344                 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
 345                                cur_req_fc_auto_adv, params->req_fc_auto_adv);
 346                 return LFA_FLOW_CTRL_MISMATCH;
 347         }
 348
 349         eee_status = REG_RD(bp, params->shmem2_base +
 350                             offsetof(struct shmem2_region,
 351                                      eee_status[params->port]));
 352
 353         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
 354              (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
 355             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
 356              (params->eee_mode & EEE_MODE_ADV_LPI))) {
 357                 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
 358                                eee_status);
 359                 return LFA_EEE_MISMATCH;
 360         }
 361
 362         /* LFA conditions are met */
 363         return 0;
 364 }
 365 /******************************************************************/
 366 /*                      EPIO/GPIO section                         */
 367 /******************************************************************/
 368 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 369 {
 370         u32 epio_mask, gp_oenable;
 371         *en = 0;
 372         /* Sanity check */
 373         if (epio_pin > 31) {
 374                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 375                 return;
 376         }
 377
 378         epio_mask = 1 << epio_pin;
 379         /* Set this EPIO to output */
 380         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 381         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 382
 383         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 384 }
 385 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 386 {
 387         u32 epio_mask, gp_output, gp_oenable;
 388
 389         /* Sanity check */
 390         if (epio_pin > 31) {
 391                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 392                 return;
 393         }
 394         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 395         epio_mask = 1 << epio_pin;
 396         /* Set this EPIO to output */
 397         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 398         if (en)
 399                 gp_output |= epio_mask;
 400         else
 401                 gp_output &= ~epio_mask;
 402
 403         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 404
 405         /* Set the value for this EPIO */
 406         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 407         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 408 }
 409
 410 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 411 {
 412         if (pin_cfg == PIN_CFG_NA)
 413                 return;
 414         if (pin_cfg >= PIN_CFG_EPIO0) {
 415                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 416         } else {
 417                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 418                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 419                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 420         }
 421 }
 422
 423 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 424 {
 425         if (pin_cfg == PIN_CFG_NA)
 426                 return -EINVAL;
 427         if (pin_cfg >= PIN_CFG_EPIO0) {
 428                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 429         } else {
 430                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 431                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 432                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 433         }
 434         return 0;
 435
 436 }
 437 /******************************************************************/
 438 /*                              ETS section                       */
 439 /******************************************************************/
 440 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 441 {
 442         /* ETS disabled configuration*/
 443         struct bnx2x *bp = params->bp;
 444
 445         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 446
 447         /* mapping between entry  priority to client number (0,1,2 -debug and
 448          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 449          * 3bits client num.
 450          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 451          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 452          */
 453
 454         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 455         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 456          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 457          * COS0 entry, 4 - COS1 entry.
 458          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 459          * bit4   bit3    bit2   bit1     bit0
 460          * MCP and debug are strict
 461          */
 462
 463         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 464         /* defines which entries (clients) are subjected to WFQ arbitration */
 465         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 466         /* For strict priority entries defines the number of consecutive
 467          * slots for the highest priority.
 468          */
 469         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 470         /* mapping between the CREDIT_WEIGHT registers and actual client
 471          * numbers
 472          */
 473         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 474         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 475         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 476
 477         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 478         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 479         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 480         /* ETS mode disable */
 481         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 482         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 483          * weight for COS0/COS1.
 484          */
 485         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 486         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 487         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 488         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 489         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 490         /* Defines the number of consecutive slots for the strict priority */
 491         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 492 }
 493 /******************************************************************************
 494 * Description:
 495 *       Getting min_w_val will be set according to line speed .
 496 *.
 497 ******************************************************************************/
 498 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 499 {
 500         u32 min_w_val = 0;
 501         /* Calculate min_w_val.*/
 502         if (vars->link_up) {
 503                 if (vars->line_speed == SPEED_20000)
 504                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 505                 else
 506                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 507         } else
 508                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 509         /* If the link isn't up (static configuration for example ) The
 510          * link will be according to 20GBPS.
 511          */
 512         return min_w_val;
 513 }
 514 /******************************************************************************
 515 * Description:
 516 *       Getting credit upper bound form min_w_val.
 517 *.
 518 ******************************************************************************/
 519 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 520 {
 521         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 522                                                 MAX_PACKET_SIZE);
 523         return credit_upper_bound;
 524 }
 525 /******************************************************************************
 526 * Description:
 527 *       Set credit upper bound for NIG.
 528 *.
 529 ******************************************************************************/
 530 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 531         const struct link_params *params,
 532         const u32 min_w_val)
 533 {
 534         struct bnx2x *bp = params->bp;
 535         const u8 port = params->port;
 536         const u32 credit_upper_bound =
 537             bnx2x_ets_get_credit_upper_bound(min_w_val);
 538
 539         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 540                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 541         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 542                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 543         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 544                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 545         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 546                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 547         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 548                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 549         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 550                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 551
 552         if (!port) {
 553                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 554                         credit_upper_bound);
 555                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 556                         credit_upper_bound);
 557                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 558                         credit_upper_bound);
 559         }
 560 }
 561 /******************************************************************************
 562 * Description:
 563 *       Will return the NIG ETS registers to init values.Except
 564 *       credit_upper_bound.
 565 *       That isn't used in this configuration (No WFQ is enabled) and will be
 566 *       configured according to spec
 567 *.
 568 ******************************************************************************/
 569 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 570                                         const struct link_vars *vars)
 571 {
 572         struct bnx2x *bp = params->bp;
 573         const u8 port = params->port;
 574         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 575         /* Mapping between entry  priority to client number (0,1,2 -debug and
 576          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 577          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 578          * reset value or init tool
 579          */
 580         if (port) {
 581                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 582                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 583         } else {
 584                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 585                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 586         }
 587         /* For strict priority entries defines the number of consecutive
 588          * slots for the highest priority.
 589          */
 590         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 591                    NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 592         /* Mapping between the CREDIT_WEIGHT registers and actual client
 593          * numbers
 594          */
 595         if (port) {
 596                 /*Port 1 has 6 COS*/
 597                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 598                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 599         } else {
 600                 /*Port 0 has 9 COS*/
 601                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 602                        0x43210876);
 603                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 604         }
 605
 606         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 607          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 608          * COS0 entry, 4 - COS1 entry.
 609          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 610          * bit4   bit3    bit2   bit1     bit0
 611          * MCP and debug are strict
 612          */
 613         if (port)
 614                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 615         else
 616                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 617         /* defines which entries (clients) are subjected to WFQ arbitration */
 618         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 619                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 620
 621         /* Please notice the register address are note continuous and a
 622          * for here is note appropriate.In 2 port mode port0 only COS0-5
 623          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 624          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 625          * are never used for WFQ
 626          */
 627         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 628                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 629         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 630                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 631         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 632                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 633         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 634                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 635         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 636                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 637         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 638                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 639         if (!port) {
 640                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 641                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 642                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 643         }
 644
 645         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 646 }
 647 /******************************************************************************
 648 * Description:
 649 *       Set credit upper bound for PBF.
 650 *.
 651 ******************************************************************************/
 652 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 653         const struct link_params *params,
 654         const u32 min_w_val)
 655 {
 656         struct bnx2x *bp = params->bp;
 657         const u32 credit_upper_bound =
 658             bnx2x_ets_get_credit_upper_bound(min_w_val);
 659         const u8 port = params->port;
 660         u32 base_upper_bound = 0;
 661         u8 max_cos = 0;
 662         u8 i = 0;
 663         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 664          * port mode port1 has COS0-2 that can be used for WFQ.
 665          */
 666         if (!port) {
 667                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 668                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 669         } else {
 670                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 671                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 672         }
 673
 674         for (i = 0; i < max_cos; i++)
 675                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 676 }
 677
 678 /******************************************************************************
 679 * Description:
 680 *       Will return the PBF ETS registers to init values.Except
 681 *       credit_upper_bound.
 682 *       That isn't used in this configuration (No WFQ is enabled) and will be
 683 *       configured according to spec
 684 *.
 685 ******************************************************************************/
 686 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 687 {
 688         struct bnx2x *bp = params->bp;
 689         const u8 port = params->port;
 690         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 691         u8 i = 0;
 692         u32 base_weight = 0;
 693         u8 max_cos = 0;
 694
 695         /* Mapping between entry  priority to client number 0 - COS0
 696          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 697          * TODO_ETS - Should be done by reset value or init tool
 698          */
 699         if (port)
 700                 /*  0x688 (|011|0 10|00 1|000) */
 701                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 702         else
 703                 /*  (10 1|100 |011|0 10|00 1|000) */
 704                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 705
 706         /* TODO_ETS - Should be done by reset value or init tool */
 707         if (port)
 708                 /* 0x688 (|011|0 10|00 1|000)*/
 709                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 710         else
 711         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 712         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 713
 714         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 715                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 716
 717
 718         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 719                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 720
 721         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 722                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 723         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 724          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 725          */
 726         if (!port) {
 727                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 728                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 729         } else {
 730                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 731                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 732         }
 733
 734         for (i = 0; i < max_cos; i++)
 735                 REG_WR(bp, base_weight + (0x4 * i), 0);
 736
 737         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 738 }
 739 /******************************************************************************
 740 * Description:
 741 *       E3B0 disable will return basically the values to init values.
 742 *.
 743 ******************************************************************************/
 744 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 745                                    const struct link_vars *vars)
 746 {
 747         struct bnx2x *bp = params->bp;
 748
 749         if (!CHIP_IS_E3B0(bp)) {
 750                 DP(NETIF_MSG_LINK,
 751                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 752                 return -EINVAL;
 753         }
 754
 755         bnx2x_ets_e3b0_nig_disabled(params, vars);
 756
 757         bnx2x_ets_e3b0_pbf_disabled(params);
 758
 759         return 0;
 760 }
 761
 762 /******************************************************************************
 763 * Description:
 764 *       Disable will return basically the values to init values.
 765 *
 766 ******************************************************************************/
 767 int bnx2x_ets_disabled(struct link_params *params,
 768                       struct link_vars *vars)
 769 {
 770         struct bnx2x *bp = params->bp;
 771         int bnx2x_status = 0;
 772
 773         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 774                 bnx2x_ets_e2e3a0_disabled(params);
 775         else if (CHIP_IS_E3B0(bp))
 776                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 777         else {
 778                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 779                 return -EINVAL;
 780         }
 781
 782         return bnx2x_status;
 783 }
 784
 785 /******************************************************************************
 786 * Description
 787 *       Set the COS mappimg to SP and BW until this point all the COS are not
 788 *       set as SP or BW.
 789 ******************************************************************************/
 790 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 791                                   const struct bnx2x_ets_params *ets_params,
 792                                   const u8 cos_sp_bitmap,
 793                                   const u8 cos_bw_bitmap)
 794 {
 795         struct bnx2x *bp = params->bp;
 796         const u8 port = params->port;
 797         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 798         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 799         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 800         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 801
 802         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 803                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 804
 805         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 806                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 807
 808         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 809                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 810                nig_cli_subject2wfq_bitmap);
 811
 812         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 813                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 814                pbf_cli_subject2wfq_bitmap);
 815
 816         return 0;
 817 }
 818
 819 /******************************************************************************
 820 * Description:
 821 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 822 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 823 ******************************************************************************/
 824 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 825                                      const u8 cos_entry,
 826                                      const u32 min_w_val_nig,
 827                                      const u32 min_w_val_pbf,
 828                                      const u16 total_bw,
 829                                      const u8 bw,
 830                                      const u8 port)
 831 {
 832         u32 nig_reg_adress_crd_weight = 0;
 833         u32 pbf_reg_adress_crd_weight = 0;
 834         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 835         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 836         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 837
 838         switch (cos_entry) {
 839         case 0:
 840             nig_reg_adress_crd_weight =
 841                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 842                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 843              pbf_reg_adress_crd_weight = (port) ?
 844                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 845              break;
 846         case 1:
 847              nig_reg_adress_crd_weight = (port) ?
 848                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 849                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 850              pbf_reg_adress_crd_weight = (port) ?
 851                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 852              break;
 853         case 2:
 854              nig_reg_adress_crd_weight = (port) ?
 855                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 856                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 857
 858                  pbf_reg_adress_crd_weight = (port) ?
 859                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 860              break;
 861         case 3:
 862             if (port)
 863                         return -EINVAL;
 864              nig_reg_adress_crd_weight =
 865                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 866              pbf_reg_adress_crd_weight =
 867                  PBF_REG_COS3_WEIGHT_P0;
 868              break;
 869         case 4:
 870             if (port)
 871                 return -EINVAL;
 872              nig_reg_adress_crd_weight =
 873                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 874              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 875              break;
 876         case 5:
 877             if (port)
 878                 return -EINVAL;
 879              nig_reg_adress_crd_weight =
 880                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 881              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 882              break;
 883         }
 884
 885         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 886
 887         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 888
 889         return 0;
 890 }
 891 /******************************************************************************
 892 * Description:
 893 *       Calculate the total BW.A value of 0 isn't legal.
 894 *
 895 ******************************************************************************/
 896 static int bnx2x_ets_e3b0_get_total_bw(
 897         const struct link_params *params,
 898         struct bnx2x_ets_params *ets_params,
 899         u16 *total_bw)
 900 {
 901         struct bnx2x *bp = params->bp;
 902         u8 cos_idx = 0;
 903         u8 is_bw_cos_exist = 0;
 904
 905         *total_bw = 0 ;
 906         /* Calculate total BW requested */
 907         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 908                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 909                         is_bw_cos_exist = 1;
 910                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 911                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 912                                                    "was set to 0\n");
 913                                 /* This is to prevent a state when ramrods
 914                                  * can't be sent
 915                                  */
 916                                 ets_params->cos[cos_idx].params.bw_params.bw
 917                                          = 1;
 918                         }
 919                         *total_bw +=
 920                                 ets_params->cos[cos_idx].params.bw_params.bw;
 921                 }
 922         }
 923
 924         /* Check total BW is valid */
 925         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 926                 if (*total_bw == 0) {
 927                         DP(NETIF_MSG_LINK,
 928                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 929                         return -EINVAL;
 930                 }
 931                 DP(NETIF_MSG_LINK,
 932                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 933                 /* We can handle a case whre the BW isn't 100 this can happen
 934                  * if the TC are joined.
 935                  */
 936         }
 937         return 0;
 938 }
 939
 940 /******************************************************************************
 941 * Description:
 942 *       Invalidate all the sp_pri_to_cos.
 943 *
 944 ******************************************************************************/
 945 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 946 {
 947         u8 pri = 0;
 948         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 949                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 950 }
 951 /******************************************************************************
 952 * Description:
 953 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 954 *       according to sp_pri_to_cos.
 955 *
 956 ******************************************************************************/
 957 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 958                                             u8 *sp_pri_to_cos, const u8 pri,
 959                                             const u8 cos_entry)
 960 {
 961         struct bnx2x *bp = params->bp;
 962         const u8 port = params->port;
 963         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 964                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 965
 966         if (pri >= max_num_of_cos) {
 967                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 968                    "parameter Illegal strict priority\n");
 969             return -EINVAL;
 970         }
 971
 972         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 973                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 974                                    "parameter There can't be two COS's with "
 975                                    "the same strict pri\n");
 976                 return -EINVAL;
 977         }
 978
 979         sp_pri_to_cos[pri] = cos_entry;
 980         return 0;
 981
 982 }
 983
 984 /******************************************************************************
 985 * Description:
 986 *       Returns the correct value according to COS and priority in
 987 *       the sp_pri_cli register.
 988 *
 989 ******************************************************************************/
 990 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 991                                          const u8 pri_set,
 992                                          const u8 pri_offset,
 993                                          const u8 entry_size)
 994 {
 995         u64 pri_cli_nig = 0;
 996         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 997                                                     (pri_set + pri_offset));
 998
 999         return pri_cli_nig;
1000 }
1001 /******************************************************************************
1002 * Description:
1003 *       Returns the correct value according to COS and priority in the
1004 *       sp_pri_cli register for NIG.
1005 *
1006 ******************************************************************************/
1007 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
1008 {
1009         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1010         const u8 nig_cos_offset = 3;
1011         const u8 nig_pri_offset = 3;
1012
1013         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1014                 nig_pri_offset, 4);
1015
1016 }
1017 /******************************************************************************
1018 * Description:
1019 *       Returns the correct value according to COS and priority in the
1020 *       sp_pri_cli register for PBF.
1021 *
1022 ******************************************************************************/
1023 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1024 {
1025         const u8 pbf_cos_offset = 0;
1026         const u8 pbf_pri_offset = 0;
1027
1028         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1029                 pbf_pri_offset, 3);
1030
1031 }
1032
1033 /******************************************************************************
1034 * Description:
1035 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1036 *       according to sp_pri_to_cos.(which COS has higher priority)
1037 *
1038 ******************************************************************************/
1039 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1040                                              u8 *sp_pri_to_cos)
1041 {
1042         struct bnx2x *bp = params->bp;
1043         u8 i = 0;
1044         const u8 port = params->port;
1045         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1046         u64 pri_cli_nig = 0x210;
1047         u32 pri_cli_pbf = 0x0;
1048         u8 pri_set = 0;
1049         u8 pri_bitmask = 0;
1050         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1051                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1052
1053         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1054
1055         /* Set all the strict priority first */
1056         for (i = 0; i < max_num_of_cos; i++) {
1057                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1058                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1059                                 DP(NETIF_MSG_LINK,
1060                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1061                                            "invalid cos entry\n");
1062                                 return -EINVAL;
1063                         }
1064
1065                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1066                             sp_pri_to_cos[i], pri_set);
1067
1068                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1069                             sp_pri_to_cos[i], pri_set);
1070                         pri_bitmask = 1 << sp_pri_to_cos[i];
1071                         /* COS is used remove it from bitmap.*/
1072                         if (!(pri_bitmask & cos_bit_to_set)) {
1073                                 DP(NETIF_MSG_LINK,
1074                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1075                                         "invalid There can't be two COS's with"
1076                                         " the same strict pri\n");
1077                                 return -EINVAL;
1078                         }
1079                         cos_bit_to_set &= ~pri_bitmask;
1080                         pri_set++;
1081                 }
1082         }
1083
1084         /* Set all the Non strict priority i= COS*/
1085         for (i = 0; i < max_num_of_cos; i++) {
1086                 pri_bitmask = 1 << i;
1087                 /* Check if COS was already used for SP */
1088                 if (pri_bitmask & cos_bit_to_set) {
1089                         /* COS wasn't used for SP */
1090                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1091                             i, pri_set);
1092
1093                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1094                             i, pri_set);
1095                         /* COS is used remove it from bitmap.*/
1096                         cos_bit_to_set &= ~pri_bitmask;
1097                         pri_set++;
1098                 }
1099         }
1100
1101         if (pri_set != max_num_of_cos) {
1102                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1103                                    "entries were set\n");
1104                 return -EINVAL;
1105         }
1106
1107         if (port) {
1108                 /* Only 6 usable clients*/
1109                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1110                        (u32)pri_cli_nig);
1111
1112                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1113         } else {
1114                 /* Only 9 usable clients*/
1115                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1116                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1117
1118                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1119                        pri_cli_nig_lsb);
1120                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1121                        pri_cli_nig_msb);
1122
1123                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1124         }
1125         return 0;
1126 }
1127
1128 /******************************************************************************
1129 * Description:
1130 *       Configure the COS to ETS according to BW and SP settings.
1131 ******************************************************************************/
1132 int bnx2x_ets_e3b0_config(const struct link_params *params,
1133                          const struct link_vars *vars,
1134                          struct bnx2x_ets_params *ets_params)
1135 {
1136         struct bnx2x *bp = params->bp;
1137         int bnx2x_status = 0;
1138         const u8 port = params->port;
1139         u16 total_bw = 0;
1140         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1141         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1142         u8 cos_bw_bitmap = 0;
1143         u8 cos_sp_bitmap = 0;
1144         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1145         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1146                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1147         u8 cos_entry = 0;
1148
1149         if (!CHIP_IS_E3B0(bp)) {
1150                 DP(NETIF_MSG_LINK,
1151                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1152                 return -EINVAL;
1153         }
1154
1155         if ((ets_params->num_of_cos > max_num_of_cos)) {
1156                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1157                                    "isn't supported\n");
1158                 return -EINVAL;
1159         }
1160
1161         /* Prepare sp strict priority parameters*/
1162         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1163
1164         /* Prepare BW parameters*/
1165         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1166                                                    &total_bw);
1167         if (bnx2x_status) {
1168                 DP(NETIF_MSG_LINK,
1169                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1170                 return -EINVAL;
1171         }
1172
1173         /* Upper bound is set according to current link speed (min_w_val
1174          * should be the same for upper bound and COS credit val).
1175          */
1176         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1177         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1178
1179
1180         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1181                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1182                         cos_bw_bitmap |= (1 << cos_entry);
1183                         /* The function also sets the BW in HW(not the mappin
1184                          * yet)
1185                          */
1186                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1187                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1188                                 total_bw,
1189                                 ets_params->cos[cos_entry].params.bw_params.bw,
1190                                  port);
1191                 } else if (bnx2x_cos_state_strict ==
1192                         ets_params->cos[cos_entry].state){
1193                         cos_sp_bitmap |= (1 << cos_entry);
1194
1195                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1196                                 params,
1197                                 sp_pri_to_cos,
1198                                 ets_params->cos[cos_entry].params.sp_params.pri,
1199                                 cos_entry);
1200
1201                 } else {
1202                         DP(NETIF_MSG_LINK,
1203                            "bnx2x_ets_e3b0_config cos state not valid\n");
1204                         return -EINVAL;
1205                 }
1206                 if (bnx2x_status) {
1207                         DP(NETIF_MSG_LINK,
1208                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1209                         return bnx2x_status;
1210                 }
1211         }
1212
1213         /* Set SP register (which COS has higher priority) */
1214         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1215                                                          sp_pri_to_cos);
1216
1217         if (bnx2x_status) {
1218                 DP(NETIF_MSG_LINK,
1219                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1220                 return bnx2x_status;
1221         }
1222
1223         /* Set client mapping of BW and strict */
1224         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1225                                               cos_sp_bitmap,
1226                                               cos_bw_bitmap);
1227
1228         if (bnx2x_status) {
1229                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1230                 return bnx2x_status;
1231         }
1232         return 0;
1233 }
1234 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1235 {
1236         /* ETS disabled configuration */
1237         struct bnx2x *bp = params->bp;
1238         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1239         /* Defines which entries (clients) are subjected to WFQ arbitration
1240          * COS0 0x8
1241          * COS1 0x10
1242          */
1243         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1244         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1245          * client numbers (WEIGHT_0 does not actually have to represent
1246          * client 0)
1247          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1248          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1249          */
1250         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1251
1252         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1253                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1254         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1255                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1256
1257         /* ETS mode enabled*/
1258         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1259
1260         /* Defines the number of consecutive slots for the strict priority */
1261         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1262         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1263          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1264          * entry, 4 - COS1 entry.
1265          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1266          * bit4   bit3    bit2     bit1    bit0
1267          * MCP and debug are strict
1268          */
1269         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1270
1271         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1272         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1273                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1274         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1275                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1276 }
1277
1278 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1279                         const u32 cos1_bw)
1280 {
1281         /* ETS disabled configuration*/
1282         struct bnx2x *bp = params->bp;
1283         const u32 total_bw = cos0_bw + cos1_bw;
1284         u32 cos0_credit_weight = 0;
1285         u32 cos1_credit_weight = 0;
1286
1287         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1288
1289         if ((!total_bw) ||
1290             (!cos0_bw) ||
1291             (!cos1_bw)) {
1292                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1293                 return;
1294         }
1295
1296         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1297                 total_bw;
1298         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1299                 total_bw;
1300
1301         bnx2x_ets_bw_limit_common(params);
1302
1303         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1304         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1305
1306         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1307         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1308 }
1309
1310 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1311 {
1312         /* ETS disabled configuration*/
1313         struct bnx2x *bp = params->bp;
1314         u32 val = 0;
1315
1316         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1317         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1318          * as strict.  Bits 0,1,2 - debug and management entries,
1319          * 3 - COS0 entry, 4 - COS1 entry.
1320          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1321          *  bit4   bit3   bit2      bit1     bit0
1322          * MCP and debug are strict
1323          */
1324         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1325         /* For strict priority entries defines the number of consecutive slots
1326          * for the highest priority.
1327          */
1328         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1329         /* ETS mode disable */
1330         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1331         /* Defines the number of consecutive slots for the strict priority */
1332         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1333
1334         /* Defines the number of consecutive slots for the strict priority */
1335         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1336
1337         /* Mapping between entry  priority to client number (0,1,2 -debug and
1338          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1339          * 3bits client num.
1340          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1341          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1342          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1343          */
1344         val = (!strict_cos) ? 0x2318 : 0x22E0;
1345         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1346
1347         return 0;
1348 }
1349
1350 /******************************************************************/
1351 /*                      PFC section                               */
1352 /******************************************************************/
1353 static void bnx2x_update_pfc_xmac(struct link_params *params,
1354                                   struct link_vars *vars,
1355                                   u8 is_lb)
1356 {
1357         struct bnx2x *bp = params->bp;
1358         u32 xmac_base;
1359         u32 pause_val, pfc0_val, pfc1_val;
1360
1361         /* XMAC base adrr */
1362         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1363
1364         /* Initialize pause and pfc registers */
1365         pause_val = 0x18000;
1366         pfc0_val = 0xFFFF8000;
1367         pfc1_val = 0x2;
1368
1369         /* No PFC support */
1370         if (!(params->feature_config_flags &
1371               FEATURE_CONFIG_PFC_ENABLED)) {
1372
1373                 /* RX flow control - Process pause frame in receive direction
1374                  */
1375                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1376                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1377
1378                 /* TX flow control - Send pause packet when buffer is full */
1379                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1380                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1381         } else {/* PFC support */
1382                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1383                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1384                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1385                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1386                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1387                 /* Write pause and PFC registers */
1388                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1389                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1390                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1391                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1392
1393         }
1394
1395         /* Write pause and PFC registers */
1396         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1397         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1398         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1399
1400
1401         /* Set MAC address for source TX Pause/PFC frames */
1402         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1403                ((params->mac_addr[2] << 24) |
1404                 (params->mac_addr[3] << 16) |
1405                 (params->mac_addr[4] << 8) |
1406                 (params->mac_addr[5])));
1407         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1408                ((params->mac_addr[0] << 8) |
1409                 (params->mac_addr[1])));
1410
1411         udelay(30);
1412 }
1413
1414 /******************************************************************/
1415 /*                      MAC/PBF section                           */
1416 /******************************************************************/
1417 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1418                                u32 emac_base)
1419 {
1420         u32 new_mode, cur_mode;
1421         u32 clc_cnt;
1422         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1423          * (a value of 49==0x31) and make sure that the AUTO poll is off
1424          */
1425         cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1426
1427         if (USES_WARPCORE(bp))
1428                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1429         else
1430                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1431
1432         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1433             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1434                 return;
1435
1436         new_mode = cur_mode &
1437                 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1438         new_mode |= clc_cnt;
1439         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1440
1441         DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1442            cur_mode, new_mode);
1443         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1444         udelay(40);
1445 }
1446
1447 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1448                                         struct link_params *params)
1449 {
1450         u8 phy_index;
1451         /* Set mdio clock per phy */
1452         for (phy_index = INT_PHY; phy_index < params->num_phys;
1453               phy_index++)
1454                 bnx2x_set_mdio_clk(bp, params->chip_id,
1455                                    params->phy[phy_index].mdio_ctrl);
1456 }
1457
1458 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1459 {
1460         u32 port4mode_ovwr_val;
1461         /* Check 4-port override enabled */
1462         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1463         if (port4mode_ovwr_val & (1<<0)) {
1464                 /* Return 4-port mode override value */
1465                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1466         }
1467         /* Return 4-port mode from input pin */
1468         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1469 }
1470
1471 static void bnx2x_emac_init(struct link_params *params,
1472                             struct link_vars *vars)
1473 {
1474         /* reset and unreset the emac core */
1475         struct bnx2x *bp = params->bp;
1476         u8 port = params->port;
1477         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1478         u32 val;
1479         u16 timeout;
1480
1481         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1482                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1483         udelay(5);
1484         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1485                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1486
1487         /* init emac - use read-modify-write */
1488         /* self clear reset */
1489         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1490         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1491
1492         timeout = 200;
1493         do {
1494                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1495                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1496                 if (!timeout) {
1497                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1498                         return;
1499                 }
1500                 timeout--;
1501         } while (val & EMAC_MODE_RESET);
1502
1503         bnx2x_set_mdio_emac_per_phy(bp, params);
1504         /* Set mac address */
1505         val = ((params->mac_addr[0] << 8) |
1506                 params->mac_addr[1]);
1507         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1508
1509         val = ((params->mac_addr[2] << 24) |
1510                (params->mac_addr[3] << 16) |
1511                (params->mac_addr[4] << 8) |
1512                 params->mac_addr[5]);
1513         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1514 }
1515
1516 static void bnx2x_set_xumac_nig(struct link_params *params,
1517                                 u16 tx_pause_en,
1518                                 u8 enable)
1519 {
1520         struct bnx2x *bp = params->bp;
1521
1522         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1523                enable);
1524         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1525                enable);
1526         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1527                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1528 }
1529
1530 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1531 {
1532         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1533         u32 val;
1534         struct bnx2x *bp = params->bp;
1535         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1536                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1537                 return;
1538         val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1539         if (en)
1540                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1541                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1542         else
1543                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1544                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1545         /* Disable RX and TX */
1546         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1547 }
1548
1549 static void bnx2x_umac_enable(struct link_params *params,
1550                             struct link_vars *vars, u8 lb)
1551 {
1552         u32 val;
1553         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1554         struct bnx2x *bp = params->bp;
1555         /* Reset UMAC */
1556         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1557                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1558         usleep_range(1000, 2000);
1559
1560         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1561                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1562
1563         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1564
1565         /* This register opens the gate for the UMAC despite its name */
1566         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1567
1568         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1569                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1570                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1571                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1572         switch (vars->line_speed) {
1573         case SPEED_10:
1574                 val |= (0<<2);
1575                 break;
1576         case SPEED_100:
1577                 val |= (1<<2);
1578                 break;
1579         case SPEED_1000:
1580                 val |= (2<<2);
1581                 break;
1582         case SPEED_2500:
1583                 val |= (3<<2);
1584                 break;
1585         default:
1586                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1587                                vars->line_speed);
1588                 break;
1589         }
1590         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1591                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1592
1593         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1594                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1595
1596         if (vars->duplex == DUPLEX_HALF)
1597                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1598
1599         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1600         udelay(50);
1601
1602         /* Configure UMAC for EEE */
1603         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1604                 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1605                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1606                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1607                 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1608         } else {
1609                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1610         }
1611
1612         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1613         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1614                ((params->mac_addr[2] << 24) |
1615                 (params->mac_addr[3] << 16) |
1616                 (params->mac_addr[4] << 8) |
1617                 (params->mac_addr[5])));
1618         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1619                ((params->mac_addr[0] << 8) |
1620                 (params->mac_addr[1])));
1621
1622         /* Enable RX and TX */
1623         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1624         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1625                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1626         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1627         udelay(50);
1628
1629         /* Remove SW Reset */
1630         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1631
1632         /* Check loopback mode */
1633         if (lb)
1634                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1635         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1636
1637         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1638          * length used by the MAC receive logic to check frames.
1639          */
1640         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1641         bnx2x_set_xumac_nig(params,
1642                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1643         vars->mac_type = MAC_TYPE_UMAC;
1644
1645 }
1646
1647 /* Define the XMAC mode */
1648 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1649 {
1650         struct bnx2x *bp = params->bp;
1651         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1652
1653         /* In 4-port mode, need to set the mode only once, so if XMAC is
1654          * already out of reset, it means the mode has already been set,
1655          * and it must not* reset the XMAC again, since it controls both
1656          * ports of the path
1657          */
1658
1659         if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1660              (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1661              (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1662             is_port4mode &&
1663             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1664              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1665                 DP(NETIF_MSG_LINK,
1666                    "XMAC already out of reset in 4-port mode\n");
1667                 return;
1668         }
1669
1670         /* Hard reset */
1671         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1672                MISC_REGISTERS_RESET_REG_2_XMAC);
1673         usleep_range(1000, 2000);
1674
1675         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1676                MISC_REGISTERS_RESET_REG_2_XMAC);
1677         if (is_port4mode) {
1678                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1679
1680                 /* Set the number of ports on the system side to up to 2 */
1681                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1682
1683                 /* Set the number of ports on the Warp Core to 10G */
1684                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1685         } else {
1686                 /* Set the number of ports on the system side to 1 */
1687                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1688                 if (max_speed == SPEED_10000) {
1689                         DP(NETIF_MSG_LINK,
1690                            "Init XMAC to 10G x 1 port per path\n");
1691                         /* Set the number of ports on the Warp Core to 10G */
1692                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1693                 } else {
1694                         DP(NETIF_MSG_LINK,
1695                            "Init XMAC to 20G x 2 ports per path\n");
1696                         /* Set the number of ports on the Warp Core to 20G */
1697                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1698                 }
1699         }
1700         /* Soft reset */
1701         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1702                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1703         usleep_range(1000, 2000);
1704
1705         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1706                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1707
1708 }
1709
1710 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1711 {
1712         u8 port = params->port;
1713         struct bnx2x *bp = params->bp;
1714         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1715         u32 val;
1716
1717         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1718             MISC_REGISTERS_RESET_REG_2_XMAC) {
1719                 /* Send an indication to change the state in the NIG back to XON
1720                  * Clearing this bit enables the next set of this bit to get
1721                  * rising edge
1722                  */
1723                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1724                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1725                        (pfc_ctrl & ~(1<<1)));
1726                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1727                        (pfc_ctrl | (1<<1)));
1728                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1729                 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1730                 if (en)
1731                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1732                 else
1733                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1734                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1735         }
1736 }
1737
1738 static int bnx2x_xmac_enable(struct link_params *params,
1739                              struct link_vars *vars, u8 lb)
1740 {
1741         u32 val, xmac_base;
1742         struct bnx2x *bp = params->bp;
1743         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1744
1745         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1746
1747         bnx2x_xmac_init(params, vars->line_speed);
1748
1749         /* This register determines on which events the MAC will assert
1750          * error on the i/f to the NIG along w/ EOP.
1751          */
1752
1753         /* This register tells the NIG whether to send traffic to UMAC
1754          * or XMAC
1755          */
1756         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1757
1758         /* When XMAC is in XLGMII mode, disable sending idles for fault
1759          * detection.
1760          */
1761         if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1762                 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1763                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1764                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1765                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1766                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1767                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1768                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1769         }
1770         /* Set Max packet size */
1771         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1772
1773         /* CRC append for Tx packets */
1774         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1775
1776         /* update PFC */
1777         bnx2x_update_pfc_xmac(params, vars, 0);
1778
1779         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1780                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1781                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1782                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1783         } else {
1784                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1785         }
1786
1787         /* Enable TX and RX */
1788         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1789
1790         /* Set MAC in XLGMII mode for dual-mode */
1791         if ((vars->line_speed == SPEED_20000) &&
1792             (params->phy[INT_PHY].supported &
1793              SUPPORTED_20000baseKR2_Full))
1794                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1795
1796         /* Check loopback mode */
1797         if (lb)
1798                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1799         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1800         bnx2x_set_xumac_nig(params,
1801                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1802
1803         vars->mac_type = MAC_TYPE_XMAC;
1804
1805         return 0;
1806 }
1807
1808 static int bnx2x_emac_enable(struct link_params *params,
1809                              struct link_vars *vars, u8 lb)
1810 {
1811         struct bnx2x *bp = params->bp;
1812         u8 port = params->port;
1813         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1814         u32 val;
1815
1816         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1817
1818         /* Disable BMAC */
1819         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1820                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1821
1822         /* enable emac and not bmac */
1823         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1824
1825         /* ASIC */
1826         if (vars->phy_flags & PHY_XGXS_FLAG) {
1827                 u32 ser_lane = ((params->lane_config &
1828                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1829                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1830
1831                 DP(NETIF_MSG_LINK, "XGXS\n");
1832                 /* select the master lanes (out of 0-3) */
1833                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1834                 /* select XGXS */
1835                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1836
1837         } else { /* SerDes */
1838                 DP(NETIF_MSG_LINK, "SerDes\n");
1839                 /* select SerDes */
1840                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1841         }
1842
1843         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1844                       EMAC_RX_MODE_RESET);
1845         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1846                       EMAC_TX_MODE_RESET);
1847
1848                 /* pause enable/disable */
1849                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1850                                EMAC_RX_MODE_FLOW_EN);
1851
1852                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1853                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1854                                 EMAC_TX_MODE_FLOW_EN));
1855                 if (!(params->feature_config_flags &
1856                       FEATURE_CONFIG_PFC_ENABLED)) {
1857                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1858                                 bnx2x_bits_en(bp, emac_base +
1859                                               EMAC_REG_EMAC_RX_MODE,
1860                                               EMAC_RX_MODE_FLOW_EN);
1861
1862                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1863                                 bnx2x_bits_en(bp, emac_base +
1864                                               EMAC_REG_EMAC_TX_MODE,
1865                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1866                                                EMAC_TX_MODE_FLOW_EN));
1867                 } else
1868                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1869                                       EMAC_TX_MODE_FLOW_EN);
1870
1871         /* KEEP_VLAN_TAG, promiscuous */
1872         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1873         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1874
1875         /* Setting this bit causes MAC control frames (except for pause
1876          * frames) to be passed on for processing. This setting has no
1877          * affect on the operation of the pause frames. This bit effects
1878          * all packets regardless of RX Parser packet sorting logic.
1879          * Turn the PFC off to make sure we are in Xon state before
1880          * enabling it.
1881          */
1882         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1883         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1884                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1885                 /* Enable PFC again */
1886                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1887                         EMAC_REG_RX_PFC_MODE_RX_EN |
1888                         EMAC_REG_RX_PFC_MODE_TX_EN |
1889                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1890
1891                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1892                         ((0x0101 <<
1893                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1894                          (0x00ff <<
1895                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1896                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1897         }
1898         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1899
1900         /* Set Loopback */
1901         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1902         if (lb)
1903                 val |= 0x810;
1904         else
1905                 val &= ~0x810;
1906         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1907
1908         /* Enable emac */
1909         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1910
1911         /* Enable emac for jumbo packets */
1912         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1913                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1914                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD)));
1915
1916         /* Strip CRC */
1917         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1918
1919         /* Disable the NIG in/out to the bmac */
1920         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1921         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1922         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1923
1924         /* Enable the NIG in/out to the emac */
1925         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1926         val = 0;
1927         if ((params->feature_config_flags &
1928               FEATURE_CONFIG_PFC_ENABLED) ||
1929             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1930                 val = 1;
1931
1932         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1933         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1934
1935         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1936
1937         vars->mac_type = MAC_TYPE_EMAC;
1938         return 0;
1939 }
1940
1941 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1942                                    struct link_vars *vars)
1943 {
1944         u32 wb_data[2];
1945         struct bnx2x *bp = params->bp;
1946         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1947                 NIG_REG_INGRESS_BMAC0_MEM;
1948
1949         u32 val = 0x14;
1950         if ((!(params->feature_config_flags &
1951               FEATURE_CONFIG_PFC_ENABLED)) &&
1952                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1953                 /* Enable BigMAC to react on received Pause packets */
1954                 val |= (1<<5);
1955         wb_data[0] = val;
1956         wb_data[1] = 0;
1957         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1958
1959         /* TX control */
1960         val = 0xc0;
1961         if (!(params->feature_config_flags &
1962               FEATURE_CONFIG_PFC_ENABLED) &&
1963                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1964                 val |= 0x800000;
1965         wb_data[0] = val;
1966         wb_data[1] = 0;
1967         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1968 }
1969
1970 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1971                                    struct link_vars *vars,
1972                                    u8 is_lb)
1973 {
1974         /* Set rx control: Strip CRC and enable BigMAC to relay
1975          * control packets to the system as well
1976          */
1977         u32 wb_data[2];
1978         struct bnx2x *bp = params->bp;
1979         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1980                 NIG_REG_INGRESS_BMAC0_MEM;
1981         u32 val = 0x14;
1982
1983         if ((!(params->feature_config_flags &
1984               FEATURE_CONFIG_PFC_ENABLED)) &&
1985                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1986                 /* Enable BigMAC to react on received Pause packets */
1987                 val |= (1<<5);
1988         wb_data[0] = val;
1989         wb_data[1] = 0;
1990         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1991         udelay(30);
1992
1993         /* Tx control */
1994         val = 0xc0;
1995         if (!(params->feature_config_flags &
1996                                 FEATURE_CONFIG_PFC_ENABLED) &&
1997             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1998                 val |= 0x800000;
1999         wb_data[0] = val;
2000         wb_data[1] = 0;
2001         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2002
2003         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2004                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2005                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2006                 wb_data[0] = 0x0;
2007                 wb_data[0] |= (1<<0);  /* RX */
2008                 wb_data[0] |= (1<<1);  /* TX */
2009                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2010                 wb_data[0] |= (1<<3);  /* 8 cos */
2011                 wb_data[0] |= (1<<5);  /* STATS */
2012                 wb_data[1] = 0;
2013                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2014                             wb_data, 2);
2015                 /* Clear the force Xon */
2016                 wb_data[0] &= ~(1<<2);
2017         } else {
2018                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2019                 /* Disable PFC RX & TX & STATS and set 8 COS */
2020                 wb_data[0] = 0x8;
2021                 wb_data[1] = 0;
2022         }
2023
2024         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2025
2026         /* Set Time (based unit is 512 bit time) between automatic
2027          * re-sending of PP packets amd enable automatic re-send of
2028          * Per-Priroity Packet as long as pp_gen is asserted and
2029          * pp_disable is low.
2030          */
2031         val = 0x8000;
2032         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2033                 val |= (1<<16); /* enable automatic re-send */
2034
2035         wb_data[0] = val;
2036         wb_data[1] = 0;
2037         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2038                     wb_data, 2);
2039
2040         /* mac control */
2041         val = 0x3; /* Enable RX and TX */
2042         if (is_lb) {
2043                 val |= 0x4; /* Local loopback */
2044                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2045         }
2046         /* When PFC enabled, Pass pause frames towards the NIG. */
2047         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2048                 val |= ((1<<6)|(1<<5));
2049
2050         wb_data[0] = val;
2051         wb_data[1] = 0;
2052         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2053 }
2054
2055 /******************************************************************************
2056 * Description:
2057 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2058 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2059 ******************************************************************************/
2060 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2061                                            u8 cos_entry,
2062                                            u32 priority_mask, u8 port)
2063 {
2064         u32 nig_reg_rx_priority_mask_add = 0;
2065
2066         switch (cos_entry) {
2067         case 0:
2068              nig_reg_rx_priority_mask_add = (port) ?
2069                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2070                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2071              break;
2072         case 1:
2073             nig_reg_rx_priority_mask_add = (port) ?
2074                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2075                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2076             break;
2077         case 2:
2078             nig_reg_rx_priority_mask_add = (port) ?
2079                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2080                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2081             break;
2082         case 3:
2083             if (port)
2084                 return -EINVAL;
2085             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2086             break;
2087         case 4:
2088             if (port)
2089                 return -EINVAL;
2090             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2091             break;
2092         case 5:
2093             if (port)
2094                 return -EINVAL;
2095             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2096             break;
2097         }
2098
2099         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2100
2101         return 0;
2102 }
2103 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2104 {
2105         struct bnx2x *bp = params->bp;
2106
2107         REG_WR(bp, params->shmem_base +
2108                offsetof(struct shmem_region,
2109                         port_mb[params->port].link_status), link_status);
2110 }
2111
2112 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2113 {
2114         struct bnx2x *bp = params->bp;
2115
2116         if (SHMEM2_HAS(bp, link_attr_sync))
2117                 REG_WR(bp, params->shmem2_base +
2118                        offsetof(struct shmem2_region,
2119                                 link_attr_sync[params->port]), link_attr);
2120 }
2121
2122 static void bnx2x_update_pfc_nig(struct link_params *params,
2123                 struct link_vars *vars,
2124                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2125 {
2126         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2127         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2128         u32 pkt_priority_to_cos = 0;
2129         struct bnx2x *bp = params->bp;
2130         u8 port = params->port;
2131
2132         int set_pfc = params->feature_config_flags &
2133                 FEATURE_CONFIG_PFC_ENABLED;
2134         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2135
2136         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2137          * MAC control frames (that are not pause packets)
2138          * will be forwarded to the XCM.
2139          */
2140         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2141                           NIG_REG_LLH0_XCM_MASK);
2142         /* NIG params will override non PFC params, since it's possible to
2143          * do transition from PFC to SAFC
2144          */
2145         if (set_pfc) {
2146                 pause_enable = 0;
2147                 llfc_out_en = 0;
2148                 llfc_enable = 0;
2149                 if (CHIP_IS_E3(bp))
2150                         ppp_enable = 0;
2151                 else
2152                         ppp_enable = 1;
2153                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2154                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2155                 xcm_out_en = 0;
2156                 hwpfc_enable = 1;
2157         } else  {
2158                 if (nig_params) {
2159                         llfc_out_en = nig_params->llfc_out_en;
2160                         llfc_enable = nig_params->llfc_enable;
2161                         pause_enable = nig_params->pause_enable;
2162                 } else  /* Default non PFC mode - PAUSE */
2163                         pause_enable = 1;
2164
2165                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2166                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2167                 xcm_out_en = 1;
2168         }
2169
2170         if (CHIP_IS_E3(bp))
2171                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2172                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2173         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2174                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2175         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2176                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2177         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2178                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2179
2180         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2181                NIG_REG_PPP_ENABLE_0, ppp_enable);
2182
2183         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2184                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2185
2186         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2187                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2188
2189         /* Output enable for RX_XCM # IF */
2190         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2191                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2192
2193         /* HW PFC TX enable */
2194         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2195                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2196
2197         if (nig_params) {
2198                 u8 i = 0;
2199                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2200
2201                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2202                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2203                 nig_params->rx_cos_priority_mask[i], port);
2204
2205                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2206                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2207                        nig_params->llfc_high_priority_classes);
2208
2209                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2210                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2211                        nig_params->llfc_low_priority_classes);
2212         }
2213         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2214                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2215                pkt_priority_to_cos);
2216 }
2217
2218 int bnx2x_update_pfc(struct link_params *params,
2219                       struct link_vars *vars,
2220                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2221 {
2222         /* The PFC and pause are orthogonal to one another, meaning when
2223          * PFC is enabled, the pause are disabled, and when PFC is
2224          * disabled, pause are set according to the pause result.
2225          */
2226         u32 val;
2227         struct bnx2x *bp = params->bp;
2228         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2229
2230         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2231                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2232         else
2233                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2234
2235         bnx2x_update_mng(params, vars->link_status);
2236
2237         /* Update NIG params */
2238         bnx2x_update_pfc_nig(params, vars, pfc_params);
2239
2240         if (!vars->link_up)
2241                 return 0;
2242
2243         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2244
2245         if (CHIP_IS_E3(bp)) {
2246                 if (vars->mac_type == MAC_TYPE_XMAC)
2247                         bnx2x_update_pfc_xmac(params, vars, 0);
2248         } else {
2249                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2250                 if ((val &
2251                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2252                     == 0) {
2253                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2254                         bnx2x_emac_enable(params, vars, 0);
2255                         return 0;
2256                 }
2257                 if (CHIP_IS_E2(bp))
2258                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2259                 else
2260                         bnx2x_update_pfc_bmac1(params, vars);
2261
2262                 val = 0;
2263                 if ((params->feature_config_flags &
2264                      FEATURE_CONFIG_PFC_ENABLED) ||
2265                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2266                         val = 1;
2267                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2268         }
2269         return 0;
2270 }
2271
2272 static int bnx2x_bmac1_enable(struct link_params *params,
2273                               struct link_vars *vars,
2274                               u8 is_lb)
2275 {
2276         struct bnx2x *bp = params->bp;
2277         u8 port = params->port;
2278         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2279                                NIG_REG_INGRESS_BMAC0_MEM;
2280         u32 wb_data[2];
2281         u32 val;
2282
2283         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2284
2285         /* XGXS control */
2286         wb_data[0] = 0x3c;
2287         wb_data[1] = 0;
2288         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2289                     wb_data, 2);
2290
2291         /* TX MAC SA */
2292         wb_data[0] = ((params->mac_addr[2] << 24) |
2293                        (params->mac_addr[3] << 16) |
2294                        (params->mac_addr[4] << 8) |
2295                         params->mac_addr[5]);
2296         wb_data[1] = ((params->mac_addr[0] << 8) |
2297                         params->mac_addr[1]);
2298         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2299
2300         /* MAC control */
2301         val = 0x3;
2302         if (is_lb) {
2303                 val |= 0x4;
2304                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2305         }
2306         wb_data[0] = val;
2307         wb_data[1] = 0;
2308         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2309
2310         /* Set rx mtu */
2311         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2312         wb_data[1] = 0;
2313         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2314
2315         bnx2x_update_pfc_bmac1(params, vars);
2316
2317         /* Set tx mtu */
2318         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2319         wb_data[1] = 0;
2320         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2321
2322         /* Set cnt max size */
2323         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2324         wb_data[1] = 0;
2325         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2326
2327         /* Configure SAFC */
2328         wb_data[0] = 0x1000200;
2329         wb_data[1] = 0;
2330         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2331                     wb_data, 2);
2332
2333         return 0;
2334 }
2335
2336 static int bnx2x_bmac2_enable(struct link_params *params,
2337                               struct link_vars *vars,
2338                               u8 is_lb)
2339 {
2340         struct bnx2x *bp = params->bp;
2341         u8 port = params->port;
2342         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2343                                NIG_REG_INGRESS_BMAC0_MEM;
2344         u32 wb_data[2];
2345
2346         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2347
2348         wb_data[0] = 0;
2349         wb_data[1] = 0;
2350         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2351         udelay(30);
2352
2353         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2354         wb_data[0] = 0x3c;
2355         wb_data[1] = 0;
2356         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2357                     wb_data, 2);
2358
2359         udelay(30);
2360
2361         /* TX MAC SA */
2362         wb_data[0] = ((params->mac_addr[2] << 24) |
2363                        (params->mac_addr[3] << 16) |
2364                        (params->mac_addr[4] << 8) |
2365                         params->mac_addr[5]);
2366         wb_data[1] = ((params->mac_addr[0] << 8) |
2367                         params->mac_addr[1]);
2368         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2369                     wb_data, 2);
2370
2371         udelay(30);
2372
2373         /* Configure SAFC */
2374         wb_data[0] = 0x1000200;
2375         wb_data[1] = 0;
2376         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2377                     wb_data, 2);
2378         udelay(30);
2379
2380         /* Set RX MTU */
2381         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2382         wb_data[1] = 0;
2383         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2384         udelay(30);
2385
2386         /* Set TX MTU */
2387         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2388         wb_data[1] = 0;
2389         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2390         udelay(30);
2391         /* Set cnt max size */
2392         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD - 2;
2393         wb_data[1] = 0;
2394         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2395         udelay(30);
2396         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2397
2398         return 0;
2399 }
2400
2401 static int bnx2x_bmac_enable(struct link_params *params,
2402                              struct link_vars *vars,
2403                              u8 is_lb, u8 reset_bmac)
2404 {
2405         int rc = 0;
2406         u8 port = params->port;
2407         struct bnx2x *bp = params->bp;
2408         u32 val;
2409         /* Reset and unreset the BigMac */
2410         if (reset_bmac) {
2411                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2412                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2413                 usleep_range(1000, 2000);
2414         }
2415
2416         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2417                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2418
2419         /* Enable access for bmac registers */
2420         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2421
2422         /* Enable BMAC according to BMAC type*/
2423         if (CHIP_IS_E2(bp))
2424                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2425         else
2426                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2427         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2428         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2429         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2430         val = 0;
2431         if ((params->feature_config_flags &
2432               FEATURE_CONFIG_PFC_ENABLED) ||
2433             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2434                 val = 1;
2435         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2436         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2437         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2438         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2439         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2440         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2441
2442         vars->mac_type = MAC_TYPE_BMAC;
2443         return rc;
2444 }
2445
2446 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2447 {
2448         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2449                         NIG_REG_INGRESS_BMAC0_MEM;
2450         u32 wb_data[2];
2451         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2452
2453         if (CHIP_IS_E2(bp))
2454                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2455         else
2456                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2457         /* Only if the bmac is out of reset */
2458         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2459                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2460             nig_bmac_enable) {
2461                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2462                 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2463                 if (en)
2464                         wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2465                 else
2466                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2467                 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2468                 usleep_range(1000, 2000);
2469         }
2470 }
2471
2472 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2473                             u32 line_speed)
2474 {
2475         struct bnx2x *bp = params->bp;
2476         u8 port = params->port;
2477         u32 init_crd, crd;
2478         u32 count = 1000;
2479
2480         /* Disable port */
2481         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2482
2483         /* Wait for init credit */
2484         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2485         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2486         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2487
2488         while ((init_crd != crd) && count) {
2489                 usleep_range(5000, 10000);
2490                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2491                 count--;
2492         }
2493         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2494         if (init_crd != crd) {
2495                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2496                           init_crd, crd);
2497                 return -EINVAL;
2498         }
2499
2500         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2501             line_speed == SPEED_10 ||
2502             line_speed == SPEED_100 ||
2503             line_speed == SPEED_1000 ||
2504             line_speed == SPEED_2500) {
2505                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2506                 /* Update threshold */
2507                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2508                 /* Update init credit */
2509                 init_crd = 778;         /* (800-18-4) */
2510
2511         } else {
2512                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2513                               ETH_OVERHEAD)/16;
2514                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2515                 /* Update threshold */
2516                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2517                 /* Update init credit */
2518                 switch (line_speed) {
2519                 case SPEED_10000:
2520                         init_crd = thresh + 553 - 22;
2521                         break;
2522                 default:
2523                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2524                                   line_speed);
2525                         return -EINVAL;
2526                 }
2527         }
2528         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2529         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2530                  line_speed, init_crd);
2531
2532         /* Probe the credit changes */
2533         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2534         usleep_range(5000, 10000);
2535         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2536
2537         /* Enable port */
2538         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2539         return 0;
2540 }
2541
2542 /**
2543  * bnx2x_get_emac_base - retrive emac base address
2544  *
2545  * @bp:                 driver handle
2546  * @mdc_mdio_access:    access type
2547  * @port:               port id
2548  *
2549  * This function selects the MDC/MDIO access (through emac0 or
2550  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2551  * phy has a default access mode, which could also be overridden
2552  * by nvram configuration. This parameter, whether this is the
2553  * default phy configuration, or the nvram overrun
2554  * configuration, is passed here as mdc_mdio_access and selects
2555  * the emac_base for the CL45 read/writes operations
2556  */
2557 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2558                                u32 mdc_mdio_access, u8 port)
2559 {
2560         u32 emac_base = 0;
2561         switch (mdc_mdio_access) {
2562         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2563                 break;
2564         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2565                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2566                         emac_base = GRCBASE_EMAC1;
2567                 else
2568                         emac_base = GRCBASE_EMAC0;
2569                 break;
2570         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2571                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2572                         emac_base = GRCBASE_EMAC0;
2573                 else
2574                         emac_base = GRCBASE_EMAC1;
2575                 break;
2576         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2577                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2578                 break;
2579         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2580                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2581                 break;
2582         default:
2583                 break;
2584         }
2585         return emac_base;
2586
2587 }
2588
2589 /******************************************************************/
2590 /*                      CL22 access functions                     */
2591 /******************************************************************/
2592 static int bnx2x_cl22_write(struct bnx2x *bp,
2593                                        struct bnx2x_phy *phy,
2594                                        u16 reg, u16 val)
2595 {
2596         u32 tmp, mode;
2597         u8 i;
2598         int rc = 0;
2599         /* Switch to CL22 */
2600         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2601         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2602                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2603
2604         /* Address */
2605         tmp = ((phy->addr << 21) | (reg << 16) | val |
2606                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2607                EMAC_MDIO_COMM_START_BUSY);
2608         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2609
2610         for (i = 0; i < 50; i++) {
2611                 udelay(10);
2612
2613                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2614                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2615                         udelay(5);
2616                         break;
2617                 }
2618         }
2619         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2620                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2621                 rc = -EFAULT;
2622         }
2623         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2624         return rc;
2625 }
2626
2627 static int bnx2x_cl22_read(struct bnx2x *bp,
2628                                       struct bnx2x_phy *phy,
2629                                       u16 reg, u16 *ret_val)
2630 {
2631         u32 val, mode;
2632         u16 i;
2633         int rc = 0;
2634
2635         /* Switch to CL22 */
2636         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2637         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2638                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2639
2640         /* Address */
2641         val = ((phy->addr << 21) | (reg << 16) |
2642                EMAC_MDIO_COMM_COMMAND_READ_22 |
2643                EMAC_MDIO_COMM_START_BUSY);
2644         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2645
2646         for (i = 0; i < 50; i++) {
2647                 udelay(10);
2648
2649                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2650                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2651                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2652                         udelay(5);
2653                         break;
2654                 }
2655         }
2656         if (val & EMAC_MDIO_COMM_START_BUSY) {
2657                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2658
2659                 *ret_val = 0;
2660                 rc = -EFAULT;
2661         }
2662         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2663         return rc;
2664 }
2665
2666 /******************************************************************/
2667 /*                      CL45 access functions                     */
2668 /******************************************************************/
2669 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2670                            u8 devad, u16 reg, u16 *ret_val)
2671 {
2672         u32 val;
2673         u16 i;
2674         int rc = 0;
2675         u32 chip_id;
2676         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2677                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2678                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2679                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2680         }
2681
2682         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2683                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2684                               EMAC_MDIO_STATUS_10MB);
2685         /* Address */
2686         val = ((phy->addr << 21) | (devad << 16) | reg |
2687                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2688                EMAC_MDIO_COMM_START_BUSY);
2689         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2690
2691         for (i = 0; i < 50; i++) {
2692                 udelay(10);
2693
2694                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2695                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2696                         udelay(5);
2697                         break;
2698                 }
2699         }
2700         if (val & EMAC_MDIO_COMM_START_BUSY) {
2701                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2702                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2703                 *ret_val = 0;
2704                 rc = -EFAULT;
2705         } else {
2706                 /* Data */
2707                 val = ((phy->addr << 21) | (devad << 16) |
2708                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2709                        EMAC_MDIO_COMM_START_BUSY);
2710                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2711
2712                 for (i = 0; i < 50; i++) {
2713                         udelay(10);
2714
2715                         val = REG_RD(bp, phy->mdio_ctrl +
2716                                      EMAC_REG_EMAC_MDIO_COMM);
2717                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2718                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2719                                 break;
2720                         }
2721                 }
2722                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2723                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2724                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2725                         *ret_val = 0;
2726                         rc = -EFAULT;
2727                 }
2728         }
2729         /* Work around for E3 A0 */
2730         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2731                 phy->flags ^= FLAGS_DUMMY_READ;
2732                 if (phy->flags & FLAGS_DUMMY_READ) {
2733                         u16 temp_val;
2734                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2735                 }
2736         }
2737
2738         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2739                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2740                                EMAC_MDIO_STATUS_10MB);
2741         return rc;
2742 }
2743
2744 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2745                             u8 devad, u16 reg, u16 val)
2746 {
2747         u32 tmp;
2748         u8 i;
2749         int rc = 0;
2750         u32 chip_id;
2751         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2752                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2753                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2754                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2755         }
2756
2757         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2758                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2759                               EMAC_MDIO_STATUS_10MB);
2760
2761         /* Address */
2762         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2763                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2764                EMAC_MDIO_COMM_START_BUSY);
2765         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2766
2767         for (i = 0; i < 50; i++) {
2768                 udelay(10);
2769
2770                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2771                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2772                         udelay(5);
2773                         break;
2774                 }
2775         }
2776         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2777                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2778                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2779                 rc = -EFAULT;
2780         } else {
2781                 /* Data */
2782                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2783                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2784                        EMAC_MDIO_COMM_START_BUSY);
2785                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2786
2787                 for (i = 0; i < 50; i++) {
2788                         udelay(10);
2789
2790                         tmp = REG_RD(bp, phy->mdio_ctrl +
2791                                      EMAC_REG_EMAC_MDIO_COMM);
2792                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2793                                 udelay(5);
2794                                 break;
2795                         }
2796                 }
2797                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2798                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2799                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2800                         rc = -EFAULT;
2801                 }
2802         }
2803         /* Work around for E3 A0 */
2804         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2805                 phy->flags ^= FLAGS_DUMMY_READ;
2806                 if (phy->flags & FLAGS_DUMMY_READ) {
2807                         u16 temp_val;
2808                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2809                 }
2810         }
2811         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2812                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2813                                EMAC_MDIO_STATUS_10MB);
2814         return rc;
2815 }
2816
2817 /******************************************************************/
2818 /*                      EEE section                                */
2819 /******************************************************************/
2820 static u8 bnx2x_eee_has_cap(struct link_params *params)
2821 {
2822         struct bnx2x *bp = params->bp;
2823
2824         if (REG_RD(bp, params->shmem2_base) <=
2825                    offsetof(struct shmem2_region, eee_status[params->port]))
2826                 return 0;
2827
2828         return 1;
2829 }
2830
2831 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2832 {
2833         switch (nvram_mode) {
2834         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2835                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2836                 break;
2837         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2838                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2839                 break;
2840         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2841                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2842                 break;
2843         default:
2844                 *idle_timer = 0;
2845                 break;
2846         }
2847
2848         return 0;
2849 }
2850
2851 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2852 {
2853         switch (idle_timer) {
2854         case EEE_MODE_NVRAM_BALANCED_TIME:
2855                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2856                 break;
2857         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2858                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2859                 break;
2860         case EEE_MODE_NVRAM_LATENCY_TIME:
2861                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2862                 break;
2863         default:
2864                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2865                 break;
2866         }
2867
2868         return 0;
2869 }
2870
2871 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2872 {
2873         u32 eee_mode, eee_idle;
2874         struct bnx2x *bp = params->bp;
2875
2876         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2877                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2878                         /* time value in eee_mode --> used directly*/
2879                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2880                 } else {
2881                         /* hsi value in eee_mode --> time */
2882                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
2883                                                     EEE_MODE_NVRAM_MASK,
2884                                                     &eee_idle))
2885                                 return 0;
2886                 }
2887         } else {
2888                 /* hsi values in nvram --> time*/
2889                 eee_mode = ((REG_RD(bp, params->shmem_base +
2890                                     offsetof(struct shmem_region, dev_info.
2891                                     port_feature_config[params->port].
2892                                     eee_power_mode)) &
2893                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2894                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2895
2896                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2897                         return 0;
2898         }
2899
2900         return eee_idle;
2901 }
2902
2903 static int bnx2x_eee_set_timers(struct link_params *params,
2904                                    struct link_vars *vars)
2905 {
2906         u32 eee_idle = 0, eee_mode;
2907         struct bnx2x *bp = params->bp;
2908
2909         eee_idle = bnx2x_eee_calc_timer(params);
2910
2911         if (eee_idle) {
2912                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2913                        eee_idle);
2914         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2915                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2916                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2917                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2918                 return -EINVAL;
2919         }
2920
2921         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2922         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2923                 /* eee_idle in 1u --> eee_status in 16u */
2924                 eee_idle >>= 4;
2925                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2926                                     SHMEM_EEE_TIME_OUTPUT_BIT;
2927         } else {
2928                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2929                         return -EINVAL;
2930                 vars->eee_status |= eee_mode;
2931         }
2932
2933         return 0;
2934 }
2935
2936 static int bnx2x_eee_initial_config(struct link_params *params,
2937                                      struct link_vars *vars, u8 mode)
2938 {
2939         vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2940
2941         /* Propagate params' bits --> vars (for migration exposure) */
2942         if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2943                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2944         else
2945                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2946
2947         if (params->eee_mode & EEE_MODE_ADV_LPI)
2948                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2949         else
2950                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2951
2952         return bnx2x_eee_set_timers(params, vars);
2953 }
2954
2955 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2956                                 struct link_params *params,
2957                                 struct link_vars *vars)
2958 {
2959         struct bnx2x *bp = params->bp;
2960
2961         /* Make Certain LPI is disabled */
2962         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2963
2964         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2965
2966         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2967
2968         return 0;
2969 }
2970
2971 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
2972                                   struct link_params *params,
2973                                   struct link_vars *vars, u8 modes)
2974 {
2975         struct bnx2x *bp = params->bp;
2976         u16 val = 0;
2977
2978         /* Mask events preventing LPI generation */
2979         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2980
2981         if (modes & SHMEM_EEE_10G_ADV) {
2982                 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
2983                 val |= 0x8;
2984         }
2985         if (modes & SHMEM_EEE_1G_ADV) {
2986                 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
2987                 val |= 0x4;
2988         }
2989
2990         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2991
2992         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2993         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
2994
2995         return 0;
2996 }
2997
2998 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
2999 {
3000         struct bnx2x *bp = params->bp;
3001
3002         if (bnx2x_eee_has_cap(params))
3003                 REG_WR(bp, params->shmem2_base +
3004                        offsetof(struct shmem2_region,
3005                                 eee_status[params->port]), eee_status);
3006 }
3007
3008 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3009                                   struct link_params *params,
3010                                   struct link_vars *vars)
3011 {
3012         struct bnx2x *bp = params->bp;
3013         u16 adv = 0, lp = 0;
3014         u32 lp_adv = 0;
3015         u8 neg = 0;
3016
3017         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3018         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3019
3020         if (lp & 0x2) {
3021                 lp_adv |= SHMEM_EEE_100M_ADV;
3022                 if (adv & 0x2) {
3023                         if (vars->line_speed == SPEED_100)
3024                                 neg = 1;
3025                         DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3026                 }
3027         }
3028         if (lp & 0x14) {
3029                 lp_adv |= SHMEM_EEE_1G_ADV;
3030                 if (adv & 0x14) {
3031                         if (vars->line_speed == SPEED_1000)
3032                                 neg = 1;
3033                         DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3034                 }
3035         }
3036         if (lp & 0x68) {
3037                 lp_adv |= SHMEM_EEE_10G_ADV;
3038                 if (adv & 0x68) {
3039                         if (vars->line_speed == SPEED_10000)
3040                                 neg = 1;
3041                         DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3042                 }
3043         }
3044
3045         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3046         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3047
3048         if (neg) {
3049                 DP(NETIF_MSG_LINK, "EEE is active\n");
3050                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3051         }
3052
3053 }
3054
3055 /******************************************************************/
3056 /*                      BSC access functions from E3              */
3057 /******************************************************************/
3058 static void bnx2x_bsc_module_sel(struct link_params *params)
3059 {
3060         int idx;
3061         u32 board_cfg, sfp_ctrl;
3062         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3063         struct bnx2x *bp = params->bp;
3064         u8 port = params->port;
3065         /* Read I2C output PINs */
3066         board_cfg = REG_RD(bp, params->shmem_base +
3067                            offsetof(struct shmem_region,
3068                                     dev_info.shared_hw_config.board));
3069         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3070         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3071                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3072
3073         /* Read I2C output value */
3074         sfp_ctrl = REG_RD(bp, params->shmem_base +
3075                           offsetof(struct shmem_region,
3076                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3077         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3078         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3079         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3080         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3081                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3082 }
3083
3084 static int bnx2x_bsc_read(struct link_params *params,
3085                           struct bnx2x *bp,
3086                           u8 sl_devid,
3087                           u16 sl_addr,
3088                           u8 lc_addr,
3089                           u8 xfer_cnt,
3090                           u32 *data_array)
3091 {
3092         u32 val, i;
3093         int rc = 0;
3094
3095         if (xfer_cnt > 16) {
3096                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3097                                         xfer_cnt);
3098                 return -EINVAL;
3099         }
3100         bnx2x_bsc_module_sel(params);
3101
3102         xfer_cnt = 16 - lc_addr;
3103
3104         /* Enable the engine */
3105         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3106         val |= MCPR_IMC_COMMAND_ENABLE;
3107         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3108
3109         /* Program slave device ID */
3110         val = (sl_devid << 16) | sl_addr;
3111         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3112
3113         /* Start xfer with 0 byte to update the address pointer ???*/
3114         val = (MCPR_IMC_COMMAND_ENABLE) |
3115               (MCPR_IMC_COMMAND_WRITE_OP <<
3116                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3117                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3118         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3119
3120         /* Poll for completion */
3121         i = 0;
3122         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3123         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3124                 udelay(10);
3125                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3126                 if (i++ > 1000) {
3127                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3128                                                                 i);
3129                         rc = -EFAULT;
3130                         break;
3131                 }
3132         }
3133         if (rc == -EFAULT)
3134                 return rc;
3135
3136         /* Start xfer with read op */
3137         val = (MCPR_IMC_COMMAND_ENABLE) |
3138                 (MCPR_IMC_COMMAND_READ_OP <<
3139                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3140                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3141                   (xfer_cnt);
3142         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3143
3144         /* Poll for completion */
3145         i = 0;
3146         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3147         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3148                 udelay(10);
3149                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3150                 if (i++ > 1000) {
3151                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3152                         rc = -EFAULT;
3153                         break;
3154                 }
3155         }
3156         if (rc == -EFAULT)
3157                 return rc;
3158
3159         for (i = (lc_addr >> 2); i < 4; i++) {
3160                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3161 #ifdef __BIG_ENDIAN
3162                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3163                                 ((data_array[i] & 0x0000ff00) << 8) |
3164                                 ((data_array[i] & 0x00ff0000) >> 8) |
3165                                 ((data_array[i] & 0xff000000) >> 24);
3166 #endif
3167         }
3168         return rc;
3169 }
3170
3171 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3172                                      u8 devad, u16 reg, u16 or_val)
3173 {
3174         u16 val;
3175         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3176         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3177 }
3178
3179 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3180                                       struct bnx2x_phy *phy,
3181                                       u8 devad, u16 reg, u16 and_val)
3182 {
3183         u16 val;
3184         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3185         bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3186 }
3187
3188 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3189                    u8 devad, u16 reg, u16 *ret_val)
3190 {
3191         u8 phy_index;
3192         /* Probe for the phy according to the given phy_addr, and execute
3193          * the read request on it
3194          */
3195         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3196                 if (params->phy[phy_index].addr == phy_addr) {
3197                         return bnx2x_cl45_read(params->bp,
3198                                                &params->phy[phy_index], devad,
3199                                                reg, ret_val);
3200                 }
3201         }
3202         return -EINVAL;
3203 }
3204
3205 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3206                     u8 devad, u16 reg, u16 val)
3207 {
3208         u8 phy_index;
3209         /* Probe for the phy according to the given phy_addr, and execute
3210          * the write request on it
3211          */
3212         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3213                 if (params->phy[phy_index].addr == phy_addr) {
3214                         return bnx2x_cl45_write(params->bp,
3215                                                 &params->phy[phy_index], devad,
3216                                                 reg, val);
3217                 }
3218         }
3219         return -EINVAL;
3220 }
3221 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3222                                   struct link_params *params)
3223 {
3224         u8 lane = 0;
3225         struct bnx2x *bp = params->bp;
3226         u32 path_swap, path_swap_ovr;
3227         u8 path, port;
3228
3229         path = BP_PATH(bp);
3230         port = params->port;
3231
3232         if (bnx2x_is_4_port_mode(bp)) {
3233                 u32 port_swap, port_swap_ovr;
3234
3235                 /* Figure out path swap value */
3236                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3237                 if (path_swap_ovr & 0x1)
3238                         path_swap = (path_swap_ovr & 0x2);
3239                 else
3240                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3241
3242                 if (path_swap)
3243                         path = path ^ 1;
3244
3245                 /* Figure out port swap value */
3246                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3247                 if (port_swap_ovr & 0x1)
3248                         port_swap = (port_swap_ovr & 0x2);
3249                 else
3250                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3251
3252                 if (port_swap)
3253                         port = port ^ 1;
3254
3255                 lane = (port<<1) + path;
3256         } else { /* Two port mode - no port swap */
3257
3258                 /* Figure out path swap value */
3259                 path_swap_ovr =
3260                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3261                 if (path_swap_ovr & 0x1) {
3262                         path_swap = (path_swap_ovr & 0x2);
3263                 } else {
3264                         path_swap =
3265                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3266                 }
3267                 if (path_swap)
3268                         path = path ^ 1;
3269
3270                 lane = path << 1 ;
3271         }
3272         return lane;
3273 }
3274
3275 static void bnx2x_set_aer_mmd(struct link_params *params,
3276                               struct bnx2x_phy *phy)
3277 {
3278         u32 ser_lane;
3279         u16 offset, aer_val;
3280         struct bnx2x *bp = params->bp;
3281         ser_lane = ((params->lane_config &
3282                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3283                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3284
3285         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3286                 (phy->addr + ser_lane) : 0;
3287
3288         if (USES_WARPCORE(bp)) {
3289                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3290                 /* In Dual-lane mode, two lanes are joined together,
3291                  * so in order to configure them, the AER broadcast method is
3292                  * used here.
3293                  * 0x200 is the broadcast address for lanes 0,1
3294                  * 0x201 is the broadcast address for lanes 2,3
3295                  */
3296                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3297                         aer_val = (aer_val >> 1) | 0x200;
3298         } else if (CHIP_IS_E2(bp))
3299                 aer_val = 0x3800 + offset - 1;
3300         else
3301                 aer_val = 0x3800 + offset;
3302
3303         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3304                           MDIO_AER_BLOCK_AER_REG, aer_val);
3305
3306 }
3307
3308 /******************************************************************/
3309 /*                      Internal phy section                      */
3310 /******************************************************************/
3311
3312 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3313 {
3314         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3315
3316         /* Set Clause 22 */
3317         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3318         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3319         udelay(500);
3320         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3321         udelay(500);
3322          /* Set Clause 45 */
3323         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3324 }
3325
3326 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3327 {
3328         u32 val;
3329
3330         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3331
3332         val = SERDES_RESET_BITS << (port*16);
3333
3334         /* Reset and unreset the SerDes/XGXS */
3335         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3336         udelay(500);
3337         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3338
3339         bnx2x_set_serdes_access(bp, port);
3340
3341         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3342                DEFAULT_PHY_DEV_ADDR);
3343 }
3344
3345 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3346                                      struct link_params *params,
3347                                      u32 action)
3348 {
3349         struct bnx2x *bp = params->bp;
3350         switch (action) {
3351         case PHY_INIT:
3352                 /* Set correct devad */
3353                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3354                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3355                        phy->def_md_devad);
3356                 break;
3357         }
3358 }
3359
3360 static void bnx2x_xgxs_deassert(struct link_params *params)
3361 {
3362         struct bnx2x *bp = params->bp;
3363         u8 port;
3364         u32 val;
3365         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3366         port = params->port;
3367
3368         val = XGXS_RESET_BITS << (port*16);
3369
3370         /* Reset and unreset the SerDes/XGXS */
3371         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3372         udelay(500);
3373         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3374         bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3375                                  PHY_INIT);
3376 }
3377
3378 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3379                                      struct link_params *params, u16 *ieee_fc)
3380 {
3381         struct bnx2x *bp = params->bp;
3382         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3383         /* Resolve pause mode and advertisement Please refer to Table
3384          * 28B-3 of the 802.3ab-1999 spec
3385          */
3386
3387         switch (phy->req_flow_ctrl) {
3388         case BNX2X_FLOW_CTRL_AUTO:
3389                 switch (params->req_fc_auto_adv) {
3390                 case BNX2X_FLOW_CTRL_BOTH:
3391                 case BNX2X_FLOW_CTRL_RX:
3392                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3393                         break;
3394                 case BNX2X_FLOW_CTRL_TX:
3395                         *ieee_fc |=
3396                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3397                         break;
3398                 default:
3399                         break;
3400                 }
3401                 break;
3402         case BNX2X_FLOW_CTRL_TX:
3403                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3404                 break;
3405
3406         case BNX2X_FLOW_CTRL_RX:
3407         case BNX2X_FLOW_CTRL_BOTH:
3408                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3409                 break;
3410
3411         case BNX2X_FLOW_CTRL_NONE:
3412         default:
3413                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3414                 break;
3415         }
3416         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3417 }
3418
3419 static void set_phy_vars(struct link_params *params,
3420                          struct link_vars *vars)
3421 {
3422         struct bnx2x *bp = params->bp;
3423         u8 actual_phy_idx, phy_index, link_cfg_idx;
3424         u8 phy_config_swapped = params->multi_phy_config &
3425                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3426         for (phy_index = INT_PHY; phy_index < params->num_phys;
3427               phy_index++) {
3428                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3429                 actual_phy_idx = phy_index;
3430                 if (phy_config_swapped) {
3431                         if (phy_index == EXT_PHY1)
3432                                 actual_phy_idx = EXT_PHY2;
3433                         else if (phy_index == EXT_PHY2)
3434                                 actual_phy_idx = EXT_PHY1;
3435                 }
3436                 params->phy[actual_phy_idx].req_flow_ctrl =
3437                         params->req_flow_ctrl[link_cfg_idx];
3438
3439                 params->phy[actual_phy_idx].req_line_speed =
3440                         params->req_line_speed[link_cfg_idx];
3441
3442                 params->phy[actual_phy_idx].speed_cap_mask =
3443                         params->speed_cap_mask[link_cfg_idx];
3444
3445                 params->phy[actual_phy_idx].req_duplex =
3446                         params->req_duplex[link_cfg_idx];
3447
3448                 if (params->req_line_speed[link_cfg_idx] ==
3449                     SPEED_AUTO_NEG)
3450                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3451
3452                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3453                            " speed_cap_mask %x\n",
3454                            params->phy[actual_phy_idx].req_flow_ctrl,
3455                            params->phy[actual_phy_idx].req_line_speed,
3456                            params->phy[actual_phy_idx].speed_cap_mask);
3457         }
3458 }
3459
3460 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3461                                     struct bnx2x_phy *phy,
3462                                     struct link_vars *vars)
3463 {
3464         u16 val;
3465         struct bnx2x *bp = params->bp;
3466         /* Read modify write pause advertizing */
3467         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3468
3469         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3470
3471         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3472         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3473         if ((vars->ieee_fc &
3474             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3475             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3476                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3477         }
3478         if ((vars->ieee_fc &
3479             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3480             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3481                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3482         }
3483         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3484         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3485 }
3486
3487 static void bnx2x_pause_resolve(struct bnx2x_phy *phy,
3488                                 struct link_params *params,
3489                                 struct link_vars *vars,
3490                                 u32 pause_result)
3491 {
3492         struct bnx2x *bp = params->bp;
3493                                                 /*  LD      LP   */
3494         switch (pause_result) {                 /* ASYM P ASYM P */
3495         case 0xb:                               /*   1  0   1  1 */
3496                 DP(NETIF_MSG_LINK, "Flow Control: TX only\n");
3497                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3498                 break;
3499
3500         case 0xe:                               /*   1  1   1  0 */
3501                 DP(NETIF_MSG_LINK, "Flow Control: RX only\n");
3502                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3503                 break;
3504
3505         case 0x5:                               /*   0  1   0  1 */
3506         case 0x7:                               /*   0  1   1  1 */
3507         case 0xd:                               /*   1  1   0  1 */
3508         case 0xf:                               /*   1  1   1  1 */
3509                 /* If the user selected to advertise RX ONLY,
3510                  * although we advertised both, need to enable
3511                  * RX only.
3512                  */
3513                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
3514                         DP(NETIF_MSG_LINK, "Flow Control: RX & TX\n");
3515                         vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3516                 } else {
3517                         DP(NETIF_MSG_LINK, "Flow Control: RX only\n");
3518                         vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3519                 }
3520                 break;
3521
3522         default:
3523                 DP(NETIF_MSG_LINK, "Flow Control: None\n");
3524                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3525                 break;
3526         }
3527         if (pause_result & (1<<0))
3528                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3529         if (pause_result & (1<<1))
3530                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3531
3532 }
3533
3534 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3535                                         struct link_params *params,
3536                                         struct link_vars *vars)
3537 {
3538         u16 ld_pause;           /* local */
3539         u16 lp_pause;           /* link partner */
3540         u16 pause_result;
3541         struct bnx2x *bp = params->bp;
3542         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3543                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3544                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3545         } else if (CHIP_IS_E3(bp) &&
3546                 SINGLE_MEDIA_DIRECT(params)) {
3547                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3548                 u16 gp_status, gp_mask;
3549                 bnx2x_cl45_read(bp, phy,
3550                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3551                                 &gp_status);
3552                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3553                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3554                         lane;
3555                 if ((gp_status & gp_mask) == gp_mask) {
3556                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3557                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3558                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3559                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3560                 } else {
3561                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3562                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3563                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3564                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3565                         ld_pause = ((ld_pause &
3566                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3567                                     << 3);
3568                         lp_pause = ((lp_pause &
3569                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3570                                     << 3);
3571                 }
3572         } else {
3573                 bnx2x_cl45_read(bp, phy,
3574                                 MDIO_AN_DEVAD,
3575                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3576                 bnx2x_cl45_read(bp, phy,
3577                                 MDIO_AN_DEVAD,
3578                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3579         }
3580         pause_result = (ld_pause &
3581                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3582         pause_result |= (lp_pause &
3583                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3584         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3585         bnx2x_pause_resolve(phy, params, vars, pause_result);
3586
3587 }
3588
3589 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3590                                    struct link_params *params,
3591                                    struct link_vars *vars)
3592 {
3593         u8 ret = 0;
3594         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3595         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3596                 /* Update the advertised flow-controled of LD/LP in AN */
3597                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3598                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3599                 /* But set the flow-control result as the requested one */
3600                 vars->flow_ctrl = phy->req_flow_ctrl;
3601         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3602                 vars->flow_ctrl = params->req_fc_auto_adv;
3603         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3604                 ret = 1;
3605                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3606         }
3607         return ret;
3608 }
3609 /******************************************************************/
3610 /*                      Warpcore section                          */
3611 /******************************************************************/
3612 /* The init_internal_warpcore should mirror the xgxs,
3613  * i.e. reset the lane (if needed), set aer for the
3614  * init configuration, and set/clear SGMII flag. Internal
3615  * phy init is done purely in phy_init stage.
3616  */
3617 #define WC_TX_DRIVER(post2, idriver, ipre, ifir) \
3618         ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3619          (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3620          (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \
3621          (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET))
3622
3623 #define WC_TX_FIR(post, main, pre) \
3624         ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3625          (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3626          (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3627
3628 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3629                                          struct link_params *params,
3630                                          struct link_vars *vars)
3631 {
3632         struct bnx2x *bp = params->bp;
3633         u16 i;
3634         static struct bnx2x_reg_set reg_set[] = {
3635                 /* Step 1 - Program the TX/RX alignment markers */
3636                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3637                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3638                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3639                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3640                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3641                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3642                 /* Step 2 - Configure the NP registers */
3643                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3644                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3645                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3646                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3647                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3648                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3649                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3650                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3651                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3652         };
3653         DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3654
3655         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3656                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3657
3658         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3659                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3660                                  reg_set[i].val);
3661
3662         /* Start KR2 work-around timer which handles BCM8073 link-parner */
3663         params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3664         bnx2x_update_link_attr(params, params->link_attr_sync);
3665 }
3666
3667 static void bnx2x_disable_kr2(struct link_params *params,
3668                               struct link_vars *vars,
3669                               struct bnx2x_phy *phy)
3670 {
3671         struct bnx2x *bp = params->bp;
3672         int i;
3673         static struct bnx2x_reg_set reg_set[] = {
3674                 /* Step 1 - Program the TX/RX alignment markers */
3675                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3676                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3677                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3678                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3679                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3680                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3681                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3682                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3683                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3684                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3685                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3686                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3687                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3688                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3689                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3690         };
3691         DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3692
3693         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3694                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3695                                  reg_set[i].val);
3696         params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3697         bnx2x_update_link_attr(params, params->link_attr_sync);
3698
3699         vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3700 }
3701
3702 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3703                                                struct link_params *params)
3704 {
3705         struct bnx2x *bp = params->bp;
3706
3707         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3708         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3709                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3710         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3711                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3712 }
3713
3714 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3715                                          struct link_params *params)
3716 {
3717         /* Restart autoneg on the leading lane only */
3718         struct bnx2x *bp = params->bp;
3719         u16 lane = bnx2x_get_warpcore_lane(phy, params);
3720         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3721                           MDIO_AER_BLOCK_AER_REG, lane);
3722         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3723                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3724
3725         /* Restore AER */
3726         bnx2x_set_aer_mmd(params, phy);
3727 }
3728
3729 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3730                                         struct link_params *params,
3731                                         struct link_vars *vars) {
3732         u16 lane, i, cl72_ctrl, an_adv = 0, val;
3733         u32 wc_lane_config;
3734         struct bnx2x *bp = params->bp;
3735         static struct bnx2x_reg_set reg_set[] = {
3736                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3737                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3738                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3739                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3740                 /* Disable Autoneg: re-enable it after adv is done. */
3741                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3742                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3743                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3744         };
3745         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3746         /* Set to default registers that may be overriden by 10G force */
3747         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3748                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3749                                  reg_set[i].val);
3750
3751         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3752                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3753         cl72_ctrl &= 0x08ff;
3754         cl72_ctrl |= 0x3800;
3755         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3756                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3757
3758         /* Check adding advertisement for 1G KX */
3759         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3760              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3761             (vars->line_speed == SPEED_1000)) {
3762                 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3763                 an_adv |= (1<<5);
3764
3765                 /* Enable CL37 1G Parallel Detect */
3766                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3767                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3768         }
3769         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3770              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3771             (vars->line_speed ==  SPEED_10000)) {
3772                 /* Check adding advertisement for 10G KR */
3773                 an_adv |= (1<<7);
3774                 /* Enable 10G Parallel Detect */
3775                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3776                                   MDIO_AER_BLOCK_AER_REG, 0);
3777
3778                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3779                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3780                 bnx2x_set_aer_mmd(params, phy);
3781                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3782         }
3783
3784         /* Set Transmit PMD settings */
3785         lane = bnx2x_get_warpcore_lane(phy, params);
3786         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3787                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3788                          WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3789         /* Configure the next lane if dual mode */
3790         if (phy->flags & FLAGS_WC_DUAL_MODE)
3791                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3792                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3793                                  WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3794         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3795                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3796                          0x03f0);
3797         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3798                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3799                          0x03f0);
3800
3801         /* Advertised speeds */
3802         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3803                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3804
3805         /* Advertised and set FEC (Forward Error Correction) */
3806         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3807                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3808                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3809                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3810
3811         /* Enable CL37 BAM */
3812         if (REG_RD(bp, params->shmem_base +
3813                    offsetof(struct shmem_region, dev_info.
3814                             port_hw_config[params->port].default_cfg)) &
3815             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3816                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3817                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3818                                          1);
3819                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3820         }
3821
3822         /* Advertise pause */
3823         bnx2x_ext_phy_set_pause(params, phy, vars);
3824         vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3825         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3826                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3827
3828         /* Over 1G - AN local device user page 1 */
3829         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3830                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3831
3832         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3833              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3834             (phy->req_line_speed == SPEED_20000)) {
3835
3836                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3837                                   MDIO_AER_BLOCK_AER_REG, lane);
3838
3839                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3840                                          MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3841                                          (1<<11));
3842
3843                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3844                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3845                 bnx2x_set_aer_mmd(params, phy);
3846
3847                 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3848         } else {
3849                 /* Enable Auto-Detect to support 1G over CL37 as well */
3850                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3851                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
3852                 wc_lane_config = REG_RD(bp, params->shmem_base +
3853                                         offsetof(struct shmem_region, dev_info.
3854                                         shared_hw_config.wc_lane_config));
3855                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3856                                 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
3857                 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
3858                  * parallel-detect loop when CL73 and CL37 are enabled.
3859                  */
3860                 val |= 1 << 11;
3861
3862                 /* Restore Polarity settings in case it was run over by
3863                  * previous link owner
3864                  */
3865                 if (wc_lane_config &
3866                     (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
3867                         val |= 3 << 2;
3868                 else
3869                         val &= ~(3 << 2);
3870                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3871                                  MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
3872                                  val);
3873
3874                 bnx2x_disable_kr2(params, vars, phy);
3875         }
3876
3877         /* Enable Autoneg: only on the main lane */
3878         bnx2x_warpcore_restart_AN_KR(phy, params);
3879 }
3880
3881 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3882                                       struct link_params *params,
3883                                       struct link_vars *vars)
3884 {
3885         struct bnx2x *bp = params->bp;
3886         u16 val16, i, lane;
3887         static struct bnx2x_reg_set reg_set[] = {
3888                 /* Disable Autoneg */
3889                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3890                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3891                         0x3f00},
3892                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3893                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3894                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3895                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3896                 /* Leave cl72 training enable, needed for KR */
3897                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3898         };
3899
3900         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3901                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3902                                  reg_set[i].val);
3903
3904         lane = bnx2x_get_warpcore_lane(phy, params);
3905         /* Global registers */
3906         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3907                           MDIO_AER_BLOCK_AER_REG, 0);
3908         /* Disable CL36 PCS Tx */
3909         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3910                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3911         val16 &= ~(0x0011 << lane);
3912         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3913                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3914
3915         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3916                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3917         val16 |= (0x0303 << (lane << 1));
3918         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3919                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3920         /* Restore AER */
3921         bnx2x_set_aer_mmd(params, phy);
3922         /* Set speed via PMA/PMD register */
3923         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3924                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3925
3926         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3927                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3928
3929         /* Enable encoded forced speed */
3930         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3931                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3932
3933         /* Turn TX scramble payload only the 64/66 scrambler */
3934         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3935                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3936
3937         /* Turn RX scramble payload only the 64/66 scrambler */
3938         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3939                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3940
3941         /* Set and clear loopback to cause a reset to 64/66 decoder */
3942         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3943                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3944         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3945                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3946
3947 }
3948
3949 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3950                                        struct link_params *params,
3951                                        u8 is_xfi)
3952 {
3953         struct bnx2x *bp = params->bp;
3954         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3955         u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3956         u32 ifir_val, ipost2_val, ipre_driver_val;
3957
3958         /* Hold rxSeqStart */
3959         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3960                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3961
3962         /* Hold tx_fifo_reset */
3963         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3964                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3965
3966         /* Disable CL73 AN */
3967         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3968
3969         /* Disable 100FX Enable and Auto-Detect */
3970         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3971                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3972
3973         /* Disable 100FX Idle detect */
3974         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3975                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3976
3977         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3978         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3979                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3980
3981         /* Turn off auto-detect & fiber mode */
3982         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3983                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3984                                   0xFFEE);
3985
3986         /* Set filter_force_link, disable_false_link and parallel_detect */
3987         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3988                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3989         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3990                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3991                          ((val | 0x0006) & 0xFFFE));
3992
3993         /* Set XFI / SFI */
3994         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3995                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3996
3997         misc1_val &= ~(0x1f);
3998
3999         if (is_xfi) {
4000                 misc1_val |= 0x5;
4001                 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
4002                 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);
4003         } else {
4004                 cfg_tap_val = REG_RD(bp, params->shmem_base +
4005                                      offsetof(struct shmem_region, dev_info.
4006                                               port_hw_config[params->port].
4007                                               sfi_tap_values));
4008
4009                 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4010
4011                 misc1_val |= 0x9;
4012
4013                 /* TAP values are controlled by nvram, if value there isn't 0 */
4014                 if (tx_equal)
4015                         tap_val = (u16)tx_equal;
4016                 else
4017                         tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4018
4019                 ifir_val = DEFAULT_TX_DRV_IFIR;
4020                 ipost2_val = DEFAULT_TX_DRV_POST2;
4021                 ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER;
4022                 tx_drv_brdct = DEFAULT_TX_DRV_BRDCT;
4023
4024                 /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all
4025                  * configuration.
4026                  */
4027                 if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK |
4028                                    PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK |
4029                                    PORT_HW_CFG_TX_DRV_POST2_MASK)) {
4030                         ifir_val = (cfg_tap_val &
4031                                     PORT_HW_CFG_TX_DRV_IFIR_MASK) >>
4032                                 PORT_HW_CFG_TX_DRV_IFIR_SHIFT;
4033                         ipre_driver_val = (cfg_tap_val &
4034                                            PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK)
4035                         >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT;
4036                         ipost2_val = (cfg_tap_val &
4037                                       PORT_HW_CFG_TX_DRV_POST2_MASK) >>
4038                                 PORT_HW_CFG_TX_DRV_POST2_SHIFT;
4039                 }
4040
4041                 if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) {
4042                         tx_drv_brdct = (cfg_tap_val &
4043                                         PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4044                                 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4045                 }
4046
4047                 tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct,
4048                                              ipre_driver_val, ifir_val);
4049         }
4050         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4051                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4052
4053         /* Set Transmit PMD settings */
4054         lane = bnx2x_get_warpcore_lane(phy, params);
4055         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4056                          MDIO_WC_REG_TX_FIR_TAP,
4057                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4058         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4059                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4060                          tx_driver_val);
4061
4062         /* Enable fiber mode, enable and invert sig_det */
4063         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4064                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4065
4066         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4067         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4068                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4069
4070         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4071
4072         /* 10G XFI Full Duplex */
4073         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4074                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4075
4076         /* Release tx_fifo_reset */
4077         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4078                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4079                                   0xFFFE);
4080         /* Release rxSeqStart */
4081         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4082                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4083 }
4084
4085 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4086                                              struct link_params *params)
4087 {
4088         u16 val;
4089         struct bnx2x *bp = params->bp;
4090         /* Set global registers, so set AER lane to 0 */
4091         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4092                           MDIO_AER_BLOCK_AER_REG, 0);
4093
4094         /* Disable sequencer */
4095         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4096                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4097
4098         bnx2x_set_aer_mmd(params, phy);
4099
4100         bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4101                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4102         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4103                          MDIO_AN_REG_CTRL, 0);
4104         /* Turn off CL73 */
4105         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4106                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4107         val &= ~(1<<5);
4108         val |= (1<<6);
4109         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4110                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
4111
4112         /* Set 20G KR2 force speed */
4113         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4114                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4115
4116         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4117                                  MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4118
4119         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4120                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4121         val &= ~(3<<14);
4122         val |= (1<<15);
4123         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4124                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4125         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4126                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4127
4128         /* Enable sequencer (over lane 0) */
4129         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4130                           MDIO_AER_BLOCK_AER_REG, 0);
4131
4132         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4133                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4134
4135         bnx2x_set_aer_mmd(params, phy);
4136 }
4137
4138 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4139                                          struct bnx2x_phy *phy,
4140                                          u16 lane)
4141 {
4142         /* Rx0 anaRxControl1G */
4143         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4144                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4145
4146         /* Rx2 anaRxControl1G */
4147         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4148                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4149
4150         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4151                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4152
4153         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4154                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4155
4156         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4157                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4158
4159         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4160                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4161
4162         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4163                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4164
4165         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4166                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4167
4168         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4169                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4170
4171         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4172                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4173
4174         /* Serdes Digital Misc1 */
4175         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4176                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4177
4178         /* Serdes Digital4 Misc3 */
4179         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4180                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4181
4182         /* Set Transmit PMD settings */
4183         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4184                          MDIO_WC_REG_TX_FIR_TAP,
4185                          (WC_TX_FIR(0x12, 0x2d, 0x00) |
4186                           MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4187         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4188                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4189                          WC_TX_DRIVER(0x02, 0x02, 0x02, 0));
4190 }
4191
4192 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4193                                            struct link_params *params,
4194                                            u8 fiber_mode,
4195                                            u8 always_autoneg)
4196 {
4197         struct bnx2x *bp = params->bp;
4198         u16 val16, digctrl_kx1, digctrl_kx2;
4199
4200         /* Clear XFI clock comp in non-10G single lane mode. */
4201         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4202                                   MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4203
4204         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4205
4206         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4207                 /* SGMII Autoneg */
4208                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4209                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4210                                          0x1000);
4211                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4212         } else {
4213                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4214                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4215                 val16 &= 0xcebf;
4216                 switch (phy->req_line_speed) {
4217                 case SPEED_10:
4218                         break;
4219                 case SPEED_100:
4220                         val16 |= 0x2000;
4221                         break;
4222                 case SPEED_1000:
4223                         val16 |= 0x0040;
4224                         break;
4225                 default:
4226                         DP(NETIF_MSG_LINK,
4227                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4228                         return;
4229                 }
4230
4231                 if (phy->req_duplex == DUPLEX_FULL)
4232                         val16 |= 0x0100;
4233
4234                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4235                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4236
4237                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4238                                phy->req_line_speed);
4239                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4240                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4241                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4242         }
4243
4244         /* SGMII Slave mode and disable signal detect */
4245         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4246                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4247         if (fiber_mode)
4248                 digctrl_kx1 = 1;
4249         else
4250                 digctrl_kx1 &= 0xff4a;
4251
4252         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4253                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4254                         digctrl_kx1);
4255
4256         /* Turn off parallel detect */
4257         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4258                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4259         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4260                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4261                         (digctrl_kx2 & ~(1<<2)));
4262
4263         /* Re-enable parallel detect */
4264         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4265                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4266                         (digctrl_kx2 | (1<<2)));
4267
4268         /* Enable autodet */
4269         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4270                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4271                         (digctrl_kx1 | 0x10));
4272 }
4273
4274 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4275                                       struct bnx2x_phy *phy,
4276                                       u8 reset)
4277 {
4278         u16 val;
4279         /* Take lane out of reset after configuration is finished */
4280         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4281                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4282         if (reset)
4283                 val |= 0xC000;
4284         else
4285                 val &= 0x3FFF;
4286         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4287                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4288         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4289                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4290 }
4291 /* Clear SFI/XFI link settings registers */
4292 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4293                                       struct link_params *params,
4294                                       u16 lane)
4295 {
4296         struct bnx2x *bp = params->bp;
4297         u16 i;
4298         static struct bnx2x_reg_set wc_regs[] = {
4299                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4300                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4301                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4302                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4303                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4304                         0x0195},
4305                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4306                         0x0007},
4307                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4308                         0x0002},
4309                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4310                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4311                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4312                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4313         };
4314         /* Set XFI clock comp as default. */
4315         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4316                                  MDIO_WC_REG_RX66_CONTROL, (3<<13));
4317
4318         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4319                 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4320                                  wc_regs[i].val);
4321
4322         lane = bnx2x_get_warpcore_lane(phy, params);
4323         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4324                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4325
4326 }
4327
4328 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4329                                                 u32 chip_id,
4330                                                 u32 shmem_base, u8 port,
4331                                                 u8 *gpio_num, u8 *gpio_port)
4332 {
4333         u32 cfg_pin;
4334         *gpio_num = 0;
4335         *gpio_port = 0;
4336         if (CHIP_IS_E3(bp)) {
4337                 cfg_pin = (REG_RD(bp, shmem_base +
4338                                 offsetof(struct shmem_region,
4339                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4340                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4341                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4342
4343                 /* Should not happen. This function called upon interrupt
4344                  * triggered by GPIO ( since EPIO can only generate interrupts
4345                  * to MCP).
4346                  * So if this function was called and none of the GPIOs was set,
4347                  * it means the shit hit the fan.
4348                  */
4349                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4350                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4351                         DP(NETIF_MSG_LINK,
4352                            "No cfg pin %x for module detect indication\n",
4353                            cfg_pin);
4354                         return -EINVAL;
4355                 }
4356
4357                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4358                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4359         } else {
4360                 *gpio_num = MISC_REGISTERS_GPIO_3;
4361                 *gpio_port = port;
4362         }
4363
4364         return 0;
4365 }
4366
4367 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4368                                        struct link_params *params)
4369 {
4370         struct bnx2x *bp = params->bp;
4371         u8 gpio_num, gpio_port;
4372         u32 gpio_val;
4373         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4374                                       params->shmem_base, params->port,
4375                                       &gpio_num, &gpio_port) != 0)
4376                 return 0;
4377         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4378
4379         /* Call the handling function in case module is detected */
4380         if (gpio_val == 0)
4381                 return 1;
4382         else
4383                 return 0;
4384 }
4385 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4386                                      struct link_params *params)
4387 {
4388         u16 gp2_status_reg0, lane;
4389         struct bnx2x *bp = params->bp;
4390
4391         lane = bnx2x_get_warpcore_lane(phy, params);
4392
4393         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4394                                  &gp2_status_reg0);
4395
4396         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4397 }
4398
4399 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4400                                           struct link_params *params,
4401                                           struct link_vars *vars)
4402 {
4403         struct bnx2x *bp = params->bp;
4404         u32 serdes_net_if;
4405         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4406
4407         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4408
4409         if (!vars->turn_to_run_wc_rt)
4410                 return;
4411
4412         if (vars->rx_tx_asic_rst) {
4413                 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4414                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4415                                 offsetof(struct shmem_region, dev_info.
4416                                 port_hw_config[params->port].default_cfg)) &
4417                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4418
4419                 switch (serdes_net_if) {
4420                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4421                         /* Do we get link yet? */
4422                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4423                                         &gp_status1);
4424                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4425                                 /*10G KR*/
4426                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4427
4428                         if (lnkup_kr || lnkup) {
4429                                 vars->rx_tx_asic_rst = 0;
4430                         } else {
4431                                 /* Reset the lane to see if link comes up.*/
4432                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4433                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4434
4435                                 /* Restart Autoneg */
4436                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4437                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4438
4439                                 vars->rx_tx_asic_rst--;
4440                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4441                                 vars->rx_tx_asic_rst);
4442                         }
4443                         break;
4444
4445                 default:
4446                         break;
4447                 }
4448
4449         } /*params->rx_tx_asic_rst*/
4450
4451 }
4452 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4453                                       struct link_params *params)
4454 {
4455         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4456         struct bnx2x *bp = params->bp;
4457         bnx2x_warpcore_clear_regs(phy, params, lane);
4458         if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4459              SPEED_10000) &&
4460             (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4461                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4462                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4463         } else {
4464                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4465                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4466         }
4467 }
4468
4469 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4470                                          struct bnx2x_phy *phy,
4471                                          u8 tx_en)
4472 {
4473         struct bnx2x *bp = params->bp;
4474         u32 cfg_pin;
4475         u8 port = params->port;
4476
4477         cfg_pin = REG_RD(bp, params->shmem_base +
4478                          offsetof(struct shmem_region,
4479                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4480                 PORT_HW_CFG_E3_TX_LASER_MASK;
4481         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4482         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4483
4484         /* For 20G, the expected pin to be used is 3 pins after the current */
4485         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4486         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4487                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4488 }
4489
4490 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4491                                        struct link_params *params,
4492                                        struct link_vars *vars)
4493 {
4494         struct bnx2x *bp = params->bp;
4495         u32 serdes_net_if;
4496         u8 fiber_mode;
4497         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4498         serdes_net_if = (REG_RD(bp, params->shmem_base +
4499                          offsetof(struct shmem_region, dev_info.
4500                                   port_hw_config[params->port].default_cfg)) &
4501                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4502         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4503                            "serdes_net_if = 0x%x\n",
4504                        vars->line_speed, serdes_net_if);
4505         bnx2x_set_aer_mmd(params, phy);
4506         bnx2x_warpcore_reset_lane(bp, phy, 1);
4507         vars->phy_flags |= PHY_XGXS_FLAG;
4508         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4509             (phy->req_line_speed &&
4510              ((phy->req_line_speed == SPEED_100) ||
4511               (phy->req_line_speed == SPEED_10)))) {
4512                 vars->phy_flags |= PHY_SGMII_FLAG;
4513                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4514                 bnx2x_warpcore_clear_regs(phy, params, lane);
4515                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4516         } else {
4517                 switch (serdes_net_if) {
4518                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4519                         /* Enable KR Auto Neg */
4520                         if (params->loopback_mode != LOOPBACK_EXT)
4521                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4522                         else {
4523                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4524                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4525                         }
4526                         break;
4527
4528                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4529                         bnx2x_warpcore_clear_regs(phy, params, lane);
4530                         if (vars->line_speed == SPEED_10000) {
4531                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4532                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4533                         } else {
4534                                 if (SINGLE_MEDIA_DIRECT(params)) {
4535                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4536                                         fiber_mode = 1;
4537                                 } else {
4538                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4539                                         fiber_mode = 0;
4540                                 }
4541                                 bnx2x_warpcore_set_sgmii_speed(phy,
4542                                                                 params,
4543                                                                 fiber_mode,
4544                                                                 0);
4545                         }
4546
4547                         break;
4548
4549                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4550                         /* Issue Module detection if module is plugged, or
4551                          * enabled transmitter to avoid current leakage in case
4552                          * no module is connected
4553                          */
4554                         if ((params->loopback_mode == LOOPBACK_NONE) ||
4555                             (params->loopback_mode == LOOPBACK_EXT)) {
4556                                 if (bnx2x_is_sfp_module_plugged(phy, params))
4557                                         bnx2x_sfp_module_detection(phy, params);
4558                                 else
4559                                         bnx2x_sfp_e3_set_transmitter(params,
4560                                                                      phy, 1);
4561                         }
4562
4563                         bnx2x_warpcore_config_sfi(phy, params);
4564                         break;
4565
4566                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4567                         if (vars->line_speed != SPEED_20000) {
4568                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4569                                 return;
4570                         }
4571                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4572                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4573                         /* Issue Module detection */
4574
4575                         bnx2x_sfp_module_detection(phy, params);
4576                         break;
4577                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4578                         if (!params->loopback_mode) {
4579                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4580                         } else {
4581                                 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4582                                 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4583                         }
4584                         break;
4585                 default:
4586                         DP(NETIF_MSG_LINK,
4587                            "Unsupported Serdes Net Interface 0x%x\n",
4588                            serdes_net_if);
4589                         return;
4590                 }
4591         }
4592
4593         /* Take lane out of reset after configuration is finished */
4594         bnx2x_warpcore_reset_lane(bp, phy, 0);
4595         DP(NETIF_MSG_LINK, "Exit config init\n");
4596 }
4597
4598 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4599                                       struct link_params *params)
4600 {
4601         struct bnx2x *bp = params->bp;
4602         u16 val16, lane;
4603         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4604         bnx2x_set_mdio_emac_per_phy(bp, params);
4605         bnx2x_set_aer_mmd(params, phy);
4606         /* Global register */
4607         bnx2x_warpcore_reset_lane(bp, phy, 1);
4608
4609         /* Clear loopback settings (if any) */
4610         /* 10G & 20G */
4611         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4612                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4613
4614         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4615                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4616
4617         /* Update those 1-copy registers */
4618         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4619                           MDIO_AER_BLOCK_AER_REG, 0);
4620         /* Enable 1G MDIO (1-copy) */
4621         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4622                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4623                                   ~0x10);
4624
4625         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4626                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4627         lane = bnx2x_get_warpcore_lane(phy, params);
4628         /* Disable CL36 PCS Tx */
4629         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4630                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4631         val16 |= (0x11 << lane);
4632         if (phy->flags & FLAGS_WC_DUAL_MODE)
4633                 val16 |= (0x22 << lane);
4634         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4635                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4636
4637         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4638                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4639         val16 &= ~(0x0303 << (lane << 1));
4640         val16 |= (0x0101 << (lane << 1));
4641         if (phy->flags & FLAGS_WC_DUAL_MODE) {
4642                 val16 &= ~(0x0c0c << (lane << 1));
4643                 val16 |= (0x0404 << (lane << 1));
4644         }
4645
4646         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4647                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4648         /* Restore AER */
4649         bnx2x_set_aer_mmd(params, phy);
4650
4651 }
4652
4653 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4654                                         struct link_params *params)
4655 {
4656         struct bnx2x *bp = params->bp;
4657         u16 val16;
4658         u32 lane;
4659         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4660                        params->loopback_mode, phy->req_line_speed);
4661
4662         if (phy->req_line_speed < SPEED_10000 ||
4663             phy->supported & SUPPORTED_20000baseKR2_Full) {
4664                 /* 10/100/1000/20G-KR2 */
4665
4666                 /* Update those 1-copy registers */
4667                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4668                                   MDIO_AER_BLOCK_AER_REG, 0);
4669                 /* Enable 1G MDIO (1-copy) */
4670                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4671                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4672                                          0x10);
4673                 /* Set 1G loopback based on lane (1-copy) */
4674                 lane = bnx2x_get_warpcore_lane(phy, params);
4675                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4676                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4677                 val16 |= (1<<lane);
4678                 if (phy->flags & FLAGS_WC_DUAL_MODE)
4679                         val16 |= (2<<lane);
4680                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4681                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4682                                  val16);
4683
4684                 /* Switch back to 4-copy registers */
4685                 bnx2x_set_aer_mmd(params, phy);
4686         } else {
4687                 /* 10G / 20G-DXGXS */
4688                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4689                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4690                                          0x4000);
4691                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4692                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4693         }
4694 }
4695
4696
4697
4698 static void bnx2x_sync_link(struct link_params *params,
4699                              struct link_vars *vars)
4700 {
4701         struct bnx2x *bp = params->bp;
4702         u8 link_10g_plus;
4703         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4704                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4705         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4706         if (vars->link_up) {
4707                 DP(NETIF_MSG_LINK, "phy link up\n");
4708
4709                 vars->phy_link_up = 1;
4710                 vars->duplex = DUPLEX_FULL;
4711                 switch (vars->link_status &
4712                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4713                 case LINK_10THD:
4714                         vars->duplex = DUPLEX_HALF;
4715                         /* Fall thru */
4716                 case LINK_10TFD:
4717                         vars->line_speed = SPEED_10;
4718                         break;
4719
4720                 case LINK_100TXHD:
4721                         vars->duplex = DUPLEX_HALF;
4722                         /* Fall thru */
4723                 case LINK_100T4:
4724                 case LINK_100TXFD:
4725                         vars->line_speed = SPEED_100;
4726                         break;
4727
4728                 case LINK_1000THD:
4729                         vars->duplex = DUPLEX_HALF;
4730                         /* Fall thru */
4731                 case LINK_1000TFD:
4732                         vars->line_speed = SPEED_1000;
4733                         break;
4734
4735                 case LINK_2500THD:
4736                         vars->duplex = DUPLEX_HALF;
4737                         /* Fall thru */
4738                 case LINK_2500TFD:
4739                         vars->line_speed = SPEED_2500;
4740                         break;
4741
4742                 case LINK_10GTFD:
4743                         vars->line_speed = SPEED_10000;
4744                         break;
4745                 case LINK_20GTFD:
4746                         vars->line_speed = SPEED_20000;
4747                         break;
4748                 default:
4749                         break;
4750                 }
4751                 vars->flow_ctrl = 0;
4752                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4753                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4754
4755                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4756                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4757
4758                 if (!vars->flow_ctrl)
4759                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4760
4761                 if (vars->line_speed &&
4762                     ((vars->line_speed == SPEED_10) ||
4763                      (vars->line_speed == SPEED_100))) {
4764                         vars->phy_flags |= PHY_SGMII_FLAG;
4765                 } else {
4766                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4767                 }
4768                 if (vars->line_speed &&
4769                     USES_WARPCORE(bp) &&
4770                     (vars->line_speed == SPEED_1000))
4771                         vars->phy_flags |= PHY_SGMII_FLAG;
4772                 /* Anything 10 and over uses the bmac */
4773                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4774
4775                 if (link_10g_plus) {
4776                         if (USES_WARPCORE(bp))
4777                                 vars->mac_type = MAC_TYPE_XMAC;
4778                         else
4779                                 vars->mac_type = MAC_TYPE_BMAC;
4780                 } else {
4781                         if (USES_WARPCORE(bp))
4782                                 vars->mac_type = MAC_TYPE_UMAC;
4783                         else
4784                                 vars->mac_type = MAC_TYPE_EMAC;
4785                 }
4786         } else { /* Link down */
4787                 DP(NETIF_MSG_LINK, "phy link down\n");
4788
4789                 vars->phy_link_up = 0;
4790
4791                 vars->line_speed = 0;
4792                 vars->duplex = DUPLEX_FULL;
4793                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4794
4795                 /* Indicate no mac active */
4796                 vars->mac_type = MAC_TYPE_NONE;
4797                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4798                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4799                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4800                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4801         }
4802 }
4803
4804 void bnx2x_link_status_update(struct link_params *params,
4805                               struct link_vars *vars)
4806 {
4807         struct bnx2x *bp = params->bp;
4808         u8 port = params->port;
4809         u32 sync_offset, media_types;
4810         /* Update PHY configuration */
4811         set_phy_vars(params, vars);
4812
4813         vars->link_status = REG_RD(bp, params->shmem_base +
4814                                    offsetof(struct shmem_region,
4815                                             port_mb[port].link_status));
4816
4817         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4818         if (params->loopback_mode != LOOPBACK_NONE &&
4819             params->loopback_mode != LOOPBACK_EXT)
4820                 vars->link_status |= LINK_STATUS_LINK_UP;
4821
4822         if (bnx2x_eee_has_cap(params))
4823                 vars->eee_status = REG_RD(bp, params->shmem2_base +
4824                                           offsetof(struct shmem2_region,
4825                                                    eee_status[params->port]));
4826
4827         vars->phy_flags = PHY_XGXS_FLAG;
4828         bnx2x_sync_link(params, vars);
4829         /* Sync media type */
4830         sync_offset = params->shmem_base +
4831                         offsetof(struct shmem_region,
4832                                  dev_info.port_hw_config[port].media_type);
4833         media_types = REG_RD(bp, sync_offset);
4834
4835         params->phy[INT_PHY].media_type =
4836                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4837                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4838         params->phy[EXT_PHY1].media_type =
4839                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4840                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4841         params->phy[EXT_PHY2].media_type =
4842                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4843                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4844         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4845
4846         /* Sync AEU offset */
4847         sync_offset = params->shmem_base +
4848                         offsetof(struct shmem_region,
4849                                  dev_info.port_hw_config[port].aeu_int_mask);
4850
4851         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4852
4853         /* Sync PFC status */
4854         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4855                 params->feature_config_flags |=
4856                                         FEATURE_CONFIG_PFC_ENABLED;
4857         else
4858                 params->feature_config_flags &=
4859                                         ~FEATURE_CONFIG_PFC_ENABLED;
4860
4861         if (SHMEM2_HAS(bp, link_attr_sync))
4862                 params->link_attr_sync = SHMEM2_RD(bp,
4863                                                  link_attr_sync[params->port]);
4864
4865         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4866                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4867         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4868                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4869 }
4870
4871 static void bnx2x_set_master_ln(struct link_params *params,
4872                                 struct bnx2x_phy *phy)
4873 {
4874         struct bnx2x *bp = params->bp;
4875         u16 new_master_ln, ser_lane;
4876         ser_lane = ((params->lane_config &
4877                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4878                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4879
4880         /* Set the master_ln for AN */
4881         CL22_RD_OVER_CL45(bp, phy,
4882                           MDIO_REG_BANK_XGXS_BLOCK2,
4883                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4884                           &new_master_ln);
4885
4886         CL22_WR_OVER_CL45(bp, phy,
4887                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4888                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4889                           (new_master_ln | ser_lane));
4890 }
4891
4892 static int bnx2x_reset_unicore(struct link_params *params,
4893                                struct bnx2x_phy *phy,
4894                                u8 set_serdes)
4895 {
4896         struct bnx2x *bp = params->bp;
4897         u16 mii_control;
4898         u16 i;
4899         CL22_RD_OVER_CL45(bp, phy,
4900                           MDIO_REG_BANK_COMBO_IEEE0,
4901                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4902
4903         /* Reset the unicore */
4904         CL22_WR_OVER_CL45(bp, phy,
4905                           MDIO_REG_BANK_COMBO_IEEE0,
4906                           MDIO_COMBO_IEEE0_MII_CONTROL,
4907                           (mii_control |
4908                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4909         if (set_serdes)
4910                 bnx2x_set_serdes_access(bp, params->port);
4911
4912         /* Wait for the reset to self clear */
4913         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4914                 udelay(5);
4915
4916                 /* The reset erased the previous bank value */
4917                 CL22_RD_OVER_CL45(bp, phy,
4918                                   MDIO_REG_BANK_COMBO_IEEE0,
4919                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4920                                   &mii_control);
4921
4922                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4923                         udelay(5);
4924                         return 0;
4925                 }
4926         }
4927
4928         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4929                               " Port %d\n",
4930                          params->port);
4931         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4932         return -EINVAL;
4933
4934 }
4935
4936 static void bnx2x_set_swap_lanes(struct link_params *params,
4937                                  struct bnx2x_phy *phy)
4938 {
4939         struct bnx2x *bp = params->bp;
4940         /* Each two bits represents a lane number:
4941          * No swap is 0123 => 0x1b no need to enable the swap
4942          */
4943         u16 rx_lane_swap, tx_lane_swap;
4944
4945         rx_lane_swap = ((params->lane_config &
4946                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4947                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4948         tx_lane_swap = ((params->lane_config &
4949                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4950                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4951
4952         if (rx_lane_swap != 0x1b) {
4953                 CL22_WR_OVER_CL45(bp, phy,
4954                                   MDIO_REG_BANK_XGXS_BLOCK2,
4955                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4956                                   (rx_lane_swap |
4957                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4958                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4959         } else {
4960                 CL22_WR_OVER_CL45(bp, phy,
4961                                   MDIO_REG_BANK_XGXS_BLOCK2,
4962                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4963         }
4964
4965         if (tx_lane_swap != 0x1b) {
4966                 CL22_WR_OVER_CL45(bp, phy,
4967                                   MDIO_REG_BANK_XGXS_BLOCK2,
4968                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4969                                   (tx_lane_swap |
4970                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4971         } else {
4972                 CL22_WR_OVER_CL45(bp, phy,
4973                                   MDIO_REG_BANK_XGXS_BLOCK2,
4974                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4975         }
4976 }
4977
4978 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4979                                          struct link_params *params)
4980 {
4981         struct bnx2x *bp = params->bp;
4982         u16 control2;
4983         CL22_RD_OVER_CL45(bp, phy,
4984                           MDIO_REG_BANK_SERDES_DIGITAL,
4985                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4986                           &control2);
4987         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4988                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4989         else
4990                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4991         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4992                 phy->speed_cap_mask, control2);
4993         CL22_WR_OVER_CL45(bp, phy,
4994                           MDIO_REG_BANK_SERDES_DIGITAL,
4995                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4996                           control2);
4997
4998         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4999              (phy->speed_cap_mask &
5000                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5001                 DP(NETIF_MSG_LINK, "XGXS\n");
5002
5003                 CL22_WR_OVER_CL45(bp, phy,
5004                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
5005                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
5006                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
5007
5008                 CL22_RD_OVER_CL45(bp, phy,
5009                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
5010                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5011                                   &control2);
5012
5013
5014                 control2 |=
5015                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5016
5017                 CL22_WR_OVER_CL45(bp, phy,
5018                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
5019                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5020                                   control2);
5021
5022                 /* Disable parallel detection of HiG */
5023                 CL22_WR_OVER_CL45(bp, phy,
5024                                   MDIO_REG_BANK_XGXS_BLOCK2,
5025                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5026                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5027                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5028         }
5029 }
5030
5031 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5032                               struct link_params *params,
5033                               struct link_vars *vars,
5034                               u8 enable_cl73)
5035 {
5036         struct bnx2x *bp = params->bp;
5037         u16 reg_val;
5038
5039         /* CL37 Autoneg */
5040         CL22_RD_OVER_CL45(bp, phy,
5041                           MDIO_REG_BANK_COMBO_IEEE0,
5042                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5043
5044         /* CL37 Autoneg Enabled */
5045         if (vars->line_speed == SPEED_AUTO_NEG)
5046                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5047         else /* CL37 Autoneg Disabled */
5048                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5049                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5050
5051         CL22_WR_OVER_CL45(bp, phy,
5052                           MDIO_REG_BANK_COMBO_IEEE0,
5053                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5054
5055         /* Enable/Disable Autodetection */
5056
5057         CL22_RD_OVER_CL45(bp, phy,
5058                           MDIO_REG_BANK_SERDES_DIGITAL,
5059                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5060         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5061                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5062         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5063         if (vars->line_speed == SPEED_AUTO_NEG)
5064                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5065         else
5066                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5067
5068         CL22_WR_OVER_CL45(bp, phy,
5069                           MDIO_REG_BANK_SERDES_DIGITAL,
5070                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5071
5072         /* Enable TetonII and BAM autoneg */
5073         CL22_RD_OVER_CL45(bp, phy,
5074                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5075                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5076                           &reg_val);
5077         if (vars->line_speed == SPEED_AUTO_NEG) {
5078                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5079                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5080                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5081         } else {
5082                 /* TetonII and BAM Autoneg Disabled */
5083                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5084                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5085         }
5086         CL22_WR_OVER_CL45(bp, phy,
5087                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5088                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5089                           reg_val);
5090
5091         if (enable_cl73) {
5092                 /* Enable Cl73 FSM status bits */
5093                 CL22_WR_OVER_CL45(bp, phy,
5094                                   MDIO_REG_BANK_CL73_USERB0,
5095                                   MDIO_CL73_USERB0_CL73_UCTRL,
5096                                   0xe);
5097
5098                 /* Enable BAM Station Manager*/
5099                 CL22_WR_OVER_CL45(bp, phy,
5100                         MDIO_REG_BANK_CL73_USERB0,
5101                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5102                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5103                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5104                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5105
5106                 /* Advertise CL73 link speeds */
5107                 CL22_RD_OVER_CL45(bp, phy,
5108                                   MDIO_REG_BANK_CL73_IEEEB1,
5109                                   MDIO_CL73_IEEEB1_AN_ADV2,
5110                                   &reg_val);
5111                 if (phy->speed_cap_mask &
5112                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5113                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5114                 if (phy->speed_cap_mask &
5115                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5116                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5117
5118                 CL22_WR_OVER_CL45(bp, phy,
5119                                   MDIO_REG_BANK_CL73_IEEEB1,
5120                                   MDIO_CL73_IEEEB1_AN_ADV2,
5121                                   reg_val);
5122
5123                 /* CL73 Autoneg Enabled */
5124                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5125
5126         } else /* CL73 Autoneg Disabled */
5127                 reg_val = 0;
5128
5129         CL22_WR_OVER_CL45(bp, phy,
5130                           MDIO_REG_BANK_CL73_IEEEB0,
5131                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5132 }
5133
5134 /* Program SerDes, forced speed */
5135 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5136                                  struct link_params *params,
5137                                  struct link_vars *vars)
5138 {
5139         struct bnx2x *bp = params->bp;
5140         u16 reg_val;
5141
5142         /* Program duplex, disable autoneg and sgmii*/
5143         CL22_RD_OVER_CL45(bp, phy,
5144                           MDIO_REG_BANK_COMBO_IEEE0,
5145                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5146         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5147                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5148                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5149         if (phy->req_duplex == DUPLEX_FULL)
5150                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5151         CL22_WR_OVER_CL45(bp, phy,
5152                           MDIO_REG_BANK_COMBO_IEEE0,
5153                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5154
5155         /* Program speed
5156          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5157          */
5158         CL22_RD_OVER_CL45(bp, phy,
5159                           MDIO_REG_BANK_SERDES_DIGITAL,
5160                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5161         /* Clearing the speed value before setting the right speed */
5162         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5163
5164         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5165                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5166
5167         if (!((vars->line_speed == SPEED_1000) ||
5168               (vars->line_speed == SPEED_100) ||
5169               (vars->line_speed == SPEED_10))) {
5170
5171                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5172                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5173                 if (vars->line_speed == SPEED_10000)
5174                         reg_val |=
5175                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5176         }
5177
5178         CL22_WR_OVER_CL45(bp, phy,
5179                           MDIO_REG_BANK_SERDES_DIGITAL,
5180                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5181
5182 }
5183
5184 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5185                                               struct link_params *params)
5186 {
5187         struct bnx2x *bp = params->bp;
5188         u16 val = 0;
5189
5190         /* Set extended capabilities */
5191         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5192                 val |= MDIO_OVER_1G_UP1_2_5G;
5193         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5194                 val |= MDIO_OVER_1G_UP1_10G;
5195         CL22_WR_OVER_CL45(bp, phy,
5196                           MDIO_REG_BANK_OVER_1G,
5197                           MDIO_OVER_1G_UP1, val);
5198
5199         CL22_WR_OVER_CL45(bp, phy,
5200                           MDIO_REG_BANK_OVER_1G,
5201                           MDIO_OVER_1G_UP3, 0x400);
5202 }
5203
5204 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5205                                               struct link_params *params,
5206                                               u16 ieee_fc)
5207 {
5208         struct bnx2x *bp = params->bp;
5209         u16 val;
5210         /* For AN, we are always publishing full duplex */
5211
5212         CL22_WR_OVER_CL45(bp, phy,
5213                           MDIO_REG_BANK_COMBO_IEEE0,
5214                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5215         CL22_RD_OVER_CL45(bp, phy,
5216                           MDIO_REG_BANK_CL73_IEEEB1,
5217                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5218         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5219         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5220         CL22_WR_OVER_CL45(bp, phy,
5221                           MDIO_REG_BANK_CL73_IEEEB1,
5222                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5223 }
5224
5225 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5226                                   struct link_params *params,
5227                                   u8 enable_cl73)
5228 {
5229         struct bnx2x *bp = params->bp;
5230         u16 mii_control;
5231
5232         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5233         /* Enable and restart BAM/CL37 aneg */
5234
5235         if (enable_cl73) {
5236                 CL22_RD_OVER_CL45(bp, phy,
5237                                   MDIO_REG_BANK_CL73_IEEEB0,
5238                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5239                                   &mii_control);
5240
5241                 CL22_WR_OVER_CL45(bp, phy,
5242                                   MDIO_REG_BANK_CL73_IEEEB0,
5243                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5244                                   (mii_control |
5245                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5246                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5247         } else {
5248
5249                 CL22_RD_OVER_CL45(bp, phy,
5250                                   MDIO_REG_BANK_COMBO_IEEE0,
5251                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5252                                   &mii_control);
5253                 DP(NETIF_MSG_LINK,
5254                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5255                          mii_control);
5256                 CL22_WR_OVER_CL45(bp, phy,
5257                                   MDIO_REG_BANK_COMBO_IEEE0,
5258                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5259                                   (mii_control |
5260                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5261                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5262         }
5263 }
5264
5265 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5266                                            struct link_params *params,
5267                                            struct link_vars *vars)
5268 {
5269         struct bnx2x *bp = params->bp;
5270         u16 control1;
5271
5272         /* In SGMII mode, the unicore is always slave */
5273
5274         CL22_RD_OVER_CL45(bp, phy,
5275                           MDIO_REG_BANK_SERDES_DIGITAL,
5276                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5277                           &control1);
5278         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5279         /* Set sgmii mode (and not fiber) */
5280         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5281                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5282                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5283         CL22_WR_OVER_CL45(bp, phy,
5284                           MDIO_REG_BANK_SERDES_DIGITAL,
5285                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5286                           control1);
5287
5288         /* If forced speed */
5289         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5290                 /* Set speed, disable autoneg */
5291                 u16 mii_control;
5292
5293                 CL22_RD_OVER_CL45(bp, phy,
5294                                   MDIO_REG_BANK_COMBO_IEEE0,
5295                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5296                                   &mii_control);
5297                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5298                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5299                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5300
5301                 switch (vars->line_speed) {
5302                 case SPEED_100:
5303                         mii_control |=
5304                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5305                         break;
5306                 case SPEED_1000:
5307                         mii_control |=
5308                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5309                         break;
5310                 case SPEED_10:
5311                         /* There is nothing to set for 10M */
5312                         break;
5313                 default:
5314                         /* Invalid speed for SGMII */
5315                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5316                                   vars->line_speed);
5317                         break;
5318                 }
5319
5320                 /* Setting the full duplex */
5321                 if (phy->req_duplex == DUPLEX_FULL)
5322                         mii_control |=
5323                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5324                 CL22_WR_OVER_CL45(bp, phy,
5325                                   MDIO_REG_BANK_COMBO_IEEE0,
5326                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5327                                   mii_control);
5328
5329         } else { /* AN mode */
5330                 /* Enable and restart AN */
5331                 bnx2x_restart_autoneg(phy, params, 0);
5332         }
5333 }
5334
5335 /* Link management
5336  */
5337 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5338                                              struct link_params *params)
5339 {
5340         struct bnx2x *bp = params->bp;
5341         u16 pd_10g, status2_1000x;
5342         if (phy->req_line_speed != SPEED_AUTO_NEG)
5343                 return 0;
5344         CL22_RD_OVER_CL45(bp, phy,
5345                           MDIO_REG_BANK_SERDES_DIGITAL,
5346                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5347                           &status2_1000x);
5348         CL22_RD_OVER_CL45(bp, phy,
5349                           MDIO_REG_BANK_SERDES_DIGITAL,
5350                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5351                           &status2_1000x);
5352         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5353                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5354                          params->port);
5355                 return 1;
5356         }
5357
5358         CL22_RD_OVER_CL45(bp, phy,
5359                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5360                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5361                           &pd_10g);
5362
5363         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5364                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5365                          params->port);
5366                 return 1;
5367         }
5368         return 0;
5369 }
5370
5371 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5372                                 struct link_params *params,
5373                                 struct link_vars *vars,
5374                                 u32 gp_status)
5375 {
5376         u16 ld_pause;   /* local driver */
5377         u16 lp_pause;   /* link partner */
5378         u16 pause_result;
5379         struct bnx2x *bp = params->bp;
5380         if ((gp_status &
5381              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5382               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5383             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5384              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5385
5386                 CL22_RD_OVER_CL45(bp, phy,
5387                                   MDIO_REG_BANK_CL73_IEEEB1,
5388                                   MDIO_CL73_IEEEB1_AN_ADV1,
5389                                   &ld_pause);
5390                 CL22_RD_OVER_CL45(bp, phy,
5391                                   MDIO_REG_BANK_CL73_IEEEB1,
5392                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5393                                   &lp_pause);
5394                 pause_result = (ld_pause &
5395                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5396                 pause_result |= (lp_pause &
5397                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5398                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5399         } else {
5400                 CL22_RD_OVER_CL45(bp, phy,
5401                                   MDIO_REG_BANK_COMBO_IEEE0,
5402                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5403                                   &ld_pause);
5404                 CL22_RD_OVER_CL45(bp, phy,
5405                         MDIO_REG_BANK_COMBO_IEEE0,
5406                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5407                         &lp_pause);
5408                 pause_result = (ld_pause &
5409                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5410                 pause_result |= (lp_pause &
5411                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5412                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5413         }
5414         bnx2x_pause_resolve(phy, params, vars, pause_result);
5415
5416 }
5417
5418 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5419                                     struct link_params *params,
5420                                     struct link_vars *vars,
5421                                     u32 gp_status)
5422 {
5423         struct bnx2x *bp = params->bp;
5424         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5425
5426         /* Resolve from gp_status in case of AN complete and not sgmii */
5427         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5428                 /* Update the advertised flow-controled of LD/LP in AN */
5429                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5430                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5431                 /* But set the flow-control result as the requested one */
5432                 vars->flow_ctrl = phy->req_flow_ctrl;
5433         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5434                 vars->flow_ctrl = params->req_fc_auto_adv;
5435         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5436                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5437                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5438                         vars->flow_ctrl = params->req_fc_auto_adv;
5439                         return;
5440                 }
5441                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5442         }
5443         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5444 }
5445
5446 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5447                                          struct link_params *params)
5448 {
5449         struct bnx2x *bp = params->bp;
5450         u16 rx_status, ustat_val, cl37_fsm_received;
5451         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5452         /* Step 1: Make sure signal is detected */
5453         CL22_RD_OVER_CL45(bp, phy,
5454                           MDIO_REG_BANK_RX0,
5455                           MDIO_RX0_RX_STATUS,
5456                           &rx_status);
5457         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5458             (MDIO_RX0_RX_STATUS_SIGDET)) {
5459                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5460                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5461                 CL22_WR_OVER_CL45(bp, phy,
5462                                   MDIO_REG_BANK_CL73_IEEEB0,
5463                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5464                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5465                 return;
5466         }
5467         /* Step 2: Check CL73 state machine */
5468         CL22_RD_OVER_CL45(bp, phy,
5469                           MDIO_REG_BANK_CL73_USERB0,
5470                           MDIO_CL73_USERB0_CL73_USTAT1,
5471                           &ustat_val);
5472         if ((ustat_val &
5473              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5474               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5475             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5476               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5477                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5478                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5479                 return;
5480         }
5481         /* Step 3: Check CL37 Message Pages received to indicate LP
5482          * supports only CL37
5483          */
5484         CL22_RD_OVER_CL45(bp, phy,
5485                           MDIO_REG_BANK_REMOTE_PHY,
5486                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5487                           &cl37_fsm_received);
5488         if ((cl37_fsm_received &
5489              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5490              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5491             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5492               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5493                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5494                              "misc_rx_status(0x8330) = 0x%x\n",
5495                          cl37_fsm_received);
5496                 return;
5497         }
5498         /* The combined cl37/cl73 fsm state information indicating that
5499          * we are connected to a device which does not support cl73, but
5500          * does support cl37 BAM. In this case we disable cl73 and
5501          * restart cl37 auto-neg
5502          */
5503
5504         /* Disable CL73 */
5505         CL22_WR_OVER_CL45(bp, phy,
5506                           MDIO_REG_BANK_CL73_IEEEB0,
5507                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5508                           0);
5509         /* Restart CL37 autoneg */
5510         bnx2x_restart_autoneg(phy, params, 0);
5511         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5512 }
5513
5514 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5515                                   struct link_params *params,
5516                                   struct link_vars *vars,
5517                                   u32 gp_status)
5518 {
5519         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5520                 vars->link_status |=
5521                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5522
5523         if (bnx2x_direct_parallel_detect_used(phy, params))
5524                 vars->link_status |=
5525                         LINK_STATUS_PARALLEL_DETECTION_USED;
5526 }
5527 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5528                                      struct link_params *params,
5529                                       struct link_vars *vars,
5530                                       u16 is_link_up,
5531                                       u16 speed_mask,
5532                                       u16 is_duplex)
5533 {
5534         struct bnx2x *bp = params->bp;
5535         if (phy->req_line_speed == SPEED_AUTO_NEG)
5536                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5537         if (is_link_up) {
5538                 DP(NETIF_MSG_LINK, "phy link up\n");
5539
5540                 vars->phy_link_up = 1;
5541                 vars->link_status |= LINK_STATUS_LINK_UP;
5542
5543                 switch (speed_mask) {
5544                 case GP_STATUS_10M:
5545                         vars->line_speed = SPEED_10;
5546                         if (is_duplex == DUPLEX_FULL)
5547                                 vars->link_status |= LINK_10TFD;
5548                         else
5549                                 vars->link_status |= LINK_10THD;
5550                         break;
5551
5552                 case GP_STATUS_100M:
5553                         vars->line_speed = SPEED_100;
5554                         if (is_duplex == DUPLEX_FULL)
5555                                 vars->link_status |= LINK_100TXFD;
5556                         else
5557                                 vars->link_status |= LINK_100TXHD;
5558                         break;
5559
5560                 case GP_STATUS_1G:
5561                 case GP_STATUS_1G_KX:
5562                         vars->line_speed = SPEED_1000;
5563                         if (is_duplex == DUPLEX_FULL)
5564                                 vars->link_status |= LINK_1000TFD;
5565                         else
5566                                 vars->link_status |= LINK_1000THD;
5567                         break;
5568
5569                 case GP_STATUS_2_5G:
5570                         vars->line_speed = SPEED_2500;
5571                         if (is_duplex == DUPLEX_FULL)
5572                                 vars->link_status |= LINK_2500TFD;
5573                         else
5574                                 vars->link_status |= LINK_2500THD;
5575                         break;
5576
5577                 case GP_STATUS_5G:
5578                 case GP_STATUS_6G:
5579                         DP(NETIF_MSG_LINK,
5580                                  "link speed unsupported  gp_status 0x%x\n",
5581                                   speed_mask);
5582                         return -EINVAL;
5583
5584                 case GP_STATUS_10G_KX4:
5585                 case GP_STATUS_10G_HIG:
5586                 case GP_STATUS_10G_CX4:
5587                 case GP_STATUS_10G_KR:
5588                 case GP_STATUS_10G_SFI:
5589                 case GP_STATUS_10G_XFI:
5590                         vars->line_speed = SPEED_10000;
5591                         vars->link_status |= LINK_10GTFD;
5592                         break;
5593                 case GP_STATUS_20G_DXGXS:
5594                 case GP_STATUS_20G_KR2:
5595                         vars->line_speed = SPEED_20000;
5596                         vars->link_status |= LINK_20GTFD;
5597                         break;
5598                 default:
5599                         DP(NETIF_MSG_LINK,
5600                                   "link speed unsupported gp_status 0x%x\n",
5601                                   speed_mask);
5602                         return -EINVAL;
5603                 }
5604         } else { /* link_down */
5605                 DP(NETIF_MSG_LINK, "phy link down\n");
5606
5607                 vars->phy_link_up = 0;
5608
5609                 vars->duplex = DUPLEX_FULL;
5610                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5611                 vars->mac_type = MAC_TYPE_NONE;
5612         }
5613         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5614                     vars->phy_link_up, vars->line_speed);
5615         return 0;
5616 }
5617
5618 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5619                                       struct link_params *params,
5620                                       struct link_vars *vars)
5621 {
5622         struct bnx2x *bp = params->bp;
5623
5624         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5625         int rc = 0;
5626
5627         /* Read gp_status */
5628         CL22_RD_OVER_CL45(bp, phy,
5629                           MDIO_REG_BANK_GP_STATUS,
5630                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5631                           &gp_status);
5632         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5633                 duplex = DUPLEX_FULL;
5634         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5635                 link_up = 1;
5636         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5637         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5638                        gp_status, link_up, speed_mask);
5639         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5640                                          duplex);
5641         if (rc == -EINVAL)
5642                 return rc;
5643
5644         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5645                 if (SINGLE_MEDIA_DIRECT(params)) {
5646                         vars->duplex = duplex;
5647                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5648                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5649                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5650                                                       gp_status);
5651                 }
5652         } else { /* Link_down */
5653                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5654                     SINGLE_MEDIA_DIRECT(params)) {
5655                         /* Check signal is detected */
5656                         bnx2x_check_fallback_to_cl37(phy, params);
5657                 }
5658         }
5659
5660         /* Read LP advertised speeds*/
5661         if (SINGLE_MEDIA_DIRECT(params) &&
5662             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5663                 u16 val;
5664
5665                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5666                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5667
5668                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5669                         vars->link_status |=
5670                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5671                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5672                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5673                         vars->link_status |=
5674                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5675
5676                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5677                                   MDIO_OVER_1G_LP_UP1, &val);
5678
5679                 if (val & MDIO_OVER_1G_UP1_2_5G)
5680                         vars->link_status |=
5681                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5682                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5683                         vars->link_status |=
5684                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5685         }
5686
5687         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5688                    vars->duplex, vars->flow_ctrl, vars->link_status);
5689         return rc;
5690 }
5691
5692 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5693                                      struct link_params *params,
5694                                      struct link_vars *vars)
5695 {
5696         struct bnx2x *bp = params->bp;
5697         u8 lane;
5698         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5699         int rc = 0;
5700         lane = bnx2x_get_warpcore_lane(phy, params);
5701         /* Read gp_status */
5702         if ((params->loopback_mode) &&
5703             (phy->flags & FLAGS_WC_DUAL_MODE)) {
5704                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5705                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5706                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5707                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5708                 link_up &= 0x1;
5709         } else if ((phy->req_line_speed > SPEED_10000) &&
5710                 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5711                 u16 temp_link_up;
5712                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5713                                 1, &temp_link_up);
5714                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5715                                 1, &link_up);
5716                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5717                                temp_link_up, link_up);
5718                 link_up &= (1<<2);
5719                 if (link_up)
5720                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5721         } else {
5722                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5723                                 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5724                                 &gp_status1);
5725                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5726                 /* Check for either KR, 1G, or AN up. */
5727                 link_up = ((gp_status1 >> 8) |
5728                            (gp_status1 >> 12) |
5729                            (gp_status1)) &
5730                         (1 << lane);
5731                 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5732                         u16 an_link;
5733                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5734                                         MDIO_AN_REG_STATUS, &an_link);
5735                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5736                                         MDIO_AN_REG_STATUS, &an_link);
5737                         link_up |= (an_link & (1<<2));
5738                 }
5739                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5740                         u16 pd, gp_status4;
5741                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5742                                 /* Check Autoneg complete */
5743                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5744                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5745                                                 &gp_status4);
5746                                 if (gp_status4 & ((1<<12)<<lane))
5747                                         vars->link_status |=
5748                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5749
5750                                 /* Check parallel detect used */
5751                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5752                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5753                                                 &pd);
5754                                 if (pd & (1<<15))
5755                                         vars->link_status |=
5756                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5757                         }
5758                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5759                         vars->duplex = duplex;
5760                 }
5761         }
5762
5763         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5764             SINGLE_MEDIA_DIRECT(params)) {
5765                 u16 val;
5766
5767                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5768                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5769
5770                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5771                         vars->link_status |=
5772                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5773                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5774                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5775                         vars->link_status |=
5776                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5777
5778                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5779                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5780
5781                 if (val & MDIO_OVER_1G_UP1_2_5G)
5782                         vars->link_status |=
5783                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5784                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5785                         vars->link_status |=
5786                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5787
5788         }
5789
5790
5791         if (lane < 2) {
5792                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5793                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5794         } else {
5795                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5796                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5797         }
5798         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5799
5800         if ((lane & 1) == 0)
5801                 gp_speed <<= 8;
5802         gp_speed &= 0x3f00;
5803         link_up = !!link_up;
5804
5805         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5806                                          duplex);
5807
5808         /* In case of KR link down, start up the recovering procedure */
5809         if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5810             (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5811                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5812
5813         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5814                    vars->duplex, vars->flow_ctrl, vars->link_status);
5815         return rc;
5816 }
5817 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5818 {
5819         struct bnx2x *bp = params->bp;
5820         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5821         u16 lp_up2;
5822         u16 tx_driver;
5823         u16 bank;
5824
5825         /* Read precomp */
5826         CL22_RD_OVER_CL45(bp, phy,
5827                           MDIO_REG_BANK_OVER_1G,
5828                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5829
5830         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5831         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5832                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5833                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5834
5835         if (lp_up2 == 0)
5836                 return;
5837
5838         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5839               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5840                 CL22_RD_OVER_CL45(bp, phy,
5841                                   bank,
5842                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5843
5844                 /* Replace tx_driver bits [15:12] */
5845                 if (lp_up2 !=
5846                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5847                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5848                         tx_driver |= lp_up2;
5849                         CL22_WR_OVER_CL45(bp, phy,
5850                                           bank,
5851                                           MDIO_TX0_TX_DRIVER, tx_driver);
5852                 }
5853         }
5854 }
5855
5856 static int bnx2x_emac_program(struct link_params *params,
5857                               struct link_vars *vars)
5858 {
5859         struct bnx2x *bp = params->bp;
5860         u8 port = params->port;
5861         u16 mode = 0;
5862
5863         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5864         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5865                        EMAC_REG_EMAC_MODE,
5866                        (EMAC_MODE_25G_MODE |
5867                         EMAC_MODE_PORT_MII_10M |
5868                         EMAC_MODE_HALF_DUPLEX));
5869         switch (vars->line_speed) {
5870         case SPEED_10:
5871                 mode |= EMAC_MODE_PORT_MII_10M;
5872                 break;
5873
5874         case SPEED_100:
5875                 mode |= EMAC_MODE_PORT_MII;
5876                 break;
5877
5878         case SPEED_1000:
5879                 mode |= EMAC_MODE_PORT_GMII;
5880                 break;
5881
5882         case SPEED_2500:
5883                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5884                 break;
5885
5886         default:
5887                 /* 10G not valid for EMAC */
5888                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5889                            vars->line_speed);
5890                 return -EINVAL;
5891         }
5892
5893         if (vars->duplex == DUPLEX_HALF)
5894                 mode |= EMAC_MODE_HALF_DUPLEX;
5895         bnx2x_bits_en(bp,
5896                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5897                       mode);
5898
5899         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5900         return 0;
5901 }
5902
5903 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5904                                   struct link_params *params)
5905 {
5906
5907         u16 bank, i = 0;
5908         struct bnx2x *bp = params->bp;
5909
5910         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5911               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5912                         CL22_WR_OVER_CL45(bp, phy,
5913                                           bank,
5914                                           MDIO_RX0_RX_EQ_BOOST,
5915                                           phy->rx_preemphasis[i]);
5916         }
5917
5918         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5919                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5920                         CL22_WR_OVER_CL45(bp, phy,
5921                                           bank,
5922                                           MDIO_TX0_TX_DRIVER,
5923                                           phy->tx_preemphasis[i]);
5924         }
5925 }
5926
5927 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5928                                    struct link_params *params,
5929                                    struct link_vars *vars)
5930 {
5931         struct bnx2x *bp = params->bp;
5932         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5933                           (params->loopback_mode == LOOPBACK_XGXS));
5934         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5935                 if (SINGLE_MEDIA_DIRECT(params) &&
5936                     (params->feature_config_flags &
5937                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5938                         bnx2x_set_preemphasis(phy, params);
5939
5940                 /* Forced speed requested? */
5941                 if (vars->line_speed != SPEED_AUTO_NEG ||
5942                     (SINGLE_MEDIA_DIRECT(params) &&
5943                      params->loopback_mode == LOOPBACK_EXT)) {
5944                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5945
5946                         /* Disable autoneg */
5947                         bnx2x_set_autoneg(phy, params, vars, 0);
5948
5949                         /* Program speed and duplex */
5950                         bnx2x_program_serdes(phy, params, vars);
5951
5952                 } else { /* AN_mode */
5953                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5954
5955                         /* AN enabled */
5956                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5957
5958                         /* Program duplex & pause advertisement (for aneg) */
5959                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5960                                                           vars->ieee_fc);
5961
5962                         /* Enable autoneg */
5963                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5964
5965                         /* Enable and restart AN */
5966                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5967                 }
5968
5969         } else { /* SGMII mode */
5970                 DP(NETIF_MSG_LINK, "SGMII\n");
5971
5972                 bnx2x_initialize_sgmii_process(phy, params, vars);
5973         }
5974 }
5975
5976 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5977                           struct link_params *params,
5978                           struct link_vars *vars)
5979 {
5980         int rc;
5981         vars->phy_flags |= PHY_XGXS_FLAG;
5982         if ((phy->req_line_speed &&
5983              ((phy->req_line_speed == SPEED_100) ||
5984               (phy->req_line_speed == SPEED_10))) ||
5985             (!phy->req_line_speed &&
5986              (phy->speed_cap_mask >=
5987               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5988              (phy->speed_cap_mask <
5989               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5990             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5991                 vars->phy_flags |= PHY_SGMII_FLAG;
5992         else
5993                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5994
5995         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5996         bnx2x_set_aer_mmd(params, phy);
5997         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5998                 bnx2x_set_master_ln(params, phy);
5999
6000         rc = bnx2x_reset_unicore(params, phy, 0);
6001         /* Reset the SerDes and wait for reset bit return low */
6002         if (rc)
6003                 return rc;
6004
6005         bnx2x_set_aer_mmd(params, phy);
6006         /* Setting the masterLn_def again after the reset */
6007         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6008                 bnx2x_set_master_ln(params, phy);
6009                 bnx2x_set_swap_lanes(params, phy);
6010         }
6011
6012         return rc;
6013 }
6014
6015 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6016                                      struct bnx2x_phy *phy,
6017                                      struct link_params *params)
6018 {
6019         u16 cnt, ctrl;
6020         /* Wait for soft reset to get cleared up to 1 sec */
6021         for (cnt = 0; cnt < 1000; cnt++) {
6022                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6023                         bnx2x_cl22_read(bp, phy,
6024                                 MDIO_PMA_REG_CTRL, &ctrl);
6025                 else
6026                         bnx2x_cl45_read(bp, phy,
6027                                 MDIO_PMA_DEVAD,
6028                                 MDIO_PMA_REG_CTRL, &ctrl);
6029                 if (!(ctrl & (1<<15)))
6030                         break;
6031                 usleep_range(1000, 2000);
6032         }
6033
6034         if (cnt == 1000)
6035                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
6036                                       " Port %d\n",
6037                          params->port);
6038         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6039         return cnt;
6040 }
6041
6042 static void bnx2x_link_int_enable(struct link_params *params)
6043 {
6044         u8 port = params->port;
6045         u32 mask;
6046         struct bnx2x *bp = params->bp;
6047
6048         /* Setting the status to report on link up for either XGXS or SerDes */
6049         if (CHIP_IS_E3(bp)) {
6050                 mask = NIG_MASK_XGXS0_LINK_STATUS;
6051                 if (!(SINGLE_MEDIA_DIRECT(params)))
6052                         mask |= NIG_MASK_MI_INT;
6053         } else if (params->switch_cfg == SWITCH_CFG_10G) {
6054                 mask = (NIG_MASK_XGXS0_LINK10G |
6055                         NIG_MASK_XGXS0_LINK_STATUS);
6056                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6057                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6058                         params->phy[INT_PHY].type !=
6059                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6060                         mask |= NIG_MASK_MI_INT;
6061                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6062                 }
6063
6064         } else { /* SerDes */
6065                 mask = NIG_MASK_SERDES0_LINK_STATUS;
6066                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6067                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6068                         params->phy[INT_PHY].type !=
6069                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6070                         mask |= NIG_MASK_MI_INT;
6071                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6072                 }
6073         }
6074         bnx2x_bits_en(bp,
6075                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6076                       mask);
6077
6078         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6079                  (params->switch_cfg == SWITCH_CFG_10G),
6080                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6081         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6082                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6083                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6084                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6085         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6086            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6087            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6088 }
6089
6090 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6091                                      u8 exp_mi_int)
6092 {
6093         u32 latch_status = 0;
6094
6095         /* Disable the MI INT ( external phy int ) by writing 1 to the
6096          * status register. Link down indication is high-active-signal,
6097          * so in this case we need to write the status to clear the XOR
6098          */
6099         /* Read Latched signals */
6100         latch_status = REG_RD(bp,
6101                                     NIG_REG_LATCH_STATUS_0 + port*8);
6102         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6103         /* Handle only those with latched-signal=up.*/
6104         if (exp_mi_int)
6105                 bnx2x_bits_en(bp,
6106                               NIG_REG_STATUS_INTERRUPT_PORT0
6107                               + port*4,
6108                               NIG_STATUS_EMAC0_MI_INT);
6109         else
6110                 bnx2x_bits_dis(bp,
6111                                NIG_REG_STATUS_INTERRUPT_PORT0
6112                                + port*4,
6113                                NIG_STATUS_EMAC0_MI_INT);
6114
6115         if (latch_status & 1) {
6116
6117                 /* For all latched-signal=up : Re-Arm Latch signals */
6118                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6119                        (latch_status & 0xfffe) | (latch_status & 1));
6120         }
6121         /* For all latched-signal=up,Write original_signal to status */
6122 }
6123
6124 static void bnx2x_link_int_ack(struct link_params *params,
6125                                struct link_vars *vars, u8 is_10g_plus)
6126 {
6127         struct bnx2x *bp = params->bp;
6128         u8 port = params->port;
6129         u32 mask;
6130         /* First reset all status we assume only one line will be
6131          * change at a time
6132          */
6133         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6134                        (NIG_STATUS_XGXS0_LINK10G |
6135                         NIG_STATUS_XGXS0_LINK_STATUS |
6136                         NIG_STATUS_SERDES0_LINK_STATUS));
6137         if (vars->phy_link_up) {
6138                 if (USES_WARPCORE(bp))
6139                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6140                 else {
6141                         if (is_10g_plus)
6142                                 mask = NIG_STATUS_XGXS0_LINK10G;
6143                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6144                                 /* Disable the link interrupt by writing 1 to
6145                                  * the relevant lane in the status register
6146                                  */
6147                                 u32 ser_lane =
6148                                         ((params->lane_config &
6149                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6150                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6151                                 mask = ((1 << ser_lane) <<
6152                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6153                         } else
6154                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6155                 }
6156                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6157                                mask);
6158                 bnx2x_bits_en(bp,
6159                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6160                               mask);
6161         }
6162 }
6163
6164 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6165 {
6166         str[0] = '\0';
6167         (*len)--;
6168         return 0;
6169 }
6170
6171 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6172 {
6173         u16 ret;
6174
6175         if (*len < 10) {
6176                 /* Need more than 10chars for this format */
6177                 bnx2x_null_format_ver(num, str, len);
6178                 return -EINVAL;
6179         }
6180
6181         ret = scnprintf(str, *len, "%hx.%hx", num >> 16, num);
6182         *len -= ret;
6183         return 0;
6184 }
6185
6186 static int bnx2x_3_seq_format_ver(u32 num, u8 *str, u16 *len)
6187 {
6188         u16 ret;
6189
6190         if (*len < 10) {
6191                 /* Need more than 10chars for this format */
6192                 bnx2x_null_format_ver(num, str, len);
6193                 return -EINVAL;
6194         }
6195
6196         ret = scnprintf(str, *len, "%hhx.%hhx.%hhx", num >> 16, num >> 8, num);
6197         *len -= ret;
6198         return 0;
6199 }
6200
6201 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6202                                  u16 len)
6203 {
6204         struct bnx2x *bp;
6205         u32 spirom_ver = 0;
6206         int status = 0;
6207         u8 *ver_p = version;
6208         u16 remain_len = len;
6209         if (version == NULL || params == NULL)
6210                 return -EINVAL;
6211         bp = params->bp;
6212
6213         /* Extract first external phy*/
6214         version[0] = '\0';
6215         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6216
6217         if (params->phy[EXT_PHY1].format_fw_ver) {
6218                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6219                                                               ver_p,
6220                                                               &remain_len);
6221                 ver_p += (len - remain_len);
6222         }
6223         if ((params->num_phys == MAX_PHYS) &&
6224             (params->phy[EXT_PHY2].ver_addr != 0)) {
6225                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6226                 if (params->phy[EXT_PHY2].format_fw_ver) {
6227                         *ver_p = '/';
6228                         ver_p++;
6229                         remain_len--;
6230                         status |= params->phy[EXT_PHY2].format_fw_ver(
6231                                 spirom_ver,
6232                                 ver_p,
6233                                 &remain_len);
6234                         ver_p = version + (len - remain_len);
6235                 }
6236         }
6237         *ver_p = '\0';
6238         return status;
6239 }
6240
6241 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6242                                     struct link_params *params)
6243 {
6244         u8 port = params->port;
6245         struct bnx2x *bp = params->bp;
6246
6247         if (phy->req_line_speed != SPEED_1000) {
6248                 u32 md_devad = 0;
6249
6250                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6251
6252                 if (!CHIP_IS_E3(bp)) {
6253                         /* Change the uni_phy_addr in the nig */
6254                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6255                                                port*0x18));
6256
6257                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6258                                0x5);
6259                 }
6260
6261                 bnx2x_cl45_write(bp, phy,
6262                                  5,
6263                                  (MDIO_REG_BANK_AER_BLOCK +
6264                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6265                                  0x2800);
6266
6267                 bnx2x_cl45_write(bp, phy,
6268                                  5,
6269                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6270                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6271                                  0x6041);
6272                 msleep(200);
6273                 /* Set aer mmd back */
6274                 bnx2x_set_aer_mmd(params, phy);
6275
6276                 if (!CHIP_IS_E3(bp)) {
6277                         /* And md_devad */
6278                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6279                                md_devad);
6280                 }
6281         } else {
6282                 u16 mii_ctrl;
6283                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6284                 bnx2x_cl45_read(bp, phy, 5,
6285                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6286                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6287                                 &mii_ctrl);
6288                 bnx2x_cl45_write(bp, phy, 5,
6289                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6290                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6291                                  mii_ctrl |
6292                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6293         }
6294 }
6295
6296 int bnx2x_set_led(struct link_params *params,
6297                   struct link_vars *vars, u8 mode, u32 speed)
6298 {
6299         u8 port = params->port;
6300         u16 hw_led_mode = params->hw_led_mode;
6301         int rc = 0;
6302         u8 phy_idx;
6303         u32 tmp;
6304         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6305         struct bnx2x *bp = params->bp;
6306         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6307         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6308                  speed, hw_led_mode);
6309         /* In case */
6310         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6311                 if (params->phy[phy_idx].set_link_led) {
6312                         params->phy[phy_idx].set_link_led(
6313                                 &params->phy[phy_idx], params, mode);
6314                 }
6315         }
6316
6317         switch (mode) {
6318         case LED_MODE_FRONT_PANEL_OFF:
6319         case LED_MODE_OFF:
6320                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6321                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6322                        SHARED_HW_CFG_LED_MAC1);
6323
6324                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6325                 if (params->phy[EXT_PHY1].type ==
6326                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6327                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6328                                 EMAC_LED_100MB_OVERRIDE |
6329                                 EMAC_LED_10MB_OVERRIDE);
6330                 else
6331                         tmp |= EMAC_LED_OVERRIDE;
6332
6333                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6334                 break;
6335
6336         case LED_MODE_OPER:
6337                 /* For all other phys, OPER mode is same as ON, so in case
6338                  * link is down, do nothing
6339                  */
6340                 if (!vars->link_up)
6341                         break;
6342                 /* else: fall through */
6343         case LED_MODE_ON:
6344                 if (((params->phy[EXT_PHY1].type ==
6345                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6346                          (params->phy[EXT_PHY1].type ==
6347                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6348                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6349                         /* This is a work-around for E2+8727 Configurations */
6350                         if (mode == LED_MODE_ON ||
6351                                 speed == SPEED_10000){
6352                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6353                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6354
6355                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6356                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6357                                         (tmp | EMAC_LED_OVERRIDE));
6358                                 /* Return here without enabling traffic
6359                                  * LED blink and setting rate in ON mode.
6360                                  * In oper mode, enabling LED blink
6361                                  * and setting rate is needed.
6362                                  */
6363                                 if (mode == LED_MODE_ON)
6364                                         return rc;
6365                         }
6366                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6367                         /* This is a work-around for HW issue found when link
6368                          * is up in CL73
6369                          */
6370                         if ((!CHIP_IS_E3(bp)) ||
6371                             (CHIP_IS_E3(bp) &&
6372                              mode == LED_MODE_ON))
6373                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6374
6375                         if (CHIP_IS_E1x(bp) ||
6376                             CHIP_IS_E2(bp) ||
6377                             (mode == LED_MODE_ON))
6378                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6379                         else
6380                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6381                                        hw_led_mode);
6382                 } else if ((params->phy[EXT_PHY1].type ==
6383                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6384                            (mode == LED_MODE_ON)) {
6385                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6386                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6387                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6388                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6389                         /* Break here; otherwise, it'll disable the
6390                          * intended override.
6391                          */
6392                         break;
6393                 } else {
6394                         u32 nig_led_mode = ((params->hw_led_mode <<
6395                                              SHARED_HW_CFG_LED_MODE_SHIFT) ==
6396                                             SHARED_HW_CFG_LED_EXTPHY2) ?
6397                                 (SHARED_HW_CFG_LED_PHY1 >>
6398                                  SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
6399                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6400                                nig_led_mode);
6401                 }
6402
6403                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6404                 /* Set blinking rate to ~15.9Hz */
6405                 if (CHIP_IS_E3(bp))
6406                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6407                                LED_BLINK_RATE_VAL_E3);
6408                 else
6409                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6410                                LED_BLINK_RATE_VAL_E1X_E2);
6411                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6412                        port*4, 1);
6413                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6414                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6415                         (tmp & (~EMAC_LED_OVERRIDE)));
6416
6417                 if (CHIP_IS_E1(bp) &&
6418                     ((speed == SPEED_2500) ||
6419                      (speed == SPEED_1000) ||
6420                      (speed == SPEED_100) ||
6421                      (speed == SPEED_10))) {
6422                         /* For speeds less than 10G LED scheme is different */
6423                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6424                                + port*4, 1);
6425                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6426                                port*4, 0);
6427                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6428                                port*4, 1);
6429                 }
6430                 break;
6431
6432         default:
6433                 rc = -EINVAL;
6434                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6435                          mode);
6436                 break;
6437         }
6438         return rc;
6439
6440 }
6441
6442 /* This function comes to reflect the actual link state read DIRECTLY from the
6443  * HW
6444  */
6445 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6446                     u8 is_serdes)
6447 {
6448         struct bnx2x *bp = params->bp;
6449         u16 gp_status = 0, phy_index = 0;
6450         u8 ext_phy_link_up = 0, serdes_phy_type;
6451         struct link_vars temp_vars;
6452         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6453
6454         if (CHIP_IS_E3(bp)) {
6455                 u16 link_up;
6456                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6457                     > SPEED_10000) {
6458                         /* Check 20G link */
6459                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6460                                         1, &link_up);
6461                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6462                                         1, &link_up);
6463                         link_up &= (1<<2);
6464                 } else {
6465                         /* Check 10G link and below*/
6466                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6467                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6468                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6469                                         &gp_status);
6470                         gp_status = ((gp_status >> 8) & 0xf) |
6471                                 ((gp_status >> 12) & 0xf);
6472                         link_up = gp_status & (1 << lane);
6473                 }
6474                 if (!link_up)
6475                         return -ESRCH;
6476         } else {
6477                 CL22_RD_OVER_CL45(bp, int_phy,
6478                           MDIO_REG_BANK_GP_STATUS,
6479                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6480                           &gp_status);
6481         /* Link is up only if both local phy and external phy are up */
6482         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6483                 return -ESRCH;
6484         }
6485         /* In XGXS loopback mode, do not check external PHY */
6486         if (params->loopback_mode == LOOPBACK_XGXS)
6487                 return 0;
6488
6489         switch (params->num_phys) {
6490         case 1:
6491                 /* No external PHY */
6492                 return 0;
6493         case 2:
6494                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6495                         &params->phy[EXT_PHY1],
6496                         params, &temp_vars);
6497                 break;
6498         case 3: /* Dual Media */
6499                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6500                       phy_index++) {
6501                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6502                                             ETH_PHY_SFPP_10G_FIBER) ||
6503                                            (params->phy[phy_index].media_type ==
6504                                             ETH_PHY_SFP_1G_FIBER) ||
6505                                            (params->phy[phy_index].media_type ==
6506                                             ETH_PHY_XFP_FIBER) ||
6507                                            (params->phy[phy_index].media_type ==
6508                                             ETH_PHY_DA_TWINAX));
6509
6510                         if (is_serdes != serdes_phy_type)
6511                                 continue;
6512                         if (params->phy[phy_index].read_status) {
6513                                 ext_phy_link_up |=
6514                                         params->phy[phy_index].read_status(
6515                                                 &params->phy[phy_index],
6516                                                 params, &temp_vars);
6517                         }
6518                 }
6519                 break;
6520         }
6521         if (ext_phy_link_up)
6522                 return 0;
6523         return -ESRCH;
6524 }
6525
6526 static int bnx2x_link_initialize(struct link_params *params,
6527                                  struct link_vars *vars)
6528 {
6529         u8 phy_index, non_ext_phy;
6530         struct bnx2x *bp = params->bp;
6531         /* In case of external phy existence, the line speed would be the
6532          * line speed linked up by the external phy. In case it is direct
6533          * only, then the line_speed during initialization will be
6534          * equal to the req_line_speed
6535          */
6536         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6537
6538         /* Initialize the internal phy in case this is a direct board
6539          * (no external phys), or this board has external phy which requires
6540          * to first.
6541          */
6542         if (!USES_WARPCORE(bp))
6543                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6544         /* init ext phy and enable link state int */
6545         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6546                        (params->loopback_mode == LOOPBACK_XGXS));
6547
6548         if (non_ext_phy ||
6549             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6550             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6551                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6552                 if (vars->line_speed == SPEED_AUTO_NEG &&
6553                     (CHIP_IS_E1x(bp) ||
6554                      CHIP_IS_E2(bp)))
6555                         bnx2x_set_parallel_detection(phy, params);
6556                 if (params->phy[INT_PHY].config_init)
6557                         params->phy[INT_PHY].config_init(phy, params, vars);
6558         }
6559
6560         /* Re-read this value in case it was changed inside config_init due to
6561          * limitations of optic module
6562          */
6563         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6564
6565         /* Init external phy*/
6566         if (non_ext_phy) {
6567                 if (params->phy[INT_PHY].supported &
6568                     SUPPORTED_FIBRE)
6569                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6570         } else {
6571                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6572                       phy_index++) {
6573                         /* No need to initialize second phy in case of first
6574                          * phy only selection. In case of second phy, we do
6575                          * need to initialize the first phy, since they are
6576                          * connected.
6577                          */
6578                         if (params->phy[phy_index].supported &
6579                             SUPPORTED_FIBRE)
6580                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6581
6582                         if (phy_index == EXT_PHY2 &&
6583                             (bnx2x_phy_selection(params) ==
6584                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6585                                 DP(NETIF_MSG_LINK,
6586                                    "Not initializing second phy\n");
6587                                 continue;
6588                         }
6589                         params->phy[phy_index].config_init(
6590                                 &params->phy[phy_index],
6591                                 params, vars);
6592                 }
6593         }
6594         /* Reset the interrupt indication after phy was initialized */
6595         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6596                        params->port*4,
6597                        (NIG_STATUS_XGXS0_LINK10G |
6598                         NIG_STATUS_XGXS0_LINK_STATUS |
6599                         NIG_STATUS_SERDES0_LINK_STATUS |
6600                         NIG_MASK_MI_INT));
6601         return 0;
6602 }
6603
6604 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6605                                  struct link_params *params)
6606 {
6607         /* Reset the SerDes/XGXS */
6608         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6609                (0x1ff << (params->port*16)));
6610 }
6611
6612 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6613                                         struct link_params *params)
6614 {
6615         struct bnx2x *bp = params->bp;
6616         u8 gpio_port;
6617         /* HW reset */
6618         if (CHIP_IS_E2(bp))
6619                 gpio_port = BP_PATH(bp);
6620         else
6621                 gpio_port = params->port;
6622         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6623                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6624                        gpio_port);
6625         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6626                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6627                        gpio_port);
6628         DP(NETIF_MSG_LINK, "reset external PHY\n");
6629 }
6630
6631 static int bnx2x_update_link_down(struct link_params *params,
6632                                   struct link_vars *vars)
6633 {
6634         struct bnx2x *bp = params->bp;
6635         u8 port = params->port;
6636
6637         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6638         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6639         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6640         /* Indicate no mac active */
6641         vars->mac_type = MAC_TYPE_NONE;
6642
6643         /* Update shared memory */
6644         vars->link_status &= ~LINK_UPDATE_MASK;
6645         vars->line_speed = 0;
6646         bnx2x_update_mng(params, vars->link_status);
6647
6648         /* Activate nig drain */
6649         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6650
6651         /* Disable emac */
6652         if (!CHIP_IS_E3(bp))
6653                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6654
6655         usleep_range(10000, 20000);
6656         /* Reset BigMac/Xmac */
6657         if (CHIP_IS_E1x(bp) ||
6658             CHIP_IS_E2(bp))
6659                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6660
6661         if (CHIP_IS_E3(bp)) {
6662                 /* Prevent LPI Generation by chip */
6663                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6664                        0);
6665                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6666                        0);
6667                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6668                                       SHMEM_EEE_ACTIVE_BIT);
6669
6670                 bnx2x_update_mng_eee(params, vars->eee_status);
6671                 bnx2x_set_xmac_rxtx(params, 0);
6672                 bnx2x_set_umac_rxtx(params, 0);
6673         }
6674
6675         return 0;
6676 }
6677
6678 static int bnx2x_update_link_up(struct link_params *params,
6679                                 struct link_vars *vars,
6680                                 u8 link_10g)
6681 {
6682         struct bnx2x *bp = params->bp;
6683         u8 phy_idx, port = params->port;
6684         int rc = 0;
6685
6686         vars->link_status |= (LINK_STATUS_LINK_UP |
6687                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6688         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6689
6690         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6691                 vars->link_status |=
6692                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6693
6694         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6695                 vars->link_status |=
6696                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6697         if (USES_WARPCORE(bp)) {
6698                 if (link_10g) {
6699                         if (bnx2x_xmac_enable(params, vars, 0) ==
6700                             -ESRCH) {
6701                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6702                                 vars->link_up = 0;
6703                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6704                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6705                         }
6706                 } else
6707                         bnx2x_umac_enable(params, vars, 0);
6708                 bnx2x_set_led(params, vars,
6709                               LED_MODE_OPER, vars->line_speed);
6710
6711                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6712                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6713                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6714                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6715                                (params->port << 2), 1);
6716                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6717                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6718                                (params->port << 2), 0xfc20);
6719                 }
6720         }
6721         if ((CHIP_IS_E1x(bp) ||
6722              CHIP_IS_E2(bp))) {
6723                 if (link_10g) {
6724                         if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6725                             -ESRCH) {
6726                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6727                                 vars->link_up = 0;
6728                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6729                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6730                         }
6731
6732                         bnx2x_set_led(params, vars,
6733                                       LED_MODE_OPER, SPEED_10000);
6734                 } else {
6735                         rc = bnx2x_emac_program(params, vars);
6736                         bnx2x_emac_enable(params, vars, 0);
6737
6738                         /* AN complete? */
6739                         if ((vars->link_status &
6740                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6741                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6742                             SINGLE_MEDIA_DIRECT(params))
6743                                 bnx2x_set_gmii_tx_driver(params);
6744                 }
6745         }
6746
6747         /* PBF - link up */
6748         if (CHIP_IS_E1x(bp))
6749                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6750                                        vars->line_speed);
6751
6752         /* Disable drain */
6753         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6754
6755         /* Update shared memory */
6756         bnx2x_update_mng(params, vars->link_status);
6757         bnx2x_update_mng_eee(params, vars->eee_status);
6758         /* Check remote fault */
6759         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6760                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6761                         bnx2x_check_half_open_conn(params, vars, 0);
6762                         break;
6763                 }
6764         }
6765         msleep(20);
6766         return rc;
6767 }
6768
6769 static void bnx2x_chng_link_count(struct link_params *params, bool clear)
6770 {
6771         struct bnx2x *bp = params->bp;
6772         u32 addr, val;
6773
6774         /* Verify the link_change_count is supported by the MFW */
6775         if (!(SHMEM2_HAS(bp, link_change_count)))
6776                 return;
6777
6778         addr = params->shmem2_base +
6779                 offsetof(struct shmem2_region, link_change_count[params->port]);
6780         if (clear)
6781                 val = 0;
6782         else
6783                 val = REG_RD(bp, addr) + 1;
6784         REG_WR(bp, addr, val);
6785 }
6786
6787 /* The bnx2x_link_update function should be called upon link
6788  * interrupt.
6789  * Link is considered up as follows:
6790  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6791  *   to be up
6792  * - SINGLE_MEDIA - The link between the 577xx and the external
6793  *   phy (XGXS) need to up as well as the external link of the
6794  *   phy (PHY_EXT1)
6795  * - DUAL_MEDIA - The link between the 577xx and the first
6796  *   external phy needs to be up, and at least one of the 2
6797  *   external phy link must be up.
6798  */
6799 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6800 {
6801         struct bnx2x *bp = params->bp;
6802         struct link_vars phy_vars[MAX_PHYS];
6803         u8 port = params->port;
6804         u8 link_10g_plus, phy_index;
6805         u32 prev_link_status = vars->link_status;
6806         u8 ext_phy_link_up = 0, cur_link_up;
6807         int rc = 0;
6808         u8 is_mi_int = 0;
6809         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6810         u8 active_external_phy = INT_PHY;
6811         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6812         vars->link_status &= ~LINK_UPDATE_MASK;
6813         for (phy_index = INT_PHY; phy_index < params->num_phys;
6814               phy_index++) {
6815                 phy_vars[phy_index].flow_ctrl = 0;
6816                 phy_vars[phy_index].link_status = 0;
6817                 phy_vars[phy_index].line_speed = 0;
6818                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6819                 phy_vars[phy_index].phy_link_up = 0;
6820                 phy_vars[phy_index].link_up = 0;
6821                 phy_vars[phy_index].fault_detected = 0;
6822                 /* different consideration, since vars holds inner state */
6823                 phy_vars[phy_index].eee_status = vars->eee_status;
6824         }
6825
6826         if (USES_WARPCORE(bp))
6827                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6828
6829         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6830                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6831                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6832
6833         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6834                                 port*0x18) > 0);
6835         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6836                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6837                  is_mi_int,
6838                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6839
6840         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6841           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6842           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6843
6844         /* Disable emac */
6845         if (!CHIP_IS_E3(bp))
6846                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6847
6848         /* Step 1:
6849          * Check external link change only for external phys, and apply
6850          * priority selection between them in case the link on both phys
6851          * is up. Note that instead of the common vars, a temporary
6852          * vars argument is used since each phy may have different link/
6853          * speed/duplex result
6854          */
6855         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6856               phy_index++) {
6857                 struct bnx2x_phy *phy = &params->phy[phy_index];
6858                 if (!phy->read_status)
6859                         continue;
6860                 /* Read link status and params of this ext phy */
6861                 cur_link_up = phy->read_status(phy, params,
6862                                                &phy_vars[phy_index]);
6863                 if (cur_link_up) {
6864                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6865                                    phy_index);
6866                 } else {
6867                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6868                                    phy_index);
6869                         continue;
6870                 }
6871
6872                 if (!ext_phy_link_up) {
6873                         ext_phy_link_up = 1;
6874                         active_external_phy = phy_index;
6875                 } else {
6876                         switch (bnx2x_phy_selection(params)) {
6877                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6878                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6879                         /* In this option, the first PHY makes sure to pass the
6880                          * traffic through itself only.
6881                          * Its not clear how to reset the link on the second phy
6882                          */
6883                                 active_external_phy = EXT_PHY1;
6884                                 break;
6885                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6886                         /* In this option, the first PHY makes sure to pass the
6887                          * traffic through the second PHY.
6888                          */
6889                                 active_external_phy = EXT_PHY2;
6890                                 break;
6891                         default:
6892                         /* Link indication on both PHYs with the following cases
6893                          * is invalid:
6894                          * - FIRST_PHY means that second phy wasn't initialized,
6895                          * hence its link is expected to be down
6896                          * - SECOND_PHY means that first phy should not be able
6897                          * to link up by itself (using configuration)
6898                          * - DEFAULT should be overridden during initialization
6899                          */
6900                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6901                                            "mpc=0x%x. DISABLING LINK !!!\n",
6902                                            params->multi_phy_config);
6903                                 ext_phy_link_up = 0;
6904                                 break;
6905                         }
6906                 }
6907         }
6908         prev_line_speed = vars->line_speed;
6909         /* Step 2:
6910          * Read the status of the internal phy. In case of
6911          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6912          * otherwise this is the link between the 577xx and the first
6913          * external phy
6914          */
6915         if (params->phy[INT_PHY].read_status)
6916                 params->phy[INT_PHY].read_status(
6917                         &params->phy[INT_PHY],
6918                         params, vars);
6919         /* The INT_PHY flow control reside in the vars. This include the
6920          * case where the speed or flow control are not set to AUTO.
6921          * Otherwise, the active external phy flow control result is set
6922          * to the vars. The ext_phy_line_speed is needed to check if the
6923          * speed is different between the internal phy and external phy.
6924          * This case may be result of intermediate link speed change.
6925          */
6926         if (active_external_phy > INT_PHY) {
6927                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6928                 /* Link speed is taken from the XGXS. AN and FC result from
6929                  * the external phy.
6930                  */
6931                 vars->link_status |= phy_vars[active_external_phy].link_status;
6932
6933                 /* if active_external_phy is first PHY and link is up - disable
6934                  * disable TX on second external PHY
6935                  */
6936                 if (active_external_phy == EXT_PHY1) {
6937                         if (params->phy[EXT_PHY2].phy_specific_func) {
6938                                 DP(NETIF_MSG_LINK,
6939                                    "Disabling TX on EXT_PHY2\n");
6940                                 params->phy[EXT_PHY2].phy_specific_func(
6941                                         &params->phy[EXT_PHY2],
6942                                         params, DISABLE_TX);
6943                         }
6944                 }
6945
6946                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6947                 vars->duplex = phy_vars[active_external_phy].duplex;
6948                 if (params->phy[active_external_phy].supported &
6949                     SUPPORTED_FIBRE)
6950                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6951                 else
6952                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6953
6954                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6955
6956                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6957                            active_external_phy);
6958         }
6959
6960         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6961               phy_index++) {
6962                 if (params->phy[phy_index].flags &
6963                     FLAGS_REARM_LATCH_SIGNAL) {
6964                         bnx2x_rearm_latch_signal(bp, port,
6965                                                  phy_index ==
6966                                                  active_external_phy);
6967                         break;
6968                 }
6969         }
6970         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6971                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6972                    vars->link_status, ext_phy_line_speed);
6973         /* Upon link speed change set the NIG into drain mode. Comes to
6974          * deals with possible FIFO glitch due to clk change when speed
6975          * is decreased without link down indicator
6976          */
6977
6978         if (vars->phy_link_up) {
6979                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6980                     (ext_phy_line_speed != vars->line_speed)) {
6981                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6982                                    " different than the external"
6983                                    " link speed %d\n", vars->line_speed,
6984                                    ext_phy_line_speed);
6985                         vars->phy_link_up = 0;
6986                 } else if (prev_line_speed != vars->line_speed) {
6987                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6988                                0);
6989                         usleep_range(1000, 2000);
6990                 }
6991         }
6992
6993         /* Anything 10 and over uses the bmac */
6994         link_10g_plus = (vars->line_speed >= SPEED_10000);
6995
6996         bnx2x_link_int_ack(params, vars, link_10g_plus);
6997
6998         /* In case external phy link is up, and internal link is down
6999          * (not initialized yet probably after link initialization, it
7000          * needs to be initialized.
7001          * Note that after link down-up as result of cable plug, the xgxs
7002          * link would probably become up again without the need
7003          * initialize it
7004          */
7005         if (!(SINGLE_MEDIA_DIRECT(params))) {
7006                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
7007                            " init_preceding = %d\n", ext_phy_link_up,
7008                            vars->phy_link_up,
7009                            params->phy[EXT_PHY1].flags &
7010                            FLAGS_INIT_XGXS_FIRST);
7011                 if (!(params->phy[EXT_PHY1].flags &
7012                       FLAGS_INIT_XGXS_FIRST)
7013                     && ext_phy_link_up && !vars->phy_link_up) {
7014                         vars->line_speed = ext_phy_line_speed;
7015                         if (vars->line_speed < SPEED_1000)
7016                                 vars->phy_flags |= PHY_SGMII_FLAG;
7017                         else
7018                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
7019
7020                         if (params->phy[INT_PHY].config_init)
7021                                 params->phy[INT_PHY].config_init(
7022                                         &params->phy[INT_PHY], params,
7023                                                 vars);
7024                 }
7025         }
7026         /* Link is up only if both local phy and external phy (in case of
7027          * non-direct board) are up and no fault detected on active PHY.
7028          */
7029         vars->link_up = (vars->phy_link_up &&
7030                          (ext_phy_link_up ||
7031                           SINGLE_MEDIA_DIRECT(params)) &&
7032                          (phy_vars[active_external_phy].fault_detected == 0));
7033
7034         /* Update the PFC configuration in case it was changed */
7035         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
7036                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7037         else
7038                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7039
7040         if (vars->link_up)
7041                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
7042         else
7043                 rc = bnx2x_update_link_down(params, vars);
7044
7045         if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)
7046                 bnx2x_chng_link_count(params, false);
7047
7048         /* Update MCP link status was changed */
7049         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7050                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7051
7052         return rc;
7053 }
7054
7055 /*****************************************************************************/
7056 /*                          External Phy section                             */
7057 /*****************************************************************************/
7058 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7059 {
7060         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7061                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7062         usleep_range(1000, 2000);
7063         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7064                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7065 }
7066
7067 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7068                                       u32 spirom_ver, u32 ver_addr)
7069 {
7070         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7071                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7072
7073         if (ver_addr)
7074                 REG_WR(bp, ver_addr, spirom_ver);
7075 }
7076
7077 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7078                                       struct bnx2x_phy *phy,
7079                                       u8 port)
7080 {
7081         u16 fw_ver1, fw_ver2;
7082
7083         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7084                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7085         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7086                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7087         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7088                                   phy->ver_addr);
7089 }
7090
7091 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7092                                        struct bnx2x_phy *phy,
7093                                        struct link_vars *vars)
7094 {
7095         u16 val;
7096         bnx2x_cl45_read(bp, phy,
7097                         MDIO_AN_DEVAD,
7098                         MDIO_AN_REG_STATUS, &val);
7099         bnx2x_cl45_read(bp, phy,
7100                         MDIO_AN_DEVAD,
7101                         MDIO_AN_REG_STATUS, &val);
7102         if (val & (1<<5))
7103                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7104         if ((val & (1<<0)) == 0)
7105                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7106 }
7107
7108 /******************************************************************/
7109 /*              common BCM8073/BCM8727 PHY SECTION                */
7110 /******************************************************************/
7111 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7112                                   struct link_params *params,
7113                                   struct link_vars *vars)
7114 {
7115         struct bnx2x *bp = params->bp;
7116         if (phy->req_line_speed == SPEED_10 ||
7117             phy->req_line_speed == SPEED_100) {
7118                 vars->flow_ctrl = phy->req_flow_ctrl;
7119                 return;
7120         }
7121
7122         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7123             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7124                 u16 pause_result;
7125                 u16 ld_pause;           /* local */
7126                 u16 lp_pause;           /* link partner */
7127                 bnx2x_cl45_read(bp, phy,
7128                                 MDIO_AN_DEVAD,
7129                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7130
7131                 bnx2x_cl45_read(bp, phy,
7132                                 MDIO_AN_DEVAD,
7133                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7134                 pause_result = (ld_pause &
7135                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7136                 pause_result |= (lp_pause &
7137                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7138
7139                 bnx2x_pause_resolve(phy, params, vars, pause_result);
7140                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7141                            pause_result);
7142         }
7143 }
7144 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7145                                              struct bnx2x_phy *phy,
7146                                              u8 port)
7147 {
7148         u32 count = 0;
7149         u16 fw_ver1, fw_msgout;
7150         int rc = 0;
7151
7152         /* Boot port from external ROM  */
7153         /* EDC grst */
7154         bnx2x_cl45_write(bp, phy,
7155                          MDIO_PMA_DEVAD,
7156                          MDIO_PMA_REG_GEN_CTRL,
7157                          0x0001);
7158
7159         /* Ucode reboot and rst */
7160         bnx2x_cl45_write(bp, phy,
7161                          MDIO_PMA_DEVAD,
7162                          MDIO_PMA_REG_GEN_CTRL,
7163                          0x008c);
7164
7165         bnx2x_cl45_write(bp, phy,
7166                          MDIO_PMA_DEVAD,
7167                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7168
7169         /* Reset internal microprocessor */
7170         bnx2x_cl45_write(bp, phy,
7171                          MDIO_PMA_DEVAD,
7172                          MDIO_PMA_REG_GEN_CTRL,
7173                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7174
7175         /* Release srst bit */
7176         bnx2x_cl45_write(bp, phy,
7177                          MDIO_PMA_DEVAD,
7178                          MDIO_PMA_REG_GEN_CTRL,
7179                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7180
7181         /* Delay 100ms per the PHY specifications */
7182         msleep(100);
7183
7184         /* 8073 sometimes taking longer to download */
7185         do {
7186                 count++;
7187                 if (count > 300) {
7188                         DP(NETIF_MSG_LINK,
7189                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7190                                  "Download failed. fw version = 0x%x\n",
7191                                  port, fw_ver1);
7192                         rc = -EINVAL;
7193                         break;
7194                 }
7195
7196                 bnx2x_cl45_read(bp, phy,
7197                                 MDIO_PMA_DEVAD,
7198                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7199                 bnx2x_cl45_read(bp, phy,
7200                                 MDIO_PMA_DEVAD,
7201                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7202
7203                 usleep_range(1000, 2000);
7204         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7205                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7206                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7207
7208         /* Clear ser_boot_ctl bit */
7209         bnx2x_cl45_write(bp, phy,
7210                          MDIO_PMA_DEVAD,
7211                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7212         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7213
7214         DP(NETIF_MSG_LINK,
7215                  "bnx2x_8073_8727_external_rom_boot port %x:"
7216                  "Download complete. fw version = 0x%x\n",
7217                  port, fw_ver1);
7218
7219         return rc;
7220 }
7221
7222 /******************************************************************/
7223 /*                      BCM8073 PHY SECTION                       */
7224 /******************************************************************/
7225 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7226 {
7227         /* This is only required for 8073A1, version 102 only */
7228         u16 val;
7229
7230         /* Read 8073 HW revision*/
7231         bnx2x_cl45_read(bp, phy,
7232                         MDIO_PMA_DEVAD,
7233                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7234
7235         if (val != 1) {
7236                 /* No need to workaround in 8073 A1 */
7237                 return 0;
7238         }
7239
7240         bnx2x_cl45_read(bp, phy,
7241                         MDIO_PMA_DEVAD,
7242                         MDIO_PMA_REG_ROM_VER2, &val);
7243
7244         /* SNR should be applied only for version 0x102 */
7245         if (val != 0x102)
7246                 return 0;
7247
7248         return 1;
7249 }
7250
7251 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7252 {
7253         u16 val, cnt, cnt1 ;
7254
7255         bnx2x_cl45_read(bp, phy,
7256                         MDIO_PMA_DEVAD,
7257                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7258
7259         if (val > 0) {
7260                 /* No need to workaround in 8073 A1 */
7261                 return 0;
7262         }
7263         /* XAUI workaround in 8073 A0: */
7264
7265         /* After loading the boot ROM and restarting Autoneg, poll
7266          * Dev1, Reg $C820:
7267          */
7268
7269         for (cnt = 0; cnt < 1000; cnt++) {
7270                 bnx2x_cl45_read(bp, phy,
7271                                 MDIO_PMA_DEVAD,
7272                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7273                                 &val);
7274                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7275                    * system initialization (XAUI work-around not required, as
7276                    * these bits indicate 2.5G or 1G link up).
7277                    */
7278                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7279                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7280                         return 0;
7281                 } else if (!(val & (1<<15))) {
7282                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7283                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7284                          * MSB (bit15) goes to 1 (indicating that the XAUI
7285                          * workaround has completed), then continue on with
7286                          * system initialization.
7287                          */
7288                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7289                                 bnx2x_cl45_read(bp, phy,
7290                                         MDIO_PMA_DEVAD,
7291                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7292                                 if (val & (1<<15)) {
7293                                         DP(NETIF_MSG_LINK,
7294                                           "XAUI workaround has completed\n");
7295                                         return 0;
7296                                  }
7297                                  usleep_range(3000, 6000);
7298                         }
7299                         break;
7300                 }
7301                 usleep_range(3000, 6000);
7302         }
7303         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7304         return -EINVAL;
7305 }
7306
7307 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7308 {
7309         /* Force KR or KX */
7310         bnx2x_cl45_write(bp, phy,
7311                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7312         bnx2x_cl45_write(bp, phy,
7313                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7314         bnx2x_cl45_write(bp, phy,
7315                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7316         bnx2x_cl45_write(bp, phy,
7317                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7318 }
7319
7320 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7321                                       struct bnx2x_phy *phy,
7322                                       struct link_vars *vars)
7323 {
7324         u16 cl37_val;
7325         struct bnx2x *bp = params->bp;
7326         bnx2x_cl45_read(bp, phy,
7327                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7328
7329         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7330         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7331         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7332         if ((vars->ieee_fc &
7333             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7334             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7335                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7336         }
7337         if ((vars->ieee_fc &
7338             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7339             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7340                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7341         }
7342         if ((vars->ieee_fc &
7343             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7344             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7345                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7346         }
7347         DP(NETIF_MSG_LINK,
7348                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7349
7350         bnx2x_cl45_write(bp, phy,
7351                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7352         msleep(500);
7353 }
7354
7355 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7356                                      struct link_params *params,
7357                                      u32 action)
7358 {
7359         struct bnx2x *bp = params->bp;
7360         switch (action) {
7361         case PHY_INIT:
7362                 /* Enable LASI */
7363                 bnx2x_cl45_write(bp, phy,
7364                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7365                 bnx2x_cl45_write(bp, phy,
7366                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7367                 break;
7368         }
7369 }
7370
7371 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7372                                   struct link_params *params,
7373                                   struct link_vars *vars)
7374 {
7375         struct bnx2x *bp = params->bp;
7376         u16 val = 0, tmp1;
7377         u8 gpio_port;
7378         DP(NETIF_MSG_LINK, "Init 8073\n");
7379
7380         if (CHIP_IS_E2(bp))
7381                 gpio_port = BP_PATH(bp);
7382         else
7383                 gpio_port = params->port;
7384         /* Restore normal power mode*/
7385         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7386                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7387
7388         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7389                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7390
7391         bnx2x_8073_specific_func(phy, params, PHY_INIT);
7392         bnx2x_8073_set_pause_cl37(params, phy, vars);
7393
7394         bnx2x_cl45_read(bp, phy,
7395                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7396
7397         bnx2x_cl45_read(bp, phy,
7398                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7399
7400         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7401
7402         /* Swap polarity if required - Must be done only in non-1G mode */
7403         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7404                 /* Configure the 8073 to swap _P and _N of the KR lines */
7405                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7406                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7407                 bnx2x_cl45_read(bp, phy,
7408                                 MDIO_PMA_DEVAD,
7409                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7410                 bnx2x_cl45_write(bp, phy,
7411                                  MDIO_PMA_DEVAD,
7412                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7413                                  (val | (3<<9)));
7414         }
7415
7416
7417         /* Enable CL37 BAM */
7418         if (REG_RD(bp, params->shmem_base +
7419                          offsetof(struct shmem_region, dev_info.
7420                                   port_hw_config[params->port].default_cfg)) &
7421             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7422
7423                 bnx2x_cl45_read(bp, phy,
7424                                 MDIO_AN_DEVAD,
7425                                 MDIO_AN_REG_8073_BAM, &val);
7426                 bnx2x_cl45_write(bp, phy,
7427                                  MDIO_AN_DEVAD,
7428                                  MDIO_AN_REG_8073_BAM, val | 1);
7429                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7430         }
7431         if (params->loopback_mode == LOOPBACK_EXT) {
7432                 bnx2x_807x_force_10G(bp, phy);
7433                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7434                 return 0;
7435         } else {
7436                 bnx2x_cl45_write(bp, phy,
7437                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7438         }
7439         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7440                 if (phy->req_line_speed == SPEED_10000) {
7441                         val = (1<<7);
7442                 } else if (phy->req_line_speed ==  SPEED_2500) {
7443                         val = (1<<5);
7444                         /* Note that 2.5G works only when used with 1G
7445                          * advertisement
7446                          */
7447                 } else
7448                         val = (1<<5);
7449         } else {
7450                 val = 0;
7451                 if (phy->speed_cap_mask &
7452                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7453                         val |= (1<<7);
7454
7455                 /* Note that 2.5G works only when used with 1G advertisement */
7456                 if (phy->speed_cap_mask &
7457                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7458                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7459                         val |= (1<<5);
7460                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7461         }
7462
7463         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7464         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7465
7466         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7467              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7468             (phy->req_line_speed == SPEED_2500)) {
7469                 u16 phy_ver;
7470                 /* Allow 2.5G for A1 and above */
7471                 bnx2x_cl45_read(bp, phy,
7472                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7473                                 &phy_ver);
7474                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7475                 if (phy_ver > 0)
7476                         tmp1 |= 1;
7477                 else
7478                         tmp1 &= 0xfffe;
7479         } else {
7480                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7481                 tmp1 &= 0xfffe;
7482         }
7483
7484         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7485         /* Add support for CL37 (passive mode) II */
7486
7487         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7488         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7489                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7490                                   0x20 : 0x40)));
7491
7492         /* Add support for CL37 (passive mode) III */
7493         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7494
7495         /* The SNR will improve about 2db by changing BW and FEE main
7496          * tap. Rest commands are executed after link is up
7497          * Change FFE main cursor to 5 in EDC register
7498          */
7499         if (bnx2x_8073_is_snr_needed(bp, phy))
7500                 bnx2x_cl45_write(bp, phy,
7501                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7502                                  0xFB0C);
7503
7504         /* Enable FEC (Forware Error Correction) Request in the AN */
7505         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7506         tmp1 |= (1<<15);
7507         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7508
7509         bnx2x_ext_phy_set_pause(params, phy, vars);
7510
7511         /* Restart autoneg */
7512         msleep(500);
7513         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7514         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7515                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7516         return 0;
7517 }
7518
7519 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7520                                  struct link_params *params,
7521                                  struct link_vars *vars)
7522 {
7523         struct bnx2x *bp = params->bp;
7524         u8 link_up = 0;
7525         u16 val1, val2;
7526         u16 link_status = 0;
7527         u16 an1000_status = 0;
7528
7529         bnx2x_cl45_read(bp, phy,
7530                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7531
7532         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7533
7534         /* Clear the interrupt LASI status register */
7535         bnx2x_cl45_read(bp, phy,
7536                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7537         bnx2x_cl45_read(bp, phy,
7538                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7539         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7540         /* Clear MSG-OUT */
7541         bnx2x_cl45_read(bp, phy,
7542                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7543
7544         /* Check the LASI */
7545         bnx2x_cl45_read(bp, phy,
7546                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7547
7548         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7549
7550         /* Check the link status */
7551         bnx2x_cl45_read(bp, phy,
7552                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7553         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7554
7555         bnx2x_cl45_read(bp, phy,
7556                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7557         bnx2x_cl45_read(bp, phy,
7558                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7559         link_up = ((val1 & 4) == 4);
7560         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7561
7562         if (link_up &&
7563              ((phy->req_line_speed != SPEED_10000))) {
7564                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7565                         return 0;
7566         }
7567         bnx2x_cl45_read(bp, phy,
7568                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7569         bnx2x_cl45_read(bp, phy,
7570                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7571
7572         /* Check the link status on 1.1.2 */
7573         bnx2x_cl45_read(bp, phy,
7574                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7575         bnx2x_cl45_read(bp, phy,
7576                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7577         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7578                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7579
7580         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7581         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7582                 /* The SNR will improve about 2dbby changing the BW and FEE main
7583                  * tap. The 1st write to change FFE main tap is set before
7584                  * restart AN. Change PLL Bandwidth in EDC register
7585                  */
7586                 bnx2x_cl45_write(bp, phy,
7587                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7588                                  0x26BC);
7589
7590                 /* Change CDR Bandwidth in EDC register */
7591                 bnx2x_cl45_write(bp, phy,
7592                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7593                                  0x0333);
7594         }
7595         bnx2x_cl45_read(bp, phy,
7596                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7597                         &link_status);
7598
7599         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7600         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7601                 link_up = 1;
7602                 vars->line_speed = SPEED_10000;
7603                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7604                            params->port);
7605         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7606                 link_up = 1;
7607                 vars->line_speed = SPEED_2500;
7608                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7609                            params->port);
7610         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7611                 link_up = 1;
7612                 vars->line_speed = SPEED_1000;
7613                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7614                            params->port);
7615         } else {
7616                 link_up = 0;
7617                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7618                            params->port);
7619         }
7620
7621         if (link_up) {
7622                 /* Swap polarity if required */
7623                 if (params->lane_config &
7624                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7625                         /* Configure the 8073 to swap P and N of the KR lines */
7626                         bnx2x_cl45_read(bp, phy,
7627                                         MDIO_XS_DEVAD,
7628                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7629                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7630                          * when it`s in 10G mode.
7631                          */
7632                         if (vars->line_speed == SPEED_1000) {
7633                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7634                                               "the 8073\n");
7635                                 val1 |= (1<<3);
7636                         } else
7637                                 val1 &= ~(1<<3);
7638
7639                         bnx2x_cl45_write(bp, phy,
7640                                          MDIO_XS_DEVAD,
7641                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7642                                          val1);
7643                 }
7644                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7645                 bnx2x_8073_resolve_fc(phy, params, vars);
7646                 vars->duplex = DUPLEX_FULL;
7647         }
7648
7649         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7650                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7651                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7652
7653                 if (val1 & (1<<5))
7654                         vars->link_status |=
7655                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7656                 if (val1 & (1<<7))
7657                         vars->link_status |=
7658                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7659         }
7660
7661         return link_up;
7662 }
7663
7664 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7665                                   struct link_params *params)
7666 {
7667         struct bnx2x *bp = params->bp;
7668         u8 gpio_port;
7669         if (CHIP_IS_E2(bp))
7670                 gpio_port = BP_PATH(bp);
7671         else
7672                 gpio_port = params->port;
7673         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7674            gpio_port);
7675         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7676                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7677                        gpio_port);
7678 }
7679
7680 /******************************************************************/
7681 /*                      BCM8705 PHY SECTION                       */
7682 /******************************************************************/
7683 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7684                                   struct link_params *params,
7685                                   struct link_vars *vars)
7686 {
7687         struct bnx2x *bp = params->bp;
7688         DP(NETIF_MSG_LINK, "init 8705\n");
7689         /* Restore normal power mode*/
7690         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7691                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7692         /* HW reset */
7693         bnx2x_ext_phy_hw_reset(bp, params->port);
7694         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7695         bnx2x_wait_reset_complete(bp, phy, params);
7696
7697         bnx2x_cl45_write(bp, phy,
7698                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7699         bnx2x_cl45_write(bp, phy,
7700                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7701         bnx2x_cl45_write(bp, phy,
7702                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7703         bnx2x_cl45_write(bp, phy,
7704                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7705         /* BCM8705 doesn't have microcode, hence the 0 */
7706         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7707         return 0;
7708 }
7709
7710 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7711                                  struct link_params *params,
7712                                  struct link_vars *vars)
7713 {
7714         u8 link_up = 0;
7715         u16 val1, rx_sd;
7716         struct bnx2x *bp = params->bp;
7717         DP(NETIF_MSG_LINK, "read status 8705\n");
7718         bnx2x_cl45_read(bp, phy,
7719                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7720         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7721
7722         bnx2x_cl45_read(bp, phy,
7723                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7724         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7725
7726         bnx2x_cl45_read(bp, phy,
7727                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7728
7729         bnx2x_cl45_read(bp, phy,
7730                       MDIO_PMA_DEVAD, 0xc809, &val1);
7731         bnx2x_cl45_read(bp, phy,
7732                       MDIO_PMA_DEVAD, 0xc809, &val1);
7733
7734         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7735         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7736         if (link_up) {
7737                 vars->line_speed = SPEED_10000;
7738                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7739         }
7740         return link_up;
7741 }
7742
7743 /******************************************************************/
7744 /*                      SFP+ module Section                       */
7745 /******************************************************************/
7746 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7747                                            struct bnx2x_phy *phy,
7748                                            u8 pmd_dis)
7749 {
7750         struct bnx2x *bp = params->bp;
7751         /* Disable transmitter only for bootcodes which can enable it afterwards
7752          * (for D3 link)
7753          */
7754         if (pmd_dis) {
7755                 if (params->feature_config_flags &
7756                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7757                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7758                 else {
7759                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7760                         return;
7761                 }
7762         } else
7763                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7764         bnx2x_cl45_write(bp, phy,
7765                          MDIO_PMA_DEVAD,
7766                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7767 }
7768
7769 static u8 bnx2x_get_gpio_port(struct link_params *params)
7770 {
7771         u8 gpio_port;
7772         u32 swap_val, swap_override;
7773         struct bnx2x *bp = params->bp;
7774         if (CHIP_IS_E2(bp))
7775                 gpio_port = BP_PATH(bp);
7776         else
7777                 gpio_port = params->port;
7778         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7779         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7780         return gpio_port ^ (swap_val && swap_override);
7781 }
7782
7783 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7784                                            struct bnx2x_phy *phy,
7785                                            u8 tx_en)
7786 {
7787         u16 val;
7788         u8 port = params->port;
7789         struct bnx2x *bp = params->bp;
7790         u32 tx_en_mode;
7791
7792         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7793         tx_en_mode = REG_RD(bp, params->shmem_base +
7794                             offsetof(struct shmem_region,
7795                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7796                 PORT_HW_CFG_TX_LASER_MASK;
7797         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7798                            "mode = %x\n", tx_en, port, tx_en_mode);
7799         switch (tx_en_mode) {
7800         case PORT_HW_CFG_TX_LASER_MDIO:
7801
7802                 bnx2x_cl45_read(bp, phy,
7803                                 MDIO_PMA_DEVAD,
7804                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7805                                 &val);
7806
7807                 if (tx_en)
7808                         val &= ~(1<<15);
7809                 else
7810                         val |= (1<<15);
7811
7812                 bnx2x_cl45_write(bp, phy,
7813                                  MDIO_PMA_DEVAD,
7814                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7815                                  val);
7816         break;
7817         case PORT_HW_CFG_TX_LASER_GPIO0:
7818         case PORT_HW_CFG_TX_LASER_GPIO1:
7819         case PORT_HW_CFG_TX_LASER_GPIO2:
7820         case PORT_HW_CFG_TX_LASER_GPIO3:
7821         {
7822                 u16 gpio_pin;
7823                 u8 gpio_port, gpio_mode;
7824                 if (tx_en)
7825                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7826                 else
7827                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7828
7829                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7830                 gpio_port = bnx2x_get_gpio_port(params);
7831                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7832                 break;
7833         }
7834         default:
7835                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7836                 break;
7837         }
7838 }
7839
7840 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7841                                       struct bnx2x_phy *phy,
7842                                       u8 tx_en)
7843 {
7844         struct bnx2x *bp = params->bp;
7845         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7846         if (CHIP_IS_E3(bp))
7847                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7848         else
7849                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7850 }
7851
7852 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7853                                              struct link_params *params,
7854                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7855                                              u8 *o_buf, u8 is_init)
7856 {
7857         struct bnx2x *bp = params->bp;
7858         u16 val = 0;
7859         u16 i;
7860         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7861                 DP(NETIF_MSG_LINK,
7862                    "Reading from eeprom is limited to 0xf\n");
7863                 return -EINVAL;
7864         }
7865         /* Set the read command byte count */
7866         bnx2x_cl45_write(bp, phy,
7867                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7868                          (byte_cnt | (dev_addr << 8)));
7869
7870         /* Set the read command address */
7871         bnx2x_cl45_write(bp, phy,
7872                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7873                          addr);
7874
7875         /* Activate read command */
7876         bnx2x_cl45_write(bp, phy,
7877                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7878                          0x2c0f);
7879
7880         /* Wait up to 500us for command complete status */
7881         for (i = 0; i < 100; i++) {
7882                 bnx2x_cl45_read(bp, phy,
7883                                 MDIO_PMA_DEVAD,
7884                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7885                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7886                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7887                         break;
7888                 udelay(5);
7889         }
7890
7891         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7892                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7893                 DP(NETIF_MSG_LINK,
7894                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7895                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7896                 return -EINVAL;
7897         }
7898
7899         /* Read the buffer */
7900         for (i = 0; i < byte_cnt; i++) {
7901                 bnx2x_cl45_read(bp, phy,
7902                                 MDIO_PMA_DEVAD,
7903                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7904                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7905         }
7906
7907         for (i = 0; i < 100; i++) {
7908                 bnx2x_cl45_read(bp, phy,
7909                                 MDIO_PMA_DEVAD,
7910                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7911                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7912                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7913                         return 0;
7914                 usleep_range(1000, 2000);
7915         }
7916         return -EINVAL;
7917 }
7918
7919 static void bnx2x_warpcore_power_module(struct link_params *params,
7920                                         u8 power)
7921 {
7922         u32 pin_cfg;
7923         struct bnx2x *bp = params->bp;
7924
7925         pin_cfg = (REG_RD(bp, params->shmem_base +
7926                           offsetof(struct shmem_region,
7927                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7928                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7929                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7930
7931         if (pin_cfg == PIN_CFG_NA)
7932                 return;
7933         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7934                        power, pin_cfg);
7935         /* Low ==> corresponding SFP+ module is powered
7936          * high ==> the SFP+ module is powered down
7937          */
7938         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7939 }
7940 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7941                                                  struct link_params *params,
7942                                                  u8 dev_addr,
7943                                                  u16 addr, u8 byte_cnt,
7944                                                  u8 *o_buf, u8 is_init)
7945 {
7946         int rc = 0;
7947         u8 i, j = 0, cnt = 0;
7948         u32 data_array[4];
7949         u16 addr32;
7950         struct bnx2x *bp = params->bp;
7951
7952         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7953                 DP(NETIF_MSG_LINK,
7954                    "Reading from eeprom is limited to 16 bytes\n");
7955                 return -EINVAL;
7956         }
7957
7958         /* 4 byte aligned address */
7959         addr32 = addr & (~0x3);
7960         do {
7961                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7962                         bnx2x_warpcore_power_module(params, 0);
7963                         /* Note that 100us are not enough here */
7964                         usleep_range(1000, 2000);
7965                         bnx2x_warpcore_power_module(params, 1);
7966                 }
7967                 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt,
7968                                     data_array);
7969         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7970
7971         if (rc == 0) {
7972                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7973                         o_buf[j] = *((u8 *)data_array + i);
7974                         j++;
7975                 }
7976         }
7977
7978         return rc;
7979 }
7980
7981 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7982                                              struct link_params *params,
7983                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7984                                              u8 *o_buf, u8 is_init)
7985 {
7986         struct bnx2x *bp = params->bp;
7987         u16 val, i;
7988
7989         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7990                 DP(NETIF_MSG_LINK,
7991                    "Reading from eeprom is limited to 0xf\n");
7992                 return -EINVAL;
7993         }
7994
7995         /* Set 2-wire transfer rate of SFP+ module EEPROM
7996          * to 100Khz since some DACs(direct attached cables) do
7997          * not work at 400Khz.
7998          */
7999         bnx2x_cl45_write(bp, phy,
8000                          MDIO_PMA_DEVAD,
8001                          MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8002                          ((dev_addr << 8) | 1));
8003
8004         /* Need to read from 1.8000 to clear it */
8005         bnx2x_cl45_read(bp, phy,
8006                         MDIO_PMA_DEVAD,
8007                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8008                         &val);
8009
8010         /* Set the read command byte count */
8011         bnx2x_cl45_write(bp, phy,
8012                          MDIO_PMA_DEVAD,
8013                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8014                          ((byte_cnt < 2) ? 2 : byte_cnt));
8015
8016         /* Set the read command address */
8017         bnx2x_cl45_write(bp, phy,
8018                          MDIO_PMA_DEVAD,
8019                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8020                          addr);
8021         /* Set the destination address */
8022         bnx2x_cl45_write(bp, phy,
8023                          MDIO_PMA_DEVAD,
8024                          0x8004,
8025                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8026
8027         /* Activate read command */
8028         bnx2x_cl45_write(bp, phy,
8029                          MDIO_PMA_DEVAD,
8030                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8031                          0x8002);
8032         /* Wait appropriate time for two-wire command to finish before
8033          * polling the status register
8034          */
8035         usleep_range(1000, 2000);
8036
8037         /* Wait up to 500us for command complete status */
8038         for (i = 0; i < 100; i++) {
8039                 bnx2x_cl45_read(bp, phy,
8040                                 MDIO_PMA_DEVAD,
8041                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8042                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8043                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8044                         break;
8045                 udelay(5);
8046         }
8047
8048         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8049                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8050                 DP(NETIF_MSG_LINK,
8051                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8052                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8053                 return -EFAULT;
8054         }
8055
8056         /* Read the buffer */
8057         for (i = 0; i < byte_cnt; i++) {
8058                 bnx2x_cl45_read(bp, phy,
8059                                 MDIO_PMA_DEVAD,
8060                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8061                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8062         }
8063
8064         for (i = 0; i < 100; i++) {
8065                 bnx2x_cl45_read(bp, phy,
8066                                 MDIO_PMA_DEVAD,
8067                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8068                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8069                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8070                         return 0;
8071                 usleep_range(1000, 2000);
8072         }
8073
8074         return -EINVAL;
8075 }
8076 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8077                                  struct link_params *params, u8 dev_addr,
8078                                  u16 addr, u16 byte_cnt, u8 *o_buf)
8079 {
8080         int rc = 0;
8081         struct bnx2x *bp = params->bp;
8082         u8 xfer_size;
8083         u8 *user_data = o_buf;
8084         read_sfp_module_eeprom_func_p read_func;
8085
8086         if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8087                 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8088                 return -EINVAL;
8089         }
8090
8091         switch (phy->type) {
8092         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8093                 read_func = bnx2x_8726_read_sfp_module_eeprom;
8094                 break;
8095         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8096         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8097                 read_func = bnx2x_8727_read_sfp_module_eeprom;
8098                 break;
8099         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8100                 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8101                 break;
8102         default:
8103                 return -EOPNOTSUPP;
8104         }
8105
8106         while (!rc && (byte_cnt > 0)) {
8107                 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8108                         SFP_EEPROM_PAGE_SIZE : byte_cnt;
8109                 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8110                                user_data, 0);
8111                 byte_cnt -= xfer_size;
8112                 user_data += xfer_size;
8113                 addr += xfer_size;
8114         }
8115         return rc;
8116 }
8117
8118 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8119                               struct link_params *params,
8120                               u16 *edc_mode)
8121 {
8122         struct bnx2x *bp = params->bp;
8123         u32 sync_offset = 0, phy_idx, media_types;
8124         u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0;
8125         *edc_mode = EDC_MODE_LIMITING;
8126         phy->media_type = ETH_PHY_UNSPECIFIED;
8127         /* First check for copper cable */
8128         if (bnx2x_read_sfp_module_eeprom(phy,
8129                                          params,
8130                                          I2C_DEV_ADDR_A0,
8131                                          0,
8132                                          SFP_EEPROM_FC_TX_TECH_ADDR + 1,
8133                                          (u8 *)val) != 0) {
8134                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8135                 return -EINVAL;
8136         }
8137         params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
8138         params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] <<
8139                 LINK_SFP_EEPROM_COMP_CODE_SHIFT;
8140         bnx2x_update_link_attr(params, params->link_attr_sync);
8141         switch (val[SFP_EEPROM_CON_TYPE_ADDR]) {
8142         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8143         {
8144                 u8 copper_module_type;
8145                 phy->media_type = ETH_PHY_DA_TWINAX;
8146                 /* Check if its active cable (includes SFP+ module)
8147                  * of passive cable
8148                  */
8149                 copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR];
8150
8151                 if (copper_module_type &
8152                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8153                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8154                         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8155                                 *edc_mode = EDC_MODE_ACTIVE_DAC;
8156                         else
8157                                 check_limiting_mode = 1;
8158                 } else {
8159                         *edc_mode = EDC_MODE_PASSIVE_DAC;
8160                         /* Even in case PASSIVE_DAC indication is not set,
8161                          * treat it as a passive DAC cable, since some cables
8162                          * don't have this indication.
8163                          */
8164                         if (copper_module_type &
8165                             SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8166                                 DP(NETIF_MSG_LINK,
8167                                    "Passive Copper cable detected\n");
8168                         } else {
8169                                 DP(NETIF_MSG_LINK,
8170                                    "Unknown copper-cable-type\n");
8171                         }
8172                 }
8173                 break;
8174         }
8175         case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
8176         case SFP_EEPROM_CON_TYPE_VAL_LC:
8177         case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8178                 check_limiting_mode = 1;
8179                 if (((val[SFP_EEPROM_10G_COMP_CODE_ADDR] &
8180                      (SFP_EEPROM_10G_COMP_CODE_SR_MASK |
8181                       SFP_EEPROM_10G_COMP_CODE_LR_MASK |
8182                        SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&
8183                     (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
8184                         DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8185                         phy->media_type = ETH_PHY_SFP_1G_FIBER;
8186                         if (phy->req_line_speed != SPEED_1000) {
8187                                 u8 gport = params->port;
8188                                 phy->req_line_speed = SPEED_1000;
8189                                 if (!CHIP_IS_E1x(bp)) {
8190                                         gport = BP_PATH(bp) +
8191                                         (params->port << 1);
8192                                 }
8193                                 netdev_err(bp->dev,
8194                                            "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8195                                            gport);
8196                         }
8197                         if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] &
8198                             SFP_EEPROM_1G_COMP_CODE_BASE_T) {
8199                                 bnx2x_sfp_set_transmitter(params, phy, 0);
8200                                 msleep(40);
8201                                 bnx2x_sfp_set_transmitter(params, phy, 1);
8202                         }
8203                 } else {
8204                         int idx, cfg_idx = 0;
8205                         DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8206                         for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8207                                 if (params->phy[idx].type == phy->type) {
8208                                         cfg_idx = LINK_CONFIG_IDX(idx);
8209                                         break;
8210                                 }
8211                         }
8212                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8213                         phy->req_line_speed = params->req_line_speed[cfg_idx];
8214                 }
8215                 break;
8216         default:
8217                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8218                          val[SFP_EEPROM_CON_TYPE_ADDR]);
8219                 return -EINVAL;
8220         }
8221         sync_offset = params->shmem_base +
8222                 offsetof(struct shmem_region,
8223                          dev_info.port_hw_config[params->port].media_type);
8224         media_types = REG_RD(bp, sync_offset);
8225         /* Update media type for non-PMF sync */
8226         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8227                 if (&(params->phy[phy_idx]) == phy) {
8228                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8229                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8230                         media_types |= ((phy->media_type &
8231                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8232                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8233                         break;
8234                 }
8235         }
8236         REG_WR(bp, sync_offset, media_types);
8237         if (check_limiting_mode) {
8238                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8239                 if (bnx2x_read_sfp_module_eeprom(phy,
8240                                                  params,
8241                                                  I2C_DEV_ADDR_A0,
8242                                                  SFP_EEPROM_OPTIONS_ADDR,
8243                                                  SFP_EEPROM_OPTIONS_SIZE,
8244                                                  options) != 0) {
8245                         DP(NETIF_MSG_LINK,
8246                            "Failed to read Option field from module EEPROM\n");
8247                         return -EINVAL;
8248                 }
8249                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8250                         *edc_mode = EDC_MODE_LINEAR;
8251                 else
8252                         *edc_mode = EDC_MODE_LIMITING;
8253         }
8254         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8255         return 0;
8256 }
8257 /* This function read the relevant field from the module (SFP+), and verify it
8258  * is compliant with this board
8259  */
8260 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8261                                    struct link_params *params)
8262 {
8263         struct bnx2x *bp = params->bp;
8264         u32 val, cmd;
8265         u32 fw_resp, fw_cmd_param;
8266         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8267         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8268         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8269         val = REG_RD(bp, params->shmem_base +
8270                          offsetof(struct shmem_region, dev_info.
8271                                   port_feature_config[params->port].config));
8272         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8273             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8274                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8275                 return 0;
8276         }
8277
8278         if (params->feature_config_flags &
8279             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8280                 /* Use specific phy request */
8281                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8282         } else if (params->feature_config_flags &
8283                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8284                 /* Use first phy request only in case of non-dual media*/
8285                 if (DUAL_MEDIA(params)) {
8286                         DP(NETIF_MSG_LINK,
8287                            "FW does not support OPT MDL verification\n");
8288                         return -EINVAL;
8289                 }
8290                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8291         } else {
8292                 /* No support in OPT MDL detection */
8293                 DP(NETIF_MSG_LINK,
8294                    "FW does not support OPT MDL verification\n");
8295                 return -EINVAL;
8296         }
8297
8298         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8299         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8300         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8301                 DP(NETIF_MSG_LINK, "Approved module\n");
8302                 return 0;
8303         }
8304
8305         /* Format the warning message */
8306         if (bnx2x_read_sfp_module_eeprom(phy,
8307                                          params,
8308                                          I2C_DEV_ADDR_A0,
8309                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8310                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8311                                          (u8 *)vendor_name))
8312                 vendor_name[0] = '\0';
8313         else
8314                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8315         if (bnx2x_read_sfp_module_eeprom(phy,
8316                                          params,
8317                                          I2C_DEV_ADDR_A0,
8318                                          SFP_EEPROM_PART_NO_ADDR,
8319                                          SFP_EEPROM_PART_NO_SIZE,
8320                                          (u8 *)vendor_pn))
8321                 vendor_pn[0] = '\0';
8322         else
8323                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8324
8325         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8326                               " Port %d from %s part number %s\n",
8327                          params->port, vendor_name, vendor_pn);
8328         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8329             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8330                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8331         return -EINVAL;
8332 }
8333
8334 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8335                                                  struct link_params *params)
8336
8337 {
8338         u8 val;
8339         int rc;
8340         struct bnx2x *bp = params->bp;
8341         u16 timeout;
8342         /* Initialization time after hot-plug may take up to 300ms for
8343          * some phys type ( e.g. JDSU )
8344          */
8345
8346         for (timeout = 0; timeout < 60; timeout++) {
8347                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8348                         rc = bnx2x_warpcore_read_sfp_module_eeprom(
8349                                 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8350                                 1);
8351                 else
8352                         rc = bnx2x_read_sfp_module_eeprom(phy, params,
8353                                                           I2C_DEV_ADDR_A0,
8354                                                           1, 1, &val);
8355                 if (rc == 0) {
8356                         DP(NETIF_MSG_LINK,
8357                            "SFP+ module initialization took %d ms\n",
8358                            timeout * 5);
8359                         return 0;
8360                 }
8361                 usleep_range(5000, 10000);
8362         }
8363         rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8364                                           1, 1, &val);
8365         return rc;
8366 }
8367
8368 static void bnx2x_8727_power_module(struct bnx2x *bp,
8369                                     struct bnx2x_phy *phy,
8370                                     u8 is_power_up) {
8371         /* Make sure GPIOs are not using for LED mode */
8372         u16 val;
8373         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8374          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8375          * output
8376          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8377          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8378          * where the 1st bit is the over-current(only input), and 2nd bit is
8379          * for power( only output )
8380          *
8381          * In case of NOC feature is disabled and power is up, set GPIO control
8382          *  as input to enable listening of over-current indication
8383          */
8384         if (phy->flags & FLAGS_NOC)
8385                 return;
8386         if (is_power_up)
8387                 val = (1<<4);
8388         else
8389                 /* Set GPIO control to OUTPUT, and set the power bit
8390                  * to according to the is_power_up
8391                  */
8392                 val = (1<<1);
8393
8394         bnx2x_cl45_write(bp, phy,
8395                          MDIO_PMA_DEVAD,
8396                          MDIO_PMA_REG_8727_GPIO_CTRL,
8397                          val);
8398 }
8399
8400 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8401                                         struct bnx2x_phy *phy,
8402                                         u16 edc_mode)
8403 {
8404         u16 cur_limiting_mode;
8405
8406         bnx2x_cl45_read(bp, phy,
8407                         MDIO_PMA_DEVAD,
8408                         MDIO_PMA_REG_ROM_VER2,
8409                         &cur_limiting_mode);
8410         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8411                  cur_limiting_mode);
8412
8413         if (edc_mode == EDC_MODE_LIMITING) {
8414                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8415                 bnx2x_cl45_write(bp, phy,
8416                                  MDIO_PMA_DEVAD,
8417                                  MDIO_PMA_REG_ROM_VER2,
8418                                  EDC_MODE_LIMITING);
8419         } else { /* LRM mode ( default )*/
8420
8421                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8422
8423                 /* Changing to LRM mode takes quite few seconds. So do it only
8424                  * if current mode is limiting (default is LRM)
8425                  */
8426                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8427                         return 0;
8428
8429                 bnx2x_cl45_write(bp, phy,
8430                                  MDIO_PMA_DEVAD,
8431                                  MDIO_PMA_REG_LRM_MODE,
8432                                  0);
8433                 bnx2x_cl45_write(bp, phy,
8434                                  MDIO_PMA_DEVAD,
8435                                  MDIO_PMA_REG_ROM_VER2,
8436                                  0x128);
8437                 bnx2x_cl45_write(bp, phy,
8438                                  MDIO_PMA_DEVAD,
8439                                  MDIO_PMA_REG_MISC_CTRL0,
8440                                  0x4008);
8441                 bnx2x_cl45_write(bp, phy,
8442                                  MDIO_PMA_DEVAD,
8443                                  MDIO_PMA_REG_LRM_MODE,
8444                                  0xaaaa);
8445         }
8446         return 0;
8447 }
8448
8449 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8450                                         struct bnx2x_phy *phy,
8451                                         u16 edc_mode)
8452 {
8453         u16 phy_identifier;
8454         u16 rom_ver2_val;
8455         bnx2x_cl45_read(bp, phy,
8456                         MDIO_PMA_DEVAD,
8457                         MDIO_PMA_REG_PHY_IDENTIFIER,
8458                         &phy_identifier);
8459
8460         bnx2x_cl45_write(bp, phy,
8461                          MDIO_PMA_DEVAD,
8462                          MDIO_PMA_REG_PHY_IDENTIFIER,
8463                          (phy_identifier & ~(1<<9)));
8464
8465         bnx2x_cl45_read(bp, phy,
8466                         MDIO_PMA_DEVAD,
8467                         MDIO_PMA_REG_ROM_VER2,
8468                         &rom_ver2_val);
8469         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8470         bnx2x_cl45_write(bp, phy,
8471                          MDIO_PMA_DEVAD,
8472                          MDIO_PMA_REG_ROM_VER2,
8473                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8474
8475         bnx2x_cl45_write(bp, phy,
8476                          MDIO_PMA_DEVAD,
8477                          MDIO_PMA_REG_PHY_IDENTIFIER,
8478                          (phy_identifier | (1<<9)));
8479
8480         return 0;
8481 }
8482
8483 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8484                                      struct link_params *params,
8485                                      u32 action)
8486 {
8487         struct bnx2x *bp = params->bp;
8488         u16 val;
8489         switch (action) {
8490         case DISABLE_TX:
8491                 bnx2x_sfp_set_transmitter(params, phy, 0);
8492                 break;
8493         case ENABLE_TX:
8494                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8495                         bnx2x_sfp_set_transmitter(params, phy, 1);
8496                 break;
8497         case PHY_INIT:
8498                 bnx2x_cl45_write(bp, phy,
8499                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8500                                  (1<<2) | (1<<5));
8501                 bnx2x_cl45_write(bp, phy,
8502                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8503                                  0);
8504                 bnx2x_cl45_write(bp, phy,
8505                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8506                 /* Make MOD_ABS give interrupt on change */
8507                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8508                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8509                                 &val);
8510                 val |= (1<<12);
8511                 if (phy->flags & FLAGS_NOC)
8512                         val |= (3<<5);
8513                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8514                  * status which reflect SFP+ module over-current
8515                  */
8516                 if (!(phy->flags & FLAGS_NOC))
8517                         val &= 0xff8f; /* Reset bits 4-6 */
8518                 bnx2x_cl45_write(bp, phy,
8519                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8520                                  val);
8521                 break;
8522         default:
8523                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8524                    action);
8525                 return;
8526         }
8527 }
8528
8529 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8530                                            u8 gpio_mode)
8531 {
8532         struct bnx2x *bp = params->bp;
8533
8534         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8535                             offsetof(struct shmem_region,
8536                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8537                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8538         switch (fault_led_gpio) {
8539         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8540                 return;
8541         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8542         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8543         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8544         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8545         {
8546                 u8 gpio_port = bnx2x_get_gpio_port(params);
8547                 u16 gpio_pin = fault_led_gpio -
8548                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8549                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8550                                    "pin %x port %x mode %x\n",
8551                                gpio_pin, gpio_port, gpio_mode);
8552                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8553         }
8554         break;
8555         default:
8556                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8557                                fault_led_gpio);
8558         }
8559 }
8560
8561 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8562                                           u8 gpio_mode)
8563 {
8564         u32 pin_cfg;
8565         u8 port = params->port;
8566         struct bnx2x *bp = params->bp;
8567         pin_cfg = (REG_RD(bp, params->shmem_base +
8568                          offsetof(struct shmem_region,
8569                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8570                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8571                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8572         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8573                        gpio_mode, pin_cfg);
8574         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8575 }
8576
8577 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8578                                            u8 gpio_mode)
8579 {
8580         struct bnx2x *bp = params->bp;
8581         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8582         if (CHIP_IS_E3(bp)) {
8583                 /* Low ==> if SFP+ module is supported otherwise
8584                  * High ==> if SFP+ module is not on the approved vendor list
8585                  */
8586                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8587         } else
8588                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8589 }
8590
8591 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8592                                     struct link_params *params)
8593 {
8594         struct bnx2x *bp = params->bp;
8595         bnx2x_warpcore_power_module(params, 0);
8596         /* Put Warpcore in low power mode */
8597         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8598
8599         /* Put LCPLL in low power mode */
8600         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8601         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8602         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8603 }
8604
8605 static void bnx2x_power_sfp_module(struct link_params *params,
8606                                    struct bnx2x_phy *phy,
8607                                    u8 power)
8608 {
8609         struct bnx2x *bp = params->bp;
8610         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8611
8612         switch (phy->type) {
8613         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8614         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8615                 bnx2x_8727_power_module(params->bp, phy, power);
8616                 break;
8617         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8618                 bnx2x_warpcore_power_module(params, power);
8619                 break;
8620         default:
8621                 break;
8622         }
8623 }
8624 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8625                                              struct bnx2x_phy *phy,
8626                                              u16 edc_mode)
8627 {
8628         u16 val = 0;
8629         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8630         struct bnx2x *bp = params->bp;
8631
8632         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8633         /* This is a global register which controls all lanes */
8634         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8635                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8636         val &= ~(0xf << (lane << 2));
8637
8638         switch (edc_mode) {
8639         case EDC_MODE_LINEAR:
8640         case EDC_MODE_LIMITING:
8641                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8642                 break;
8643         case EDC_MODE_PASSIVE_DAC:
8644         case EDC_MODE_ACTIVE_DAC:
8645                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8646                 break;
8647         default:
8648                 break;
8649         }
8650
8651         val |= (mode << (lane << 2));
8652         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8653                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8654         /* A must read */
8655         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8656                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8657
8658         /* Restart microcode to re-read the new mode */
8659         bnx2x_warpcore_reset_lane(bp, phy, 1);
8660         bnx2x_warpcore_reset_lane(bp, phy, 0);
8661
8662 }
8663
8664 static void bnx2x_set_limiting_mode(struct link_params *params,
8665                                     struct bnx2x_phy *phy,
8666                                     u16 edc_mode)
8667 {
8668         switch (phy->type) {
8669         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8670                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8671                 break;
8672         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8673         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8674                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8675                 break;
8676         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8677                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8678                 break;
8679         }
8680 }
8681
8682 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8683                                       struct link_params *params)
8684 {
8685         struct bnx2x *bp = params->bp;
8686         u16 edc_mode;
8687         int rc = 0;
8688
8689         u32 val = REG_RD(bp, params->shmem_base +
8690                              offsetof(struct shmem_region, dev_info.
8691                                      port_feature_config[params->port].config));
8692         /* Enabled transmitter by default */
8693         bnx2x_sfp_set_transmitter(params, phy, 1);
8694         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8695                  params->port);
8696         /* Power up module */
8697         bnx2x_power_sfp_module(params, phy, 1);
8698         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8699                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8700                 return -EINVAL;
8701         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8702                 /* Check SFP+ module compatibility */
8703                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8704                 rc = -EINVAL;
8705                 /* Turn on fault module-detected led */
8706                 bnx2x_set_sfp_module_fault_led(params,
8707                                                MISC_REGISTERS_GPIO_HIGH);
8708
8709                 /* Check if need to power down the SFP+ module */
8710                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8711                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8712                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8713                         bnx2x_power_sfp_module(params, phy, 0);
8714                         return rc;
8715                 }
8716         } else {
8717                 /* Turn off fault module-detected led */
8718                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8719         }
8720
8721         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8722          * is done automatically
8723          */
8724         bnx2x_set_limiting_mode(params, phy, edc_mode);
8725
8726         /* Disable transmit for this module if the module is not approved, and
8727          * laser needs to be disabled.
8728          */
8729         if ((rc) &&
8730             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8731              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8732                 bnx2x_sfp_set_transmitter(params, phy, 0);
8733
8734         return rc;
8735 }
8736
8737 void bnx2x_handle_module_detect_int(struct link_params *params)
8738 {
8739         struct bnx2x *bp = params->bp;
8740         struct bnx2x_phy *phy;
8741         u32 gpio_val;
8742         u8 gpio_num, gpio_port;
8743         if (CHIP_IS_E3(bp)) {
8744                 phy = &params->phy[INT_PHY];
8745                 /* Always enable TX laser,will be disabled in case of fault */
8746                 bnx2x_sfp_set_transmitter(params, phy, 1);
8747         } else {
8748                 phy = &params->phy[EXT_PHY1];
8749         }
8750         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8751                                       params->port, &gpio_num, &gpio_port) ==
8752             -EINVAL) {
8753                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8754                 return;
8755         }
8756
8757         /* Set valid module led off */
8758         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8759
8760         /* Get current gpio val reflecting module plugged in / out*/
8761         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8762
8763         /* Call the handling function in case module is detected */
8764         if (gpio_val == 0) {
8765                 bnx2x_set_mdio_emac_per_phy(bp, params);
8766                 bnx2x_set_aer_mmd(params, phy);
8767
8768                 bnx2x_power_sfp_module(params, phy, 1);
8769                 bnx2x_set_gpio_int(bp, gpio_num,
8770                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8771                                    gpio_port);
8772                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8773                         bnx2x_sfp_module_detection(phy, params);
8774                         if (CHIP_IS_E3(bp)) {
8775                                 u16 rx_tx_in_reset;
8776                                 /* In case WC is out of reset, reconfigure the
8777                                  * link speed while taking into account 1G
8778                                  * module limitation.
8779                                  */
8780                                 bnx2x_cl45_read(bp, phy,
8781                                                 MDIO_WC_DEVAD,
8782                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8783                                                 &rx_tx_in_reset);
8784                                 if ((!rx_tx_in_reset) &&
8785                                     (params->link_flags &
8786                                      PHY_INITIALIZED)) {
8787                                         bnx2x_warpcore_reset_lane(bp, phy, 1);
8788                                         bnx2x_warpcore_config_sfi(phy, params);
8789                                         bnx2x_warpcore_reset_lane(bp, phy, 0);
8790                                 }
8791                         }
8792                 } else {
8793                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8794                 }
8795         } else {
8796                 bnx2x_set_gpio_int(bp, gpio_num,
8797                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8798                                    gpio_port);
8799                 /* Module was plugged out.
8800                  * Disable transmit for this module
8801                  */
8802                 phy->media_type = ETH_PHY_NOT_PRESENT;
8803         }
8804 }
8805
8806 /******************************************************************/
8807 /*              Used by 8706 and 8727                             */
8808 /******************************************************************/
8809 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8810                                  struct bnx2x_phy *phy,
8811                                  u16 alarm_status_offset,
8812                                  u16 alarm_ctrl_offset)
8813 {
8814         u16 alarm_status, val;
8815         bnx2x_cl45_read(bp, phy,
8816                         MDIO_PMA_DEVAD, alarm_status_offset,
8817                         &alarm_status);
8818         bnx2x_cl45_read(bp, phy,
8819                         MDIO_PMA_DEVAD, alarm_status_offset,
8820                         &alarm_status);
8821         /* Mask or enable the fault event. */
8822         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8823         if (alarm_status & (1<<0))
8824                 val &= ~(1<<0);
8825         else
8826                 val |= (1<<0);
8827         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8828 }
8829 /******************************************************************/
8830 /*              common BCM8706/BCM8726 PHY SECTION                */
8831 /******************************************************************/
8832 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8833                                       struct link_params *params,
8834                                       struct link_vars *vars)
8835 {
8836         u8 link_up = 0;
8837         u16 val1, val2, rx_sd, pcs_status;
8838         struct bnx2x *bp = params->bp;
8839         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8840         /* Clear RX Alarm*/
8841         bnx2x_cl45_read(bp, phy,
8842                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8843
8844         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8845                              MDIO_PMA_LASI_TXCTRL);
8846
8847         /* Clear LASI indication*/
8848         bnx2x_cl45_read(bp, phy,
8849                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8850         bnx2x_cl45_read(bp, phy,
8851                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8852         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8853
8854         bnx2x_cl45_read(bp, phy,
8855                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8856         bnx2x_cl45_read(bp, phy,
8857                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8858         bnx2x_cl45_read(bp, phy,
8859                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8860         bnx2x_cl45_read(bp, phy,
8861                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8862
8863         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8864                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8865         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8866          * are set, or if the autoneg bit 1 is set
8867          */
8868         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8869         if (link_up) {
8870                 if (val2 & (1<<1))
8871                         vars->line_speed = SPEED_1000;
8872                 else
8873                         vars->line_speed = SPEED_10000;
8874                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8875                 vars->duplex = DUPLEX_FULL;
8876         }
8877
8878         /* Capture 10G link fault. Read twice to clear stale value. */
8879         if (vars->line_speed == SPEED_10000) {
8880                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8881                             MDIO_PMA_LASI_TXSTAT, &val1);
8882                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8883                             MDIO_PMA_LASI_TXSTAT, &val1);
8884                 if (val1 & (1<<0))
8885                         vars->fault_detected = 1;
8886         }
8887
8888         return link_up;
8889 }
8890
8891 /******************************************************************/
8892 /*                      BCM8706 PHY SECTION                       */
8893 /******************************************************************/
8894 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8895                                  struct link_params *params,
8896                                  struct link_vars *vars)
8897 {
8898         u32 tx_en_mode;
8899         u16 cnt, val, tmp1;
8900         struct bnx2x *bp = params->bp;
8901
8902         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8903                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8904         /* HW reset */
8905         bnx2x_ext_phy_hw_reset(bp, params->port);
8906         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8907         bnx2x_wait_reset_complete(bp, phy, params);
8908
8909         /* Wait until fw is loaded */
8910         for (cnt = 0; cnt < 100; cnt++) {
8911                 bnx2x_cl45_read(bp, phy,
8912                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8913                 if (val)
8914                         break;
8915                 usleep_range(10000, 20000);
8916         }
8917         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8918         if ((params->feature_config_flags &
8919              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8920                 u8 i;
8921                 u16 reg;
8922                 for (i = 0; i < 4; i++) {
8923                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8924                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8925                                    MDIO_XS_8706_REG_BANK_RX0);
8926                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8927                         /* Clear first 3 bits of the control */
8928                         val &= ~0x7;
8929                         /* Set control bits according to configuration */
8930                         val |= (phy->rx_preemphasis[i] & 0x7);
8931                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8932                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8933                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8934                 }
8935         }
8936         /* Force speed */
8937         if (phy->req_line_speed == SPEED_10000) {
8938                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8939
8940                 bnx2x_cl45_write(bp, phy,
8941                                  MDIO_PMA_DEVAD,
8942                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8943                 bnx2x_cl45_write(bp, phy,
8944                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8945                                  0);
8946                 /* Arm LASI for link and Tx fault. */
8947                 bnx2x_cl45_write(bp, phy,
8948                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8949         } else {
8950                 /* Force 1Gbps using autoneg with 1G advertisement */
8951
8952                 /* Allow CL37 through CL73 */
8953                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8954                 bnx2x_cl45_write(bp, phy,
8955                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8956
8957                 /* Enable Full-Duplex advertisement on CL37 */
8958                 bnx2x_cl45_write(bp, phy,
8959                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8960                 /* Enable CL37 AN */
8961                 bnx2x_cl45_write(bp, phy,
8962                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8963                 /* 1G support */
8964                 bnx2x_cl45_write(bp, phy,
8965                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8966
8967                 /* Enable clause 73 AN */
8968                 bnx2x_cl45_write(bp, phy,
8969                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8970                 bnx2x_cl45_write(bp, phy,
8971                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8972                                  0x0400);
8973                 bnx2x_cl45_write(bp, phy,
8974                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8975                                  0x0004);
8976         }
8977         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8978
8979         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8980          * power mode, if TX Laser is disabled
8981          */
8982
8983         tx_en_mode = REG_RD(bp, params->shmem_base +
8984                             offsetof(struct shmem_region,
8985                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8986                         & PORT_HW_CFG_TX_LASER_MASK;
8987
8988         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8989                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8990                 bnx2x_cl45_read(bp, phy,
8991                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8992                 tmp1 |= 0x1;
8993                 bnx2x_cl45_write(bp, phy,
8994                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8995         }
8996
8997         return 0;
8998 }
8999
9000 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
9001                                   struct link_params *params,
9002                                   struct link_vars *vars)
9003 {
9004         return bnx2x_8706_8726_read_status(phy, params, vars);
9005 }
9006
9007 /******************************************************************/
9008 /*                      BCM8726 PHY SECTION                       */
9009 /******************************************************************/
9010 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
9011                                        struct link_params *params)
9012 {
9013         struct bnx2x *bp = params->bp;
9014         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
9015         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9016 }
9017
9018 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
9019                                          struct link_params *params)
9020 {
9021         struct bnx2x *bp = params->bp;
9022         /* Need to wait 100ms after reset */
9023         msleep(100);
9024
9025         /* Micro controller re-boot */
9026         bnx2x_cl45_write(bp, phy,
9027                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
9028
9029         /* Set soft reset */
9030         bnx2x_cl45_write(bp, phy,
9031                          MDIO_PMA_DEVAD,
9032                          MDIO_PMA_REG_GEN_CTRL,
9033                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9034
9035         bnx2x_cl45_write(bp, phy,
9036                          MDIO_PMA_DEVAD,
9037                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9038
9039         bnx2x_cl45_write(bp, phy,
9040                          MDIO_PMA_DEVAD,
9041                          MDIO_PMA_REG_GEN_CTRL,
9042                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9043
9044         /* Wait for 150ms for microcode load */
9045         msleep(150);
9046
9047         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9048         bnx2x_cl45_write(bp, phy,
9049                          MDIO_PMA_DEVAD,
9050                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9051
9052         msleep(200);
9053         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9054 }
9055
9056 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
9057                                  struct link_params *params,
9058                                  struct link_vars *vars)
9059 {
9060         struct bnx2x *bp = params->bp;
9061         u16 val1;
9062         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
9063         if (link_up) {
9064                 bnx2x_cl45_read(bp, phy,
9065                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9066                                 &val1);
9067                 if (val1 & (1<<15)) {
9068                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
9069                         link_up = 0;
9070                         vars->line_speed = 0;
9071                 }
9072         }
9073         return link_up;
9074 }
9075
9076
9077 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
9078                                   struct link_params *params,
9079                                   struct link_vars *vars)
9080 {
9081         struct bnx2x *bp = params->bp;
9082         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
9083
9084         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9085         bnx2x_wait_reset_complete(bp, phy, params);
9086
9087         bnx2x_8726_external_rom_boot(phy, params);
9088
9089         /* Need to call module detected on initialization since the module
9090          * detection triggered by actual module insertion might occur before
9091          * driver is loaded, and when driver is loaded, it reset all
9092          * registers, including the transmitter
9093          */
9094         bnx2x_sfp_module_detection(phy, params);
9095
9096         if (phy->req_line_speed == SPEED_1000) {
9097                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9098                 bnx2x_cl45_write(bp, phy,
9099                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9100                 bnx2x_cl45_write(bp, phy,
9101                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9102                 bnx2x_cl45_write(bp, phy,
9103                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9104                 bnx2x_cl45_write(bp, phy,
9105                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9106                                  0x400);
9107         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9108                    (phy->speed_cap_mask &
9109                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9110                    ((phy->speed_cap_mask &
9111                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9112                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9113                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9114                 /* Set Flow control */
9115                 bnx2x_ext_phy_set_pause(params, phy, vars);
9116                 bnx2x_cl45_write(bp, phy,
9117                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9118                 bnx2x_cl45_write(bp, phy,
9119                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9120                 bnx2x_cl45_write(bp, phy,
9121                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9122                 bnx2x_cl45_write(bp, phy,
9123                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9124                 bnx2x_cl45_write(bp, phy,
9125                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9126                 /* Enable RX-ALARM control to receive interrupt for 1G speed
9127                  * change
9128                  */
9129                 bnx2x_cl45_write(bp, phy,
9130                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9131                 bnx2x_cl45_write(bp, phy,
9132                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9133                                  0x400);
9134
9135         } else { /* Default 10G. Set only LASI control */
9136                 bnx2x_cl45_write(bp, phy,
9137                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9138         }
9139
9140         /* Set TX PreEmphasis if needed */
9141         if ((params->feature_config_flags &
9142              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9143                 DP(NETIF_MSG_LINK,
9144                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9145                          phy->tx_preemphasis[0],
9146                          phy->tx_preemphasis[1]);
9147                 bnx2x_cl45_write(bp, phy,
9148                                  MDIO_PMA_DEVAD,
9149                                  MDIO_PMA_REG_8726_TX_CTRL1,
9150                                  phy->tx_preemphasis[0]);
9151
9152                 bnx2x_cl45_write(bp, phy,
9153                                  MDIO_PMA_DEVAD,
9154                                  MDIO_PMA_REG_8726_TX_CTRL2,
9155                                  phy->tx_preemphasis[1]);
9156         }
9157
9158         return 0;
9159
9160 }
9161
9162 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9163                                   struct link_params *params)
9164 {
9165         struct bnx2x *bp = params->bp;
9166         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9167         /* Set serial boot control for external load */
9168         bnx2x_cl45_write(bp, phy,
9169                          MDIO_PMA_DEVAD,
9170                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
9171 }
9172
9173 /******************************************************************/
9174 /*                      BCM8727 PHY SECTION                       */
9175 /******************************************************************/
9176
9177 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9178                                     struct link_params *params, u8 mode)
9179 {
9180         struct bnx2x *bp = params->bp;
9181         u16 led_mode_bitmask = 0;
9182         u16 gpio_pins_bitmask = 0;
9183         u16 val;
9184         /* Only NOC flavor requires to set the LED specifically */
9185         if (!(phy->flags & FLAGS_NOC))
9186                 return;
9187         switch (mode) {
9188         case LED_MODE_FRONT_PANEL_OFF:
9189         case LED_MODE_OFF:
9190                 led_mode_bitmask = 0;
9191                 gpio_pins_bitmask = 0x03;
9192                 break;
9193         case LED_MODE_ON:
9194                 led_mode_bitmask = 0;
9195                 gpio_pins_bitmask = 0x02;
9196                 break;
9197         case LED_MODE_OPER:
9198                 led_mode_bitmask = 0x60;
9199                 gpio_pins_bitmask = 0x11;
9200                 break;
9201         }
9202         bnx2x_cl45_read(bp, phy,
9203                         MDIO_PMA_DEVAD,
9204                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9205                         &val);
9206         val &= 0xff8f;
9207         val |= led_mode_bitmask;
9208         bnx2x_cl45_write(bp, phy,
9209                          MDIO_PMA_DEVAD,
9210                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9211                          val);
9212         bnx2x_cl45_read(bp, phy,
9213                         MDIO_PMA_DEVAD,
9214                         MDIO_PMA_REG_8727_GPIO_CTRL,
9215                         &val);
9216         val &= 0xffe0;
9217         val |= gpio_pins_bitmask;
9218         bnx2x_cl45_write(bp, phy,
9219                          MDIO_PMA_DEVAD,
9220                          MDIO_PMA_REG_8727_GPIO_CTRL,
9221                          val);
9222 }
9223 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9224                                 struct link_params *params) {
9225         u32 swap_val, swap_override;
9226         u8 port;
9227         /* The PHY reset is controlled by GPIO 1. Fake the port number
9228          * to cancel the swap done in set_gpio()
9229          */
9230         struct bnx2x *bp = params->bp;
9231         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9232         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9233         port = (swap_val && swap_override) ^ 1;
9234         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9235                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9236 }
9237
9238 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9239                                     struct link_params *params)
9240 {
9241         struct bnx2x *bp = params->bp;
9242         u16 tmp1, val;
9243         /* Set option 1G speed */
9244         if ((phy->req_line_speed == SPEED_1000) ||
9245             (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9246                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9247                 bnx2x_cl45_write(bp, phy,
9248                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9249                 bnx2x_cl45_write(bp, phy,
9250                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9251                 bnx2x_cl45_read(bp, phy,
9252                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9253                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9254                 /* Power down the XAUI until link is up in case of dual-media
9255                  * and 1G
9256                  */
9257                 if (DUAL_MEDIA(params)) {
9258                         bnx2x_cl45_read(bp, phy,
9259                                         MDIO_PMA_DEVAD,
9260                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9261                         val |= (3<<10);
9262                         bnx2x_cl45_write(bp, phy,
9263                                          MDIO_PMA_DEVAD,
9264                                          MDIO_PMA_REG_8727_PCS_GP, val);
9265                 }
9266         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9267                    ((phy->speed_cap_mask &
9268                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9269                    ((phy->speed_cap_mask &
9270                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9271                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9272
9273                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9274                 bnx2x_cl45_write(bp, phy,
9275                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9276                 bnx2x_cl45_write(bp, phy,
9277                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9278         } else {
9279                 /* Since the 8727 has only single reset pin, need to set the 10G
9280                  * registers although it is default
9281                  */
9282                 bnx2x_cl45_write(bp, phy,
9283                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9284                                  0x0020);
9285                 bnx2x_cl45_write(bp, phy,
9286                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9287                 bnx2x_cl45_write(bp, phy,
9288                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9289                 bnx2x_cl45_write(bp, phy,
9290                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9291                                  0x0008);
9292         }
9293 }
9294
9295 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9296                                   struct link_params *params,
9297                                   struct link_vars *vars)
9298 {
9299         u32 tx_en_mode;
9300         u16 tmp1, mod_abs, tmp2;
9301         struct bnx2x *bp = params->bp;
9302         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9303
9304         bnx2x_wait_reset_complete(bp, phy, params);
9305
9306         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9307
9308         bnx2x_8727_specific_func(phy, params, PHY_INIT);
9309         /* Initially configure MOD_ABS to interrupt when module is
9310          * presence( bit 8)
9311          */
9312         bnx2x_cl45_read(bp, phy,
9313                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9314         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9315          * When the EDC is off it locks onto a reference clock and avoids
9316          * becoming 'lost'
9317          */
9318         mod_abs &= ~(1<<8);
9319         if (!(phy->flags & FLAGS_NOC))
9320                 mod_abs &= ~(1<<9);
9321         bnx2x_cl45_write(bp, phy,
9322                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9323
9324         /* Enable/Disable PHY transmitter output */
9325         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9326
9327         bnx2x_8727_power_module(bp, phy, 1);
9328
9329         bnx2x_cl45_read(bp, phy,
9330                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9331
9332         bnx2x_cl45_read(bp, phy,
9333                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9334
9335         bnx2x_8727_config_speed(phy, params);
9336
9337
9338         /* Set TX PreEmphasis if needed */
9339         if ((params->feature_config_flags &
9340              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9341                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9342                            phy->tx_preemphasis[0],
9343                            phy->tx_preemphasis[1]);
9344                 bnx2x_cl45_write(bp, phy,
9345                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9346                                  phy->tx_preemphasis[0]);
9347
9348                 bnx2x_cl45_write(bp, phy,
9349                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9350                                  phy->tx_preemphasis[1]);
9351         }
9352
9353         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9354          * power mode, if TX Laser is disabled
9355          */
9356         tx_en_mode = REG_RD(bp, params->shmem_base +
9357                             offsetof(struct shmem_region,
9358                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9359                         & PORT_HW_CFG_TX_LASER_MASK;
9360
9361         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9362
9363                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9364                 bnx2x_cl45_read(bp, phy,
9365                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9366                 tmp2 |= 0x1000;
9367                 tmp2 &= 0xFFEF;
9368                 bnx2x_cl45_write(bp, phy,
9369                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9370                 bnx2x_cl45_read(bp, phy,
9371                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9372                                 &tmp2);
9373                 bnx2x_cl45_write(bp, phy,
9374                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9375                                  (tmp2 & 0x7fff));
9376         }
9377
9378         return 0;
9379 }
9380
9381 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9382                                       struct link_params *params)
9383 {
9384         struct bnx2x *bp = params->bp;
9385         u16 mod_abs, rx_alarm_status;
9386         u32 val = REG_RD(bp, params->shmem_base +
9387                              offsetof(struct shmem_region, dev_info.
9388                                       port_feature_config[params->port].
9389                                       config));
9390         bnx2x_cl45_read(bp, phy,
9391                         MDIO_PMA_DEVAD,
9392                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9393         if (mod_abs & (1<<8)) {
9394
9395                 /* Module is absent */
9396                 DP(NETIF_MSG_LINK,
9397                    "MOD_ABS indication show module is absent\n");
9398                 phy->media_type = ETH_PHY_NOT_PRESENT;
9399                 /* 1. Set mod_abs to detect next module
9400                  *    presence event
9401                  * 2. Set EDC off by setting OPTXLOS signal input to low
9402                  *    (bit 9).
9403                  *    When the EDC is off it locks onto a reference clock and
9404                  *    avoids becoming 'lost'.
9405                  */
9406                 mod_abs &= ~(1<<8);
9407                 if (!(phy->flags & FLAGS_NOC))
9408                         mod_abs &= ~(1<<9);
9409                 bnx2x_cl45_write(bp, phy,
9410                                  MDIO_PMA_DEVAD,
9411                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9412
9413                 /* Clear RX alarm since it stays up as long as
9414                  * the mod_abs wasn't changed
9415                  */
9416                 bnx2x_cl45_read(bp, phy,
9417                                 MDIO_PMA_DEVAD,
9418                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9419
9420         } else {
9421                 /* Module is present */
9422                 DP(NETIF_MSG_LINK,
9423                    "MOD_ABS indication show module is present\n");
9424                 /* First disable transmitter, and if the module is ok, the
9425                  * module_detection will enable it
9426                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9427                  * 2. Restore the default polarity of the OPRXLOS signal and
9428                  * this signal will then correctly indicate the presence or
9429                  * absence of the Rx signal. (bit 9)
9430                  */
9431                 mod_abs |= (1<<8);
9432                 if (!(phy->flags & FLAGS_NOC))
9433                         mod_abs |= (1<<9);
9434                 bnx2x_cl45_write(bp, phy,
9435                                  MDIO_PMA_DEVAD,
9436                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9437
9438                 /* Clear RX alarm since it stays up as long as the mod_abs
9439                  * wasn't changed. This is need to be done before calling the
9440                  * module detection, otherwise it will clear* the link update
9441                  * alarm
9442                  */
9443                 bnx2x_cl45_read(bp, phy,
9444                                 MDIO_PMA_DEVAD,
9445                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9446
9447
9448                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9449                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9450                         bnx2x_sfp_set_transmitter(params, phy, 0);
9451
9452                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9453                         bnx2x_sfp_module_detection(phy, params);
9454                 else
9455                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9456
9457                 /* Reconfigure link speed based on module type limitations */
9458                 bnx2x_8727_config_speed(phy, params);
9459         }
9460
9461         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9462                    rx_alarm_status);
9463         /* No need to check link status in case of module plugged in/out */
9464 }
9465
9466 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9467                                  struct link_params *params,
9468                                  struct link_vars *vars)
9469
9470 {
9471         struct bnx2x *bp = params->bp;
9472         u8 link_up = 0, oc_port = params->port;
9473         u16 link_status = 0;
9474         u16 rx_alarm_status, lasi_ctrl, val1;
9475
9476         /* If PHY is not initialized, do not check link status */
9477         bnx2x_cl45_read(bp, phy,
9478                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9479                         &lasi_ctrl);
9480         if (!lasi_ctrl)
9481                 return 0;
9482
9483         /* Check the LASI on Rx */
9484         bnx2x_cl45_read(bp, phy,
9485                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9486                         &rx_alarm_status);
9487         vars->line_speed = 0;
9488         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9489
9490         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9491                              MDIO_PMA_LASI_TXCTRL);
9492
9493         bnx2x_cl45_read(bp, phy,
9494                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9495
9496         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9497
9498         /* Clear MSG-OUT */
9499         bnx2x_cl45_read(bp, phy,
9500                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9501
9502         /* If a module is present and there is need to check
9503          * for over current
9504          */
9505         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9506                 /* Check over-current using 8727 GPIO0 input*/
9507                 bnx2x_cl45_read(bp, phy,
9508                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9509                                 &val1);
9510
9511                 if ((val1 & (1<<8)) == 0) {
9512                         if (!CHIP_IS_E1x(bp))
9513                                 oc_port = BP_PATH(bp) + (params->port << 1);
9514                         DP(NETIF_MSG_LINK,
9515                            "8727 Power fault has been detected on port %d\n",
9516                            oc_port);
9517                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9518                                             "been detected and the power to "
9519                                             "that SFP+ module has been removed "
9520                                             "to prevent failure of the card. "
9521                                             "Please remove the SFP+ module and "
9522                                             "restart the system to clear this "
9523                                             "error.\n",
9524                          oc_port);
9525                         /* Disable all RX_ALARMs except for mod_abs */
9526                         bnx2x_cl45_write(bp, phy,
9527                                          MDIO_PMA_DEVAD,
9528                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9529
9530                         bnx2x_cl45_read(bp, phy,
9531                                         MDIO_PMA_DEVAD,
9532                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9533                         /* Wait for module_absent_event */
9534                         val1 |= (1<<8);
9535                         bnx2x_cl45_write(bp, phy,
9536                                          MDIO_PMA_DEVAD,
9537                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9538                         /* Clear RX alarm */
9539                         bnx2x_cl45_read(bp, phy,
9540                                 MDIO_PMA_DEVAD,
9541                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9542                         bnx2x_8727_power_module(params->bp, phy, 0);
9543                         return 0;
9544                 }
9545         } /* Over current check */
9546
9547         /* When module absent bit is set, check module */
9548         if (rx_alarm_status & (1<<5)) {
9549                 bnx2x_8727_handle_mod_abs(phy, params);
9550                 /* Enable all mod_abs and link detection bits */
9551                 bnx2x_cl45_write(bp, phy,
9552                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9553                                  ((1<<5) | (1<<2)));
9554         }
9555
9556         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9557                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9558                 bnx2x_sfp_set_transmitter(params, phy, 1);
9559         } else {
9560                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9561                 return 0;
9562         }
9563
9564         bnx2x_cl45_read(bp, phy,
9565                         MDIO_PMA_DEVAD,
9566                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9567
9568         /* Bits 0..2 --> speed detected,
9569          * Bits 13..15--> link is down
9570          */
9571         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9572                 link_up = 1;
9573                 vars->line_speed = SPEED_10000;
9574                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9575                            params->port);
9576         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9577                 link_up = 1;
9578                 vars->line_speed = SPEED_1000;
9579                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9580                            params->port);
9581         } else {
9582                 link_up = 0;
9583                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9584                            params->port);
9585         }
9586
9587         /* Capture 10G link fault. */
9588         if (vars->line_speed == SPEED_10000) {
9589                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9590                             MDIO_PMA_LASI_TXSTAT, &val1);
9591
9592                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9593                             MDIO_PMA_LASI_TXSTAT, &val1);
9594
9595                 if (val1 & (1<<0)) {
9596                         vars->fault_detected = 1;
9597                 }
9598         }
9599
9600         if (link_up) {
9601                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9602                 vars->duplex = DUPLEX_FULL;
9603                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9604         }
9605
9606         if ((DUAL_MEDIA(params)) &&
9607             (phy->req_line_speed == SPEED_1000)) {
9608                 bnx2x_cl45_read(bp, phy,
9609                                 MDIO_PMA_DEVAD,
9610                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9611                 /* In case of dual-media board and 1G, power up the XAUI side,
9612                  * otherwise power it down. For 10G it is done automatically
9613                  */
9614                 if (link_up)
9615                         val1 &= ~(3<<10);
9616                 else
9617                         val1 |= (3<<10);
9618                 bnx2x_cl45_write(bp, phy,
9619                                  MDIO_PMA_DEVAD,
9620                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9621         }
9622         return link_up;
9623 }
9624
9625 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9626                                   struct link_params *params)
9627 {
9628         struct bnx2x *bp = params->bp;
9629
9630         /* Enable/Disable PHY transmitter output */
9631         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9632
9633         /* Disable Transmitter */
9634         bnx2x_sfp_set_transmitter(params, phy, 0);
9635         /* Clear LASI */
9636         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9637
9638 }
9639
9640 /******************************************************************/
9641 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9642 /******************************************************************/
9643 static int bnx2x_is_8483x_8485x(struct bnx2x_phy *phy)
9644 {
9645         return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9646                 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||
9647                 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));
9648 }
9649
9650 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9651                                             struct bnx2x *bp,
9652                                             u8 port)
9653 {
9654         u16 val, fw_ver2, cnt, i;
9655         static struct bnx2x_reg_set reg_set[] = {
9656                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9657                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9658                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9659                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9660                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9661         };
9662         u16 fw_ver1;
9663
9664         if (bnx2x_is_8483x_8485x(phy)) {
9665                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9666                 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9667                         fw_ver1 &= 0xfff;
9668                 bnx2x_save_spirom_version(bp, port, fw_ver1, phy->ver_addr);
9669         } else {
9670                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9671                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9672                 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9673                         bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9674                                          reg_set[i].reg, reg_set[i].val);
9675
9676                 for (cnt = 0; cnt < 100; cnt++) {
9677                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9678                         if (val & 1)
9679                                 break;
9680                         udelay(5);
9681                 }
9682                 if (cnt == 100) {
9683                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9684                                         "phy fw version(1)\n");
9685                         bnx2x_save_spirom_version(bp, port, 0,
9686                                                   phy->ver_addr);
9687                         return;
9688                 }
9689
9690
9691                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9692                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9693                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9694                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9695                 for (cnt = 0; cnt < 100; cnt++) {
9696                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9697                         if (val & 1)
9698                                 break;
9699                         udelay(5);
9700                 }
9701                 if (cnt == 100) {
9702                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9703                                         "version(2)\n");
9704                         bnx2x_save_spirom_version(bp, port, 0,
9705                                                   phy->ver_addr);
9706                         return;
9707                 }
9708
9709                 /* lower 16 bits of the register SPI_FW_STATUS */
9710                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9711                 /* upper 16 bits of register SPI_FW_STATUS */
9712                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9713
9714                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9715                                           phy->ver_addr);
9716         }
9717
9718 }
9719 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9720                                 struct bnx2x_phy *phy)
9721 {
9722         u16 val, led3_blink_rate, offset, i;
9723         static struct bnx2x_reg_set reg_set[] = {
9724                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9725                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9726                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9727                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9728                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9729                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9730         };
9731
9732         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
9733                 /* Set LED5 source */
9734                 bnx2x_cl45_write(bp, phy,
9735                                  MDIO_PMA_DEVAD,
9736                                  MDIO_PMA_REG_8481_LED5_MASK,
9737                                  0x90);
9738                 led3_blink_rate = 0x000f;
9739         } else {
9740                 led3_blink_rate = 0x0000;
9741         }
9742         /* Set LED3 BLINK */
9743         bnx2x_cl45_write(bp, phy,
9744                          MDIO_PMA_DEVAD,
9745                          MDIO_PMA_REG_8481_LED3_BLINK,
9746                          led3_blink_rate);
9747
9748         /* PHYC_CTL_LED_CTL */
9749         bnx2x_cl45_read(bp, phy,
9750                         MDIO_PMA_DEVAD,
9751                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9752         val &= 0xFE00;
9753         val |= 0x0092;
9754
9755         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9756                 val |= 2 << 12; /* LED5 ON based on source */
9757
9758         bnx2x_cl45_write(bp, phy,
9759                          MDIO_PMA_DEVAD,
9760                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9761
9762         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9763                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9764                                  reg_set[i].val);
9765
9766         if (bnx2x_is_8483x_8485x(phy))
9767                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9768         else
9769                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9770
9771         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9772                 val = MDIO_PMA_REG_84858_ALLOW_GPHY_ACT |
9773                       MDIO_PMA_REG_84823_LED3_STRETCH_EN;
9774         else
9775                 val = MDIO_PMA_REG_84823_LED3_STRETCH_EN;
9776
9777         /* stretch_en for LEDs */
9778         bnx2x_cl45_read_or_write(bp, phy,
9779                                  MDIO_PMA_DEVAD,
9780                                  offset,
9781                                  val);
9782 }
9783
9784 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9785                                       struct link_params *params,
9786                                       u32 action)
9787 {
9788         struct bnx2x *bp = params->bp;
9789         switch (action) {
9790         case PHY_INIT:
9791                 if (bnx2x_is_8483x_8485x(phy)) {
9792                         /* Save spirom version */
9793                         bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9794                 }
9795                 /* This phy uses the NIG latch mechanism since link indication
9796                  * arrives through its LED4 and not via its LASI signal, so we
9797                  * get steady signal instead of clear on read
9798                  */
9799                 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9800                               1 << NIG_LATCH_BC_ENABLE_MI_INT);
9801
9802                 bnx2x_848xx_set_led(bp, phy);
9803                 break;
9804         }
9805 }
9806
9807 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9808                                        struct link_params *params,
9809                                        struct link_vars *vars)
9810 {
9811         struct bnx2x *bp = params->bp;
9812         u16 autoneg_val, an_1000_val, an_10_100_val;
9813
9814         bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9815         bnx2x_cl45_write(bp, phy,
9816                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9817
9818         /* set 1000 speed advertisement */
9819         bnx2x_cl45_read(bp, phy,
9820                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9821                         &an_1000_val);
9822
9823         bnx2x_ext_phy_set_pause(params, phy, vars);
9824         bnx2x_cl45_read(bp, phy,
9825                         MDIO_AN_DEVAD,
9826                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9827                         &an_10_100_val);
9828         bnx2x_cl45_read(bp, phy,
9829                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9830                         &autoneg_val);
9831         /* Disable forced speed */
9832         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9833         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9834
9835         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9836              (phy->speed_cap_mask &
9837              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9838             (phy->req_line_speed == SPEED_1000)) {
9839                 an_1000_val |= (1<<8);
9840                 autoneg_val |= (1<<9 | 1<<12);
9841                 if (phy->req_duplex == DUPLEX_FULL)
9842                         an_1000_val |= (1<<9);
9843                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9844         } else
9845                 an_1000_val &= ~((1<<8) | (1<<9));
9846
9847         bnx2x_cl45_write(bp, phy,
9848                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9849                          an_1000_val);
9850
9851         /* Set 10/100 speed advertisement */
9852         if (phy->req_line_speed == SPEED_AUTO_NEG) {
9853                 if (phy->speed_cap_mask &
9854                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9855                         /* Enable autoneg and restart autoneg for legacy speeds
9856                          */
9857                         autoneg_val |= (1<<9 | 1<<12);
9858                         an_10_100_val |= (1<<8);
9859                         DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9860                 }
9861
9862                 if (phy->speed_cap_mask &
9863                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9864                         /* Enable autoneg and restart autoneg for legacy speeds
9865                          */
9866                         autoneg_val |= (1<<9 | 1<<12);
9867                         an_10_100_val |= (1<<7);
9868                         DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9869                 }
9870
9871                 if ((phy->speed_cap_mask &
9872                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9873                     (phy->supported & SUPPORTED_10baseT_Full)) {
9874                         an_10_100_val |= (1<<6);
9875                         autoneg_val |= (1<<9 | 1<<12);
9876                         DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
9877                 }
9878
9879                 if ((phy->speed_cap_mask &
9880                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9881                     (phy->supported & SUPPORTED_10baseT_Half)) {
9882                         an_10_100_val |= (1<<5);
9883                         autoneg_val |= (1<<9 | 1<<12);
9884                         DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
9885                 }
9886         }
9887
9888         /* Only 10/100 are allowed to work in FORCE mode */
9889         if ((phy->req_line_speed == SPEED_100) &&
9890             (phy->supported &
9891              (SUPPORTED_100baseT_Half |
9892               SUPPORTED_100baseT_Full))) {
9893                 autoneg_val |= (1<<13);
9894                 /* Enabled AUTO-MDIX when autoneg is disabled */
9895                 bnx2x_cl45_write(bp, phy,
9896                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9897                                  (1<<15 | 1<<9 | 7<<0));
9898                 /* The PHY needs this set even for forced link. */
9899                 an_10_100_val |= (1<<8) | (1<<7);
9900                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9901         }
9902         if ((phy->req_line_speed == SPEED_10) &&
9903             (phy->supported &
9904              (SUPPORTED_10baseT_Half |
9905               SUPPORTED_10baseT_Full))) {
9906                 /* Enabled AUTO-MDIX when autoneg is disabled */
9907                 bnx2x_cl45_write(bp, phy,
9908                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9909                                  (1<<15 | 1<<9 | 7<<0));
9910                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9911         }
9912
9913         bnx2x_cl45_write(bp, phy,
9914                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9915                          an_10_100_val);
9916
9917         if (phy->req_duplex == DUPLEX_FULL)
9918                 autoneg_val |= (1<<8);
9919
9920         /* Always write this if this is not 84833/4.
9921          * For 84833/4, write it only when it's a forced speed.
9922          */
9923         if (!bnx2x_is_8483x_8485x(phy) ||
9924             ((autoneg_val & (1<<12)) == 0))
9925                 bnx2x_cl45_write(bp, phy,
9926                          MDIO_AN_DEVAD,
9927                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9928
9929         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9930             (phy->speed_cap_mask &
9931              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9932                 (phy->req_line_speed == SPEED_10000)) {
9933                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9934                         /* Restart autoneg for 10G*/
9935
9936                         bnx2x_cl45_read_or_write(
9937                                 bp, phy,
9938                                 MDIO_AN_DEVAD,
9939                                 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9940                                 0x1000);
9941                         bnx2x_cl45_write(bp, phy,
9942                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9943                                          0x3200);
9944         } else
9945                 bnx2x_cl45_write(bp, phy,
9946                                  MDIO_AN_DEVAD,
9947                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9948                                  1);
9949
9950         return 0;
9951 }
9952
9953 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9954                                   struct link_params *params,
9955                                   struct link_vars *vars)
9956 {
9957         struct bnx2x *bp = params->bp;
9958         /* Restore normal power mode*/
9959         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9960                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9961
9962         /* HW reset */
9963         bnx2x_ext_phy_hw_reset(bp, params->port);
9964         bnx2x_wait_reset_complete(bp, phy, params);
9965
9966         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9967         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9968 }
9969
9970 #define PHY848xx_CMDHDLR_WAIT 300
9971 #define PHY848xx_CMDHDLR_MAX_ARGS 5
9972
9973 static int bnx2x_84858_cmd_hdlr(struct bnx2x_phy *phy,
9974                                 struct link_params *params,
9975                                 u16 fw_cmd,
9976                                 u16 cmd_args[], int argc)
9977 {
9978         int idx;
9979         u16 val;
9980         struct bnx2x *bp = params->bp;
9981
9982         /* Step 1: Poll the STATUS register to see whether the previous command
9983          * is in progress or the system is busy (CMD_IN_PROGRESS or
9984          * SYSTEM_BUSY). If previous command is in progress or system is busy,
9985          * check again until the previous command finishes execution and the
9986          * system is available for taking command
9987          */
9988
9989         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
9990                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9991                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
9992                 if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) &&
9993                     (val != PHY84858_STATUS_CMD_SYSTEM_BUSY))
9994                         break;
9995                 usleep_range(1000, 2000);
9996         }
9997         if (idx >= PHY848xx_CMDHDLR_WAIT) {
9998                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9999                 return -EINVAL;
10000         }
10001
10002         /* Step2: If any parameters are required for the function, write them
10003          * to the required DATA registers
10004          */
10005
10006         for (idx = 0; idx < argc; idx++) {
10007                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10008                                  MDIO_848xx_CMD_HDLR_DATA1 + idx,
10009                                  cmd_args[idx]);
10010         }
10011
10012         /* Step3: When the firmware is ready for commands, write the 'Command
10013          * code' to the CMD register
10014          */
10015         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10016                          MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10017
10018         /* Step4: Once the command has been written, poll the STATUS register
10019          * to check whether the command has completed (CMD_COMPLETED_PASS/
10020          * CMD_FOR_CMDS or CMD_COMPLETED_ERROR).
10021          */
10022
10023         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10024                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10025                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
10026                 if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) ||
10027                     (val == PHY84858_STATUS_CMD_COMPLETE_ERROR))
10028                         break;
10029                 usleep_range(1000, 2000);
10030         }
10031         if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10032             (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) {
10033                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
10034                 return -EINVAL;
10035         }
10036         /* Step5: Once the command has completed, read the specficied DATA
10037          * registers for any saved results for the command, if applicable
10038          */
10039
10040         /* Gather returning data */
10041         for (idx = 0; idx < argc; idx++) {
10042                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10043                                 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10044                                 &cmd_args[idx]);
10045         }
10046
10047         return 0;
10048 }
10049
10050 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
10051                                 struct link_params *params, u16 fw_cmd,
10052                                 u16 cmd_args[], int argc, int process)
10053 {
10054         int idx;
10055         u16 val;
10056         struct bnx2x *bp = params->bp;
10057         int rc = 0;
10058
10059         if (process == PHY84833_MB_PROCESS2) {
10060                 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
10061                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10062                                  MDIO_848xx_CMD_HDLR_STATUS,
10063                                  PHY84833_STATUS_CMD_OPEN_OVERRIDE);
10064         }
10065
10066         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10067                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10068                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
10069                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
10070                         break;
10071                 usleep_range(1000, 2000);
10072         }
10073         if (idx >= PHY848xx_CMDHDLR_WAIT) {
10074                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
10075                 /* if the status is CMD_COMPLETE_PASS or CMD_COMPLETE_ERROR
10076                  * clear the status to CMD_CLEAR_COMPLETE
10077                  */
10078                 if (val == PHY84833_STATUS_CMD_COMPLETE_PASS ||
10079                     val == PHY84833_STATUS_CMD_COMPLETE_ERROR) {
10080                         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10081                                          MDIO_848xx_CMD_HDLR_STATUS,
10082                                          PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10083                 }
10084                 return -EINVAL;
10085         }
10086         if (process == PHY84833_MB_PROCESS1 ||
10087             process == PHY84833_MB_PROCESS2) {
10088                 /* Prepare argument(s) */
10089                 for (idx = 0; idx < argc; idx++) {
10090                         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10091                                          MDIO_848xx_CMD_HDLR_DATA1 + idx,
10092                                          cmd_args[idx]);
10093                 }
10094         }
10095
10096         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10097                         MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10098         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10099                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10100                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
10101                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
10102                     (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
10103                         break;
10104                 usleep_range(1000, 2000);
10105         }
10106         if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10107             (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
10108                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
10109                 rc = -EINVAL;
10110         }
10111         if (process == PHY84833_MB_PROCESS3 && rc == 0) {
10112                 /* Gather returning data */
10113                 for (idx = 0; idx < argc; idx++) {
10114                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10115                                         MDIO_848xx_CMD_HDLR_DATA1 + idx,
10116                                         &cmd_args[idx]);
10117                 }
10118         }
10119         if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR ||
10120             val == PHY84833_STATUS_CMD_COMPLETE_PASS) {
10121                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10122                                  MDIO_848xx_CMD_HDLR_STATUS,
10123                                  PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10124         }
10125         return rc;
10126 }
10127
10128 static int bnx2x_848xx_cmd_hdlr(struct bnx2x_phy *phy,
10129                                 struct link_params *params,
10130                                 u16 fw_cmd,
10131                                            u16 cmd_args[], int argc,
10132                                            int process)
10133 {
10134         struct bnx2x *bp = params->bp;
10135
10136         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||
10137             (REG_RD(bp, params->shmem2_base +
10138                     offsetof(struct shmem2_region,
10139                              link_attr_sync[params->port])) &
10140              LINK_ATTR_84858)) {
10141                 return bnx2x_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10142                                             argc);
10143         } else {
10144                 return bnx2x_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10145                                             argc, process);
10146         }
10147 }
10148
10149 static int bnx2x_848xx_pair_swap_cfg(struct bnx2x_phy *phy,
10150                                      struct link_params *params,
10151                                      struct link_vars *vars)
10152 {
10153         u32 pair_swap;
10154         u16 data[PHY848xx_CMDHDLR_MAX_ARGS];
10155         int status;
10156         struct bnx2x *bp = params->bp;
10157
10158         /* Check for configuration. */
10159         pair_swap = REG_RD(bp, params->shmem_base +
10160                            offsetof(struct shmem_region,
10161                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10162                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
10163
10164         if (pair_swap == 0)
10165                 return 0;
10166
10167         /* Only the second argument is used for this command */
10168         data[1] = (u16)pair_swap;
10169
10170         status = bnx2x_848xx_cmd_hdlr(phy, params,
10171                                       PHY848xx_CMD_SET_PAIR_SWAP, data,
10172                                       2, PHY84833_MB_PROCESS2);
10173         if (status == 0)
10174                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
10175
10176         return status;
10177 }
10178
10179 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
10180                                       u32 shmem_base_path[],
10181                                       u32 chip_id)
10182 {
10183         u32 reset_pin[2];
10184         u32 idx;
10185         u8 reset_gpios;
10186         if (CHIP_IS_E3(bp)) {
10187                 /* Assume that these will be GPIOs, not EPIOs. */
10188                 for (idx = 0; idx < 2; idx++) {
10189                         /* Map config param to register bit. */
10190                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10191                                 offsetof(struct shmem_region,
10192                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
10193                         reset_pin[idx] = (reset_pin[idx] &
10194                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10195                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10196                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
10197                         reset_pin[idx] = (1 << reset_pin[idx]);
10198                 }
10199                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10200         } else {
10201                 /* E2, look from diff place of shmem. */
10202                 for (idx = 0; idx < 2; idx++) {
10203                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10204                                 offsetof(struct shmem_region,
10205                                 dev_info.port_hw_config[0].default_cfg));
10206                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10207                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10208                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10209                         reset_pin[idx] = (1 << reset_pin[idx]);
10210                 }
10211                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10212         }
10213
10214         return reset_gpios;
10215 }
10216
10217 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10218                                 struct link_params *params)
10219 {
10220         struct bnx2x *bp = params->bp;
10221         u8 reset_gpios;
10222         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
10223                                 offsetof(struct shmem2_region,
10224                                 other_shmem_base_addr));
10225
10226         u32 shmem_base_path[2];
10227
10228         /* Work around for 84833 LED failure inside RESET status */
10229         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10230                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10231                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10232         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10233                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10234                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10235
10236         shmem_base_path[0] = params->shmem_base;
10237         shmem_base_path[1] = other_shmem_base_addr;
10238
10239         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10240                                                   params->chip_id);
10241
10242         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10243         udelay(10);
10244         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10245                 reset_gpios);
10246
10247         return 0;
10248 }
10249
10250 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10251                                    struct link_params *params,
10252                                    struct link_vars *vars)
10253 {
10254         int rc;
10255         struct bnx2x *bp = params->bp;
10256         u16 cmd_args = 0;
10257
10258         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10259
10260         /* Prevent Phy from working in EEE and advertising it */
10261         rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
10262                                   &cmd_args, 1, PHY84833_MB_PROCESS1);
10263         if (rc) {
10264                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10265                 return rc;
10266         }
10267
10268         return bnx2x_eee_disable(phy, params, vars);
10269 }
10270
10271 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10272                                    struct link_params *params,
10273                                    struct link_vars *vars)
10274 {
10275         int rc;
10276         struct bnx2x *bp = params->bp;
10277         u16 cmd_args = 1;
10278
10279         rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
10280                                   &cmd_args, 1, PHY84833_MB_PROCESS1);
10281         if (rc) {
10282                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10283                 return rc;
10284         }
10285
10286         return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10287 }
10288
10289 #define PHY84833_CONSTANT_LATENCY 1193
10290 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10291                                    struct link_params *params,
10292                                    struct link_vars *vars)
10293 {
10294         struct bnx2x *bp = params->bp;
10295         u8 port, initialize = 1;
10296         u16 val;
10297         u32 actual_phy_selection;
10298         u16 cmd_args[PHY848xx_CMDHDLR_MAX_ARGS];
10299         int rc = 0;
10300
10301         usleep_range(1000, 2000);
10302
10303         if (!(CHIP_IS_E1x(bp)))
10304                 port = BP_PATH(bp);
10305         else
10306                 port = params->port;
10307
10308         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10309                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10310                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10311                                port);
10312         } else {
10313                 /* MDIO reset */
10314                 bnx2x_cl45_write(bp, phy,
10315                                 MDIO_PMA_DEVAD,
10316                                 MDIO_PMA_REG_CTRL, 0x8000);
10317         }
10318
10319         bnx2x_wait_reset_complete(bp, phy, params);
10320
10321         /* Wait for GPHY to come out of reset */
10322         msleep(50);
10323         if (!bnx2x_is_8483x_8485x(phy)) {
10324                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10325                  * behavior.
10326                  */
10327                 u16 temp;
10328                 temp = vars->line_speed;
10329                 vars->line_speed = SPEED_10000;
10330                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10331                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10332                 vars->line_speed = temp;
10333         }
10334         /* Check if this is actually BCM84858 */
10335         if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10336                 u16 hw_rev;
10337
10338                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10339                                 MDIO_AN_REG_848xx_ID_MSB, &hw_rev);
10340                 if (hw_rev == BCM84858_PHY_ID) {
10341                         params->link_attr_sync |= LINK_ATTR_84858;
10342                         bnx2x_update_link_attr(params, params->link_attr_sync);
10343                 }
10344         }
10345
10346         /* Set dual-media configuration according to configuration */
10347         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10348                         MDIO_CTL_REG_84823_MEDIA, &val);
10349         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10350                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10351                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10352                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10353                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10354
10355         if (CHIP_IS_E3(bp)) {
10356                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10357                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10358         } else {
10359                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10360                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10361         }
10362
10363         actual_phy_selection = bnx2x_phy_selection(params);
10364
10365         switch (actual_phy_selection) {
10366         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10367                 /* Do nothing. Essentially this is like the priority copper */
10368                 break;
10369         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10370                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10371                 break;
10372         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10373                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10374                 break;
10375         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10376                 /* Do nothing here. The first PHY won't be initialized at all */
10377                 break;
10378         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10379                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10380                 initialize = 0;
10381                 break;
10382         }
10383         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10384                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10385
10386         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10387                          MDIO_CTL_REG_84823_MEDIA, val);
10388         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10389                    params->multi_phy_config, val);
10390
10391         if (bnx2x_is_8483x_8485x(phy)) {
10392                 bnx2x_848xx_pair_swap_cfg(phy, params, vars);
10393
10394                 /* Keep AutogrEEEn disabled. */
10395                 cmd_args[0] = 0x0;
10396                 cmd_args[1] = 0x0;
10397                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10398                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10399                 rc = bnx2x_848xx_cmd_hdlr(phy, params,
10400                                           PHY848xx_CMD_SET_EEE_MODE, cmd_args,
10401                                           4, PHY84833_MB_PROCESS1);
10402                 if (rc)
10403                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10404         }
10405         if (initialize)
10406                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10407         else
10408                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10409         /* 84833 PHY has a better feature and doesn't need to support this. */
10410         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10411                 u32 cms_enable = REG_RD(bp, params->shmem_base +
10412                         offsetof(struct shmem_region,
10413                         dev_info.port_hw_config[params->port].default_cfg)) &
10414                         PORT_HW_CFG_ENABLE_CMS_MASK;
10415
10416                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10417                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10418                 if (cms_enable)
10419                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10420                 else
10421                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10422                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10423                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10424         }
10425
10426         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10427                         MDIO_84833_TOP_CFG_FW_REV, &val);
10428
10429         /* Configure EEE support */
10430         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10431             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10432             bnx2x_eee_has_cap(params)) {
10433                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10434                 if (rc) {
10435                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10436                         bnx2x_8483x_disable_eee(phy, params, vars);
10437                         return rc;
10438                 }
10439
10440                 if ((phy->req_duplex == DUPLEX_FULL) &&
10441                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10442                     (bnx2x_eee_calc_timer(params) ||
10443                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10444                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10445                 else
10446                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10447                 if (rc) {
10448                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10449                         return rc;
10450                 }
10451         } else {
10452                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10453         }
10454
10455         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10456                 /* Additional settings for jumbo packets in 1000BASE-T mode */
10457                 /* Allow rx extended length */
10458                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10459                                 MDIO_AN_REG_8481_AUX_CTRL, &val);
10460                 val |= 0x4000;
10461                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10462                                  MDIO_AN_REG_8481_AUX_CTRL, val);
10463                 /* TX FIFO Elasticity LSB */
10464                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10465                                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, &val);
10466                 val |= 0x1;
10467                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10468                                  MDIO_AN_REG_8481_1G_100T_EXT_CTRL, val);
10469                 /* TX FIFO Elasticity MSB */
10470                 /* Enable expansion register 0x46 (Pattern Generator status) */
10471                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10472                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf46);
10473
10474                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10475                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, &val);
10476                 val |= 0x4000;
10477                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10478                                  MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, val);
10479         }
10480
10481         if (bnx2x_is_8483x_8485x(phy)) {
10482                 /* Bring PHY out of super isolate mode as the final step. */
10483                 bnx2x_cl45_read_and_write(bp, phy,
10484                                           MDIO_CTL_DEVAD,
10485                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10486                                           (u16)~MDIO_84833_SUPER_ISOLATE);
10487         }
10488         return rc;
10489 }
10490
10491 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10492                                   struct link_params *params,
10493                                   struct link_vars *vars)
10494 {
10495         struct bnx2x *bp = params->bp;
10496         u16 val, val1, val2;
10497         u8 link_up = 0;
10498
10499
10500         /* Check 10G-BaseT link status */
10501         /* Check PMD signal ok */
10502         bnx2x_cl45_read(bp, phy,
10503                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10504         bnx2x_cl45_read(bp, phy,
10505                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10506                         &val2);
10507         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10508
10509         /* Check link 10G */
10510         if (val2 & (1<<11)) {
10511                 vars->line_speed = SPEED_10000;
10512                 vars->duplex = DUPLEX_FULL;
10513                 link_up = 1;
10514                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10515         } else { /* Check Legacy speed link */
10516                 u16 legacy_status, legacy_speed;
10517
10518                 /* Enable expansion register 0x42 (Operation mode status) */
10519                 bnx2x_cl45_write(bp, phy,
10520                                  MDIO_AN_DEVAD,
10521                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10522
10523                 /* Get legacy speed operation status */
10524                 bnx2x_cl45_read(bp, phy,
10525                                 MDIO_AN_DEVAD,
10526                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10527                                 &legacy_status);
10528
10529                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10530                    legacy_status);
10531                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10532                 legacy_speed = (legacy_status & (3<<9));
10533                 if (legacy_speed == (0<<9))
10534                         vars->line_speed = SPEED_10;
10535                 else if (legacy_speed == (1<<9))
10536                         vars->line_speed = SPEED_100;
10537                 else if (legacy_speed == (2<<9))
10538                         vars->line_speed = SPEED_1000;
10539                 else { /* Should not happen: Treat as link down */
10540                         vars->line_speed = 0;
10541                         link_up = 0;
10542                 }
10543
10544                 if (link_up) {
10545                         if (legacy_status & (1<<8))
10546                                 vars->duplex = DUPLEX_FULL;
10547                         else
10548                                 vars->duplex = DUPLEX_HALF;
10549
10550                         DP(NETIF_MSG_LINK,
10551                            "Link is up in %dMbps, is_duplex_full= %d\n",
10552                            vars->line_speed,
10553                            (vars->duplex == DUPLEX_FULL));
10554                         /* Check legacy speed AN resolution */
10555                         bnx2x_cl45_read(bp, phy,
10556                                         MDIO_AN_DEVAD,
10557                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10558                                         &val);
10559                         if (val & (1<<5))
10560                                 vars->link_status |=
10561                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10562                         bnx2x_cl45_read(bp, phy,
10563                                         MDIO_AN_DEVAD,
10564                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10565                                         &val);
10566                         if ((val & (1<<0)) == 0)
10567                                 vars->link_status |=
10568                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10569                 }
10570         }
10571         if (link_up) {
10572                 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10573                            vars->line_speed);
10574                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10575
10576                 /* Read LP advertised speeds */
10577                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10578                                 MDIO_AN_REG_CL37_FC_LP, &val);
10579                 if (val & (1<<5))
10580                         vars->link_status |=
10581                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10582                 if (val & (1<<6))
10583                         vars->link_status |=
10584                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10585                 if (val & (1<<7))
10586                         vars->link_status |=
10587                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10588                 if (val & (1<<8))
10589                         vars->link_status |=
10590                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10591                 if (val & (1<<9))
10592                         vars->link_status |=
10593                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10594
10595                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10596                                 MDIO_AN_REG_1000T_STATUS, &val);
10597
10598                 if (val & (1<<10))
10599                         vars->link_status |=
10600                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10601                 if (val & (1<<11))
10602                         vars->link_status |=
10603                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10604
10605                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10606                                 MDIO_AN_REG_MASTER_STATUS, &val);
10607
10608                 if (val & (1<<11))
10609                         vars->link_status |=
10610                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10611
10612                 /* Determine if EEE was negotiated */
10613                 if (bnx2x_is_8483x_8485x(phy))
10614                         bnx2x_eee_an_resolve(phy, params, vars);
10615         }
10616
10617         return link_up;
10618 }
10619
10620 static int bnx2x_8485x_format_ver(u32 raw_ver, u8 *str, u16 *len)
10621 {
10622         u32 num;
10623
10624         num = ((raw_ver & 0xF80) >> 7) << 16 | ((raw_ver & 0x7F) << 8) |
10625               ((raw_ver & 0xF000) >> 12);
10626         return bnx2x_3_seq_format_ver(num, str, len);
10627 }
10628
10629 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10630 {
10631         u32 spirom_ver;
10632
10633         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10634         return bnx2x_format_ver(spirom_ver, str, len);
10635 }
10636
10637 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10638                                 struct link_params *params)
10639 {
10640         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10641                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10642         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10643                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10644 }
10645
10646 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10647                                         struct link_params *params)
10648 {
10649         bnx2x_cl45_write(params->bp, phy,
10650                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10651         bnx2x_cl45_write(params->bp, phy,
10652                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10653 }
10654
10655 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10656                                    struct link_params *params)
10657 {
10658         struct bnx2x *bp = params->bp;
10659         u8 port;
10660         u16 val16;
10661
10662         if (!(CHIP_IS_E1x(bp)))
10663                 port = BP_PATH(bp);
10664         else
10665                 port = params->port;
10666
10667         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10668                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10669                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10670                                port);
10671         } else {
10672                 bnx2x_cl45_read(bp, phy,
10673                                 MDIO_CTL_DEVAD,
10674                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10675                 val16 |= MDIO_84833_SUPER_ISOLATE;
10676                 bnx2x_cl45_write(bp, phy,
10677                                  MDIO_CTL_DEVAD,
10678                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10679         }
10680 }
10681
10682 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10683                                      struct link_params *params, u8 mode)
10684 {
10685         struct bnx2x *bp = params->bp;
10686         u16 val;
10687         u8 port;
10688
10689         if (!(CHIP_IS_E1x(bp)))
10690                 port = BP_PATH(bp);
10691         else
10692                 port = params->port;
10693
10694         switch (mode) {
10695         case LED_MODE_OFF:
10696
10697                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10698
10699                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10700                     SHARED_HW_CFG_LED_EXTPHY1) {
10701
10702                         /* Set LED masks */
10703                         bnx2x_cl45_write(bp, phy,
10704                                         MDIO_PMA_DEVAD,
10705                                         MDIO_PMA_REG_8481_LED1_MASK,
10706                                         0x0);
10707
10708                         bnx2x_cl45_write(bp, phy,
10709                                         MDIO_PMA_DEVAD,
10710                                         MDIO_PMA_REG_8481_LED2_MASK,
10711                                         0x0);
10712
10713                         bnx2x_cl45_write(bp, phy,
10714                                         MDIO_PMA_DEVAD,
10715                                         MDIO_PMA_REG_8481_LED3_MASK,
10716                                         0x0);
10717
10718                         bnx2x_cl45_write(bp, phy,
10719                                         MDIO_PMA_DEVAD,
10720                                         MDIO_PMA_REG_8481_LED5_MASK,
10721                                         0x0);
10722
10723                 } else {
10724                         /* LED 1 OFF */
10725                         bnx2x_cl45_write(bp, phy,
10726                                          MDIO_PMA_DEVAD,
10727                                          MDIO_PMA_REG_8481_LED1_MASK,
10728                                          0x0);
10729
10730                         if (phy->type ==
10731                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10732                                 /* LED 2 OFF */
10733                                 bnx2x_cl45_write(bp, phy,
10734                                                  MDIO_PMA_DEVAD,
10735                                                  MDIO_PMA_REG_8481_LED2_MASK,
10736                                                  0x0);
10737                                 /* LED 3 OFF */
10738                                 bnx2x_cl45_write(bp, phy,
10739                                                  MDIO_PMA_DEVAD,
10740                                                  MDIO_PMA_REG_8481_LED3_MASK,
10741                                                  0x0);
10742                         }
10743                 }
10744                 break;
10745         case LED_MODE_FRONT_PANEL_OFF:
10746
10747                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10748                    port);
10749
10750                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10751                     SHARED_HW_CFG_LED_EXTPHY1) {
10752
10753                         /* Set LED masks */
10754                         bnx2x_cl45_write(bp, phy,
10755                                          MDIO_PMA_DEVAD,
10756                                          MDIO_PMA_REG_8481_LED1_MASK,
10757                                          0x0);
10758
10759                         bnx2x_cl45_write(bp, phy,
10760                                          MDIO_PMA_DEVAD,
10761                                          MDIO_PMA_REG_8481_LED2_MASK,
10762                                          0x0);
10763
10764                         bnx2x_cl45_write(bp, phy,
10765                                          MDIO_PMA_DEVAD,
10766                                          MDIO_PMA_REG_8481_LED3_MASK,
10767                                          0x0);
10768
10769                         bnx2x_cl45_write(bp, phy,
10770                                          MDIO_PMA_DEVAD,
10771                                          MDIO_PMA_REG_8481_LED5_MASK,
10772                                          0x20);
10773
10774                 } else {
10775                         bnx2x_cl45_write(bp, phy,
10776                                          MDIO_PMA_DEVAD,
10777                                          MDIO_PMA_REG_8481_LED1_MASK,
10778                                          0x0);
10779                         if (phy->type ==
10780                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10781                                 /* Disable MI_INT interrupt before setting LED4
10782                                  * source to constant off.
10783                                  */
10784                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10785                                            params->port*4) &
10786                                     NIG_MASK_MI_INT) {
10787                                         params->link_flags |=
10788                                         LINK_FLAGS_INT_DISABLED;
10789
10790                                         bnx2x_bits_dis(
10791                                                 bp,
10792                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10793                                                 params->port*4,
10794                                                 NIG_MASK_MI_INT);
10795                                 }
10796                                 bnx2x_cl45_write(bp, phy,
10797                                                  MDIO_PMA_DEVAD,
10798                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10799                                                  0x0);
10800                         }
10801                         if (phy->type ==
10802                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10803                                 /* LED 2 OFF */
10804                                 bnx2x_cl45_write(bp, phy,
10805                                                  MDIO_PMA_DEVAD,
10806                                                  MDIO_PMA_REG_8481_LED2_MASK,
10807                                                  0x0);
10808                                 /* LED 3 OFF */
10809                                 bnx2x_cl45_write(bp, phy,
10810                                                  MDIO_PMA_DEVAD,
10811                                                  MDIO_PMA_REG_8481_LED3_MASK,
10812                                                  0x0);
10813                         }
10814                 }
10815                 break;
10816         case LED_MODE_ON:
10817
10818                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10819
10820                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10821                     SHARED_HW_CFG_LED_EXTPHY1) {
10822                         /* Set control reg */
10823                         bnx2x_cl45_read(bp, phy,
10824                                         MDIO_PMA_DEVAD,
10825                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10826                                         &val);
10827                         val &= 0x8000;
10828                         val |= 0x2492;
10829
10830                         bnx2x_cl45_write(bp, phy,
10831                                          MDIO_PMA_DEVAD,
10832                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10833                                          val);
10834
10835                         /* Set LED masks */
10836                         bnx2x_cl45_write(bp, phy,
10837                                          MDIO_PMA_DEVAD,
10838                                          MDIO_PMA_REG_8481_LED1_MASK,
10839                                          0x0);
10840
10841                         bnx2x_cl45_write(bp, phy,
10842                                          MDIO_PMA_DEVAD,
10843                                          MDIO_PMA_REG_8481_LED2_MASK,
10844                                          0x20);
10845
10846                         bnx2x_cl45_write(bp, phy,
10847                                          MDIO_PMA_DEVAD,
10848                                          MDIO_PMA_REG_8481_LED3_MASK,
10849                                          0x20);
10850
10851                         bnx2x_cl45_write(bp, phy,
10852                                          MDIO_PMA_DEVAD,
10853                                          MDIO_PMA_REG_8481_LED5_MASK,
10854                                          0x0);
10855                 } else {
10856                         bnx2x_cl45_write(bp, phy,
10857                                          MDIO_PMA_DEVAD,
10858                                          MDIO_PMA_REG_8481_LED1_MASK,
10859                                          0x20);
10860                         if (phy->type ==
10861                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10862                                 /* Disable MI_INT interrupt before setting LED4
10863                                  * source to constant on.
10864                                  */
10865                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10866                                            params->port*4) &
10867                                     NIG_MASK_MI_INT) {
10868                                         params->link_flags |=
10869                                         LINK_FLAGS_INT_DISABLED;
10870
10871                                         bnx2x_bits_dis(
10872                                                 bp,
10873                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10874                                                 params->port*4,
10875                                                 NIG_MASK_MI_INT);
10876                                 }
10877                         }
10878                         if (phy->type ==
10879                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10880                                 /* Tell LED3 to constant on */
10881                                 bnx2x_cl45_read(bp, phy,
10882                                                 MDIO_PMA_DEVAD,
10883                                                 MDIO_PMA_REG_8481_LINK_SIGNAL,
10884                                                 &val);
10885                                 val &= ~(7<<6);
10886                                 val |= (2<<6);  /* A83B[8:6]= 2 */
10887                                 bnx2x_cl45_write(bp, phy,
10888                                                  MDIO_PMA_DEVAD,
10889                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10890                                                  val);
10891                                 bnx2x_cl45_write(bp, phy,
10892                                                  MDIO_PMA_DEVAD,
10893                                                  MDIO_PMA_REG_8481_LED3_MASK,
10894                                                  0x20);
10895                         } else {
10896                                 bnx2x_cl45_write(bp, phy,
10897                                                  MDIO_PMA_DEVAD,
10898                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10899                                                  0x20);
10900                         }
10901                 }
10902                 break;
10903
10904         case LED_MODE_OPER:
10905
10906                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10907
10908                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10909                     SHARED_HW_CFG_LED_EXTPHY1) {
10910
10911                         /* Set control reg */
10912                         bnx2x_cl45_read(bp, phy,
10913                                         MDIO_PMA_DEVAD,
10914                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10915                                         &val);
10916
10917                         if (!((val &
10918                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10919                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10920                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10921                                 bnx2x_cl45_write(bp, phy,
10922                                                  MDIO_PMA_DEVAD,
10923                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10924                                                  0xa492);
10925                         }
10926
10927                         /* Set LED masks */
10928                         bnx2x_cl45_write(bp, phy,
10929                                          MDIO_PMA_DEVAD,
10930                                          MDIO_PMA_REG_8481_LED1_MASK,
10931                                          0x10);
10932
10933                         bnx2x_cl45_write(bp, phy,
10934                                          MDIO_PMA_DEVAD,
10935                                          MDIO_PMA_REG_8481_LED2_MASK,
10936                                          0x80);
10937
10938                         bnx2x_cl45_write(bp, phy,
10939                                          MDIO_PMA_DEVAD,
10940                                          MDIO_PMA_REG_8481_LED3_MASK,
10941                                          0x98);
10942
10943                         bnx2x_cl45_write(bp, phy,
10944                                          MDIO_PMA_DEVAD,
10945                                          MDIO_PMA_REG_8481_LED5_MASK,
10946                                          0x40);
10947
10948                 } else {
10949                         /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10950                          * sources are all wired through LED1, rather than only
10951                          * 10G in other modes.
10952                          */
10953                         val = ((params->hw_led_mode <<
10954                                 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10955                                SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10956
10957                         bnx2x_cl45_write(bp, phy,
10958                                          MDIO_PMA_DEVAD,
10959                                          MDIO_PMA_REG_8481_LED1_MASK,
10960                                          val);
10961
10962                         /* Tell LED3 to blink on source */
10963                         bnx2x_cl45_read(bp, phy,
10964                                         MDIO_PMA_DEVAD,
10965                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10966                                         &val);
10967                         val &= ~(7<<6);
10968                         val |= (1<<6); /* A83B[8:6]= 1 */
10969                         bnx2x_cl45_write(bp, phy,
10970                                          MDIO_PMA_DEVAD,
10971                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10972                                          val);
10973                         if (phy->type ==
10974                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10975                                 bnx2x_cl45_write(bp, phy,
10976                                                  MDIO_PMA_DEVAD,
10977                                                  MDIO_PMA_REG_8481_LED2_MASK,
10978                                                  0x18);
10979                                 bnx2x_cl45_write(bp, phy,
10980                                                  MDIO_PMA_DEVAD,
10981                                                  MDIO_PMA_REG_8481_LED3_MASK,
10982                                                  0x06);
10983                         }
10984                         if (phy->type ==
10985                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10986                                 /* Restore LED4 source to external link,
10987                                  * and re-enable interrupts.
10988                                  */
10989                                 bnx2x_cl45_write(bp, phy,
10990                                                  MDIO_PMA_DEVAD,
10991                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10992                                                  0x40);
10993                                 if (params->link_flags &
10994                                     LINK_FLAGS_INT_DISABLED) {
10995                                         bnx2x_link_int_enable(params);
10996                                         params->link_flags &=
10997                                                 ~LINK_FLAGS_INT_DISABLED;
10998                                 }
10999                         }
11000                 }
11001                 break;
11002         }
11003
11004         /* This is a workaround for E3+84833 until autoneg
11005          * restart is fixed in f/w
11006          */
11007         if (CHIP_IS_E3(bp)) {
11008                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
11009                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
11010         }
11011 }
11012
11013 /******************************************************************/
11014 /*                      54618SE PHY SECTION                       */
11015 /******************************************************************/
11016 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
11017                                         struct link_params *params,
11018                                         u32 action)
11019 {
11020         struct bnx2x *bp = params->bp;
11021         u16 temp;
11022         switch (action) {
11023         case PHY_INIT:
11024                 /* Configure LED4: set to INTR (0x6). */
11025                 /* Accessing shadow register 0xe. */
11026                 bnx2x_cl22_write(bp, phy,
11027                                  MDIO_REG_GPHY_SHADOW,
11028                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
11029                 bnx2x_cl22_read(bp, phy,
11030                                 MDIO_REG_GPHY_SHADOW,
11031                                 &temp);
11032                 temp &= ~(0xf << 4);
11033                 temp |= (0x6 << 4);
11034                 bnx2x_cl22_write(bp, phy,
11035                                  MDIO_REG_GPHY_SHADOW,
11036                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11037                 /* Configure INTR based on link status change. */
11038                 bnx2x_cl22_write(bp, phy,
11039                                  MDIO_REG_INTR_MASK,
11040                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
11041                 break;
11042         }
11043 }
11044
11045 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
11046                                                struct link_params *params,
11047                                                struct link_vars *vars)
11048 {
11049         struct bnx2x *bp = params->bp;
11050         u8 port;
11051         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
11052         u32 cfg_pin;
11053
11054         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
11055         usleep_range(1000, 2000);
11056
11057         /* This works with E3 only, no need to check the chip
11058          * before determining the port.
11059          */
11060         port = params->port;
11061
11062         cfg_pin = (REG_RD(bp, params->shmem_base +
11063                         offsetof(struct shmem_region,
11064                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11065                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11066                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11067
11068         /* Drive pin high to bring the GPHY out of reset. */
11069         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
11070
11071         /* wait for GPHY to reset */
11072         msleep(50);
11073
11074         /* reset phy */
11075         bnx2x_cl22_write(bp, phy,
11076                          MDIO_PMA_REG_CTRL, 0x8000);
11077         bnx2x_wait_reset_complete(bp, phy, params);
11078
11079         /* Wait for GPHY to reset */
11080         msleep(50);
11081
11082
11083         bnx2x_54618se_specific_func(phy, params, PHY_INIT);
11084         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
11085         bnx2x_cl22_write(bp, phy,
11086                         MDIO_REG_GPHY_SHADOW,
11087                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
11088         bnx2x_cl22_read(bp, phy,
11089                         MDIO_REG_GPHY_SHADOW,
11090                         &temp);
11091         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
11092         bnx2x_cl22_write(bp, phy,
11093                         MDIO_REG_GPHY_SHADOW,
11094                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11095
11096         /* Set up fc */
11097         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
11098         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
11099         fc_val = 0;
11100         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
11101                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
11102                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
11103
11104         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
11105                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
11106                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
11107
11108         /* Read all advertisement */
11109         bnx2x_cl22_read(bp, phy,
11110                         0x09,
11111                         &an_1000_val);
11112
11113         bnx2x_cl22_read(bp, phy,
11114                         0x04,
11115                         &an_10_100_val);
11116
11117         bnx2x_cl22_read(bp, phy,
11118                         MDIO_PMA_REG_CTRL,
11119                         &autoneg_val);
11120
11121         /* Disable forced speed */
11122         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
11123         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
11124                            (1<<11));
11125
11126         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
11127              (phy->speed_cap_mask &
11128               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
11129             (phy->req_line_speed == SPEED_1000)) {
11130                 an_1000_val |= (1<<8);
11131                 autoneg_val |= (1<<9 | 1<<12);
11132                 if (phy->req_duplex == DUPLEX_FULL)
11133                         an_1000_val |= (1<<9);
11134                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
11135         } else
11136                 an_1000_val &= ~((1<<8) | (1<<9));
11137
11138         bnx2x_cl22_write(bp, phy,
11139                         0x09,
11140                         an_1000_val);
11141         bnx2x_cl22_read(bp, phy,
11142                         0x09,
11143                         &an_1000_val);
11144
11145         /* Advertise 10/100 link speed */
11146         if (phy->req_line_speed == SPEED_AUTO_NEG) {
11147                 if (phy->speed_cap_mask &
11148                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11149                         an_10_100_val |= (1<<5);
11150                         autoneg_val |= (1<<9 | 1<<12);
11151                         DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
11152                 }
11153                 if (phy->speed_cap_mask &
11154                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
11155                         an_10_100_val |= (1<<6);
11156                         autoneg_val |= (1<<9 | 1<<12);
11157                         DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
11158                 }
11159                 if (phy->speed_cap_mask &
11160                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
11161                         an_10_100_val |= (1<<7);
11162                         autoneg_val |= (1<<9 | 1<<12);
11163                         DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
11164                 }
11165                 if (phy->speed_cap_mask &
11166                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
11167                         an_10_100_val |= (1<<8);
11168                         autoneg_val |= (1<<9 | 1<<12);
11169                         DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
11170                 }
11171         }
11172
11173         /* Only 10/100 are allowed to work in FORCE mode */
11174         if (phy->req_line_speed == SPEED_100) {
11175                 autoneg_val |= (1<<13);
11176                 /* Enabled AUTO-MDIX when autoneg is disabled */
11177                 bnx2x_cl22_write(bp, phy,
11178                                 0x18,
11179                                 (1<<15 | 1<<9 | 7<<0));
11180                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
11181         }
11182         if (phy->req_line_speed == SPEED_10) {
11183                 /* Enabled AUTO-MDIX when autoneg is disabled */
11184                 bnx2x_cl22_write(bp, phy,
11185                                 0x18,
11186                                 (1<<15 | 1<<9 | 7<<0));
11187                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
11188         }
11189
11190         if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
11191                 int rc;
11192
11193                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
11194                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
11195                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
11196                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11197                 temp &= 0xfffe;
11198                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
11199
11200                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
11201                 if (rc) {
11202                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
11203                         bnx2x_eee_disable(phy, params, vars);
11204                 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
11205                            (phy->req_duplex == DUPLEX_FULL) &&
11206                            (bnx2x_eee_calc_timer(params) ||
11207                             !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
11208                         /* Need to advertise EEE only when requested,
11209                          * and either no LPI assertion was requested,
11210                          * or it was requested and a valid timer was set.
11211                          * Also notice full duplex is required for EEE.
11212                          */
11213                         bnx2x_eee_advertise(phy, params, vars,
11214                                             SHMEM_EEE_1G_ADV);
11215                 } else {
11216                         DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
11217                         bnx2x_eee_disable(phy, params, vars);
11218                 }
11219         } else {
11220                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
11221                                     SHMEM_EEE_SUPPORTED_SHIFT;
11222
11223                 if (phy->flags & FLAGS_EEE) {
11224                         /* Handle legacy auto-grEEEn */
11225                         if (params->feature_config_flags &
11226                             FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
11227                                 temp = 6;
11228                                 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
11229                         } else {
11230                                 temp = 0;
11231                                 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
11232                         }
11233                         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
11234                                          MDIO_AN_REG_EEE_ADV, temp);
11235                 }
11236         }
11237
11238         bnx2x_cl22_write(bp, phy,
11239                         0x04,
11240                         an_10_100_val | fc_val);
11241
11242         if (phy->req_duplex == DUPLEX_FULL)
11243                 autoneg_val |= (1<<8);
11244
11245         bnx2x_cl22_write(bp, phy,
11246                         MDIO_PMA_REG_CTRL, autoneg_val);
11247
11248         return 0;
11249 }
11250
11251
11252 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
11253                                        struct link_params *params, u8 mode)
11254 {
11255         struct bnx2x *bp = params->bp;
11256         u16 temp;
11257
11258         bnx2x_cl22_write(bp, phy,
11259                 MDIO_REG_GPHY_SHADOW,
11260                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
11261         bnx2x_cl22_read(bp, phy,
11262                 MDIO_REG_GPHY_SHADOW,
11263                 &temp);
11264         temp &= 0xff00;
11265
11266         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
11267         switch (mode) {
11268         case LED_MODE_FRONT_PANEL_OFF:
11269         case LED_MODE_OFF:
11270                 temp |= 0x00ee;
11271                 break;
11272         case LED_MODE_OPER:
11273                 temp |= 0x0001;
11274                 break;
11275         case LED_MODE_ON:
11276                 temp |= 0x00ff;
11277                 break;
11278         default:
11279                 break;
11280         }
11281         bnx2x_cl22_write(bp, phy,
11282                 MDIO_REG_GPHY_SHADOW,
11283                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11284         return;
11285 }
11286
11287
11288 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
11289                                      struct link_params *params)
11290 {
11291         struct bnx2x *bp = params->bp;
11292         u32 cfg_pin;
11293         u8 port;
11294
11295         /* In case of no EPIO routed to reset the GPHY, put it
11296          * in low power mode.
11297          */
11298         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
11299         /* This works with E3 only, no need to check the chip
11300          * before determining the port.
11301          */
11302         port = params->port;
11303         cfg_pin = (REG_RD(bp, params->shmem_base +
11304                         offsetof(struct shmem_region,
11305                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11306                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11307                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11308
11309         /* Drive pin low to put GPHY in reset. */
11310         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
11311 }
11312
11313 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
11314                                     struct link_params *params,
11315                                     struct link_vars *vars)
11316 {
11317         struct bnx2x *bp = params->bp;
11318         u16 val;
11319         u8 link_up = 0;
11320         u16 legacy_status, legacy_speed;
11321
11322         /* Get speed operation status */
11323         bnx2x_cl22_read(bp, phy,
11324                         MDIO_REG_GPHY_AUX_STATUS,
11325                         &legacy_status);
11326         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
11327
11328         /* Read status to clear the PHY interrupt. */
11329         bnx2x_cl22_read(bp, phy,
11330                         MDIO_REG_INTR_STATUS,
11331                         &val);
11332
11333         link_up = ((legacy_status & (1<<2)) == (1<<2));
11334
11335         if (link_up) {
11336                 legacy_speed = (legacy_status & (7<<8));
11337                 if (legacy_speed == (7<<8)) {
11338                         vars->line_speed = SPEED_1000;
11339                         vars->duplex = DUPLEX_FULL;
11340                 } else if (legacy_speed == (6<<8)) {
11341                         vars->line_speed = SPEED_1000;
11342                         vars->duplex = DUPLEX_HALF;
11343                 } else if (legacy_speed == (5<<8)) {
11344                         vars->line_speed = SPEED_100;
11345                         vars->duplex = DUPLEX_FULL;
11346                 }
11347                 /* Omitting 100Base-T4 for now */
11348                 else if (legacy_speed == (3<<8)) {
11349                         vars->line_speed = SPEED_100;
11350                         vars->duplex = DUPLEX_HALF;
11351                 } else if (legacy_speed == (2<<8)) {
11352                         vars->line_speed = SPEED_10;
11353                         vars->duplex = DUPLEX_FULL;
11354                 } else if (legacy_speed == (1<<8)) {
11355                         vars->line_speed = SPEED_10;
11356                         vars->duplex = DUPLEX_HALF;
11357                 } else /* Should not happen */
11358                         vars->line_speed = 0;
11359
11360                 DP(NETIF_MSG_LINK,
11361                    "Link is up in %dMbps, is_duplex_full= %d\n",
11362                    vars->line_speed,
11363                    (vars->duplex == DUPLEX_FULL));
11364
11365                 /* Check legacy speed AN resolution */
11366                 bnx2x_cl22_read(bp, phy,
11367                                 0x01,
11368                                 &val);
11369                 if (val & (1<<5))
11370                         vars->link_status |=
11371                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11372                 bnx2x_cl22_read(bp, phy,
11373                                 0x06,
11374                                 &val);
11375                 if ((val & (1<<0)) == 0)
11376                         vars->link_status |=
11377                                 LINK_STATUS_PARALLEL_DETECTION_USED;
11378
11379                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11380                            vars->line_speed);
11381
11382                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11383
11384                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11385                         /* Report LP advertised speeds */
11386                         bnx2x_cl22_read(bp, phy, 0x5, &val);
11387
11388                         if (val & (1<<5))
11389                                 vars->link_status |=
11390                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11391                         if (val & (1<<6))
11392                                 vars->link_status |=
11393                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11394                         if (val & (1<<7))
11395                                 vars->link_status |=
11396                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11397                         if (val & (1<<8))
11398                                 vars->link_status |=
11399                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11400                         if (val & (1<<9))
11401                                 vars->link_status |=
11402                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11403
11404                         bnx2x_cl22_read(bp, phy, 0xa, &val);
11405                         if (val & (1<<10))
11406                                 vars->link_status |=
11407                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11408                         if (val & (1<<11))
11409                                 vars->link_status |=
11410                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11411
11412                         if ((phy->flags & FLAGS_EEE) &&
11413                             bnx2x_eee_has_cap(params))
11414                                 bnx2x_eee_an_resolve(phy, params, vars);
11415                 }
11416         }
11417         return link_up;
11418 }
11419
11420 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11421                                           struct link_params *params)
11422 {
11423         struct bnx2x *bp = params->bp;
11424         u16 val;
11425         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11426
11427         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11428
11429         /* Enable master/slave manual mmode and set to master */
11430         /* mii write 9 [bits set 11 12] */
11431         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11432
11433         /* forced 1G and disable autoneg */
11434         /* set val [mii read 0] */
11435         /* set val [expr $val & [bits clear 6 12 13]] */
11436         /* set val [expr $val | [bits set 6 8]] */
11437         /* mii write 0 $val */
11438         bnx2x_cl22_read(bp, phy, 0x00, &val);
11439         val &= ~((1<<6) | (1<<12) | (1<<13));
11440         val |= (1<<6) | (1<<8);
11441         bnx2x_cl22_write(bp, phy, 0x00, val);
11442
11443         /* Set external loopback and Tx using 6dB coding */
11444         /* mii write 0x18 7 */
11445         /* set val [mii read 0x18] */
11446         /* mii write 0x18 [expr $val | [bits set 10 15]] */
11447         bnx2x_cl22_write(bp, phy, 0x18, 7);
11448         bnx2x_cl22_read(bp, phy, 0x18, &val);
11449         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11450
11451         /* This register opens the gate for the UMAC despite its name */
11452         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11453
11454         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11455          * length used by the MAC receive logic to check frames.
11456          */
11457         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11458 }
11459
11460 /******************************************************************/
11461 /*                      SFX7101 PHY SECTION                       */
11462 /******************************************************************/
11463 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11464                                        struct link_params *params)
11465 {
11466         struct bnx2x *bp = params->bp;
11467         /* SFX7101_XGXS_TEST1 */
11468         bnx2x_cl45_write(bp, phy,
11469                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11470 }
11471
11472 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11473                                   struct link_params *params,
11474                                   struct link_vars *vars)
11475 {
11476         u16 fw_ver1, fw_ver2, val;
11477         struct bnx2x *bp = params->bp;
11478         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11479
11480         /* Restore normal power mode*/
11481         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11482                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11483         /* HW reset */
11484         bnx2x_ext_phy_hw_reset(bp, params->port);
11485         bnx2x_wait_reset_complete(bp, phy, params);
11486
11487         bnx2x_cl45_write(bp, phy,
11488                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11489         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11490         bnx2x_cl45_write(bp, phy,
11491                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11492
11493         bnx2x_ext_phy_set_pause(params, phy, vars);
11494         /* Restart autoneg */
11495         bnx2x_cl45_read(bp, phy,
11496                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11497         val |= 0x200;
11498         bnx2x_cl45_write(bp, phy,
11499                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11500
11501         /* Save spirom version */
11502         bnx2x_cl45_read(bp, phy,
11503                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11504
11505         bnx2x_cl45_read(bp, phy,
11506                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11507         bnx2x_save_spirom_version(bp, params->port,
11508                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11509         return 0;
11510 }
11511
11512 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11513                                  struct link_params *params,
11514                                  struct link_vars *vars)
11515 {
11516         struct bnx2x *bp = params->bp;
11517         u8 link_up;
11518         u16 val1, val2;
11519         bnx2x_cl45_read(bp, phy,
11520                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11521         bnx2x_cl45_read(bp, phy,
11522                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11523         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11524                    val2, val1);
11525         bnx2x_cl45_read(bp, phy,
11526                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11527         bnx2x_cl45_read(bp, phy,
11528                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11529         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11530                    val2, val1);
11531         link_up = ((val1 & 4) == 4);
11532         /* If link is up print the AN outcome of the SFX7101 PHY */
11533         if (link_up) {
11534                 bnx2x_cl45_read(bp, phy,
11535                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11536                                 &val2);
11537                 vars->line_speed = SPEED_10000;
11538                 vars->duplex = DUPLEX_FULL;
11539                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11540                            val2, (val2 & (1<<14)));
11541                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11542                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11543
11544                 /* Read LP advertised speeds */
11545                 if (val2 & (1<<11))
11546                         vars->link_status |=
11547                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11548         }
11549         return link_up;
11550 }
11551
11552 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11553 {
11554         if (*len < 5)
11555                 return -EINVAL;
11556         str[0] = (spirom_ver & 0xFF);
11557         str[1] = (spirom_ver & 0xFF00) >> 8;
11558         str[2] = (spirom_ver & 0xFF0000) >> 16;
11559         str[3] = (spirom_ver & 0xFF000000) >> 24;
11560         str[4] = '\0';
11561         *len -= 5;
11562         return 0;
11563 }
11564
11565 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11566 {
11567         u16 val, cnt;
11568
11569         bnx2x_cl45_read(bp, phy,
11570                         MDIO_PMA_DEVAD,
11571                         MDIO_PMA_REG_7101_RESET, &val);
11572
11573         for (cnt = 0; cnt < 10; cnt++) {
11574                 msleep(50);
11575                 /* Writes a self-clearing reset */
11576                 bnx2x_cl45_write(bp, phy,
11577                                  MDIO_PMA_DEVAD,
11578                                  MDIO_PMA_REG_7101_RESET,
11579                                  (val | (1<<15)));
11580                 /* Wait for clear */
11581                 bnx2x_cl45_read(bp, phy,
11582                                 MDIO_PMA_DEVAD,
11583                                 MDIO_PMA_REG_7101_RESET, &val);
11584
11585                 if ((val & (1<<15)) == 0)
11586                         break;
11587         }
11588 }
11589
11590 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11591                                 struct link_params *params) {
11592         /* Low power mode is controlled by GPIO 2 */
11593         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11594                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11595         /* The PHY reset is controlled by GPIO 1 */
11596         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11597                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11598 }
11599
11600 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11601                                     struct link_params *params, u8 mode)
11602 {
11603         u16 val = 0;
11604         struct bnx2x *bp = params->bp;
11605         switch (mode) {
11606         case LED_MODE_FRONT_PANEL_OFF:
11607         case LED_MODE_OFF:
11608                 val = 2;
11609                 break;
11610         case LED_MODE_ON:
11611                 val = 1;
11612                 break;
11613         case LED_MODE_OPER:
11614                 val = 0;
11615                 break;
11616         }
11617         bnx2x_cl45_write(bp, phy,
11618                          MDIO_PMA_DEVAD,
11619                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11620                          val);
11621 }
11622
11623 /******************************************************************/
11624 /*                      STATIC PHY DECLARATION                    */
11625 /******************************************************************/
11626
11627 static const struct bnx2x_phy phy_null = {
11628         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11629         .addr           = 0,
11630         .def_md_devad   = 0,
11631         .flags          = FLAGS_INIT_XGXS_FIRST,
11632         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11633         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11634         .mdio_ctrl      = 0,
11635         .supported      = 0,
11636         .media_type     = ETH_PHY_NOT_PRESENT,
11637         .ver_addr       = 0,
11638         .req_flow_ctrl  = 0,
11639         .req_line_speed = 0,
11640         .speed_cap_mask = 0,
11641         .req_duplex     = 0,
11642         .rsrv           = 0,
11643         .config_init    = (config_init_t)NULL,
11644         .read_status    = (read_status_t)NULL,
11645         .link_reset     = (link_reset_t)NULL,
11646         .config_loopback = (config_loopback_t)NULL,
11647         .format_fw_ver  = (format_fw_ver_t)NULL,
11648         .hw_reset       = (hw_reset_t)NULL,
11649         .set_link_led   = (set_link_led_t)NULL,
11650         .phy_specific_func = (phy_specific_func_t)NULL
11651 };
11652
11653 static const struct bnx2x_phy phy_serdes = {
11654         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11655         .addr           = 0xff,
11656         .def_md_devad   = 0,
11657         .flags          = 0,
11658         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11659         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11660         .mdio_ctrl      = 0,
11661         .supported      = (SUPPORTED_10baseT_Half |
11662                            SUPPORTED_10baseT_Full |
11663                            SUPPORTED_100baseT_Half |
11664                            SUPPORTED_100baseT_Full |
11665                            SUPPORTED_1000baseT_Full |
11666                            SUPPORTED_2500baseX_Full |
11667                            SUPPORTED_TP |
11668                            SUPPORTED_Autoneg |
11669                            SUPPORTED_Pause |
11670                            SUPPORTED_Asym_Pause),
11671         .media_type     = ETH_PHY_BASE_T,
11672         .ver_addr       = 0,
11673         .req_flow_ctrl  = 0,
11674         .req_line_speed = 0,
11675         .speed_cap_mask = 0,
11676         .req_duplex     = 0,
11677         .rsrv           = 0,
11678         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11679         .read_status    = (read_status_t)bnx2x_link_settings_status,
11680         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11681         .config_loopback = (config_loopback_t)NULL,
11682         .format_fw_ver  = (format_fw_ver_t)NULL,
11683         .hw_reset       = (hw_reset_t)NULL,
11684         .set_link_led   = (set_link_led_t)NULL,
11685         .phy_specific_func = (phy_specific_func_t)NULL
11686 };
11687
11688 static const struct bnx2x_phy phy_xgxs = {
11689         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11690         .addr           = 0xff,
11691         .def_md_devad   = 0,
11692         .flags          = 0,
11693         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11694         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11695         .mdio_ctrl      = 0,
11696         .supported      = (SUPPORTED_10baseT_Half |
11697                            SUPPORTED_10baseT_Full |
11698                            SUPPORTED_100baseT_Half |
11699                            SUPPORTED_100baseT_Full |
11700                            SUPPORTED_1000baseT_Full |
11701                            SUPPORTED_2500baseX_Full |
11702                            SUPPORTED_10000baseT_Full |
11703                            SUPPORTED_FIBRE |
11704                            SUPPORTED_Autoneg |
11705                            SUPPORTED_Pause |
11706                            SUPPORTED_Asym_Pause),
11707         .media_type     = ETH_PHY_CX4,
11708         .ver_addr       = 0,
11709         .req_flow_ctrl  = 0,
11710         .req_line_speed = 0,
11711         .speed_cap_mask = 0,
11712         .req_duplex     = 0,
11713         .rsrv           = 0,
11714         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11715         .read_status    = (read_status_t)bnx2x_link_settings_status,
11716         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11717         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11718         .format_fw_ver  = (format_fw_ver_t)NULL,
11719         .hw_reset       = (hw_reset_t)NULL,
11720         .set_link_led   = (set_link_led_t)NULL,
11721         .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11722 };
11723 static const struct bnx2x_phy phy_warpcore = {
11724         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11725         .addr           = 0xff,
11726         .def_md_devad   = 0,
11727         .flags          = FLAGS_TX_ERROR_CHECK,
11728         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11729         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11730         .mdio_ctrl      = 0,
11731         .supported      = (SUPPORTED_10baseT_Half |
11732                            SUPPORTED_10baseT_Full |
11733                            SUPPORTED_100baseT_Half |
11734                            SUPPORTED_100baseT_Full |
11735                            SUPPORTED_1000baseT_Full |
11736                            SUPPORTED_1000baseKX_Full |
11737                            SUPPORTED_10000baseT_Full |
11738                            SUPPORTED_10000baseKR_Full |
11739                            SUPPORTED_20000baseKR2_Full |
11740                            SUPPORTED_20000baseMLD2_Full |
11741                            SUPPORTED_FIBRE |
11742                            SUPPORTED_Autoneg |
11743                            SUPPORTED_Pause |
11744                            SUPPORTED_Asym_Pause),
11745         .media_type     = ETH_PHY_UNSPECIFIED,
11746         .ver_addr       = 0,
11747         .req_flow_ctrl  = 0,
11748         .req_line_speed = 0,
11749         .speed_cap_mask = 0,
11750         /* req_duplex = */0,
11751         /* rsrv = */0,
11752         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11753         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11754         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11755         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11756         .format_fw_ver  = (format_fw_ver_t)NULL,
11757         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11758         .set_link_led   = (set_link_led_t)NULL,
11759         .phy_specific_func = (phy_specific_func_t)NULL
11760 };
11761
11762
11763 static const struct bnx2x_phy phy_7101 = {
11764         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11765         .addr           = 0xff,
11766         .def_md_devad   = 0,
11767         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11768         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11769         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11770         .mdio_ctrl      = 0,
11771         .supported      = (SUPPORTED_10000baseT_Full |
11772                            SUPPORTED_TP |
11773                            SUPPORTED_Autoneg |
11774                            SUPPORTED_Pause |
11775                            SUPPORTED_Asym_Pause),
11776         .media_type     = ETH_PHY_BASE_T,
11777         .ver_addr       = 0,
11778         .req_flow_ctrl  = 0,
11779         .req_line_speed = 0,
11780         .speed_cap_mask = 0,
11781         .req_duplex     = 0,
11782         .rsrv           = 0,
11783         .config_init    = (config_init_t)bnx2x_7101_config_init,
11784         .read_status    = (read_status_t)bnx2x_7101_read_status,
11785         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11786         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11787         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11788         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11789         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11790         .phy_specific_func = (phy_specific_func_t)NULL
11791 };
11792 static const struct bnx2x_phy phy_8073 = {
11793         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11794         .addr           = 0xff,
11795         .def_md_devad   = 0,
11796         .flags          = 0,
11797         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11798         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11799         .mdio_ctrl      = 0,
11800         .supported      = (SUPPORTED_10000baseT_Full |
11801                            SUPPORTED_2500baseX_Full |
11802                            SUPPORTED_1000baseT_Full |
11803                            SUPPORTED_FIBRE |
11804                            SUPPORTED_Autoneg |
11805                            SUPPORTED_Pause |
11806                            SUPPORTED_Asym_Pause),
11807         .media_type     = ETH_PHY_KR,
11808         .ver_addr       = 0,
11809         .req_flow_ctrl  = 0,
11810         .req_line_speed = 0,
11811         .speed_cap_mask = 0,
11812         .req_duplex     = 0,
11813         .rsrv           = 0,
11814         .config_init    = (config_init_t)bnx2x_8073_config_init,
11815         .read_status    = (read_status_t)bnx2x_8073_read_status,
11816         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11817         .config_loopback = (config_loopback_t)NULL,
11818         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11819         .hw_reset       = (hw_reset_t)NULL,
11820         .set_link_led   = (set_link_led_t)NULL,
11821         .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11822 };
11823 static const struct bnx2x_phy phy_8705 = {
11824         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11825         .addr           = 0xff,
11826         .def_md_devad   = 0,
11827         .flags          = FLAGS_INIT_XGXS_FIRST,
11828         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11829         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11830         .mdio_ctrl      = 0,
11831         .supported      = (SUPPORTED_10000baseT_Full |
11832                            SUPPORTED_FIBRE |
11833                            SUPPORTED_Pause |
11834                            SUPPORTED_Asym_Pause),
11835         .media_type     = ETH_PHY_XFP_FIBER,
11836         .ver_addr       = 0,
11837         .req_flow_ctrl  = 0,
11838         .req_line_speed = 0,
11839         .speed_cap_mask = 0,
11840         .req_duplex     = 0,
11841         .rsrv           = 0,
11842         .config_init    = (config_init_t)bnx2x_8705_config_init,
11843         .read_status    = (read_status_t)bnx2x_8705_read_status,
11844         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11845         .config_loopback = (config_loopback_t)NULL,
11846         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11847         .hw_reset       = (hw_reset_t)NULL,
11848         .set_link_led   = (set_link_led_t)NULL,
11849         .phy_specific_func = (phy_specific_func_t)NULL
11850 };
11851 static const struct bnx2x_phy phy_8706 = {
11852         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11853         .addr           = 0xff,
11854         .def_md_devad   = 0,
11855         .flags          = FLAGS_INIT_XGXS_FIRST,
11856         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11857         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11858         .mdio_ctrl      = 0,
11859         .supported      = (SUPPORTED_10000baseT_Full |
11860                            SUPPORTED_1000baseT_Full |
11861                            SUPPORTED_FIBRE |
11862                            SUPPORTED_Pause |
11863                            SUPPORTED_Asym_Pause),
11864         .media_type     = ETH_PHY_SFPP_10G_FIBER,
11865         .ver_addr       = 0,
11866         .req_flow_ctrl  = 0,
11867         .req_line_speed = 0,
11868         .speed_cap_mask = 0,
11869         .req_duplex     = 0,
11870         .rsrv           = 0,
11871         .config_init    = (config_init_t)bnx2x_8706_config_init,
11872         .read_status    = (read_status_t)bnx2x_8706_read_status,
11873         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11874         .config_loopback = (config_loopback_t)NULL,
11875         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11876         .hw_reset       = (hw_reset_t)NULL,
11877         .set_link_led   = (set_link_led_t)NULL,
11878         .phy_specific_func = (phy_specific_func_t)NULL
11879 };
11880
11881 static const struct bnx2x_phy phy_8726 = {
11882         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11883         .addr           = 0xff,
11884         .def_md_devad   = 0,
11885         .flags          = (FLAGS_INIT_XGXS_FIRST |
11886                            FLAGS_TX_ERROR_CHECK),
11887         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11888         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11889         .mdio_ctrl      = 0,
11890         .supported      = (SUPPORTED_10000baseT_Full |
11891                            SUPPORTED_1000baseT_Full |
11892                            SUPPORTED_Autoneg |
11893                            SUPPORTED_FIBRE |
11894                            SUPPORTED_Pause |
11895                            SUPPORTED_Asym_Pause),
11896         .media_type     = ETH_PHY_NOT_PRESENT,
11897         .ver_addr       = 0,
11898         .req_flow_ctrl  = 0,
11899         .req_line_speed = 0,
11900         .speed_cap_mask = 0,
11901         .req_duplex     = 0,
11902         .rsrv           = 0,
11903         .config_init    = (config_init_t)bnx2x_8726_config_init,
11904         .read_status    = (read_status_t)bnx2x_8726_read_status,
11905         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11906         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11907         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11908         .hw_reset       = (hw_reset_t)NULL,
11909         .set_link_led   = (set_link_led_t)NULL,
11910         .phy_specific_func = (phy_specific_func_t)NULL
11911 };
11912
11913 static const struct bnx2x_phy phy_8727 = {
11914         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11915         .addr           = 0xff,
11916         .def_md_devad   = 0,
11917         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11918                            FLAGS_TX_ERROR_CHECK),
11919         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11920         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11921         .mdio_ctrl      = 0,
11922         .supported      = (SUPPORTED_10000baseT_Full |
11923                            SUPPORTED_1000baseT_Full |
11924                            SUPPORTED_FIBRE |
11925                            SUPPORTED_Pause |
11926                            SUPPORTED_Asym_Pause),
11927         .media_type     = ETH_PHY_NOT_PRESENT,
11928         .ver_addr       = 0,
11929         .req_flow_ctrl  = 0,
11930         .req_line_speed = 0,
11931         .speed_cap_mask = 0,
11932         .req_duplex     = 0,
11933         .rsrv           = 0,
11934         .config_init    = (config_init_t)bnx2x_8727_config_init,
11935         .read_status    = (read_status_t)bnx2x_8727_read_status,
11936         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11937         .config_loopback = (config_loopback_t)NULL,
11938         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11939         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11940         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11941         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11942 };
11943 static const struct bnx2x_phy phy_8481 = {
11944         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11945         .addr           = 0xff,
11946         .def_md_devad   = 0,
11947         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11948                           FLAGS_REARM_LATCH_SIGNAL,
11949         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11950         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11951         .mdio_ctrl      = 0,
11952         .supported      = (SUPPORTED_10baseT_Half |
11953                            SUPPORTED_10baseT_Full |
11954                            SUPPORTED_100baseT_Half |
11955                            SUPPORTED_100baseT_Full |
11956                            SUPPORTED_1000baseT_Full |
11957                            SUPPORTED_10000baseT_Full |
11958                            SUPPORTED_TP |
11959                            SUPPORTED_Autoneg |
11960                            SUPPORTED_Pause |
11961                            SUPPORTED_Asym_Pause),
11962         .media_type     = ETH_PHY_BASE_T,
11963         .ver_addr       = 0,
11964         .req_flow_ctrl  = 0,
11965         .req_line_speed = 0,
11966         .speed_cap_mask = 0,
11967         .req_duplex     = 0,
11968         .rsrv           = 0,
11969         .config_init    = (config_init_t)bnx2x_8481_config_init,
11970         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11971         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11972         .config_loopback = (config_loopback_t)NULL,
11973         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11974         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11975         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11976         .phy_specific_func = (phy_specific_func_t)NULL
11977 };
11978
11979 static const struct bnx2x_phy phy_84823 = {
11980         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11981         .addr           = 0xff,
11982         .def_md_devad   = 0,
11983         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11984                            FLAGS_REARM_LATCH_SIGNAL |
11985                            FLAGS_TX_ERROR_CHECK),
11986         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11987         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11988         .mdio_ctrl      = 0,
11989         .supported      = (SUPPORTED_10baseT_Half |
11990                            SUPPORTED_10baseT_Full |
11991                            SUPPORTED_100baseT_Half |
11992                            SUPPORTED_100baseT_Full |
11993                            SUPPORTED_1000baseT_Full |
11994                            SUPPORTED_10000baseT_Full |
11995                            SUPPORTED_TP |
11996                            SUPPORTED_Autoneg |
11997                            SUPPORTED_Pause |
11998                            SUPPORTED_Asym_Pause),
11999         .media_type     = ETH_PHY_BASE_T,
12000         .ver_addr       = 0,
12001         .req_flow_ctrl  = 0,
12002         .req_line_speed = 0,
12003         .speed_cap_mask = 0,
12004         .req_duplex     = 0,
12005         .rsrv           = 0,
12006         .config_init    = (config_init_t)bnx2x_848x3_config_init,
12007         .read_status    = (read_status_t)bnx2x_848xx_read_status,
12008         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
12009         .config_loopback = (config_loopback_t)NULL,
12010         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
12011         .hw_reset       = (hw_reset_t)NULL,
12012         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
12013         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12014 };
12015
12016 static const struct bnx2x_phy phy_84833 = {
12017         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
12018         .addr           = 0xff,
12019         .def_md_devad   = 0,
12020         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
12021                            FLAGS_REARM_LATCH_SIGNAL |
12022                            FLAGS_TX_ERROR_CHECK),
12023         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12024         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12025         .mdio_ctrl      = 0,
12026         .supported      = (SUPPORTED_100baseT_Half |
12027                            SUPPORTED_100baseT_Full |
12028                            SUPPORTED_1000baseT_Full |
12029                            SUPPORTED_10000baseT_Full |
12030                            SUPPORTED_TP |
12031                            SUPPORTED_Autoneg |
12032                            SUPPORTED_Pause |
12033                            SUPPORTED_Asym_Pause),
12034         .media_type     = ETH_PHY_BASE_T,
12035         .ver_addr       = 0,
12036         .req_flow_ctrl  = 0,
12037         .req_line_speed = 0,
12038         .speed_cap_mask = 0,
12039         .req_duplex     = 0,
12040         .rsrv           = 0,
12041         .config_init    = (config_init_t)bnx2x_848x3_config_init,
12042         .read_status    = (read_status_t)bnx2x_848xx_read_status,
12043         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
12044         .config_loopback = (config_loopback_t)NULL,
12045         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
12046         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
12047         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
12048         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12049 };
12050
12051 static const struct bnx2x_phy phy_84834 = {
12052         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
12053         .addr           = 0xff,
12054         .def_md_devad   = 0,
12055         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
12056                             FLAGS_REARM_LATCH_SIGNAL,
12057         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12058         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12059         .mdio_ctrl      = 0,
12060         .supported      = (SUPPORTED_100baseT_Half |
12061                            SUPPORTED_100baseT_Full |
12062                            SUPPORTED_1000baseT_Full |
12063                            SUPPORTED_10000baseT_Full |
12064                            SUPPORTED_TP |
12065                            SUPPORTED_Autoneg |
12066                            SUPPORTED_Pause |
12067                            SUPPORTED_Asym_Pause),
12068         .media_type     = ETH_PHY_BASE_T,
12069         .ver_addr       = 0,
12070         .req_flow_ctrl  = 0,
12071         .req_line_speed = 0,
12072         .speed_cap_mask = 0,
12073         .req_duplex     = 0,
12074         .rsrv           = 0,
12075         .config_init    = (config_init_t)bnx2x_848x3_config_init,
12076         .read_status    = (read_status_t)bnx2x_848xx_read_status,
12077         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
12078         .config_loopback = (config_loopback_t)NULL,
12079         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
12080         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
12081         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
12082         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12083 };
12084
12085 static const struct bnx2x_phy phy_84858 = {
12086         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858,
12087         .addr           = 0xff,
12088         .def_md_devad   = 0,
12089         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
12090                             FLAGS_REARM_LATCH_SIGNAL,
12091         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12092         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12093         .mdio_ctrl      = 0,
12094         .supported      = (SUPPORTED_100baseT_Half |
12095                            SUPPORTED_100baseT_Full |
12096                            SUPPORTED_1000baseT_Full |
12097                            SUPPORTED_10000baseT_Full |
12098                            SUPPORTED_TP |
12099                            SUPPORTED_Autoneg |
12100                            SUPPORTED_Pause |
12101                            SUPPORTED_Asym_Pause),
12102         .media_type     = ETH_PHY_BASE_T,
12103         .ver_addr       = 0,
12104         .req_flow_ctrl  = 0,
12105         .req_line_speed = 0,
12106         .speed_cap_mask = 0,
12107         .req_duplex     = 0,
12108         .rsrv           = 0,
12109         .config_init    = (config_init_t)bnx2x_848x3_config_init,
12110         .read_status    = (read_status_t)bnx2x_848xx_read_status,
12111         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
12112         .config_loopback = (config_loopback_t)NULL,
12113         .format_fw_ver  = (format_fw_ver_t)bnx2x_8485x_format_ver,
12114         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
12115         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
12116         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12117 };
12118
12119 static const struct bnx2x_phy phy_54618se = {
12120         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
12121         .addr           = 0xff,
12122         .def_md_devad   = 0,
12123         .flags          = FLAGS_INIT_XGXS_FIRST,
12124         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12125         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12126         .mdio_ctrl      = 0,
12127         .supported      = (SUPPORTED_10baseT_Half |
12128                            SUPPORTED_10baseT_Full |
12129                            SUPPORTED_100baseT_Half |
12130                            SUPPORTED_100baseT_Full |
12131                            SUPPORTED_1000baseT_Full |
12132                            SUPPORTED_TP |
12133                            SUPPORTED_Autoneg |
12134                            SUPPORTED_Pause |
12135                            SUPPORTED_Asym_Pause),
12136         .media_type     = ETH_PHY_BASE_T,
12137         .ver_addr       = 0,
12138         .req_flow_ctrl  = 0,
12139         .req_line_speed = 0,
12140         .speed_cap_mask = 0,
12141         /* req_duplex = */0,
12142         /* rsrv = */0,
12143         .config_init    = (config_init_t)bnx2x_54618se_config_init,
12144         .read_status    = (read_status_t)bnx2x_54618se_read_status,
12145         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
12146         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
12147         .format_fw_ver  = (format_fw_ver_t)NULL,
12148         .hw_reset       = (hw_reset_t)NULL,
12149         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
12150         .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
12151 };
12152 /*****************************************************************/
12153 /*                                                               */
12154 /* Populate the phy according. Main function: bnx2x_populate_phy   */
12155 /*                                                               */
12156 /*****************************************************************/
12157
12158 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
12159                                      struct bnx2x_phy *phy, u8 port,
12160                                      u8 phy_index)
12161 {
12162         /* Get the 4 lanes xgxs config rx and tx */
12163         u32 rx = 0, tx = 0, i;
12164         for (i = 0; i < 2; i++) {
12165                 /* INT_PHY and EXT_PHY1 share the same value location in
12166                  * the shmem. When num_phys is greater than 1, than this value
12167                  * applies only to EXT_PHY1
12168                  */
12169                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
12170                         rx = REG_RD(bp, shmem_base +
12171                                     offsetof(struct shmem_region,
12172                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
12173
12174                         tx = REG_RD(bp, shmem_base +
12175                                     offsetof(struct shmem_region,
12176                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
12177                 } else {
12178                         rx = REG_RD(bp, shmem_base +
12179                                     offsetof(struct shmem_region,
12180                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12181
12182                         tx = REG_RD(bp, shmem_base +
12183                                     offsetof(struct shmem_region,
12184                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12185                 }
12186
12187                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
12188                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
12189
12190                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
12191                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
12192         }
12193 }
12194
12195 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
12196                                     u8 phy_index, u8 port)
12197 {
12198         u32 ext_phy_config = 0;
12199         switch (phy_index) {
12200         case EXT_PHY1:
12201                 ext_phy_config = REG_RD(bp, shmem_base +
12202                                               offsetof(struct shmem_region,
12203                         dev_info.port_hw_config[port].external_phy_config));
12204                 break;
12205         case EXT_PHY2:
12206                 ext_phy_config = REG_RD(bp, shmem_base +
12207                                               offsetof(struct shmem_region,
12208                         dev_info.port_hw_config[port].external_phy_config2));
12209                 break;
12210         default:
12211                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
12212                 return -EINVAL;
12213         }
12214
12215         return ext_phy_config;
12216 }
12217 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
12218                                   struct bnx2x_phy *phy)
12219 {
12220         u32 phy_addr;
12221         u32 chip_id;
12222         u32 switch_cfg = (REG_RD(bp, shmem_base +
12223                                        offsetof(struct shmem_region,
12224                         dev_info.port_feature_config[port].link_config)) &
12225                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
12226         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
12227                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
12228
12229         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
12230         if (USES_WARPCORE(bp)) {
12231                 u32 serdes_net_if;
12232                 phy_addr = REG_RD(bp,
12233                                   MISC_REG_WC0_CTRL_PHY_ADDR);
12234                 *phy = phy_warpcore;
12235                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
12236                         phy->flags |= FLAGS_4_PORT_MODE;
12237                 else
12238                         phy->flags &= ~FLAGS_4_PORT_MODE;
12239                         /* Check Dual mode */
12240                 serdes_net_if = (REG_RD(bp, shmem_base +
12241                                         offsetof(struct shmem_region, dev_info.
12242                                         port_hw_config[port].default_cfg)) &
12243                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
12244                 /* Set the appropriate supported and flags indications per
12245                  * interface type of the chip
12246                  */
12247                 switch (serdes_net_if) {
12248                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
12249                         phy->supported &= (SUPPORTED_10baseT_Half |
12250                                            SUPPORTED_10baseT_Full |
12251                                            SUPPORTED_100baseT_Half |
12252                                            SUPPORTED_100baseT_Full |
12253                                            SUPPORTED_1000baseT_Full |
12254                                            SUPPORTED_FIBRE |
12255                                            SUPPORTED_Autoneg |
12256                                            SUPPORTED_Pause |
12257                                            SUPPORTED_Asym_Pause);
12258                         phy->media_type = ETH_PHY_BASE_T;
12259                         break;
12260                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
12261                         phy->supported &= (SUPPORTED_1000baseT_Full |
12262                                            SUPPORTED_10000baseT_Full |
12263                                            SUPPORTED_FIBRE |
12264                                            SUPPORTED_Pause |
12265                                            SUPPORTED_Asym_Pause);
12266                         phy->media_type = ETH_PHY_XFP_FIBER;
12267                         break;
12268                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
12269                         phy->supported &= (SUPPORTED_1000baseT_Full |
12270                                            SUPPORTED_10000baseT_Full |
12271                                            SUPPORTED_FIBRE |
12272                                            SUPPORTED_Pause |
12273                                            SUPPORTED_Asym_Pause);
12274                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
12275                         break;
12276                 case PORT_HW_CFG_NET_SERDES_IF_KR:
12277                         phy->media_type = ETH_PHY_KR;
12278                         phy->supported &= (SUPPORTED_1000baseKX_Full |
12279                                            SUPPORTED_10000baseKR_Full |
12280                                            SUPPORTED_FIBRE |
12281                                            SUPPORTED_Autoneg |
12282                                            SUPPORTED_Pause |
12283                                            SUPPORTED_Asym_Pause);
12284                         break;
12285                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
12286                         phy->media_type = ETH_PHY_KR;
12287                         phy->flags |= FLAGS_WC_DUAL_MODE;
12288                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
12289                                            SUPPORTED_FIBRE |
12290                                            SUPPORTED_Pause |
12291                                            SUPPORTED_Asym_Pause);
12292                         break;
12293                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
12294                         phy->media_type = ETH_PHY_KR;
12295                         phy->flags |= FLAGS_WC_DUAL_MODE;
12296                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
12297                                            SUPPORTED_10000baseKR_Full |
12298                                            SUPPORTED_1000baseKX_Full |
12299                                            SUPPORTED_Autoneg |
12300                                            SUPPORTED_FIBRE |
12301                                            SUPPORTED_Pause |
12302                                            SUPPORTED_Asym_Pause);
12303                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12304                         break;
12305                 default:
12306                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
12307                                        serdes_net_if);
12308                         break;
12309                 }
12310
12311                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
12312                  * was not set as expected. For B0, ECO will be enabled so there
12313                  * won't be an issue there
12314                  */
12315                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12316                         phy->flags |= FLAGS_MDC_MDIO_WA;
12317                 else
12318                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
12319         } else {
12320                 switch (switch_cfg) {
12321                 case SWITCH_CFG_1G:
12322                         phy_addr = REG_RD(bp,
12323                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
12324                                           port * 0x10);
12325                         *phy = phy_serdes;
12326                         break;
12327                 case SWITCH_CFG_10G:
12328                         phy_addr = REG_RD(bp,
12329                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
12330                                           port * 0x18);
12331                         *phy = phy_xgxs;
12332                         break;
12333                 default:
12334                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
12335                         return -EINVAL;
12336                 }
12337         }
12338         phy->addr = (u8)phy_addr;
12339         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
12340                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
12341                                             port);
12342         if (CHIP_IS_E2(bp))
12343                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
12344         else
12345                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
12346
12347         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12348                    port, phy->addr, phy->mdio_ctrl);
12349
12350         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
12351         return 0;
12352 }
12353
12354 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
12355                                   u8 phy_index,
12356                                   u32 shmem_base,
12357                                   u32 shmem2_base,
12358                                   u8 port,
12359                                   struct bnx2x_phy *phy)
12360 {
12361         u32 ext_phy_config, phy_type, config2;
12362         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12363         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
12364                                                   phy_index, port);
12365         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12366         /* Select the phy type */
12367         switch (phy_type) {
12368         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12369                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12370                 *phy = phy_8073;
12371                 break;
12372         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12373                 *phy = phy_8705;
12374                 break;
12375         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12376                 *phy = phy_8706;
12377                 break;
12378         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12379                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12380                 *phy = phy_8726;
12381                 break;
12382         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12383                 /* BCM8727_NOC => BCM8727 no over current */
12384                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12385                 *phy = phy_8727;
12386                 phy->flags |= FLAGS_NOC;
12387                 break;
12388         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12389         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12390                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12391                 *phy = phy_8727;
12392                 break;
12393         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12394                 *phy = phy_8481;
12395                 break;
12396         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12397                 *phy = phy_84823;
12398                 break;
12399         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12400                 *phy = phy_84833;
12401                 break;
12402         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12403                 *phy = phy_84834;
12404                 break;
12405         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
12406                 *phy = phy_84858;
12407                 break;
12408         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12409         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12410                 *phy = phy_54618se;
12411                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12412                         phy->flags |= FLAGS_EEE;
12413                 break;
12414         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12415                 *phy = phy_7101;
12416                 break;
12417         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12418                 *phy = phy_null;
12419                 return -EINVAL;
12420         default:
12421                 *phy = phy_null;
12422                 /* In case external PHY wasn't found */
12423                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12424                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12425                         return -EINVAL;
12426                 return 0;
12427         }
12428
12429         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12430         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12431
12432         /* The shmem address of the phy version is located on different
12433          * structures. In case this structure is too old, do not set
12434          * the address
12435          */
12436         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12437                                         dev_info.shared_hw_config.config2));
12438         if (phy_index == EXT_PHY1) {
12439                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12440                                 port_mb[port].ext_phy_fw_version);
12441
12442                 /* Check specific mdc mdio settings */
12443                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12444                         mdc_mdio_access = config2 &
12445                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12446         } else {
12447                 u32 size = REG_RD(bp, shmem2_base);
12448
12449                 if (size >
12450                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12451                         phy->ver_addr = shmem2_base +
12452                             offsetof(struct shmem2_region,
12453                                      ext_phy_fw_version2[port]);
12454                 }
12455                 /* Check specific mdc mdio settings */
12456                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12457                         mdc_mdio_access = (config2 &
12458                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12459                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12460                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12461         }
12462         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12463
12464         if (bnx2x_is_8483x_8485x(phy) && (phy->ver_addr)) {
12465                 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12466                  * version lower than or equal to 1.39
12467                  */
12468                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12469                 if (((raw_ver & 0x7F) <= 39) &&
12470                     (((raw_ver & 0xF80) >> 7) <= 1))
12471                         phy->supported &= ~(SUPPORTED_100baseT_Half |
12472                                             SUPPORTED_100baseT_Full);
12473         }
12474
12475         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12476                    phy_type, port, phy_index);
12477         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
12478                    phy->addr, phy->mdio_ctrl);
12479         return 0;
12480 }
12481
12482 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12483                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12484 {
12485         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12486         if (phy_index == INT_PHY)
12487                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12488
12489         return bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12490                                         port, phy);
12491 }
12492
12493 static void bnx2x_phy_def_cfg(struct link_params *params,
12494                               struct bnx2x_phy *phy,
12495                               u8 phy_index)
12496 {
12497         struct bnx2x *bp = params->bp;
12498         u32 link_config;
12499         /* Populate the default phy configuration for MF mode */
12500         if (phy_index == EXT_PHY2) {
12501                 link_config = REG_RD(bp, params->shmem_base +
12502                                      offsetof(struct shmem_region, dev_info.
12503                         port_feature_config[params->port].link_config2));
12504                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12505                                              offsetof(struct shmem_region,
12506                                                       dev_info.
12507                         port_hw_config[params->port].speed_capability_mask2));
12508         } else {
12509                 link_config = REG_RD(bp, params->shmem_base +
12510                                      offsetof(struct shmem_region, dev_info.
12511                                 port_feature_config[params->port].link_config));
12512                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12513                                              offsetof(struct shmem_region,
12514                                                       dev_info.
12515                         port_hw_config[params->port].speed_capability_mask));
12516         }
12517         DP(NETIF_MSG_LINK,
12518            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12519            phy_index, link_config, phy->speed_cap_mask);
12520
12521         phy->req_duplex = DUPLEX_FULL;
12522         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
12523         case PORT_FEATURE_LINK_SPEED_10M_HALF:
12524                 phy->req_duplex = DUPLEX_HALF;
12525                 /* fall through */
12526         case PORT_FEATURE_LINK_SPEED_10M_FULL:
12527                 phy->req_line_speed = SPEED_10;
12528                 break;
12529         case PORT_FEATURE_LINK_SPEED_100M_HALF:
12530                 phy->req_duplex = DUPLEX_HALF;
12531                 /* fall through */
12532         case PORT_FEATURE_LINK_SPEED_100M_FULL:
12533                 phy->req_line_speed = SPEED_100;
12534                 break;
12535         case PORT_FEATURE_LINK_SPEED_1G:
12536                 phy->req_line_speed = SPEED_1000;
12537                 break;
12538         case PORT_FEATURE_LINK_SPEED_2_5G:
12539                 phy->req_line_speed = SPEED_2500;
12540                 break;
12541         case PORT_FEATURE_LINK_SPEED_10G_CX4:
12542                 phy->req_line_speed = SPEED_10000;
12543                 break;
12544         default:
12545                 phy->req_line_speed = SPEED_AUTO_NEG;
12546                 break;
12547         }
12548
12549         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
12550         case PORT_FEATURE_FLOW_CONTROL_AUTO:
12551                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12552                 break;
12553         case PORT_FEATURE_FLOW_CONTROL_TX:
12554                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12555                 break;
12556         case PORT_FEATURE_FLOW_CONTROL_RX:
12557                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12558                 break;
12559         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12560                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12561                 break;
12562         default:
12563                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12564                 break;
12565         }
12566 }
12567
12568 u32 bnx2x_phy_selection(struct link_params *params)
12569 {
12570         u32 phy_config_swapped, prio_cfg;
12571         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12572
12573         phy_config_swapped = params->multi_phy_config &
12574                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12575
12576         prio_cfg = params->multi_phy_config &
12577                         PORT_HW_CFG_PHY_SELECTION_MASK;
12578
12579         if (phy_config_swapped) {
12580                 switch (prio_cfg) {
12581                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12582                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12583                      break;
12584                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12585                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12586                      break;
12587                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12588                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12589                      break;
12590                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12591                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12592                      break;
12593                 }
12594         } else
12595                 return_cfg = prio_cfg;
12596
12597         return return_cfg;
12598 }
12599
12600 int bnx2x_phy_probe(struct link_params *params)
12601 {
12602         u8 phy_index, actual_phy_idx;
12603         u32 phy_config_swapped, sync_offset, media_types;
12604         struct bnx2x *bp = params->bp;
12605         struct bnx2x_phy *phy;
12606         params->num_phys = 0;
12607         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12608         phy_config_swapped = params->multi_phy_config &
12609                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12610
12611         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12612               phy_index++) {
12613                 actual_phy_idx = phy_index;
12614                 if (phy_config_swapped) {
12615                         if (phy_index == EXT_PHY1)
12616                                 actual_phy_idx = EXT_PHY2;
12617                         else if (phy_index == EXT_PHY2)
12618                                 actual_phy_idx = EXT_PHY1;
12619                 }
12620                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12621                                " actual_phy_idx %x\n", phy_config_swapped,
12622                            phy_index, actual_phy_idx);
12623                 phy = &params->phy[actual_phy_idx];
12624                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12625                                        params->shmem2_base, params->port,
12626                                        phy) != 0) {
12627                         params->num_phys = 0;
12628                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12629                                    phy_index);
12630                         for (phy_index = INT_PHY;
12631                               phy_index < MAX_PHYS;
12632                               phy_index++)
12633                                 *phy = phy_null;
12634                         return -EINVAL;
12635                 }
12636                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12637                         break;
12638
12639                 if (params->feature_config_flags &
12640                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12641                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12642
12643                 if (!(params->feature_config_flags &
12644                       FEATURE_CONFIG_MT_SUPPORT))
12645                         phy->flags |= FLAGS_MDC_MDIO_WA_G;
12646
12647                 sync_offset = params->shmem_base +
12648                         offsetof(struct shmem_region,
12649                         dev_info.port_hw_config[params->port].media_type);
12650                 media_types = REG_RD(bp, sync_offset);
12651
12652                 /* Update media type for non-PMF sync only for the first time
12653                  * In case the media type changes afterwards, it will be updated
12654                  * using the update_status function
12655                  */
12656                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12657                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12658                                      actual_phy_idx))) == 0) {
12659                         media_types |= ((phy->media_type &
12660                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12661                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12662                                  actual_phy_idx));
12663                 }
12664                 REG_WR(bp, sync_offset, media_types);
12665
12666                 bnx2x_phy_def_cfg(params, phy, phy_index);
12667                 params->num_phys++;
12668         }
12669
12670         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12671         return 0;
12672 }
12673
12674 static void bnx2x_init_bmac_loopback(struct link_params *params,
12675                                      struct link_vars *vars)
12676 {
12677         struct bnx2x *bp = params->bp;
12678                 vars->link_up = 1;
12679                 vars->line_speed = SPEED_10000;
12680                 vars->duplex = DUPLEX_FULL;
12681                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12682                 vars->mac_type = MAC_TYPE_BMAC;
12683
12684                 vars->phy_flags = PHY_XGXS_FLAG;
12685
12686                 bnx2x_xgxs_deassert(params);
12687
12688                 /* Set bmac loopback */
12689                 bnx2x_bmac_enable(params, vars, 1, 1);
12690
12691                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12692 }
12693
12694 static void bnx2x_init_emac_loopback(struct link_params *params,
12695                                      struct link_vars *vars)
12696 {
12697         struct bnx2x *bp = params->bp;
12698                 vars->link_up = 1;
12699                 vars->line_speed = SPEED_1000;
12700                 vars->duplex = DUPLEX_FULL;
12701                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12702                 vars->mac_type = MAC_TYPE_EMAC;
12703
12704                 vars->phy_flags = PHY_XGXS_FLAG;
12705
12706                 bnx2x_xgxs_deassert(params);
12707                 /* Set bmac loopback */
12708                 bnx2x_emac_enable(params, vars, 1);
12709                 bnx2x_emac_program(params, vars);
12710                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12711 }
12712
12713 static void bnx2x_init_xmac_loopback(struct link_params *params,
12714                                      struct link_vars *vars)
12715 {
12716         struct bnx2x *bp = params->bp;
12717         vars->link_up = 1;
12718         if (!params->req_line_speed[0])
12719                 vars->line_speed = SPEED_10000;
12720         else
12721                 vars->line_speed = params->req_line_speed[0];
12722         vars->duplex = DUPLEX_FULL;
12723         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12724         vars->mac_type = MAC_TYPE_XMAC;
12725         vars->phy_flags = PHY_XGXS_FLAG;
12726         /* Set WC to loopback mode since link is required to provide clock
12727          * to the XMAC in 20G mode
12728          */
12729         bnx2x_set_aer_mmd(params, &params->phy[0]);
12730         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12731         params->phy[INT_PHY].config_loopback(
12732                         &params->phy[INT_PHY],
12733                         params);
12734
12735         bnx2x_xmac_enable(params, vars, 1);
12736         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12737 }
12738
12739 static void bnx2x_init_umac_loopback(struct link_params *params,
12740                                      struct link_vars *vars)
12741 {
12742         struct bnx2x *bp = params->bp;
12743         vars->link_up = 1;
12744         vars->line_speed = SPEED_1000;
12745         vars->duplex = DUPLEX_FULL;
12746         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12747         vars->mac_type = MAC_TYPE_UMAC;
12748         vars->phy_flags = PHY_XGXS_FLAG;
12749         bnx2x_umac_enable(params, vars, 1);
12750
12751         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12752 }
12753
12754 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12755                                      struct link_vars *vars)
12756 {
12757         struct bnx2x *bp = params->bp;
12758         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
12759         vars->link_up = 1;
12760         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12761         vars->duplex = DUPLEX_FULL;
12762         if (params->req_line_speed[0] == SPEED_1000)
12763                 vars->line_speed = SPEED_1000;
12764         else if ((params->req_line_speed[0] == SPEED_20000) ||
12765                  (int_phy->flags & FLAGS_WC_DUAL_MODE))
12766                 vars->line_speed = SPEED_20000;
12767         else
12768                 vars->line_speed = SPEED_10000;
12769
12770         if (!USES_WARPCORE(bp))
12771                 bnx2x_xgxs_deassert(params);
12772         bnx2x_link_initialize(params, vars);
12773
12774         if (params->req_line_speed[0] == SPEED_1000) {
12775                 if (USES_WARPCORE(bp))
12776                         bnx2x_umac_enable(params, vars, 0);
12777                 else {
12778                         bnx2x_emac_program(params, vars);
12779                         bnx2x_emac_enable(params, vars, 0);
12780                 }
12781         } else {
12782                 if (USES_WARPCORE(bp))
12783                         bnx2x_xmac_enable(params, vars, 0);
12784                 else
12785                         bnx2x_bmac_enable(params, vars, 0, 1);
12786         }
12787
12788         if (params->loopback_mode == LOOPBACK_XGXS) {
12789                 /* Set 10G XGXS loopback */
12790                 int_phy->config_loopback(int_phy, params);
12791         } else {
12792                 /* Set external phy loopback */
12793                 u8 phy_index;
12794                 for (phy_index = EXT_PHY1;
12795                       phy_index < params->num_phys; phy_index++)
12796                         if (params->phy[phy_index].config_loopback)
12797                                 params->phy[phy_index].config_loopback(
12798                                         &params->phy[phy_index],
12799                                         params);
12800         }
12801         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12802
12803         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12804 }
12805
12806 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12807 {
12808         struct bnx2x *bp = params->bp;
12809         u8 val = en * 0x1F;
12810
12811         /* Open / close the gate between the NIG and the BRB */
12812         if (!CHIP_IS_E1x(bp))
12813                 val |= en * 0x20;
12814         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12815
12816         if (!CHIP_IS_E1(bp)) {
12817                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12818                        en*0x3);
12819         }
12820
12821         REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12822                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
12823 }
12824 static int bnx2x_avoid_link_flap(struct link_params *params,
12825                                             struct link_vars *vars)
12826 {
12827         u32 phy_idx;
12828         u32 dont_clear_stat, lfa_sts;
12829         struct bnx2x *bp = params->bp;
12830
12831         bnx2x_set_mdio_emac_per_phy(bp, params);
12832         /* Sync the link parameters */
12833         bnx2x_link_status_update(params, vars);
12834
12835         /*
12836          * The module verification was already done by previous link owner,
12837          * so this call is meant only to get warning message
12838          */
12839
12840         for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12841                 struct bnx2x_phy *phy = &params->phy[phy_idx];
12842                 if (phy->phy_specific_func) {
12843                         DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12844                         phy->phy_specific_func(phy, params, PHY_INIT);
12845                 }
12846                 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12847                     (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12848                     (phy->media_type == ETH_PHY_DA_TWINAX))
12849                         bnx2x_verify_sfp_module(phy, params);
12850         }
12851         lfa_sts = REG_RD(bp, params->lfa_base +
12852                          offsetof(struct shmem_lfa,
12853                                   lfa_sts));
12854
12855         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12856
12857         /* Re-enable the NIG/MAC */
12858         if (CHIP_IS_E3(bp)) {
12859                 if (!dont_clear_stat) {
12860                         REG_WR(bp, GRCBASE_MISC +
12861                                MISC_REGISTERS_RESET_REG_2_CLEAR,
12862                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12863                                 params->port));
12864                         REG_WR(bp, GRCBASE_MISC +
12865                                MISC_REGISTERS_RESET_REG_2_SET,
12866                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12867                                 params->port));
12868                 }
12869                 if (vars->line_speed < SPEED_10000)
12870                         bnx2x_umac_enable(params, vars, 0);
12871                 else
12872                         bnx2x_xmac_enable(params, vars, 0);
12873         } else {
12874                 if (vars->line_speed < SPEED_10000)
12875                         bnx2x_emac_enable(params, vars, 0);
12876                 else
12877                         bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12878         }
12879
12880         /* Increment LFA count */
12881         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12882                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12883                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12884                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12885         /* Clear link flap reason */
12886         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12887
12888         REG_WR(bp, params->lfa_base +
12889                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12890
12891         /* Disable NIG DRAIN */
12892         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12893
12894         /* Enable interrupts */
12895         bnx2x_link_int_enable(params);
12896         return 0;
12897 }
12898
12899 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12900                                          struct link_vars *vars,
12901                                          int lfa_status)
12902 {
12903         u32 lfa_sts, cfg_idx, tmp_val;
12904         struct bnx2x *bp = params->bp;
12905
12906         bnx2x_link_reset(params, vars, 1);
12907
12908         if (!params->lfa_base)
12909                 return;
12910         /* Store the new link parameters */
12911         REG_WR(bp, params->lfa_base +
12912                offsetof(struct shmem_lfa, req_duplex),
12913                params->req_duplex[0] | (params->req_duplex[1] << 16));
12914
12915         REG_WR(bp, params->lfa_base +
12916                offsetof(struct shmem_lfa, req_flow_ctrl),
12917                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12918
12919         REG_WR(bp, params->lfa_base +
12920                offsetof(struct shmem_lfa, req_line_speed),
12921                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12922
12923         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12924                 REG_WR(bp, params->lfa_base +
12925                        offsetof(struct shmem_lfa,
12926                                 speed_cap_mask[cfg_idx]),
12927                        params->speed_cap_mask[cfg_idx]);
12928         }
12929
12930         tmp_val = REG_RD(bp, params->lfa_base +
12931                          offsetof(struct shmem_lfa, additional_config));
12932         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12933         tmp_val |= params->req_fc_auto_adv;
12934
12935         REG_WR(bp, params->lfa_base +
12936                offsetof(struct shmem_lfa, additional_config), tmp_val);
12937
12938         lfa_sts = REG_RD(bp, params->lfa_base +
12939                          offsetof(struct shmem_lfa, lfa_sts));
12940
12941         /* Clear the "Don't Clear Statistics" bit, and set reason */
12942         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12943
12944         /* Set link flap reason */
12945         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12946         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12947                     LFA_LINK_FLAP_REASON_OFFSET);
12948
12949         /* Increment link flap counter */
12950         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12951                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12952                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12953                     << LINK_FLAP_COUNT_OFFSET));
12954         REG_WR(bp, params->lfa_base +
12955                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12956         /* Proceed with regular link initialization */
12957 }
12958
12959 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12960 {
12961         int lfa_status;
12962         struct bnx2x *bp = params->bp;
12963         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12964         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12965                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12966         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12967                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12968         DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12969         vars->link_status = 0;
12970         vars->phy_link_up = 0;
12971         vars->link_up = 0;
12972         vars->line_speed = 0;
12973         vars->duplex = DUPLEX_FULL;
12974         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12975         vars->mac_type = MAC_TYPE_NONE;
12976         vars->phy_flags = 0;
12977         vars->check_kr2_recovery_cnt = 0;
12978         params->link_flags = PHY_INITIALIZED;
12979         /* Driver opens NIG-BRB filters */
12980         bnx2x_set_rx_filter(params, 1);
12981         bnx2x_chng_link_count(params, true);
12982         /* Check if link flap can be avoided */
12983         lfa_status = bnx2x_check_lfa(params);
12984
12985         if (lfa_status == 0) {
12986                 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12987                 return bnx2x_avoid_link_flap(params, vars);
12988         }
12989
12990         DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12991                        lfa_status);
12992         bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12993
12994         /* Disable attentions */
12995         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12996                        (NIG_MASK_XGXS0_LINK_STATUS |
12997                         NIG_MASK_XGXS0_LINK10G |
12998                         NIG_MASK_SERDES0_LINK_STATUS |
12999                         NIG_MASK_MI_INT));
13000
13001         bnx2x_emac_init(params, vars);
13002
13003         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
13004                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
13005
13006         if (params->num_phys == 0) {
13007                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
13008                 return -EINVAL;
13009         }
13010         set_phy_vars(params, vars);
13011
13012         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
13013         switch (params->loopback_mode) {
13014         case LOOPBACK_BMAC:
13015                 bnx2x_init_bmac_loopback(params, vars);
13016                 break;
13017         case LOOPBACK_EMAC:
13018                 bnx2x_init_emac_loopback(params, vars);
13019                 break;
13020         case LOOPBACK_XMAC:
13021                 bnx2x_init_xmac_loopback(params, vars);
13022                 break;
13023         case LOOPBACK_UMAC:
13024                 bnx2x_init_umac_loopback(params, vars);
13025                 break;
13026         case LOOPBACK_XGXS:
13027         case LOOPBACK_EXT_PHY:
13028                 bnx2x_init_xgxs_loopback(params, vars);
13029                 break;
13030         default:
13031                 if (!CHIP_IS_E3(bp)) {
13032                         if (params->switch_cfg == SWITCH_CFG_10G)
13033                                 bnx2x_xgxs_deassert(params);
13034                         else
13035                                 bnx2x_serdes_deassert(bp, params->port);
13036                 }
13037                 bnx2x_link_initialize(params, vars);
13038                 msleep(30);
13039                 bnx2x_link_int_enable(params);
13040                 break;
13041         }
13042         bnx2x_update_mng(params, vars->link_status);
13043
13044         bnx2x_update_mng_eee(params, vars->eee_status);
13045         return 0;
13046 }
13047
13048 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
13049                      u8 reset_ext_phy)
13050 {
13051         struct bnx2x *bp = params->bp;
13052         u8 phy_index, port = params->port, clear_latch_ind = 0;
13053         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
13054         /* Disable attentions */
13055         vars->link_status = 0;
13056         bnx2x_chng_link_count(params, true);
13057         bnx2x_update_mng(params, vars->link_status);
13058         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
13059                               SHMEM_EEE_ACTIVE_BIT);
13060         bnx2x_update_mng_eee(params, vars->eee_status);
13061         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
13062                        (NIG_MASK_XGXS0_LINK_STATUS |
13063                         NIG_MASK_XGXS0_LINK10G |
13064                         NIG_MASK_SERDES0_LINK_STATUS |
13065                         NIG_MASK_MI_INT));
13066
13067         /* Activate nig drain */
13068         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
13069
13070         /* Disable nig egress interface */
13071         if (!CHIP_IS_E3(bp)) {
13072                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
13073                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
13074         }
13075
13076                 if (!CHIP_IS_E3(bp)) {
13077                         bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
13078                 } else {
13079                         bnx2x_set_xmac_rxtx(params, 0);
13080                         bnx2x_set_umac_rxtx(params, 0);
13081                 }
13082         /* Disable emac */
13083         if (!CHIP_IS_E3(bp))
13084                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
13085
13086         usleep_range(10000, 20000);
13087         /* The PHY reset is controlled by GPIO 1
13088          * Hold it as vars low
13089          */
13090          /* Clear link led */
13091         bnx2x_set_mdio_emac_per_phy(bp, params);
13092         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
13093
13094         if (reset_ext_phy) {
13095                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
13096                       phy_index++) {
13097                         if (params->phy[phy_index].link_reset) {
13098                                 bnx2x_set_aer_mmd(params,
13099                                                   &params->phy[phy_index]);
13100                                 params->phy[phy_index].link_reset(
13101                                         &params->phy[phy_index],
13102                                         params);
13103                         }
13104                         if (params->phy[phy_index].flags &
13105                             FLAGS_REARM_LATCH_SIGNAL)
13106                                 clear_latch_ind = 1;
13107                 }
13108         }
13109
13110         if (clear_latch_ind) {
13111                 /* Clear latching indication */
13112                 bnx2x_rearm_latch_signal(bp, port, 0);
13113                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
13114                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
13115         }
13116         if (params->phy[INT_PHY].link_reset)
13117                 params->phy[INT_PHY].link_reset(
13118                         &params->phy[INT_PHY], params);
13119
13120         /* Disable nig ingress interface */
13121         if (!CHIP_IS_E3(bp)) {
13122                 /* Reset BigMac */
13123                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
13124                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
13125                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
13126                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
13127         } else {
13128                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13129                 bnx2x_set_xumac_nig(params, 0, 0);
13130                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13131                     MISC_REGISTERS_RESET_REG_2_XMAC)
13132                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
13133                                XMAC_CTRL_REG_SOFT_RESET);
13134         }
13135         vars->link_up = 0;
13136         vars->phy_flags = 0;
13137         return 0;
13138 }
13139 int bnx2x_lfa_reset(struct link_params *params,
13140                                struct link_vars *vars)
13141 {
13142         struct bnx2x *bp = params->bp;
13143         vars->link_up = 0;
13144         vars->phy_flags = 0;
13145         params->link_flags &= ~PHY_INITIALIZED;
13146         if (!params->lfa_base)
13147                 return bnx2x_link_reset(params, vars, 1);
13148         /*
13149          * Activate NIG drain so that during this time the device won't send
13150          * anything while it is unable to response.
13151          */
13152         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13153
13154         /*
13155          * Close gracefully the gate from BMAC to NIG such that no half packets
13156          * are passed.
13157          */
13158         if (!CHIP_IS_E3(bp))
13159                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
13160
13161         if (CHIP_IS_E3(bp)) {
13162                 bnx2x_set_xmac_rxtx(params, 0);
13163                 bnx2x_set_umac_rxtx(params, 0);
13164         }
13165         /* Wait 10ms for the pipe to clean up*/
13166         usleep_range(10000, 20000);
13167
13168         /* Clean the NIG-BRB using the network filters in a way that will
13169          * not cut a packet in the middle.
13170          */
13171         bnx2x_set_rx_filter(params, 0);
13172
13173         /*
13174          * Re-open the gate between the BMAC and the NIG, after verifying the
13175          * gate to the BRB is closed, otherwise packets may arrive to the
13176          * firmware before driver had initialized it. The target is to achieve
13177          * minimum management protocol down time.
13178          */
13179         if (!CHIP_IS_E3(bp))
13180                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
13181
13182         if (CHIP_IS_E3(bp)) {
13183                 bnx2x_set_xmac_rxtx(params, 1);
13184                 bnx2x_set_umac_rxtx(params, 1);
13185         }
13186         /* Disable NIG drain */
13187         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13188         return 0;
13189 }
13190
13191 /****************************************************************************/
13192 /*                              Common function                             */
13193 /****************************************************************************/
13194 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
13195                                       u32 shmem_base_path[],
13196                                       u32 shmem2_base_path[], u8 phy_index,
13197                                       u32 chip_id)
13198 {
13199         struct bnx2x_phy phy[PORT_MAX];
13200         struct bnx2x_phy *phy_blk[PORT_MAX];
13201         u16 val;
13202         s8 port = 0;
13203         s8 port_of_path = 0;
13204         u32 swap_val, swap_override;
13205         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
13206         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
13207         port ^= (swap_val && swap_override);
13208         bnx2x_ext_phy_hw_reset(bp, port);
13209         /* PART1 - Reset both phys */
13210         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13211                 u32 shmem_base, shmem2_base;
13212                 /* In E2, same phy is using for port0 of the two paths */
13213                 if (CHIP_IS_E1x(bp)) {
13214                         shmem_base = shmem_base_path[0];
13215                         shmem2_base = shmem2_base_path[0];
13216                         port_of_path = port;
13217                 } else {
13218                         shmem_base = shmem_base_path[port];
13219                         shmem2_base = shmem2_base_path[port];
13220                         port_of_path = 0;
13221                 }
13222
13223                 /* Extract the ext phy address for the port */
13224                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13225                                        port_of_path, &phy[port]) !=
13226                     0) {
13227                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
13228                         return -EINVAL;
13229                 }
13230                 /* Disable attentions */
13231                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13232                                port_of_path*4,
13233                                (NIG_MASK_XGXS0_LINK_STATUS |
13234                                 NIG_MASK_XGXS0_LINK10G |
13235                                 NIG_MASK_SERDES0_LINK_STATUS |
13236                                 NIG_MASK_MI_INT));
13237
13238                 /* Need to take the phy out of low power mode in order
13239                  * to write to access its registers
13240                  */
13241                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
13242                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13243                                port);
13244
13245                 /* Reset the phy */
13246                 bnx2x_cl45_write(bp, &phy[port],
13247                                  MDIO_PMA_DEVAD,
13248                                  MDIO_PMA_REG_CTRL,
13249                                  1<<15);
13250         }
13251
13252         /* Add delay of 150ms after reset */
13253         msleep(150);
13254
13255         if (phy[PORT_0].addr & 0x1) {
13256                 phy_blk[PORT_0] = &(phy[PORT_1]);
13257                 phy_blk[PORT_1] = &(phy[PORT_0]);
13258         } else {
13259                 phy_blk[PORT_0] = &(phy[PORT_0]);
13260                 phy_blk[PORT_1] = &(phy[PORT_1]);
13261         }
13262
13263         /* PART2 - Download firmware to both phys */
13264         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13265                 if (CHIP_IS_E1x(bp))
13266                         port_of_path = port;
13267                 else
13268                         port_of_path = 0;
13269
13270                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13271                            phy_blk[port]->addr);
13272                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13273                                                       port_of_path))
13274                         return -EINVAL;
13275
13276                 /* Only set bit 10 = 1 (Tx power down) */
13277                 bnx2x_cl45_read(bp, phy_blk[port],
13278                                 MDIO_PMA_DEVAD,
13279                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13280
13281                 /* Phase1 of TX_POWER_DOWN reset */
13282                 bnx2x_cl45_write(bp, phy_blk[port],
13283                                  MDIO_PMA_DEVAD,
13284                                  MDIO_PMA_REG_TX_POWER_DOWN,
13285                                  (val | 1<<10));
13286         }
13287
13288         /* Toggle Transmitter: Power down and then up with 600ms delay
13289          * between
13290          */
13291         msleep(600);
13292
13293         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
13294         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13295                 /* Phase2 of POWER_DOWN_RESET */
13296                 /* Release bit 10 (Release Tx power down) */
13297                 bnx2x_cl45_read(bp, phy_blk[port],
13298                                 MDIO_PMA_DEVAD,
13299                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13300
13301                 bnx2x_cl45_write(bp, phy_blk[port],
13302                                 MDIO_PMA_DEVAD,
13303                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
13304                 usleep_range(15000, 30000);
13305
13306                 /* Read modify write the SPI-ROM version select register */
13307                 bnx2x_cl45_read(bp, phy_blk[port],
13308                                 MDIO_PMA_DEVAD,
13309                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
13310                 bnx2x_cl45_write(bp, phy_blk[port],
13311                                  MDIO_PMA_DEVAD,
13312                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
13313
13314                 /* set GPIO2 back to LOW */
13315                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
13316                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
13317         }
13318         return 0;
13319 }
13320 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
13321                                       u32 shmem_base_path[],
13322                                       u32 shmem2_base_path[], u8 phy_index,
13323                                       u32 chip_id)
13324 {
13325         u32 val;
13326         s8 port;
13327         struct bnx2x_phy phy;
13328         /* Use port1 because of the static port-swap */
13329         /* Enable the module detection interrupt */
13330         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13331         val |= ((1<<MISC_REGISTERS_GPIO_3)|
13332                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
13333         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13334
13335         bnx2x_ext_phy_hw_reset(bp, 0);
13336         usleep_range(5000, 10000);
13337         for (port = 0; port < PORT_MAX; port++) {
13338                 u32 shmem_base, shmem2_base;
13339
13340                 /* In E2, same phy is using for port0 of the two paths */
13341                 if (CHIP_IS_E1x(bp)) {
13342                         shmem_base = shmem_base_path[0];
13343                         shmem2_base = shmem2_base_path[0];
13344                 } else {
13345                         shmem_base = shmem_base_path[port];
13346                         shmem2_base = shmem2_base_path[port];
13347                 }
13348                 /* Extract the ext phy address for the port */
13349                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13350                                        port, &phy) !=
13351                     0) {
13352                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13353                         return -EINVAL;
13354                 }
13355
13356                 /* Reset phy*/
13357                 bnx2x_cl45_write(bp, &phy,
13358                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
13359
13360
13361                 /* Set fault module detected LED on */
13362                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
13363                                MISC_REGISTERS_GPIO_HIGH,
13364                                port);
13365         }
13366
13367         return 0;
13368 }
13369 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
13370                                          u8 *io_gpio, u8 *io_port)
13371 {
13372
13373         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
13374                                           offsetof(struct shmem_region,
13375                                 dev_info.port_hw_config[PORT_0].default_cfg));
13376         switch (phy_gpio_reset) {
13377         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13378                 *io_gpio = 0;
13379                 *io_port = 0;
13380                 break;
13381         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13382                 *io_gpio = 1;
13383                 *io_port = 0;
13384                 break;
13385         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13386                 *io_gpio = 2;
13387                 *io_port = 0;
13388                 break;
13389         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13390                 *io_gpio = 3;
13391                 *io_port = 0;
13392                 break;
13393         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13394                 *io_gpio = 0;
13395                 *io_port = 1;
13396                 break;
13397         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13398                 *io_gpio = 1;
13399                 *io_port = 1;
13400                 break;
13401         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13402                 *io_gpio = 2;
13403                 *io_port = 1;
13404                 break;
13405         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13406                 *io_gpio = 3;
13407                 *io_port = 1;
13408                 break;
13409         default:
13410                 /* Don't override the io_gpio and io_port */
13411                 break;
13412         }
13413 }
13414
13415 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13416                                       u32 shmem_base_path[],
13417                                       u32 shmem2_base_path[], u8 phy_index,
13418                                       u32 chip_id)
13419 {
13420         s8 port, reset_gpio;
13421         u32 swap_val, swap_override;
13422         struct bnx2x_phy phy[PORT_MAX];
13423         struct bnx2x_phy *phy_blk[PORT_MAX];
13424         s8 port_of_path;
13425         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13426         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13427
13428         reset_gpio = MISC_REGISTERS_GPIO_1;
13429         port = 1;
13430
13431         /* Retrieve the reset gpio/port which control the reset.
13432          * Default is GPIO1, PORT1
13433          */
13434         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13435                                      (u8 *)&reset_gpio, (u8 *)&port);
13436
13437         /* Calculate the port based on port swap */
13438         port ^= (swap_val && swap_override);
13439
13440         /* Initiate PHY reset*/
13441         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13442                        port);
13443         usleep_range(1000, 2000);
13444         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13445                        port);
13446
13447         usleep_range(5000, 10000);
13448
13449         /* PART1 - Reset both phys */
13450         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13451                 u32 shmem_base, shmem2_base;
13452
13453                 /* In E2, same phy is using for port0 of the two paths */
13454                 if (CHIP_IS_E1x(bp)) {
13455                         shmem_base = shmem_base_path[0];
13456                         shmem2_base = shmem2_base_path[0];
13457                         port_of_path = port;
13458                 } else {
13459                         shmem_base = shmem_base_path[port];
13460                         shmem2_base = shmem2_base_path[port];
13461                         port_of_path = 0;
13462                 }
13463
13464                 /* Extract the ext phy address for the port */
13465                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13466                                        port_of_path, &phy[port]) !=
13467                                        0) {
13468                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13469                         return -EINVAL;
13470                 }
13471                 /* disable attentions */
13472                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13473                                port_of_path*4,
13474                                (NIG_MASK_XGXS0_LINK_STATUS |
13475                                 NIG_MASK_XGXS0_LINK10G |
13476                                 NIG_MASK_SERDES0_LINK_STATUS |
13477                                 NIG_MASK_MI_INT));
13478
13479
13480                 /* Reset the phy */
13481                 bnx2x_cl45_write(bp, &phy[port],
13482                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13483         }
13484
13485         /* Add delay of 150ms after reset */
13486         msleep(150);
13487         if (phy[PORT_0].addr & 0x1) {
13488                 phy_blk[PORT_0] = &(phy[PORT_1]);
13489                 phy_blk[PORT_1] = &(phy[PORT_0]);
13490         } else {
13491                 phy_blk[PORT_0] = &(phy[PORT_0]);
13492                 phy_blk[PORT_1] = &(phy[PORT_1]);
13493         }
13494         /* PART2 - Download firmware to both phys */
13495         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13496                 if (CHIP_IS_E1x(bp))
13497                         port_of_path = port;
13498                 else
13499                         port_of_path = 0;
13500                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13501                            phy_blk[port]->addr);
13502                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13503                                                       port_of_path))
13504                         return -EINVAL;
13505                 /* Disable PHY transmitter output */
13506                 bnx2x_cl45_write(bp, phy_blk[port],
13507                                  MDIO_PMA_DEVAD,
13508                                  MDIO_PMA_REG_TX_DISABLE, 1);
13509
13510         }
13511         return 0;
13512 }
13513
13514 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13515                                                 u32 shmem_base_path[],
13516                                                 u32 shmem2_base_path[],
13517                                                 u8 phy_index,
13518                                                 u32 chip_id)
13519 {
13520         u8 reset_gpios;
13521         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13522         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13523         udelay(10);
13524         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13525         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13526                 reset_gpios);
13527         return 0;
13528 }
13529
13530 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13531                                      u32 shmem2_base_path[], u8 phy_index,
13532                                      u32 ext_phy_type, u32 chip_id)
13533 {
13534         int rc = 0;
13535
13536         switch (ext_phy_type) {
13537         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13538                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13539                                                 shmem2_base_path,
13540                                                 phy_index, chip_id);
13541                 break;
13542         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13543         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13544         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13545                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13546                                                 shmem2_base_path,
13547                                                 phy_index, chip_id);
13548                 break;
13549
13550         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13551                 /* GPIO1 affects both ports, so there's need to pull
13552                  * it for single port alone
13553                  */
13554                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13555                                                 shmem2_base_path,
13556                                                 phy_index, chip_id);
13557                 break;
13558         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13559         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13560         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
13561                 /* GPIO3's are linked, and so both need to be toggled
13562                  * to obtain required 2us pulse.
13563                  */
13564                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13565                                                 shmem2_base_path,
13566                                                 phy_index, chip_id);
13567                 break;
13568         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13569                 rc = -EINVAL;
13570                 break;
13571         default:
13572                 DP(NETIF_MSG_LINK,
13573                            "ext_phy 0x%x common init not required\n",
13574                            ext_phy_type);
13575                 break;
13576         }
13577
13578         if (rc)
13579                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
13580                                       " Port %d\n",
13581                          0);
13582         return rc;
13583 }
13584
13585 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13586                           u32 shmem2_base_path[], u32 chip_id)
13587 {
13588         int rc = 0;
13589         u32 phy_ver, val;
13590         u8 phy_index = 0;
13591         u32 ext_phy_type, ext_phy_config;
13592
13593         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13594         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13595         DP(NETIF_MSG_LINK, "Begin common phy init\n");
13596         if (CHIP_IS_E3(bp)) {
13597                 /* Enable EPIO */
13598                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13599                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13600         }
13601         /* Check if common init was already done */
13602         phy_ver = REG_RD(bp, shmem_base_path[0] +
13603                          offsetof(struct shmem_region,
13604                                   port_mb[PORT_0].ext_phy_fw_version));
13605         if (phy_ver) {
13606                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13607                                phy_ver);
13608                 return 0;
13609         }
13610
13611         /* Read the ext_phy_type for arbitrary port(0) */
13612         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13613               phy_index++) {
13614                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13615                                                           shmem_base_path[0],
13616                                                           phy_index, 0);
13617                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13618                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13619                                                 shmem2_base_path,
13620                                                 phy_index, ext_phy_type,
13621                                                 chip_id);
13622         }
13623         return rc;
13624 }
13625
13626 static void bnx2x_check_over_curr(struct link_params *params,
13627                                   struct link_vars *vars)
13628 {
13629         struct bnx2x *bp = params->bp;
13630         u32 cfg_pin;
13631         u8 port = params->port;
13632         u32 pin_val;
13633
13634         cfg_pin = (REG_RD(bp, params->shmem_base +
13635                           offsetof(struct shmem_region,
13636                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13637                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13638                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13639
13640         /* Ignore check if no external input PIN available */
13641         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13642                 return;
13643
13644         if (!pin_val) {
13645                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13646                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
13647                                             " been detected and the power to "
13648                                             "that SFP+ module has been removed"
13649                                             " to prevent failure of the card."
13650                                             " Please remove the SFP+ module and"
13651                                             " restart the system to clear this"
13652                                             " error.\n",
13653                          params->port);
13654                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13655                         bnx2x_warpcore_power_module(params, 0);
13656                 }
13657         } else
13658                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13659 }
13660
13661 /* Returns 0 if no change occurred since last check; 1 otherwise. */
13662 static u8 bnx2x_analyze_link_error(struct link_params *params,
13663                                     struct link_vars *vars, u32 status,
13664                                     u32 phy_flag, u32 link_flag, u8 notify)
13665 {
13666         struct bnx2x *bp = params->bp;
13667         /* Compare new value with previous value */
13668         u8 led_mode;
13669         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13670
13671         if ((status ^ old_status) == 0)
13672                 return 0;
13673
13674         /* If values differ */
13675         switch (phy_flag) {
13676         case PHY_HALF_OPEN_CONN_FLAG:
13677                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13678                 break;
13679         case PHY_SFP_TX_FAULT_FLAG:
13680                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13681                 break;
13682         default:
13683                 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13684         }
13685         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13686            old_status, status);
13687
13688         /* Do not touch the link in case physical link down */
13689         if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
13690                 return 1;
13691
13692         /* a. Update shmem->link_status accordingly
13693          * b. Update link_vars->link_up
13694          */
13695         if (status) {
13696                 vars->link_status &= ~LINK_STATUS_LINK_UP;
13697                 vars->link_status |= link_flag;
13698                 vars->link_up = 0;
13699                 vars->phy_flags |= phy_flag;
13700
13701                 /* activate nig drain */
13702                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13703                 /* Set LED mode to off since the PHY doesn't know about these
13704                  * errors
13705                  */
13706                 led_mode = LED_MODE_OFF;
13707         } else {
13708                 vars->link_status |= LINK_STATUS_LINK_UP;
13709                 vars->link_status &= ~link_flag;
13710                 vars->link_up = 1;
13711                 vars->phy_flags &= ~phy_flag;
13712                 led_mode = LED_MODE_OPER;
13713
13714                 /* Clear nig drain */
13715                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13716         }
13717         bnx2x_sync_link(params, vars);
13718         /* Update the LED according to the link state */
13719         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13720
13721         /* Update link status in the shared memory */
13722         bnx2x_update_mng(params, vars->link_status);
13723
13724         /* C. Trigger General Attention */
13725         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13726         if (notify)
13727                 bnx2x_notify_link_changed(bp);
13728
13729         return 1;
13730 }
13731
13732 /******************************************************************************
13733 * Description:
13734 *       This function checks for half opened connection change indication.
13735 *       When such change occurs, it calls the bnx2x_analyze_link_error
13736 *       to check if Remote Fault is set or cleared. Reception of remote fault
13737 *       status message in the MAC indicates that the peer's MAC has detected
13738 *       a fault, for example, due to break in the TX side of fiber.
13739 *
13740 ******************************************************************************/
13741 static int bnx2x_check_half_open_conn(struct link_params *params,
13742                                       struct link_vars *vars,
13743                                       u8 notify)
13744 {
13745         struct bnx2x *bp = params->bp;
13746         u32 lss_status = 0;
13747         u32 mac_base;
13748         /* In case link status is physically up @ 10G do */
13749         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13750             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13751                 return 0;
13752
13753         if (CHIP_IS_E3(bp) &&
13754             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13755               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13756                 /* Check E3 XMAC */
13757                 /* Note that link speed cannot be queried here, since it may be
13758                  * zero while link is down. In case UMAC is active, LSS will
13759                  * simply not be set
13760                  */
13761                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13762
13763                 /* Clear stick bits (Requires rising edge) */
13764                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13765                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13766                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13767                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13768                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13769                         lss_status = 1;
13770
13771                 bnx2x_analyze_link_error(params, vars, lss_status,
13772                                          PHY_HALF_OPEN_CONN_FLAG,
13773                                          LINK_STATUS_NONE, notify);
13774         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13775                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13776                 /* Check E1X / E2 BMAC */
13777                 u32 lss_status_reg;
13778                 u32 wb_data[2];
13779                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13780                         NIG_REG_INGRESS_BMAC0_MEM;
13781                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13782                 if (CHIP_IS_E2(bp))
13783                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13784                 else
13785                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13786
13787                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13788                 lss_status = (wb_data[0] > 0);
13789
13790                 bnx2x_analyze_link_error(params, vars, lss_status,
13791                                          PHY_HALF_OPEN_CONN_FLAG,
13792                                          LINK_STATUS_NONE, notify);
13793         }
13794         return 0;
13795 }
13796 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13797                                          struct link_params *params,
13798                                          struct link_vars *vars)
13799 {
13800         struct bnx2x *bp = params->bp;
13801         u32 cfg_pin, value = 0;
13802         u8 led_change, port = params->port;
13803
13804         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13805         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13806                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13807                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13808                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13809
13810         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13811                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13812                 return;
13813         }
13814
13815         led_change = bnx2x_analyze_link_error(params, vars, value,
13816                                               PHY_SFP_TX_FAULT_FLAG,
13817                                               LINK_STATUS_SFP_TX_FAULT, 1);
13818
13819         if (led_change) {
13820                 /* Change TX_Fault led, set link status for further syncs */
13821                 u8 led_mode;
13822
13823                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13824                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13825                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13826                 } else {
13827                         led_mode = MISC_REGISTERS_GPIO_LOW;
13828                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13829                 }
13830
13831                 /* If module is unapproved, led should be on regardless */
13832                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13833                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13834                            led_mode);
13835                         bnx2x_set_e3_module_fault_led(params, led_mode);
13836                 }
13837         }
13838 }
13839 static void bnx2x_kr2_recovery(struct link_params *params,
13840                                struct link_vars *vars,
13841                                struct bnx2x_phy *phy)
13842 {
13843         struct bnx2x *bp = params->bp;
13844         DP(NETIF_MSG_LINK, "KR2 recovery\n");
13845         bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13846         bnx2x_warpcore_restart_AN_KR(phy, params);
13847 }
13848
13849 static void bnx2x_check_kr2_wa(struct link_params *params,
13850                                struct link_vars *vars,
13851                                struct bnx2x_phy *phy)
13852 {
13853         struct bnx2x *bp = params->bp;
13854         u16 base_page, next_page, not_kr2_device, lane;
13855         int sigdet;
13856
13857         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13858          * Since some switches tend to reinit the AN process and clear the
13859          * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13860          * and recovered many times
13861          */
13862         if (vars->check_kr2_recovery_cnt > 0) {
13863                 vars->check_kr2_recovery_cnt--;
13864                 return;
13865         }
13866
13867         sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13868         if (!sigdet) {
13869                 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13870                         bnx2x_kr2_recovery(params, vars, phy);
13871                         DP(NETIF_MSG_LINK, "No sigdet\n");
13872                 }
13873                 return;
13874         }
13875
13876         lane = bnx2x_get_warpcore_lane(phy, params);
13877         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13878                           MDIO_AER_BLOCK_AER_REG, lane);
13879         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13880                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13881         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13882                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13883         bnx2x_set_aer_mmd(params, phy);
13884
13885         /* CL73 has not begun yet */
13886         if (base_page == 0) {
13887                 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13888                         bnx2x_kr2_recovery(params, vars, phy);
13889                         DP(NETIF_MSG_LINK, "No BP\n");
13890                 }
13891                 return;
13892         }
13893
13894         /* In case NP bit is not set in the BasePage, or it is set,
13895          * but only KX is advertised, declare this link partner as non-KR2
13896          * device.
13897          */
13898         not_kr2_device = (((base_page & 0x8000) == 0) ||
13899                           (((base_page & 0x8000) &&
13900                             ((next_page & 0xe0) == 0x20))));
13901
13902         /* In case KR2 is already disabled, check if we need to re-enable it */
13903         if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13904                 if (!not_kr2_device) {
13905                         DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13906                            next_page);
13907                         bnx2x_kr2_recovery(params, vars, phy);
13908                 }
13909                 return;
13910         }
13911         /* KR2 is enabled, but not KR2 device */
13912         if (not_kr2_device) {
13913                 /* Disable KR2 on both lanes */
13914                 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13915                 bnx2x_disable_kr2(params, vars, phy);
13916                 /* Restart AN on leading lane */
13917                 bnx2x_warpcore_restart_AN_KR(phy, params);
13918                 return;
13919         }
13920 }
13921
13922 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13923 {
13924         u16 phy_idx;
13925         struct bnx2x *bp = params->bp;
13926         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13927                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13928                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13929                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13930                             0)
13931                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13932                         break;
13933                 }
13934         }
13935
13936         if (CHIP_IS_E3(bp)) {
13937                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13938                 bnx2x_set_aer_mmd(params, phy);
13939                 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
13940                      (phy->speed_cap_mask &
13941                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
13942                     (phy->req_line_speed == SPEED_20000))
13943                         bnx2x_check_kr2_wa(params, vars, phy);
13944                 bnx2x_check_over_curr(params, vars);
13945                 if (vars->rx_tx_asic_rst)
13946                         bnx2x_warpcore_config_runtime(phy, params, vars);
13947
13948                 if ((REG_RD(bp, params->shmem_base +
13949                             offsetof(struct shmem_region, dev_info.
13950                                 port_hw_config[params->port].default_cfg))
13951                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13952                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
13953                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
13954                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13955                         } else if (vars->link_status &
13956                                 LINK_STATUS_SFP_TX_FAULT) {
13957                                 /* Clean trail, interrupt corrects the leds */
13958                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13959                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13960                                 /* Update link status in the shared memory */
13961                                 bnx2x_update_mng(params, vars->link_status);
13962                         }
13963                 }
13964         }
13965 }
13966
13967 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13968                              u32 shmem_base,
13969                              u32 shmem2_base,
13970                              u8 port)
13971 {
13972         u8 phy_index, fan_failure_det_req = 0;
13973         struct bnx2x_phy phy;
13974         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13975               phy_index++) {
13976                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13977                                        port, &phy)
13978                     != 0) {
13979                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13980                         return 0;
13981                 }
13982                 fan_failure_det_req |= (phy.flags &
13983                                         FLAGS_FAN_FAILURE_DET_REQ);
13984         }
13985         return fan_failure_det_req;
13986 }
13987
13988 void bnx2x_hw_reset_phy(struct link_params *params)
13989 {
13990         u8 phy_index;
13991         struct bnx2x *bp = params->bp;
13992         bnx2x_update_mng(params, 0);
13993         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13994                        (NIG_MASK_XGXS0_LINK_STATUS |
13995                         NIG_MASK_XGXS0_LINK10G |
13996                         NIG_MASK_SERDES0_LINK_STATUS |
13997                         NIG_MASK_MI_INT));
13998
13999         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
14000               phy_index++) {
14001                 if (params->phy[phy_index].hw_reset) {
14002                         params->phy[phy_index].hw_reset(
14003                                 &params->phy[phy_index],
14004                                 params);
14005                         params->phy[phy_index] = phy_null;
14006                 }
14007         }
14008 }
14009
14010 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
14011                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
14012                             u8 port)
14013 {
14014         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
14015         u32 val;
14016         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
14017         if (CHIP_IS_E3(bp)) {
14018                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
14019                                               shmem_base,
14020                                               port,
14021                                               &gpio_num,
14022                                               &gpio_port) != 0)
14023                         return;
14024         } else {
14025                 struct bnx2x_phy phy;
14026                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
14027                       phy_index++) {
14028                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
14029                                                shmem2_base, port, &phy)
14030                             != 0) {
14031                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
14032                                 return;
14033                         }
14034                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
14035                                 gpio_num = MISC_REGISTERS_GPIO_3;
14036                                 gpio_port = port;
14037                                 break;
14038                         }
14039                 }
14040         }
14041
14042         if (gpio_num == 0xff)
14043                 return;
14044
14045         /* Set GPIO3 to trigger SFP+ module insertion/removal */
14046         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
14047
14048         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
14049         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
14050         gpio_port ^= (swap_val && swap_override);
14051
14052         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
14053                 (gpio_num + (gpio_port << 2));
14054
14055         sync_offset = shmem_base +
14056                 offsetof(struct shmem_region,
14057                          dev_info.port_hw_config[port].aeu_int_mask);
14058         REG_WR(bp, sync_offset, vars->aeu_int_mask);
14059
14060         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
14061                        gpio_num, gpio_port, vars->aeu_int_mask);
14062
14063         if (port == 0)
14064                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
14065         else
14066                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
14067
14068         /* Open appropriate AEU for interrupts */
14069         aeu_mask = REG_RD(bp, offset);
14070         aeu_mask |= vars->aeu_int_mask;
14071         REG_WR(bp, offset, aeu_mask);
14072
14073         /* Enable the GPIO to trigger interrupt */
14074         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
14075         val |= 1 << (gpio_num + (gpio_port << 2));
14076         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
14077 }